-;; verilog-mode.el --- major mode for editing verilog source in Emacs
+;;; verilog-mode.el --- major mode for editing verilog source in Emacs
-;; Copyright (C) 1996-2012 Free Software Foundation, Inc.
+;; Copyright (C) 1996-2014 Free Software Foundation, Inc.
-;; Author: Michael McNamara (mac@verilog.com),
-;; Wilson Snyder (wsnyder@wsnyder.org)
-;; Please see our web sites:
+;; Author: Michael McNamara <mac@verilog.com>
+;; Wilson Snyder <wsnyder@wsnyder.org>
;; http://www.verilog.com
;; http://www.veripool.org
-;;
+;; Created: 3 Jan 1996
;; Keywords: languages
;; Yoni Rabkin <yoni@rabkins.net> contacted the maintainer of this
;;; Commentary:
-;; This mode borrows heavily from the Pascal-mode and the cc-mode of Emacs
-
;; USAGE
;; =====
-;; A major mode for editing Verilog HDL source code. When you have
-;; entered Verilog mode, you may get more info by pressing C-h m. You
-;; may also get online help describing various functions by: C-h f
-;; <Name of function you want described>
+;; A major mode for editing Verilog and SystemVerilog HDL source code (IEEE
+;; 1364-2005 and IEEE 1800-2012 standards). When you have entered Verilog
+;; mode, you may get more info by pressing C-h m. You may also get online
+;; help describing various functions by: C-h f <Name of function you want
+;; described>
;; KNOWN BUGS / BUG REPORTS
;; =======================
-;; Verilog is a rapidly evolving language, and hence this mode is
-;; under continuous development. Hence this is beta code, and likely
-;; has bugs. Please report any issues to the issue tracker at
-;; http://www.veripool.org/verilog-mode
+;; SystemVerilog is a rapidly evolving language, and hence this mode is
+;; under continuous development. Please report any issues to the issue
+;; tracker at
+;;
+;; http://www.veripool.org/verilog-mode
+;;
;; Please use verilog-submit-bug-report to submit a report; type C-c
-;; C-b to invoke this and as a result I will have a much easier time
+;; C-b to invoke this and as a result we will have a much easier time
;; of reproducing the bug you find, and hence fixing it.
;; INSTALLING THE MODE
; verilog-indent-begin-after-if t
; verilog-auto-lineup 'declarations
; verilog-highlight-p1800-keywords nil
-; verilog-linter "my_lint_shell_command"
-; )
+; verilog-linter "my_lint_shell_command"
+; )
;; \f
;;; Code:
;; This variable will always hold the version number of the mode
-(defconst verilog-mode-version "800"
+(defconst verilog-mode-version "2014-03-15-702457d-vpo"
"Version of this Verilog mode.")
-(defconst verilog-mode-release-date "2012-04-23-GNU"
- "Release date of this Verilog mode.")
(defconst verilog-mode-release-emacs t
"If non-nil, this version of Verilog mode was released with Emacs itself.")
(condition-case nil
(if (fboundp 'store-match-data)
nil ;; fab
- (defmacro store-match-data (&rest args) nil))
+ (defmacro store-match-data (&rest _args) nil))
(error nil))
(condition-case nil
(if (fboundp 'char-before)
nil ;; great
- (defmacro char-before (&rest body)
+ (defmacro char-before (&rest _body)
(char-after (1- (point)))))
(error nil))
(condition-case nil
(if (and (featurep 'custom) (fboundp 'custom-declare-variable))
nil ;; We've got what we needed
;; We have the old custom-library, hack around it!
- (defmacro defgroup (&rest args) nil)
- (defmacro customize (&rest args)
+ (defmacro defgroup (&rest _args) nil)
+ (defmacro customize (&rest _args)
(message
"Sorry, Customize is not available with this version of Emacs"))
- (defmacro defcustom (var value doc &rest args)
+ (defmacro defcustom (var value doc &rest _args)
`(defvar ,var ,value ,doc))
)
(if (fboundp 'defface)
nil ; great!
- (defmacro defface (var values doc &rest args)
+ (defmacro defface (var values doc &rest _args)
`(make-face ,var))
)
(if (and (featurep 'custom) (fboundp 'customize-group))
nil ;; We've got what we needed
;; We have an intermediate custom-library, hack around it!
- (defmacro customize-group (var &rest args)
+ (defmacro customize-group (var &rest _args)
`(customize ,var))
)
;with just a two input regexp
(defun verilog-regexp-opt (a b)
"Deal with differing number of required arguments for `regexp-opt'.
- Call 'regexp-opt' on A and B."
- (regexp-opt a b 't))
+ Call `regexp-opt' on A and B."
+ (regexp-opt a b t))
(error nil))
)
((eq args 2) ;; It takes 2
(defun verilog-regexp-opt (a b)
- "Call 'regexp-opt' on A and B."
+ "Call `regexp-opt' on A and B."
(regexp-opt a b))
)
(t nil)))
;; We can't tell; assume it takes 2
(defun verilog-regexp-opt (a b)
- "Call 'regexp-opt' on A and B."
+ "Call `regexp-opt' on A and B."
(regexp-opt a b))
)
;; There is no regexp-opt, provide our own
- (defun verilog-regexp-opt (strings &optional paren shy)
+ (defun verilog-regexp-opt (strings &optional paren _shy)
(let ((open (if paren "\\(" "")) (close (if paren "\\)" "")))
(concat open (mapconcat 'regexp-quote strings "\\|") close)))
)
"Type of statements to lineup across multiple lines.
If 'all' is selected, then all line ups described below are done.
-If 'declaration', then just declarations are lined up with any
+If 'declarations', then just declarations are lined up with any
preceding declarations, taking into account widths and the like,
so or example the code:
- reg [31:0] a;
- reg b;
+ reg [31:0] a;
+ reg b;
would become
- reg [31:0] a;
- reg b;
+ reg [31:0] a;
+ reg b;
If 'assignment', then assignments are lined up with any preceding
assignments, so for example the code
(put 'verilog-highlight-p1800-keywords 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-highlight-grouping-keywords nil
- "Non-nil means highlight grouping keywords 'begin' and 'end' more dramatically.
+ "Non-nil means highlight grouping keywords more dramatically.
If false, these words are in the `font-lock-type-face'; if True then they are in
`verilog-font-lock-ams-face'. Some find that special highlighting on these
grouping constructs allow the structure of the code to be understood at a glance."
(put 'verilog-library-extensions 'safe-local-variable 'listp)
(defcustom verilog-active-low-regexp nil
- "If set, treat signals matching this regexp as active low.
+ "If true, treat signals matching this regexp as active low.
This is used for AUTORESET and AUTOTIEOFF. For proper behavior,
you will probably also need `verilog-auto-reset-widths' set."
:group 'verilog-mode-auto
- :type 'string)
+ :type '(choice (const nil) regexp))
(put 'verilog-active-low-regexp 'safe-local-variable 'stringp)
(defcustom verilog-auto-sense-include-inputs nil
"True means AUTORESET should determine the width of signals.
This is then used to set the width of the zero (32'h0 for example). This
is required by some lint tools that aren't smart enough to ignore widths of
-the constant zero. This may result in ugly code when parameters determine
+the constant zero. This may result in ugly code when parameters determine
the MSB or LSB of a signal inside an AUTORESET.
If nil, AUTORESET uses \"0\" as the constant.
module ExampInst;
InstModule
- #(PARAM(10))
+ #(.PARAM(10))
instName
(/*AUTOINST*/
.i (i[PARAM-1:0]));
module ExampInst;
InstModule
- #(PARAM(10))
+ #(.PARAM(10))
instName
(/*AUTOINST*/
.i (i[9:0]));"
:type 'integer)
(put 'verilog-auto-inst-column 'safe-local-variable 'integerp)
-(defcustom verilog-auto-inst-interfaced-ports t
+(defcustom verilog-auto-inst-interfaced-ports nil
"Non-nil means include interfaced ports in AUTOINST expansions."
+ :version "24.3" ;; rev773, default change rev815
:group 'verilog-mode-auto
:type 'boolean)
(put 'verilog-auto-inst-interfaced-ports 'safe-local-variable 'verilog-booleanp)
(defcustom verilog-auto-input-ignore-regexp nil
- "If set, when creating AUTOINPUT list, ignore signals matching this regexp.
+ "If non-nil, when creating AUTOINPUT, ignore signals matching this regexp.
See the \\[verilog-faq] for examples on using this."
:group 'verilog-mode-auto
- :type 'string)
+ :type '(choice (const nil) regexp))
(put 'verilog-auto-input-ignore-regexp 'safe-local-variable 'stringp)
(defcustom verilog-auto-inout-ignore-regexp nil
- "If set, when creating AUTOINOUT list, ignore signals matching this regexp.
+ "If non-nil, when creating AUTOINOUT, ignore signals matching this regexp.
See the \\[verilog-faq] for examples on using this."
:group 'verilog-mode-auto
- :type 'string)
+ :type '(choice (const nil) regexp))
(put 'verilog-auto-inout-ignore-regexp 'safe-local-variable 'stringp)
(defcustom verilog-auto-output-ignore-regexp nil
- "If set, when creating AUTOOUTPUT list, ignore signals matching this regexp.
+ "If non-nil, when creating AUTOOUTPUT, ignore signals matching this regexp.
See the \\[verilog-faq] for examples on using this."
:group 'verilog-mode-auto
- :type 'string)
+ :type '(choice (const nil) regexp))
(put 'verilog-auto-output-ignore-regexp 'safe-local-variable 'stringp)
(defcustom verilog-auto-template-warn-unused nil
"Non-nil means report warning if an AUTO_TEMPLATE line is not used.
This feature is not supported before Emacs 21.1 or XEmacs 21.4."
+ :version "24.3" ;;rev787
:group 'verilog-mode-auto
:type 'boolean)
(put 'verilog-auto-template-warn-unused 'safe-local-variable 'verilog-booleanp)
(put 'verilog-auto-tieoff-declaration 'safe-local-variable 'stringp)
(defcustom verilog-auto-tieoff-ignore-regexp nil
- "If set, when creating AUTOTIEOFF list, ignore signals matching this regexp.
+ "If non-nil, when creating AUTOTIEOFF, ignore signals matching this regexp.
See the \\[verilog-faq] for examples on using this."
:group 'verilog-mode-auto
- :type 'string)
+ :type '(choice (const nil) regexp))
(put 'verilog-auto-tieoff-ignore-regexp 'safe-local-variable 'stringp)
(defcustom verilog-auto-unused-ignore-regexp nil
- "If set, when creating AUTOUNUSED list, ignore signals matching this regexp.
+ "If non-nil, when creating AUTOUNUSED, ignore signals matching this regexp.
See the \\[verilog-faq] for examples on using this."
:group 'verilog-mode-auto
- :type 'string)
+ :type '(choice (const nil) regexp))
(put 'verilog-auto-unused-ignore-regexp 'safe-local-variable 'stringp)
+(defcustom verilog-case-fold t
+ "Non-nil means `verilog-mode' regexps should ignore case.
+This variable is t for backward compatibility; nil is suggested."
+ :version "24.4"
+ :group 'verilog-mode
+ :type 'boolean)
+(put 'verilog-case-fold 'safe-local-variable 'verilog-booleanp)
+
(defcustom verilog-typedef-regexp nil
"If non-nil, regular expression that matches Verilog-2001 typedef names.
-For example, \"_t$\" matches typedefs named with _t, as in the C language."
+For example, \"_t$\" matches typedefs named with _t, as in the C language.
+See also `verilog-case-fold'."
:group 'verilog-mode-auto
- :type 'string)
+ :type '(choice (const nil) regexp))
(put 'verilog-typedef-regexp 'safe-local-variable 'stringp)
(defcustom verilog-mode-hook 'verilog-set-compile-command
(defcustom verilog-before-save-font-hook nil
"Hook run before `verilog-save-font-mods' removes highlighting."
+ :version "24.3" ;;rev735
:group 'verilog-mode-auto
:type 'hook)
(defcustom verilog-after-save-font-hook nil
"Hook run after `verilog-save-font-mods' restores highlighting."
+ :version "24.3" ;;rev735
:group 'verilog-mode-auto
:type 'hook)
:help "Help on AUTOARG - declaring module port list"]
["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum)
:help "Help on AUTOASCIIENUM - creating ASCII for enumerations"]
+ ["AUTOASSIGNMODPORT" (describe-function 'verilog-auto-assign-modport)
+ :help "Help on AUTOASSIGNMODPORT - creating assignments to/from modports"]
+ ["AUTOINOUT" (describe-function 'verilog-auto-inout)
+ :help "Help on AUTOINOUT - adding inouts from cells"]
["AUTOINOUTCOMP" (describe-function 'verilog-auto-inout-comp)
:help "Help on AUTOINOUTCOMP - copying complemented i/o from another file"]
["AUTOINOUTIN" (describe-function 'verilog-auto-inout-in)
- :help "Help on AUTOINOUTCOMP - copying i/o from another file as all inputs"]
+ :help "Help on AUTOINOUTIN - copying i/o from another file as all inputs"]
+ ["AUTOINOUTMODPORT" (describe-function 'verilog-auto-inout-modport)
+ :help "Help on AUTOINOUTMODPORT - copying i/o from an interface modport"]
["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module)
:help "Help on AUTOINOUTMODULE - copying i/o from another file"]
- ["AUTOINSERTLISP" (describe-function 'verilog-auto-insert-lisp)
- :help "Help on AUTOINSERTLISP - insert text from a lisp function"]
- ["AUTOINOUT" (describe-function 'verilog-auto-inout)
- :help "Help on AUTOINOUT - adding inouts from cells"]
+ ["AUTOINOUTPARAM" (describe-function 'verilog-auto-inout-param)
+ :help "Help on AUTOINOUTPARAM - copying parameters from another file"]
["AUTOINPUT" (describe-function 'verilog-auto-input)
:help "Help on AUTOINPUT - adding inputs from cells"]
+ ["AUTOINSERTLISP" (describe-function 'verilog-auto-insert-lisp)
+ :help "Help on AUTOINSERTLISP - insert text from a lisp function"]
["AUTOINST" (describe-function 'verilog-auto-inst)
:help "Help on AUTOINST - adding pins for cells"]
["AUTOINST (.*)" (describe-function 'verilog-auto-star)
:help "Help on AUTOREGINPUT - declaring inputs for non-wires"]
["AUTORESET" (describe-function 'verilog-auto-reset)
:help "Help on AUTORESET - resetting always blocks"]
- ["AUTOSENSE" (describe-function 'verilog-auto-sense)
+ ["AUTOSENSE or AS" (describe-function 'verilog-auto-sense)
:help "Help on AUTOSENSE - sensitivity lists for always blocks"]
["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff)
:help "Help on AUTOTIEOFF - tying off unused outputs"]
:help "Insert a module .. (/*AUTOARG*/);.. endmodule block"]
["OVM Class" verilog-sk-ovm-class
:help "Insert an OVM class block"]
- ["UVM Class" verilog-sk-uvm-class
- :help "Insert an UVM class block"]
+ ["UVM Object" verilog-sk-uvm-object
+ :help "Insert an UVM object block"]
+ ["UVM Component" verilog-sk-uvm-component
+ :help "Insert an UVM component block"]
["Primitive" verilog-sk-primitive
:help "Insert a primitive .. (.. );.. endprimitive block"]
"----"
(defsubst verilog-within-string ()
(nth 3 (parse-partial-sexp (point-at-bol) (point))))
+(defsubst verilog-string-match-fold (regexp string &optional start)
+ "Like `string-match', but use `verilog-case-fold'.
+Return index of start of first match for REGEXP in STRING, or nil.
+Matching ignores case if `verilog-case-fold' is non-nil.
+If third arg START is non-nil, start search at that index in STRING."
+ (let ((case-fold-search verilog-case-fold))
+ (string-match regexp string start)))
+
(defsubst verilog-string-replace-matches (from-string to-string fixedcase literal string)
"Replace occurrences of FROM-STRING with TO-STRING.
FIXEDCASE and LITERAL as in `replace-match`. STRING is what to replace.
string))
(defsubst verilog-re-search-forward (REGEXP BOUND NOERROR)
- ; checkdoc-params: (REGEXP BOUND NOERROR)
+ ;; checkdoc-params: (REGEXP BOUND NOERROR)
"Like `re-search-forward', but skips over match in comments or strings."
(let ((mdata '(nil nil))) ;; So match-end will return nil if no matches found
(while (and
(match-end 0)))
(defsubst verilog-re-search-backward (REGEXP BOUND NOERROR)
- ; checkdoc-params: (REGEXP BOUND NOERROR)
+ ;; checkdoc-params: (REGEXP BOUND NOERROR)
"Like `re-search-backward', but skips over match in comments or strings."
(let ((mdata '(nil nil))) ;; So match-end will return nil if no matches found
(while (and
pt))
(defsubst verilog-re-search-backward-quick (regexp bound noerror)
- ; checkdoc-params: (REGEXP BOUND NOERROR)
+ ;; checkdoc-params: (REGEXP BOUND NOERROR)
"Like `verilog-re-search-backward', including use of REGEXP BOUND and NOERROR,
but trashes match data and is faster for REGEXP that doesn't match often.
This uses `verilog-scan' and text properties to ignore comments,
;;(verilog-re-search-backward-substr "-end" "get-end-of" nil t) ;;-end (test bait)
(defun verilog-delete-trailing-whitespace ()
- "Delete trailing spaces or tabs, but not newlines nor linefeeds."
+ "Delete trailing spaces or tabs, but not newlines nor linefeeds.
+Also add missing final newline.
+
+To call this from the command line, see \\[verilog-batch-diff-auto].
+
+To call on \\[verilog-auto], set `verilog-auto-delete-trailing-whitespace'."
;; Similar to `delete-trailing-whitespace' but that's not present in XEmacs
(save-excursion
(goto-char (point-min))
(while (re-search-forward "[ \t]+$" nil t) ;; Not syntactic WS as no formfeed
- (replace-match "" nil nil))))
+ (replace-match "" nil nil))
+ (goto-char (point-max))
+ (unless (bolp) (insert "\n"))))
(defvar compile-command)
+(defvar create-lockfiles) ;; Emacs 24
;; compilation program
(defun verilog-set-compile-command ()
;; verilog-forward-sexp and verilog-calc-indent
(defconst verilog-beg-block-re-ordered
( concat "\\(\\<begin\\>\\)" ;1
- "\\|\\(\\<randcase\\>\\|\\(\\<unique\\s-+\\|priority\\s-+\\)?case[xz]?\\>\\)" ; 2,3
+ "\\|\\(\\<randcase\\>\\|\\(\\<unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\>\\)" ; 2,3
"\\|\\(\\(\\<disable\\>\\s-+\\|\\<wait\\>\\s-+\\)?fork\\>\\)" ;4,5
"\\|\\(\\<class\\>\\)" ;6
"\\|\\(\\<table\\>\\)" ;7
(eval-when-compile (verilog-regexp-words `("initial" "final" "always" "always_comb" "always_latch" "always_ff"
"function" "task"))))
(defconst verilog-coverpoint-re "\\w+\\s*:\\s*\\(coverpoint\\|cross\\constraint\\)" )
+(defconst verilog-in-constraint-re ;; keywords legal in constraint blocks starting a statement/block
+ (eval-when-compile (verilog-regexp-words `("if" "else" "solve" "foreach"))))
+
(defconst verilog-indent-re
(eval-when-compile
(verilog-regexp-words
"endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass"
))))
(defconst verilog-disable-fork-re "\\(disable\\|wait\\)\\s-+fork\\>")
-(defconst verilog-extended-case-re "\\(\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
+(defconst verilog-extended-case-re "\\(\\(unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
(defconst verilog-extended-complete-re
(concat "\\(\\(\\<extern\\s-+\\|\\<\\(\\<pure\\>\\s-+\\)?virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)\\)"
"\\|\\(\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)\\)"
"let" "nexttime" "reject_on" "restrict" "s_always" "s_eventually"
"s_nexttime" "s_until" "s_until_with" "strong" "sync_accept_on"
"sync_reject_on" "unique0" "until" "until_with" "untyped" "weak"
- )
- "List of Verilog keywords.")
+ ;; 1800-2012
+ "implements" "interconnect" "nettype" "soft"
+ )
+ "List of Verilog keywords.")
(defconst verilog-comment-start-regexp "//\\|/\\*"
"Dual comment value for `comment-start-regexp'.")
(modify-syntax-entry ?> "." table)
(modify-syntax-entry ?& "." table)
(modify-syntax-entry ?| "." table)
- (modify-syntax-entry ?` "w" table)
+ ;; FIXME: This goes against Emacs conventions. Use "_" syntax instead and
+ ;; then use regexps with things like "\\_<...\\_>".
+ (modify-syntax-entry ?` "w" table) ;; ` is part of definition symbols in Verilog
(modify-syntax-entry ?_ "w" table)
(modify-syntax-entry ?\' "." table)
"sync_accept_on" "sync_reject_on" "unique0" "until"
"until_with" "untyped" "weak" ) nil )))
+ (verilog-1800-2012-keywords
+ (eval-when-compile
+ (verilog-regexp-opt
+ '("implements" "interconnect" "nettype" "soft" ) nil )))
+
(verilog-ams-keywords
(eval-when-compile
(verilog-regexp-opt
'verilog-font-lock-p1800-face)
(cons (concat "\\<\\(" verilog-1800-2009-keywords "\\)\\>")
'font-lock-type-face))
+ ;; Fontify IEEE-1800-2012 keywords appropriately
+ (if verilog-highlight-p1800-keywords
+ (cons (concat "\\<\\(" verilog-1800-2012-keywords "\\)\\>")
+ 'verilog-font-lock-p1800-face)
+ (cons (concat "\\<\\(" verilog-1800-2012-keywords "\\)\\>")
+ 'font-lock-type-face))
;; Fontify Verilog-AMS keywords
(cons (concat "\\<\\(" verilog-ams-keywords "\\)\\>")
'verilog-font-lock-ams-face)))
;; Comment detection and caching
(defvar verilog-scan-cache-preserving nil
- "If set, the specified buffer's comment properties are static.
+ "If true, the specified buffer's comment properties are static.
Buffer changes will be ignored. See `verilog-inside-comment-or-string-p'
and `verilog-scan'.")
(setq verilog-scan-cache-tick nil))
(defun verilog-scan-cache-ok-p ()
- "Return t iff the scan cache is up to date."
+ "Return t if the scan cache is up to date."
(or (and verilog-scan-cache-preserving
(eq verilog-scan-cache-preserving (current-buffer))
verilog-scan-cache-tick)
(defun verilog-point-text (&optional pointnum)
"Return text describing where POINTNUM or current point is (for errors).
Use filename, if current buffer being edited shorten to just buffer name."
- (concat (or (and (equal (window-buffer (selected-window)) (current-buffer))
+ (concat (or (and (equal (window-buffer) (current-buffer))
(buffer-name))
buffer-file-name
(buffer-name))
(verilog-re-search-backward reg nil 'move))
(cond
((match-end 1) ; matched verilog-end-block-re
- ; try to leap back to matching outward block by striding across
- ; indent level changing tokens then immediately
- ; previous line governs indentation.
+ ;; try to leap back to matching outward block by striding across
+ ;; indent level changing tokens then immediately
+ ;; previous line governs indentation.
(verilog-leap-to-head))
((match-end 2) ; else, we're in deep
(setq elsec (1+ elsec)))
(setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
((match-end 2)
;; Search forward for matching endcase
- (setq reg "\\(\\<randcase\\>\\|\\(\\<unique\\>\\s-+\\|\\<priority\\>\\s-+\\)?\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )
+ (setq reg "\\(\\<randcase\\>\\|\\(\\<unique
0?\\>\\s-+\\|\\<priority\\>\\s-+\\)?\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )
(setq md 3) ;; ender is third item in regexp
)
((match-end 4)
\\[verilog-sk-fork] Insert a fork begin .. end .. join block.
\\[verilog-sk-module] Insert a module .. (/*AUTOARG*/);.. endmodule block.
\\[verilog-sk-ovm-class] Insert an OVM Class block.
- \\[verilog-sk-uvm-class] Insert an UVM Class block.
+ \\[verilog-sk-uvm-object] Insert an UVM Object block.
+ \\[verilog-sk-uvm-component] Insert an UVM Component block.
\\[verilog-sk-primitive] Insert a primitive .. (.. );.. endprimitive block.
\\[verilog-sk-repeat] Insert a repeat (..) begin .. end block.
\\[verilog-sk-specify] Insert a specify .. endspecify block.
(set-syntax-table verilog-mode-syntax-table)
(set (make-local-variable 'indent-line-function)
#'verilog-indent-line-relative)
- (setq comment-indent-function 'verilog-comment-indent)
+ (set (make-local-variable 'comment-indent-function) 'verilog-comment-indent)
(set (make-local-variable 'parse-sexp-ignore-comments) nil)
(set (make-local-variable 'comment-start) "// ")
(set (make-local-variable 'comment-end) "")
(mark-defun)))
(defun verilog-comment-region (start end)
- ; checkdoc-params: (start end)
+ ;; checkdoc-params: (start end)
"Put the region into a Verilog comment.
The comments that are in this area are \"deformed\":
`*)' becomes `!(*' and `}' becomes `!{'.
(interactive)
(verilog-re-search-forward verilog-end-defun-re nil 'move))
-(defun verilog-get-beg-of-defun (&optional warn)
- (save-excursion
- (cond ((verilog-re-search-forward-quick verilog-defun-re nil t)
- (point))
- (t
- (error "%s: Can't find module beginning" (verilog-point-text))
- (point-max)))))
-(defun verilog-get-end-of-defun (&optional warn)
+(defun verilog-get-end-of-defun ()
(save-excursion
(cond ((verilog-re-search-forward-quick verilog-end-defun-re nil t)
(point))
(error "%s: Can't find endmodule" (verilog-point-text))
(point-max)))))
-(defun verilog-label-be (&optional arg)
- "Label matching begin ... end, fork ... join and case ... endcase statements.
-With ARG, first kill any existing labels."
+(defun verilog-label-be ()
+ "Label matching begin ... end, fork ... join and case ... endcase statements."
(interactive)
(let ((cnt 0)
(oldpos (point))
((equal (char-after) ?\})
(forward-char))
- ;; Skip to end of statement
+ ;; Skip to end of statement
((condition-case nil
(setq pos
(catch 'found
(setq nest (1+ nest)))
((match-end 2)
(if (= nest 1)
- (throw 'found 1))
+ (throw 'found 1))
(setq nest (1- nest)))
(t
(throw 'found (= nest 0)))))))
"\\(`ifdef\\>\\)\\|"
"\\(`ifndef\\>\\)\\|"
"\\(`elsif\\>\\)"))
+
(defun verilog-set-auto-endcomments (indent-str kill-existing-comment)
"Add ending comment with given INDENT-STR.
With KILL-EXISTING-COMMENT, remove what was there before.
((looking-at "\\<randcase\\>")
(setq str "randcase")
(setq err nil))
- ((looking-at "\\(\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
+ ((looking-at "\\(\\(unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
(goto-char (match-end 0))
(setq str (concat (match-string 0) " " (verilog-get-expr)))
(setq err nil))
))))))))))
(defun verilog-get-expr()
- "Grab expression at point, e.g, case ( a | b & (c ^d))."
+ "Grab expression at point, e.g., case ( a | b & (c ^d))."
(let* ((b (progn
(verilog-forward-syntactic-ws)
(skip-chars-forward " \t")
(list
(let ((default (verilog-expand-command verilog-preprocessor)))
(set (make-local-variable `verilog-preprocessor)
- (read-from-minibuffer "Run Preprocessor (like this): "
- default nil nil
- 'verilog-preprocess-history default)))))
+ (read-from-minibuffer "Run Preprocessor (like this): "
+ default nil nil
+ 'verilog-preprocess-history default)))))
(unless command (setq command (verilog-expand-command verilog-preprocessor)))
(let* ((fontlocked (and (boundp 'font-lock-mode) font-lock-mode))
- (dir (file-name-directory (or filename buffer-file-name)))
- (cmd (concat "cd " dir "; " command)))
+ (dir (file-name-directory (or filename buffer-file-name)))
+ (cmd (concat "cd " dir "; " command)))
(with-output-to-temp-buffer "*Verilog-Preprocessed*"
(with-current-buffer (get-buffer "*Verilog-Preprocessed*")
(insert (concat "// " cmd "\n"))
(setq-default make-backup-files nil)
(setq enable-local-variables t)
(setq enable-local-eval t)
+ (setq create-lockfiles nil)
;; Make sure any sub-files we read get proper mode
(setq-default major-mode 'verilog-mode)
;; Ditto files already read in
(error "Use verilog-batch-delete-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
(verilog-batch-execute-func `verilog-delete-auto))
+(defun verilog-batch-delete-trailing-whitespace ()
+ "For use with --batch, perform whitespace deletion as a stand-alone tool.
+This sets up the appropriate Verilog mode environment, removes
+whitespace with \\[verilog-delete-trailing-whitespace] on all
+command-line files, and saves the buffers."
+ (unless noninteractive
+ (error "Use verilog-batch-delete-trailing-whitespace only with --batch")) ;; Otherwise we'd mess up buffer modes
+ (verilog-batch-execute-func `verilog-delete-trailing-whitespace))
+
(defun verilog-batch-diff-auto ()
"For use with --batch, perform automatic differences as a stand-alone tool.
This sets up the appropriate Verilog mode environment, expand automatics
(par 0)
(begin (looking-at "[ \t]*begin\\>"))
(lim (save-excursion (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)" nil t)))
+ (structres nil)
(type (catch 'nesting
;; Keep working backwards until we can figure out
;; what type of statement this is.
(if (save-excursion (beginning-of-line)
(and (looking-at verilog-directive-re-1)
(not (or (looking-at "[ \t]*`[ou]vm_")
- (looking-at "[ \t]*`vmm_")))))
+ (looking-at "[ \t]*`vmm_")))))
(throw 'nesting 'directive))
;; indent structs as if there were module level
- (if (verilog-in-struct-p)
- (throw 'nesting 'block))
+ (setq structres (verilog-in-struct-nested-p))
+ (cond ((not structres) nil)
+ ;;((and structres (equal (char-after) ?\})) (throw 'nesting 'struct-close))
+ ((> structres 0) (throw 'nesting 'nested-struct))
+ ((= structres 0) (throw 'nesting 'block))
+ (t nil))
;; if we are in a parenthesized list, and the user likes to indent these, return.
;; unless we are in the newfangled coverpoint or constraint blocks
;; trap out if we crawl off the top of the buffer
(if (bobp) (throw 'nesting 'cpp))
- (if (verilog-continued-line-1 lim)
+ (if (and (verilog-continued-line-1 lim)
+ (or (not (verilog-in-coverage-p))
+ (looking-at verilog-in-constraint-re) )) ;; may still get hosed if concat in constraint
(let ((sp (point)))
(if (and
(not (looking-at verilog-complete-reg))
(throw 'nesting 'cexp))
(goto-char sp))
-
+ (if (and (verilog-in-coverage-p)
+ (looking-at verilog-in-constraint-re))
+ (progn
+ (beginning-of-line)
+ (skip-chars-forward " \t")
+ (throw 'nesting 'constraint)))
(if (and begin
- (not verilog-indent-begin-after-if)
- (looking-at verilog-no-indent-begin-re))
+ (not verilog-indent-begin-after-if)
+ (looking-at verilog-no-indent-begin-re))
(progn
(beginning-of-line)
(skip-chars-forward " \t")
(list type (current-column)))
((eq type 'defun)
(list type 0))
+ ((eq type 'constraint)
+ (list 'block (current-column)))
+ ((eq type 'nested-struct)
+ (list 'block structres))
(t
(list type (verilog-current-indent-level))))))))
(t
(setq depth (verilog-current-indent-level)))))
(message "You are at nesting %s depth %d" type depth))))
+
(defun verilog-calc-1 ()
(catch 'nesting
- (let ((re (concat "\\({\\|}\\|" verilog-indent-re "\\)")))
+ (let ((re (concat "\\({\\|}\\|" verilog-indent-re "\\)"))
+ (inconstraint (verilog-in-coverage-p)))
(while (verilog-re-search-backward re nil 'move)
(catch 'continue
(cond
((equal (char-after) ?\{)
+ ;; block type returned based on outer constraint { or inner
(if (verilog-at-constraint-p)
- (throw 'nesting 'block)))
-
+ (cond (inconstraint (throw 'nesting 'constraint))
+ (t (throw 'nesting 'statement)))))
((equal (char-after) ?\})
- (let ((there (verilog-at-close-constraint-p)))
+ (let (par-pos
+ (there (verilog-at-close-constraint-p)))
(if there ;; we are at the } that closes a constraint. Find the { that opens it
(progn
- (forward-char 1)
- (backward-list 1)
- (verilog-beg-of-statement)))))
+ (if (> (verilog-in-paren-count) 0)
+ (forward-char 1))
+ (setq par-pos (verilog-parenthesis-depth))
+ (cond (par-pos
+ (goto-char par-pos)
+ (forward-char 1))
+ (t
+ (backward-char 1)))))))
((looking-at verilog-beg-block-re-ordered)
(cond
; endfunction
(verilog-beg-of-statement)
(if (looking-at verilog-beg-block-re-ordered)
- (throw 'nesting 'block)
- (throw 'nesting 'defun)))
+ (throw 'nesting 'block)
+ (throw 'nesting 'defun)))
- ;;
+ ;;
((looking-at "\\<property\\>")
; *sigh*
; {assert|assume|cover} property (); are complete
(while (/= 0 nest)
(verilog-re-search-backward
(concat
- "\\(\\<randcase\\>\\|\\(\\<unique\\s-+\\|priority\\s-+\\)?\\<case[xz]?\\>\\)"
+ "\\(\\<randcase\\>\\|\\(\\<unique0?\\s-+\\|priority\\s-+\\)?\\<case[xz]?\\>\\)"
"\\|\\(\\<endcase\\>\\)" )
nil 'move)
(cond
(setq sreg reg)
(setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
)))
- ;no nesting
+ ;; no nesting
(if (and
(verilog-re-search-backward reg nil 'move)
(match-end 1)) ; task -> could be virtual and/or protected
(let ((state (save-excursion (verilog-syntax-ppss))))
(> (nth 0 state) 0 )))
+(defun verilog-in-paren-count ()
+ "Return paren depth, floor to 0.
+May cache result using `verilog-syntax-ppss'."
+ (let ((state (save-excursion (verilog-syntax-ppss))))
+ (if (> (nth 0 state) 0)
+ (nth 0 state)
+ 0 )))
+
(defun verilog-in-paren-quick ()
"Return true if in a parenthetical expression.
Always starts from `point-min', to allow inserts with hooks disabled."
)
nil)))
+(defun verilog-in-struct-nested-p ()
+ "Return nil for not in struct.
+Return 0 for in non-nested struct.
+Return >0 for nested struct."
+ (interactive)
+ (let (col)
+ (save-excursion
+ (if (verilog-in-paren)
+ (progn
+ (verilog-backward-up-list 1)
+ (setq col (verilog-at-struct-mv-p))
+ (if col
+ (if (verilog-in-struct-p) (current-column) 0)))
+ nil))))
+
(defun verilog-in-coverage-p ()
"Return true if in a constraint or coverpoint expression."
(interactive)
"If at the } that closes a constraint or covergroup, return true."
(if (and
(equal (char-after) ?\})
- (verilog-in-paren))
+ (verilog-in-coverage-p))
(save-excursion
(verilog-backward-ws&directives)
- (if (equal (char-before) ?\;)
+ (if (or (equal (char-before) ?\;)
+ (equal (char-before) ?\}) ;; can end with inner constraint { } block or ;
+ (equal (char-before) ?\{)) ;; empty constraint block
(point)
nil))))
(forward-list)
(progn (backward-char 1)
(verilog-backward-ws&directives)
- (equal (char-before) ?\;))))
- ;; maybe
- (verilog-re-search-backward "\\<constraint\\|coverpoint\\|cross\\>" nil 'move)
+ (or (equal (char-before) ?\{) ;; empty case
+ (equal (char-before) ?\;)
+ (equal (char-before) ?\})))))
+ (progn
+ (let ( (pt (point)) (pass 0))
+ (verilog-backward-ws&directives)
+ (verilog-backward-token)
+ (if (looking-at (concat "\\<constraint\\|coverpoint\\|cross\\|with\\>\\|" verilog-in-constraint-re))
+ (progn (setq pass 1)
+ (if (looking-at "\\<with\\>")
+ (progn (verilog-backward-ws&directives)
+ (beginning-of-line) ;; 1
+ (verilog-forward-ws&directives)
+ 1 )
+ (verilog-beg-of-statement)
+ ))
+ ;; if first word token not keyword, it maybe the instance name
+ ;; check next word token
+ (if (looking-at "\\<\\w+\\>\\|\\s-*(\\s-*\\w+")
+ (progn (verilog-beg-of-statement)
+ (if (looking-at (concat "\\<\\(constraint\\|"
+ "\\(?:\\w+\\s-*:\\s-*\\)?\\(coverpoint\\|cross\\)"
+ "\\|with\\)\\>\\|" verilog-in-constraint-re))
+ (setq pass 1)))))
+ (if (eq pass 0)
+ (progn (goto-char pt) nil) 1)))
;; not
nil))
(defun verilog-at-struct-p ()
- "If at the { of a struct, return true, moving point to struct."
+ "If at the { of a struct, return true, not moving point."
(save-excursion
(if (and (equal (char-after) ?\{)
(verilog-backward-token))
(looking-at "\\<struct\\|union\\|packed\\|\\(un\\)?signed\\>")
nil)))
+(defun verilog-at-struct-mv-p ()
+ "If at the { of a struct, return true, moving point to struct."
+ (let ((pt (point)))
+ (if (and (equal (char-after) ?\{)
+ (verilog-backward-token))
+ (if (looking-at "\\<struct\\|union\\|packed\\|\\(un\\)?signed\\>")
+ (progn (verilog-beg-of-statement) (point))
+ (progn (goto-char pt) nil))
+ (progn (goto-char pt) nil))))
+
+(defun verilog-at-close-struct-p ()
+ "If at the } that closes a struct, return true."
+ (if (and
+ (equal (char-after) ?\})
+ (verilog-in-struct-p))
+ ;; true
+ (save-excursion
+ (if (looking-at "}\\(?:\\s-*\\w+\\s-*\\)?;") 1))
+ ;; false
+ nil))
+
(defun verilog-parenthesis-depth ()
"Return non zero if in parenthetical-expression."
(save-excursion (nth 1 (verilog-syntax-ppss))))
(;-- Handle the ends
(or
- (looking-at verilog-end-block-re )
- (verilog-at-close-constraint-p))
+ (looking-at verilog-end-block-re)
+ (verilog-at-close-constraint-p)
+ (verilog-at-close-struct-p))
(let ((val (if (eq type 'statement)
(- ind verilog-indent-level)
ind)))
(looking-at "\*")))
(insert "* ")))))
-(defun verilog-comment-indent (&optional arg)
+(defun verilog-comment-indent (&optional _arg)
"Return the column number the line should be indented to.
-ARG is ignored, for `comment-indent-function' compatibility."
+_ARG is ignored, for `comment-indent-function' compatibility."
(cond
((verilog-in-star-comment-p)
(save-excursion
endpos (set-marker (make-marker) end)
base-ind (progn
(goto-char start)
- (forward-char 1)
- (skip-chars-forward " \t")
- (current-column))
- )
+ (forward-char 1)
+ (skip-chars-forward " \t")
+ (current-column)))
;; in a declaration block (not in argument list)
(setq
start (progn
(forward-line 1))
(unless quiet (message "")))))))
-(defun verilog-pretty-expr (&optional quiet myre)
- "Line up expressions around point, optionally QUIET with regexp MYRE ignored."
+(defun verilog-pretty-expr (&optional quiet _myre)
+ "Line up expressions around point, optionally QUIET with regexp _MYRE ignored."
(interactive)
(if (not (verilog-in-comment-or-string-p))
(save-excursion
((b (prog2
(beginning-of-line)
(point-marker)
- (end-of-line)))
- (e (point-marker)))
+ (end-of-line))))
(if (re-search-backward " /\\* \[#-\]# \[a-zA-Z\]+ \[0-9\]+ ## \\*/" b t)
(progn
(replace-match " /* -# ## */")
(forward-line 1)))
verilog-all)
-(defun verilog-type-completion ()
- "Calculate all possible completions for types."
- (let ((start (point))
- goon)
- ;; Search for all reachable type declarations
- (while (or (verilog-beg-of-defun)
- (setq goon (not goon)))
- (save-excursion
- (if (and (< start (prog1 (save-excursion (verilog-end-of-defun)
- (point))
- (forward-char 1)))
- (verilog-re-search-forward
- "\\<type\\>\\|\\<\\(begin\\|function\\|procedure\\)\\>"
- start t)
- (not (match-end 1)))
- ;; Check current type declaration
- (verilog-get-completion-decl start))))))
-
(defun verilog-var-completion ()
"Calculate all possible completions for variables (or constants)."
(let ((start (point)))
;; Return nil if there was no matching label
nil
;; Get longest string common in the labels
+ ;; FIXME: Why not use `try-completion'?
(let* ((elm (cdr verilog-all))
(match (car verilog-all))
(min (length match))
"Complete word at current point.
\(See also `verilog-toggle-completions', `verilog-type-keywords',
and `verilog-separator-keywords'.)"
+ ;; FIXME: Provide completion-at-point-function.
(interactive)
(let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
(e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
(list name bits comment mem enum signed type multidim modport))
(defsubst verilog-sig-name (sig)
(car sig))
-(defsubst verilog-sig-bits (sig)
+(defsubst verilog-sig-bits (sig) ;; First element of packed array (pre signal-name)
(nth 1 sig))
(defsubst verilog-sig-comment (sig)
(nth 2 sig))
-(defsubst verilog-sig-memory (sig)
+(defsubst verilog-sig-memory (sig) ;; Unpacked array (post signal-name)
(nth 3 sig))
(defsubst verilog-sig-enum (sig)
(nth 4 sig))
(nth 6 sig))
(defsubst verilog-sig-type-set (sig type)
(setcar (nthcdr 6 sig) type))
-(defsubst verilog-sig-multidim (sig)
+(defsubst verilog-sig-multidim (sig) ;; Second and additional elements of packed array
(nth 7 sig))
(defsubst verilog-sig-multidim-string (sig)
(if (verilog-sig-multidim sig)
(defsubst verilog-alw-get-uses-delayed (sigs)
(aref sigs 0))
+(defsubst verilog-modport-new (name clockings decls)
+ (list name clockings decls))
+(defsubst verilog-modport-name (sig)
+ (car sig))
+(defsubst verilog-modport-clockings (sig)
+ (nth 1 sig)) ;; Returns list of names
+(defsubst verilog-modport-clockings-add (sig val)
+ (setcar (nthcdr 1 sig) (cons val (nth 1 sig))))
+(defsubst verilog-modport-decls (sig)
+ (nth 2 sig)) ;; Returns verilog-decls-* structure
+(defsubst verilog-modport-decls-set (sig val)
+ (setcar (nthcdr 2 sig) val))
+
(defsubst verilog-modi-new (name fob pt type)
(vector name fob pt type))
(defsubst verilog-modi-name (modi)
;; Signal reading for given module
;; Note these all take modi's - as returned from verilog-modi-current
-(defsubst verilog-decls-new (out inout in vars unuseds assigns consts gparams interfaces)
- (vector out inout in vars unuseds assigns consts gparams interfaces))
+(defsubst verilog-decls-new (out inout in vars modports assigns consts gparams interfaces)
+ (vector out inout in vars modports assigns consts gparams interfaces))
+(defsubst verilog-decls-append (a b)
+ (cond ((not a) b) ((not b) a)
+ (t (vector (append (aref a 0) (aref b 0)) (append (aref a 1) (aref b 1))
+ (append (aref a 2) (aref b 2)) (append (aref a 3) (aref b 3))
+ (append (aref a 4) (aref b 4)) (append (aref a 5) (aref b 5))
+ (append (aref a 6) (aref b 6)) (append (aref a 7) (aref b 7))
+ (append (aref a 8) (aref b 8))))))
(defsubst verilog-decls-get-outputs (decls)
(aref decls 0))
(defsubst verilog-decls-get-inouts (decls)
(aref decls 2))
(defsubst verilog-decls-get-vars (decls)
(aref decls 3))
-;;(defsubst verilog-decls-get-unused (decls)
-;; (aref decls 4))
+(defsubst verilog-decls-get-modports (decls) ;; Also for clocking blocks; contains another verilog-decls struct
+ (aref decls 4)) ;; Returns verilog-modport* structure
(defsubst verilog-decls-get-assigns (decls)
(aref decls 5))
(defsubst verilog-decls-get-consts (decls)
(defsubst verilog-decls-get-interfaces (decls)
(aref decls 8))
+
(defsubst verilog-subdecls-new (out inout in intf intfd)
(vector out inout in intf intfd))
(defsubst verilog-subdecls-get-outputs (subdecls)
(mapcar (lambda (name) (verilog-sig-new name nil nil nil nil nil nil nil nil))
signame-list))
+(defun verilog-signals-in (in-list not-list)
+ "Return list of signals in IN-LIST that are also in NOT-LIST.
+Also remove any duplicates in IN-LIST.
+Signals must be in standard (base vector) form."
+ ;; This function is hot, so implemented as O(1)
+ (cond ((eval-when-compile (fboundp 'make-hash-table))
+ (let ((ht (make-hash-table :test 'equal :rehash-size 4.0))
+ (ht-not (make-hash-table :test 'equal :rehash-size 4.0))
+ out-list)
+ (while not-list
+ (puthash (car (car not-list)) t ht-not)
+ (setq not-list (cdr not-list)))
+ (while in-list
+ (when (and (gethash (verilog-sig-name (car in-list)) ht-not)
+ (not (gethash (verilog-sig-name (car in-list)) ht)))
+ (setq out-list (cons (car in-list) out-list))
+ (puthash (verilog-sig-name (car in-list)) t ht))
+ (setq in-list (cdr in-list)))
+ (nreverse out-list)))
+ ;; Slower Fallback if no hash tables (pre Emacs 21.1/XEmacs 21.4)
+ (t
+ (let (out-list)
+ (while in-list
+ (if (and (assoc (verilog-sig-name (car in-list)) not-list)
+ (not (assoc (verilog-sig-name (car in-list)) out-list)))
+ (setq out-list (cons (car in-list) out-list)))
+ (setq in-list (cdr in-list)))
+ (nreverse out-list)))))
+;;(verilog-signals-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("C" "")))
+
(defun verilog-signals-not-in (in-list not-list)
"Return list of signals in IN-LIST that aren't also in NOT-LIST.
Also remove any duplicates in IN-LIST.
(t
(let (out-list)
(while in-list
- (if (not (or (assoc (verilog-sig-name (car in-list)) not-list)
- (assoc (verilog-sig-name (car in-list)) out-list)))
+ (if (and (not (assoc (verilog-sig-name (car in-list)) not-list))
+ (not (assoc (verilog-sig-name (car in-list)) out-list)))
(setq out-list (cons (car in-list) out-list)))
(setq in-list (cdr in-list)))
(nreverse out-list)))))
"Return list of signals in IN-LIST that aren't parameters or numeric constants."
(let (out-list)
(while in-list
+ ;; Namespace intentionally short for AUTOs and compatibility
(unless (boundp (intern (concat "vh-" (verilog-sig-name (car in-list)))))
(setq out-list (cons (car in-list) out-list)))
(setq in-list (cdr in-list)))
(nreverse out-list)))
(defun verilog-signals-with (func in-list)
- "Return IN-LIST with only signals where FUNC passed each signal is true."
+ "Return list of signals where FUNC is true executed on each signal in IN-LIST."
(let (out-list)
(while in-list
(when (funcall func (car in-list))
`verilog-auto-reset-widths'."
(concat
(if (and verilog-active-low-regexp
- (string-match verilog-active-low-regexp (verilog-sig-name sig)))
+ (verilog-string-match-fold verilog-active-low-regexp (verilog-sig-name sig)))
"~" "")
(cond ((not verilog-auto-reset-widths)
"0")
;; Else presume verilog-auto-reset-widths is true
(t
(let* ((width (verilog-sig-width sig)))
- (if (string-match "^[0-9]+$" width)
- (concat width (if (verilog-sig-signed sig) "'sh0" "'h0"))
- (concat "{" width "{1'b0}}")))))))
+ (cond ((not width)
+ "`0/*NOWIDTH*/")
+ ((string-match "^[0-9]+$" width)
+ (concat width (if (verilog-sig-signed sig) "'sh0" "'h0")))
+ (t
+ (concat "{" width "{1'b0}}"))))))))
;;
;; Dumping
;;
-(defun verilog-decls-princ (decls)
+(defun verilog-decls-princ (decls &optional header prefix)
"For debug, dump the `verilog-read-decls' structure DECLS."
- (verilog-signals-princ (verilog-decls-get-outputs decls)
- "Outputs:\n" " ")
- (verilog-signals-princ (verilog-decls-get-inouts decls)
- "Inout:\n" " ")
- (verilog-signals-princ (verilog-decls-get-inputs decls)
- "Inputs:\n" " ")
- (verilog-signals-princ (verilog-decls-get-vars decls)
- "Vars:\n" " ")
- (verilog-signals-princ (verilog-decls-get-assigns decls)
- "Assigns:\n" " ")
- (verilog-signals-princ (verilog-decls-get-consts decls)
- "Consts:\n" " ")
- (verilog-signals-princ (verilog-decls-get-gparams decls)
- "Gparams:\n" " ")
- (verilog-signals-princ (verilog-decls-get-interfaces decls)
- "Interfaces:\n" " ")
- (princ "\n"))
+ (when decls
+ (if header (princ header))
+ (setq prefix (or prefix ""))
+ (verilog-signals-princ (verilog-decls-get-outputs decls)
+ (concat prefix "Outputs:\n") (concat prefix " "))
+ (verilog-signals-princ (verilog-decls-get-inouts decls)
+ (concat prefix "Inout:\n") (concat prefix " "))
+ (verilog-signals-princ (verilog-decls-get-inputs decls)
+ (concat prefix "Inputs:\n") (concat prefix " "))
+ (verilog-signals-princ (verilog-decls-get-vars decls)
+ (concat prefix "Vars:\n") (concat prefix " "))
+ (verilog-signals-princ (verilog-decls-get-assigns decls)
+ (concat prefix "Assigns:\n") (concat prefix " "))
+ (verilog-signals-princ (verilog-decls-get-consts decls)
+ (concat prefix "Consts:\n") (concat prefix " "))
+ (verilog-signals-princ (verilog-decls-get-gparams decls)
+ (concat prefix "Gparams:\n") (concat prefix " "))
+ (verilog-signals-princ (verilog-decls-get-interfaces decls)
+ (concat prefix "Interfaces:\n") (concat prefix " "))
+ (verilog-modport-princ (verilog-decls-get-modports decls)
+ (concat prefix "Modports:\n") (concat prefix " "))
+ (princ "\n")))
(defun verilog-signals-princ (signals &optional header prefix)
"For debug, dump internal SIGNALS structures, with HEADER and PREFIX."
(when signals
- (princ header)
+ (if header (princ header))
(while signals
(let ((sig (car signals)))
(setq signals (cdr signals))
(princ " modp=") (princ (verilog-sig-modport sig))
(princ "\n")))))
+(defun verilog-modport-princ (modports &optional header prefix)
+ "For debug, dump internal MODPORT structures, with HEADER and PREFIX."
+ (when modports
+ (if header (princ header))
+ (while modports
+ (let ((sig (car modports)))
+ (setq modports (cdr modports))
+ (princ prefix)
+ (princ "\"") (princ (verilog-modport-name sig)) (princ "\"")
+ (princ " clockings=") (princ (verilog-modport-clockings sig))
+ (princ "\n")
+ (verilog-decls-princ (verilog-modport-decls sig)
+ (concat prefix " syms:\n")
+ (concat prefix " "))))))
+
;;
;; Port/Wire/Etc Reading
;;
(verilog-backward-open-paren)
(verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil))
(skip-chars-backward "a-zA-Z0-9'_$")
+ ;; #1 is legal syntax for gate primitives
+ (when (save-excursion
+ (verilog-backward-syntactic-ws-quick)
+ (eq ?# (char-before)))
+ (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil)
+ (skip-chars-backward "a-zA-Z0-9'_$"))
(looking-at "[a-zA-Z0-9`_\$]+")
;; Important: don't use match string, this must work with Emacs 19 font-lock on
(buffer-substring-no-properties (match-beginning 0) (match-end 0))
(defun verilog-read-decls ()
"Compute signal declaration information for the current module at point.
Return an array of [outputs inouts inputs wire reg assign const]."
- (let ((end-mod-point (or (verilog-get-end-of-defun t) (point-max)))
+ (let ((end-mod-point (or (verilog-get-end-of-defun) (point-max)))
(functask 0) (paren 0) (sig-paren 0) (v2kargs-ok t)
- in-modport ptype ign-prop
+ in-modport in-clocking in-ign-to-semi ptype ign-prop
sigs-in sigs-out sigs-inout sigs-var sigs-assign sigs-const
- sigs-gparam sigs-intf
+ sigs-gparam sigs-intf sigs-modports
vec expect-signal keywd newsig rvalue enum io signed typedefed multidim
- modport)
+ modport
+ varstack tmp)
+ ;;(if dbg (setq dbg (concat dbg (format "\n\nverilog-read-decls START PT %s END %s\n" (point) end-mod-point))))
(save-excursion
(verilog-beg-of-defun-quick)
(setq sigs-const (verilog-read-auto-constants (point) end-mod-point))
(or (re-search-forward "[^\\]\"" nil t) ;; don't forward-char first, since we look for a non backslash first
(error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
((eq ?\; (following-char))
- (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil
- v2kargs-ok nil in-modport nil ign-prop nil)
+ (cond (in-ign-to-semi ;; Such as inside a "import ...;" in a module header
+ (setq in-ign-to-semi nil))
+ ((and in-modport (not (eq in-modport t))) ;; end of a modport declaration
+ (verilog-modport-decls-set
+ in-modport
+ (verilog-decls-new sigs-out sigs-inout sigs-in
+ nil nil nil nil nil nil))
+ ;; Pop from varstack to restore state to pre-clocking
+ (setq tmp (car varstack)
+ varstack (cdr varstack)
+ sigs-out (aref tmp 0)
+ sigs-inout (aref tmp 1)
+ sigs-in (aref tmp 2))
+ (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil
+ v2kargs-ok nil in-modport nil ign-prop nil))
+ (t
+ (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil
+ v2kargs-ok nil in-modport nil ign-prop nil)))
(forward-char 1))
((eq ?= (following-char))
(setq rvalue t newsig nil)
(setq paren (1- paren))
(forward-char 1)
(when (< paren sig-paren)
- (setq expect-signal nil))) ; ) that ends variables inside v2k arg list
+ (setq expect-signal nil rvalue nil))) ; ) that ends variables inside v2k arg list
((looking-at "\\s-*\\(\\[[^]]+\\]\\)")
(goto-char (match-end 0))
(cond (newsig ; Memory, not just width. Patch last signal added's memory (nth 3)
(setq signed keywd))
((member keywd '("assert" "assume" "cover" "expect" "restrict"))
(setq ign-prop t))
- ((member keywd '("class" "clocking" "covergroup" "function"
+ ((member keywd '("class" "covergroup" "function"
"property" "randsequence" "sequence" "task"))
(unless ign-prop
(setq functask (1+ functask))))
- ((member keywd '("endclass" "endclocking" "endgroup" "endfunction"
+ ((member keywd '("endclass" "endgroup" "endfunction"
"endproperty" "endsequence" "endtask"))
(setq functask (1- functask)))
((equal keywd "modport")
(setq in-modport t))
+ ((equal keywd "clocking")
+ (setq in-clocking t))
+ ((equal keywd "import")
+ (if v2kargs-ok ;; import in module header, not a modport import
+ (setq in-ign-to-semi t rvalue t)))
((equal keywd "type")
(setq ptype t))
+ ((equal keywd "var"))
;; Ifdef? Ignore name of define
((member keywd '("`ifdef" "`ifndef" "`elsif"))
(setq rvalue t))
;; Type?
((unless ptype
(verilog-typedef-name-p keywd))
- (setq typedefed keywd))
+ (cond (io
+ (setq typedefed
+ (if typedefed (concat typedefed " " keywd) keywd)))
+ (t (setq vec nil enum nil rvalue nil signed nil
+ typedefed nil multidim nil sig-paren paren
+ expect-signal 'sigs-var modport nil))))
;; Interface with optional modport in v2k arglist?
;; Skip over parsing modport, and take the interface name as the type
((and v2kargs-ok
(goto-char (match-end 0))
(when (not rvalue)
(setq expect-signal nil)))
+ ;; "modport <keywd>"
+ ((and (eq in-modport t)
+ (not (member keywd verilog-keywords)))
+ (setq in-modport (verilog-modport-new keywd nil nil))
+ (setq sigs-modports (cons in-modport sigs-modports))
+ ;; Push old sig values to stack and point to new signal list
+ (setq varstack (cons (vector sigs-out sigs-inout sigs-in)
+ varstack))
+ (setq sigs-in nil sigs-inout nil sigs-out nil))
+ ;; "modport x (clocking <keywd>)"
+ ((and in-modport in-clocking)
+ (verilog-modport-clockings-add in-modport keywd)
+ (setq in-clocking nil))
+ ;; endclocking
+ ((and in-clocking
+ (equal keywd "endclocking"))
+ (unless (eq in-clocking t)
+ (verilog-modport-decls-set
+ in-clocking
+ (verilog-decls-new sigs-out sigs-inout sigs-in
+ nil nil nil nil nil nil))
+ ;; Pop from varstack to restore state to pre-clocking
+ (setq tmp (car varstack)
+ varstack (cdr varstack)
+ sigs-out (aref tmp 0)
+ sigs-inout (aref tmp 1)
+ sigs-in (aref tmp 2)))
+ (setq in-clocking nil))
+ ;; "clocking <keywd>"
+ ((and (eq in-clocking t)
+ (not (member keywd verilog-keywords)))
+ (setq in-clocking (verilog-modport-new keywd nil nil))
+ (setq sigs-modports (cons in-clocking sigs-modports))
+ ;; Push old sig values to stack and point to new signal list
+ (setq varstack (cons (vector sigs-out sigs-inout sigs-in)
+ varstack))
+ (setq sigs-in nil sigs-inout nil sigs-out nil))
;; New signal, maybe?
((and expect-signal
(not rvalue)
(eq functask 0)
- (not in-modport)
(not (member keywd verilog-keywords)))
;; Add new signal to expect-signal's variable
+ ;;(if dbg (setq dbg (concat dbg (format "Pt %s New sig %s'\n" (point) keywd))))
(setq newsig (verilog-sig-new keywd vec nil nil enum signed typedefed multidim modport))
(set expect-signal (cons newsig
(symbol-value expect-signal))))))
(forward-char 1)))
(skip-syntax-forward " "))
;; Return arguments
- (verilog-decls-new (nreverse sigs-out)
- (nreverse sigs-inout)
- (nreverse sigs-in)
- (nreverse sigs-var)
- nil
- (nreverse sigs-assign)
- (nreverse sigs-const)
- (nreverse sigs-gparam)
- (nreverse sigs-intf)))))
+ (setq tmp (verilog-decls-new (nreverse sigs-out)
+ (nreverse sigs-inout)
+ (nreverse sigs-in)
+ (nreverse sigs-var)
+ (nreverse sigs-modports)
+ (nreverse sigs-assign)
+ (nreverse sigs-const)
+ (nreverse sigs-gparam)
+ (nreverse sigs-intf)))
+ ;;(if dbg (verilog-decls-princ tmp))
+ tmp)))
(defvar verilog-read-sub-decls-in-interfaced nil
"For `verilog-read-sub-decls', process next signal as under interfaced block.")
;; - we want an error when we are debugging this code if they are refed.
(defvar sigs-in)
(defvar sigs-inout)
- (defvar sigs-out)
(defvar sigs-intf)
- (defvar sigs-intfd))
+ (defvar sigs-intfd)
+ (defvar sigs-out)
+ (defvar sigs-out-d)
+ (defvar sigs-out-i)
+ (defvar sigs-out-unk)
+ (defvar sigs-temp)
+ ;; These are known to be from other packages and may not be defined
+ (defvar diff-command nil)
+ (defvar vector-skip-list)
+ ;; There are known to be from newer versions of Emacs
+ (defvar create-lockfiles))
(defun verilog-read-sub-decls-sig (submoddecls comment port sig vec multidim)
"For `verilog-read-sub-decls-line', add a signal."
// Inputs
.in (in));"
(save-excursion
- (let ((end-mod-point (verilog-get-end-of-defun t))
+ (let ((end-mod-point (verilog-get-end-of-defun))
st-point end-inst-point
;; below 3 modified by verilog-read-sub-decls-line
sigs-out sigs-inout sigs-in sigs-intf sigs-intfd)
(subprim (member submod verilog-gate-keywords))
(comment (concat inst " of " submod ".v"))
submodi submoddecls)
- (cond
+ (cond
(subprim
(setq submodi `primitive
submoddecls (verilog-decls-new nil nil nil nil nil nil nil nil nil)
(verilog-in-hooks t))
(eval-region beg-pt end-pt nil))))))
-(eval-when-compile
- ;; Prevent compile warnings; these are let's, not globals
- ;; Do not remove the eval-when-compile
- ;; - we want an error when we are debugging this code if they are refed.
- (defvar sigs-in)
- (defvar sigs-out-d)
- (defvar sigs-out-i)
- (defvar sigs-out-unk)
- (defvar sigs-temp)
- (defvar vector-skip-list))
-
(defun verilog-read-always-signals-recurse
(exit-keywd rvalue temp-next)
"Recursive routine for parentheses/bracket matching.
(defun verilog-read-instants ()
"Parse module at point and return list of ( ( file instance ) ... )."
(verilog-beg-of-defun-quick)
- (let* ((end-mod-point (verilog-get-end-of-defun t))
+ (let* ((end-mod-point (verilog-get-end-of-defun))
(state nil)
(instants-list nil))
(save-excursion
"Set the definition DEFNAME to the DEFVALUE in the given BUFFER.
Optionally associate it with the specified enumeration ENUMNAME."
(with-current-buffer (or buffer (current-buffer))
+ ;; Namespace intentionally short for AUTOs and compatibility
(let ((mac (intern (concat "vh-" defname))))
;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
;; Need to define to a constant if no value given
(set (make-local-variable mac)
(if (equal defvalue "") "1" defvalue)))
(if enumname
+ ;; Namespace intentionally short for AUTOs and compatibility
(let ((enumvar (intern (concat "venum-" enumname))))
;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
(unless (boundp enumvar) (set enumvar nil))
\\[find-alternate-file] RET to have these take effect after editing them!
If you want to disable the \"Process `eval' or hook local variables\"
-warning message, you need to add to your .emacs file:
+warning message, you need to add to your init file:
(setq enable-local-eval t)"
(let ((origbuf (current-buffer)))
(while (re-search-forward "^\\s-*`define\\s-+\\([a-zA-Z0-9_$]+\\)\\s-+\\(.*\\)$" nil t)
(let ((defname (match-string-no-properties 1))
(defvalue (match-string-no-properties 2)))
- (setq defvalue (verilog-string-replace-matches "\\s-*/[/*].*$" "" nil nil defvalue))
- (verilog-set-define defname defvalue origbuf)))
+ (unless (verilog-inside-comment-or-string-p (match-beginning 0))
+ (setq defvalue (verilog-string-replace-matches "\\s-*/[/*].*$" "" nil nil defvalue))
+ (verilog-set-define defname defvalue origbuf))))
;; Hack: Read parameters
(goto-char (point-min))
(while (re-search-forward
(forward-comment 99999)
(while (looking-at (concat "\\s-*,?\\s-*\\(?:/[/*].*?$\\)?\\s-*\\([a-zA-Z0-9_$]+\\)"
"\\s-*=\\s-*\\([^;,]*\\),?\\s-*\\(/[/*].*?$\\)?\\s-*"))
- (verilog-set-define (match-string-no-properties 1)
- (match-string-no-properties 2) origbuf enumname)
+ (unless (verilog-inside-comment-or-string-p (match-beginning 0))
+ (verilog-set-define (match-string-no-properties 1)
+ (match-string-no-properties 2) origbuf enumname))
(goto-char (match-end 0))
(forward-comment 99999)))))))
`define _FOO_V
... contents of file
`endif // _FOO_V"
-;;slow: (verilog-read-defines nil t))
+ ;;slow: (verilog-read-defines nil t)
(save-excursion
(verilog-getopt-flags)
(goto-char (point-min))
;;
(defvar verilog-dir-cache-preserving nil
- "If set, the directory cache is enabled, and file system changes are ignored.
+ "If true, the directory cache is enabled, and file system changes are ignored.
See `verilog-dir-exists-p' and `verilog-dir-files'.")
;; If adding new cached variable, add also to verilog-preserve-dir-cache
(while (and symbol (string-match "^`" symbol))
(setq symbol (substring symbol 1))
(setq symbol
+ ;; Namespace intentionally short for AUTOs and compatibility
(if (boundp (intern (concat "vh-" symbol)))
;; Emacs has a bug where boundp on a buffer-local
;; variable in only one buffer returns t in another.
;; This can confuse, so check for nil.
+ ;; Namespace intentionally short for AUTOs and compatibility
(let ((val (eval (intern (concat "vh-" symbol)))))
(if (eq val nil)
(if wing-it symbol nil)
(setq symbol (match-string 1 text))
;;(message symbol)
(cond ((and
+ ;; Namespace intentionally short for AUTOs and compatibility
(boundp (intern (concat "vh-" symbol)))
;; Emacs has a bug where boundp on a buffer-local
;; variable in only one buffer returns t in another.
;; This can confuse, so check for nil.
+ ;; Namespace intentionally short for AUTOs and compatibility
(setq val (eval (intern (concat "vh-" symbol)))))
(setq text (replace-match val nil nil text)))
(t (setq ok nil)))))
(setq outlist (cons (expand-file-name
fn (file-name-directory current))
outlist)))
- (setq chkexts (cdr chkexts)))
+ (setq chkexts (cdr chkexts)))
(setq chkdirs (cdr chkdirs)))
(setq outlist (nreverse outlist))
(setq verilog-dir-cache-lib-filenames
;;(message "verilog-modi-lookup: HIT %S" modi)
modi)
;; Miss
- (t (let* ((realmod (verilog-symbol-detick module t))
- (orig-filenames (verilog-module-filenames realmod current))
+ (t (let* ((realname (verilog-symbol-detick module t))
+ (orig-filenames (verilog-module-filenames realname current))
(filenames orig-filenames)
mif)
(while (and filenames (not mif))
- (if (not (setq mif (verilog-module-inside-filename-p realmod (car filenames))))
+ (if (not (setq mif (verilog-module-inside-filename-p realname (car filenames))))
(setq filenames (cdr filenames))))
;; mif has correct form to become later elements of modi
(cond (mif (setq modi mif))
(or ignore-error
(error (concat (verilog-point-text)
": Can't locate " module " module definition"
- (if (not (equal module realmod))
- (concat " (Expanded macro to " realmod ")")
+ (if (not (equal module realname))
+ (concat " (Expanded macro to " realname ")")
"")
"\n Check the verilog-library-directories variable."
"\n I looked in (if not listed, doesn't exist):\n\t"
(progn ,@body)))
+(defun verilog-modi-modport-lookup-one (modi name &optional ignore-error)
+ "Given a MODI, return the declarations related to the given modport NAME."
+ ;; Recursive routine - see below
+ (let* ((realname (verilog-symbol-detick name t))
+ (modport (assoc name (verilog-decls-get-modports (verilog-modi-get-decls modi)))))
+ (or modport ignore-error
+ (error (concat (verilog-point-text)
+ ": Can't locate " name " modport definition"
+ (if (not (equal name realname))
+ (concat " (Expanded macro to " realname ")")
+ ""))))
+ (let* ((decls (verilog-modport-decls modport))
+ (clks (verilog-modport-clockings modport)))
+ ;; Now expand any clocking's
+ (while clks
+ (setq decls (verilog-decls-append
+ decls
+ (verilog-modi-modport-lookup-one modi (car clks) ignore-error)))
+ (setq clks (cdr clks)))
+ decls)))
+
+(defun verilog-modi-modport-lookup (modi name-re &optional ignore-error)
+ "Given a MODI, return the declarations related to the given modport NAME-RE.
+If the modport points to any clocking blocks, expand the signals to include
+those clocking block's signals."
+ ;; Recursive routine - see below
+ (let* ((mod-decls (verilog-modi-get-decls modi))
+ (clks (verilog-decls-get-modports mod-decls))
+ (name-re (concat "^" name-re "$"))
+ (decls (verilog-decls-new nil nil nil nil nil nil nil nil nil)))
+ ;; Pull in all modports
+ (while clks
+ (when (string-match name-re (verilog-modport-name (car clks)))
+ (setq decls (verilog-decls-append
+ decls
+ (verilog-modi-modport-lookup-one modi (verilog-modport-name (car clks)) ignore-error))))
+ (setq clks (cdr clks)))
+ decls))
+
(defun verilog-signals-matching-enum (in-list enum)
"Return all signals in IN-LIST matching the given ENUM."
(let (out-list)
(setq out-list (cons (car in-list) out-list)))
(setq in-list (cdr in-list)))
;; New scheme
+ ;; Namespace intentionally short for AUTOs and compatibility
(let* ((enumvar (intern (concat "venum-" enum)))
(enumlist (and (boundp enumvar) (eval enumvar))))
(while enumlist
"Return all signals in IN-LIST matching the given REGEXP, if non-nil."
(if (or (not regexp) (equal regexp ""))
in-list
- (let (out-list)
+ (let ((case-fold-search verilog-case-fold)
+ out-list)
(while in-list
(if (string-match regexp (verilog-sig-name (car in-list)))
(setq out-list (cons (car in-list) out-list)))
"Return all signals in IN-LIST not matching the given REGEXP, if non-nil."
(if (or (not regexp) (equal regexp ""))
in-list
- (let (out-list)
+ (let ((case-fold-search verilog-case-fold)
+ out-list)
(while in-list
(if (not (string-match regexp (verilog-sig-name (car in-list))))
(setq out-list (cons (car in-list) out-list)))
(verilog-decls-get-inouts decls)
(verilog-decls-get-inputs decls)))
+(defun verilog-decls-get-iovars (decls)
+ (append
+ (verilog-decls-get-vars decls)
+ (verilog-decls-get-outputs decls)
+ (verilog-decls-get-inouts decls)
+ (verilog-decls-get-inputs decls)))
+
(defsubst verilog-modi-cache-add-outputs (modi sig-list)
(verilog-modi-cache-add modi 'verilog-read-decls 0 sig-list))
(defsubst verilog-modi-cache-add-inouts (modi sig-list)
(verilog-modi-cache-add modi 'verilog-read-decls 2 sig-list))
(defsubst verilog-modi-cache-add-vars (modi sig-list)
(verilog-modi-cache-add modi 'verilog-read-decls 3 sig-list))
+(defsubst verilog-modi-cache-add-gparams (modi sig-list)
+ (verilog-modi-cache-add modi 'verilog-read-decls 7 sig-list))
\f
;;
(when verilog-auto-declare-nettype
(verilog-modi-cache-add-vars modi sigs)))
((equal direction "interface"))
+ ((equal direction "parameter")
+ (verilog-modi-cache-add-gparams modi sigs))
(t
(error "Unsupported verilog-insert-definition direction: %s" direction))))
(or dont-sort
stuff (cdr stuff)))))
;;(let ((indent-pt 10)) (verilog-insert-indent "hello\n" "addon" "there\n"))
+(defun verilog-forward-or-insert-line ()
+ "Move forward a line, unless at EOB, then insert a newline."
+ (if (eobp) (insert "\n")
+ (forward-line)))
+
(defun verilog-repair-open-comma ()
"Insert comma if previous argument is other than an open parenthesis or endif."
;; We can't just search backward for ) as it might be inside another expression.
(when (looking-at ",")
(delete-char 1))))
-(defun verilog-get-list (start end)
- "Return the elements of a comma separated list between START and END."
- (interactive)
- (let ((my-list (list))
- my-string)
- (save-excursion
- (while (< (point) end)
- (when (re-search-forward "\\([^,{]+\\)" end t)
- (setq my-string (verilog-string-remove-spaces (match-string 1)))
- (setq my-list (nconc my-list (list my-string) ))
- (goto-char (match-end 0))))
- my-list)))
-
(defun verilog-make-width-expression (range-exp)
"Return an expression calculating the length of a range [x:y] in RANGE-EXP."
;; strip off the []
"\\([])}:*+-]\\)")
out)
(setq out (replace-match "\\1\\2\\3" nil nil out)))
+ (while (string-match
+ (concat "\\([[({:*+-]\\)" ; - must be last
+ "\\$clog2\\s *(\\<\\([0-9]+\\))"
+ "\\([])}:*+-]\\)")
+ out)
+ (setq out (replace-match
+ (concat
+ (match-string 1 out)
+ (int-to-string (verilog-clog2 (string-to-number (match-string 2 out))))
+ (match-string 3 out))
+ nil nil out)))
;; For precedence do * before +/-
(while (string-match
(concat "\\([[({:*+-]\\)"
post)
nil nil out)) )))
out)))
+
;;(verilog-simplify-range-expression "[1:3]") ;; 1
;;(verilog-simplify-range-expression "[(1):3]") ;; 1
;;(verilog-simplify-range-expression "[(((16)+1)+1+(1+1))]") ;;20
;;(verilog-simplify-range-expression "[(FOO*4+1-1)]") ;; FOO*4+0
;;(verilog-simplify-range-expression "[(func(BAR))]") ;; func(BAR)
;;(verilog-simplify-range-expression "[FOO-1+1-1+1]") ;; FOO-0
+;;(verilog-simplify-range-expression "[$clog2(2)]") ;; 1
+;;(verilog-simplify-range-expression "[$clog2(7)]") ;; 3
+
+(defun verilog-clog2 (value)
+ "Compute $clog2 - ceiling log2 of VALUE."
+ (if (< value 1)
+ 0
+ (ceiling (/ (log value) (log 2)))))
(defun verilog-typedef-name-p (variable-name)
"Return true if the VARIABLE-NAME is a type definition."
(when verilog-typedef-regexp
- (string-match verilog-typedef-regexp variable-name)))
+ (verilog-string-match-fold verilog-typedef-regexp variable-name)))
\f
;;
;; Auto deletion
(let ((name1 (with-current-buffer b1 (buffer-file-name))))
(verilog-warn "%s:%d: Difference in AUTO expansion found"
name1 (with-current-buffer b1
- (1+ (count-lines (point-min) (point)))))
+ (count-lines (point-min) diffpt)))
(cond (noninteractive
(verilog-diff-file-with-buffer name1 b2 t t))
(t
(defun verilog-diff-auto ()
"Expand AUTOs in a temporary buffer and indicate any change.
-Whitespace differences are ignored to determine identicalness, but
-once a difference is detected, whitespace differences may be shown.
+Whitespace is ignored when detecting differences, but once a
+difference is detected, whitespace differences may be shown.
To call this from the command line, see \\[verilog-batch-diff-auto].
(insert "\n"))
(indent-to verilog-indent-level-declaration))))
-(defun verilog-auto-inst-port-map (port-st)
+(defun verilog-auto-assign-modport ()
+ "Expand AUTOASSIGNMODPORT statements, as part of \\[verilog-auto].
+Take input/output/inout statements from the specified interface
+and modport and use to build assignments into the modport, for
+making verification modules that connect to UVM interfaces.
+
+ The first parameter is the name of an interface.
+
+ The second parameter is a regexp of modports to read from in
+ that interface.
+
+ The third parameter is the instance name to use to dot reference into.
+
+ The optional fourth parameter is a regular expression, and only
+ signals matching the regular expression will be included.
+
+Limitations:
+
+ Interface names must be resolvable to filenames. See `verilog-auto-inst'.
+
+ Inouts are not supported, as assignments must be unidirectional.
+
+ If a signal is part of the interface header and in both a
+ modport and the interface itself, it will not be listed. (As
+ this would result in a syntax error when the connections are
+ made.)
+
+See the example in `verilog-auto-inout-modport'."
+ (save-excursion
+ (let* ((params (verilog-read-auto-params 3 4))
+ (submod (nth 0 params))
+ (modport-re (nth 1 params))
+ (inst-name (nth 2 params))
+ (regexp (nth 3 params))
+ direction-re submodi) ;; direction argument not supported until requested
+ ;; Lookup position, etc of co-module
+ ;; Note this may raise an error
+ (when (setq submodi (verilog-modi-lookup submod t))
+ (let* ((indent-pt (current-indentation))
+ (submoddecls (verilog-modi-get-decls submodi))
+ (submodportdecls (verilog-modi-modport-lookup submodi modport-re))
+ (sig-list-i (verilog-signals-in ;; Decls doesn't have data types, must resolve
+ (verilog-decls-get-vars submoddecls)
+ (verilog-signals-not-in
+ (verilog-decls-get-inputs submodportdecls)
+ (verilog-decls-get-ports submoddecls))))
+ (sig-list-o (verilog-signals-in ;; Decls doesn't have data types, must resolve
+ (verilog-decls-get-vars submoddecls)
+ (verilog-signals-not-in
+ (verilog-decls-get-outputs submodportdecls)
+ (verilog-decls-get-ports submoddecls)))))
+ (forward-line 1)
+ (setq sig-list-i (verilog-signals-edit-wire-reg
+ (verilog-signals-matching-dir-re
+ (verilog-signals-matching-regexp sig-list-i regexp)
+ "input" direction-re))
+ sig-list-o (verilog-signals-edit-wire-reg
+ (verilog-signals-matching-dir-re
+ (verilog-signals-matching-regexp sig-list-o regexp)
+ "output" direction-re)))
+ (setq sig-list-i (sort (copy-alist sig-list-i) `verilog-signals-sort-compare))
+ (setq sig-list-o (sort (copy-alist sig-list-o) `verilog-signals-sort-compare))
+ (when (or sig-list-i sig-list-o)
+ (verilog-insert-indent "// Beginning of automatic assignments from modport\n")
+ ;; Don't sort them so an upper AUTOINST will match the main module
+ (let ((sigs sig-list-o))
+ (while sigs
+ (verilog-insert-indent "assign " (verilog-sig-name (car sigs))
+ " = " inst-name
+ "." (verilog-sig-name (car sigs)) ";\n")
+ (setq sigs (cdr sigs))))
+ (let ((sigs sig-list-i))
+ (while sigs
+ (verilog-insert-indent "assign " inst-name
+ "." (verilog-sig-name (car sigs))
+ " = " (verilog-sig-name (car sigs)) ";\n")
+ (setq sigs (cdr sigs))))
+ (verilog-insert-indent "// End of automatics\n")))))))
+
+(defun verilog-auto-inst-port-map (_port-st)
nil)
(defvar vl-cell-type nil "See `verilog-auto-inst'.") ; Prevent compile warning
""))
(case-fold-search nil)
(check-values par-values)
- tpl-net)
+ tpl-net dflt-bits)
;; Replace parameters in bit-width
(when (and check-values
(not (equal vl-bits "")))
vl-mbits (verilog-simplify-range-expression vl-mbits)
vl-width (verilog-make-width-expression vl-bits))) ; Not in the loop for speed
;; Default net value if not found
- (setq tpl-net (concat port
+ (setq dflt-bits (if (and (verilog-sig-bits port-st)
+ (or (verilog-sig-multidim port-st)
+ (verilog-sig-memory port-st)))
+ (concat "/*" vl-mbits vl-bits "*/")
+ (concat vl-bits))
+ tpl-net (concat port
(if vl-modport (concat "." vl-modport) "")
- (if (verilog-sig-multidim port-st)
- (concat "/*" vl-mbits vl-bits "*/")
- (concat vl-bits))))
+ dflt-bits))
;; Find template
(cond (tpl-ass ; Template of exact port name
(setq tpl-net (nth 1 tpl-ass)))
(setq expr (verilog-string-replace-matches "\\\\\"" "\"" nil nil expr))
(setq expr (verilog-string-replace-matches "@" tpl-num nil nil expr))
(prin1 (eval (car (read-from-string expr)))
- (lambda (ch) ())))))
+ (lambda (_ch) ())))))
(if (numberp value) (setq value (number-to-string value)))
value))
(substring tpl-net (match-end 0))))))
;; Replace @ and [] magic variables in final output
(setq tpl-net (verilog-string-replace-matches "@" tpl-num nil nil tpl-net))
+ (setq tpl-net (verilog-string-replace-matches "\\[\\]\\[\\]" dflt-bits nil nil tpl-net))
(setq tpl-net (verilog-string-replace-matches "\\[\\]" vl-bits nil nil tpl-net)))
;; Insert it
(indent-to indent-pt)
AUTOWIRE declarations, etc. Gates are the only case when
position based connections are passed.
+ The array part of arrayed instances are ignored; this may
+ result in undesirable default AUTOINST connections; use a
+ template instead.
+
For example, first take the submodule InstModule.v:
module InstModule (o,i);
words and capitalized. Only signals that must be different for each
instantiation need to be listed.
+ Inside a template, a [] in a connection name (with nothing else
+ inside the brackets) will be replaced by the same bus subscript
+ as it is being connected to, or the [] will be removed if it is
+ a single bit signal.
+
+ Inside a template, a [][] in a connection name will behave
+ similarly to a [] for scalar or single-dimensional connection;
+ for a multidimensional connection it will print a comment
+ similar to that printed when a template is not used. Generally
+ it is a good idea to do this for all connections in a template,
+ as then they will work for any width signal, and with AUTOWIRE.
+ See PTL_BUS becoming PTL_BUSNEW below.
+
Inside a template, a [] in a connection name (with nothing else inside
the brackets) will be replaced by the same bus subscript as it is being
connected to, or the [] will be removed if it is a single bit signal.
;; automatic variable instantiation program.
(let* ((tpl-info (verilog-read-auto-template submod))
(tpl-regexp (aref tpl-info 0)))
- (setq tpl-num (if (string-match tpl-regexp inst)
+ (setq tpl-num (if (verilog-string-match-fold tpl-regexp inst)
(match-string 1 inst)
"")
tpl-list (aref tpl-info 1)))
;; automatic variable instantiation program.
(let* ((tpl-info (verilog-read-auto-template submod))
(tpl-regexp (aref tpl-info 0)))
- (setq tpl-num (if (string-match tpl-regexp inst)
+ (setq tpl-num (if (verilog-string-match-fold tpl-regexp inst)
(match-string 1 inst)
"")
tpl-list (aref tpl-info 1)))
(verilog-subdecls-get-interfaced modsubdecls)
(verilog-subdecls-get-outputs modsubdecls)
(verilog-subdecls-get-inouts modsubdecls)))))
- (forward-line 1)
(when sig-list
+ (verilog-forward-or-insert-line)
(verilog-insert-indent "// Beginning of automatic regs (for this module's undeclared outputs)\n")
(verilog-insert-definition modi sig-list "reg" indent-pt nil)
(verilog-insert-indent "// End of automatics\n")))))
(verilog-subdecls-get-inouts modsubdecls))
(append (verilog-decls-get-signals moddecls)
(verilog-decls-get-assigns moddecls))))))
- (forward-line 1)
(when sig-list
+ (verilog-forward-or-insert-line)
(verilog-insert-indent "// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)\n")
(verilog-insert-definition modi sig-list "reg" indent-pt nil)
(verilog-insert-indent "// End of automatics\n")))))
(append (verilog-subdecls-get-outputs modsubdecls)
(verilog-subdecls-get-inouts modsubdecls))
(verilog-decls-get-signals moddecls)))))
- (forward-line 1)
(when sig-list
+ (verilog-forward-or-insert-line)
(verilog-insert-indent "// Beginning of automatic wires (for undeclared instantiated-module outputs)\n")
(verilog-insert-definition modi sig-list "wire" indent-pt nil)
(verilog-insert-indent "// End of automatics\n")
;; syntax-ppss which is broken when change hooks are disabled.
))))
-(defun verilog-auto-output (&optional with-params)
+(defun verilog-auto-output ()
"Expand AUTOOUTPUT statements, as part of \\[verilog-auto].
Make output statements for any output signal from an /*AUTOINST*/ that
isn't an input to another AUTOINST. This is useful for modules which
(save-excursion
;; Point must be at insertion point.
(let* ((indent-pt (current-indentation))
- (regexp (and with-params
- (nth 0 (verilog-read-auto-params 1))))
+ (params (verilog-read-auto-params 0 1))
+ (regexp (nth 0 params))
(v2k (verilog-in-paren-quick))
(modi (verilog-modi-current))
(moddecls (verilog-modi-get-decls modi))
(verilog-subdecls-get-outputs modsubdecls)
(append (verilog-decls-get-outputs moddecls)
(verilog-decls-get-inouts moddecls)
+ (verilog-decls-get-inputs moddecls)
(verilog-subdecls-get-inputs modsubdecls)
(verilog-subdecls-get-inouts modsubdecls)))))
(when regexp
sig-list regexp)))
(setq sig-list (verilog-signals-not-matching-regexp
sig-list verilog-auto-output-ignore-regexp))
- (forward-line 1)
+ (verilog-forward-or-insert-line)
(when v2k (verilog-repair-open-comma))
(when sig-list
(verilog-insert-indent "// Beginning of automatic outputs (from unused autoinst outputs)\n")
(verilog-signals-not-in
(verilog-decls-get-signals moddecls)
(verilog-decls-get-ports moddecls)))))
- (forward-line 1)
+ (verilog-forward-or-insert-line)
(when v2k (verilog-repair-open-comma))
(when sig-list
(verilog-insert-indent "// Beginning of automatic outputs (every signal)\n")
(verilog-insert-indent "// End of automatics\n"))
(when v2k (verilog-repair-close-comma)))))
-(defun verilog-auto-input (&optional with-params)
+(defun verilog-auto-input ()
"Expand AUTOINPUT statements, as part of \\[verilog-auto].
Make input statements for any input signal into an /*AUTOINST*/ that
isn't declared elsewhere inside the module. This is useful for modules which
/*AUTOINPUT(\"^i\")*/"
(save-excursion
(let* ((indent-pt (current-indentation))
- (regexp (and with-params
- (nth 0 (verilog-read-auto-params 1))))
+ (params (verilog-read-auto-params 0 1))
+ (regexp (nth 0 params))
(v2k (verilog-in-paren-quick))
(modi (verilog-modi-current))
(moddecls (verilog-modi-get-decls modi))
(verilog-subdecls-get-inputs modsubdecls)
(append (verilog-decls-get-inputs moddecls)
(verilog-decls-get-inouts moddecls)
+ (verilog-decls-get-outputs moddecls)
(verilog-decls-get-vars moddecls)
(verilog-decls-get-consts moddecls)
(verilog-decls-get-gparams moddecls)
sig-list regexp)))
(setq sig-list (verilog-signals-not-matching-regexp
sig-list verilog-auto-input-ignore-regexp))
- (forward-line 1)
+ (verilog-forward-or-insert-line)
(when v2k (verilog-repair-open-comma))
(when sig-list
(verilog-insert-indent "// Beginning of automatic inputs (from unused autoinst inputs)\n")
(verilog-insert-indent "// End of automatics\n"))
(when v2k (verilog-repair-close-comma)))))
-(defun verilog-auto-inout (&optional with-params)
+(defun verilog-auto-inout ()
"Expand AUTOINOUT statements, as part of \\[verilog-auto].
Make inout statements for any inout signal in an /*AUTOINST*/ that
isn't declared elsewhere inside the module.
(save-excursion
;; Point must be at insertion point.
(let* ((indent-pt (current-indentation))
- (regexp (and with-params
- (nth 0 (verilog-read-auto-params 1))))
+ (params (verilog-read-auto-params 0 1))
+ (regexp (nth 0 params))
(v2k (verilog-in-paren-quick))
(modi (verilog-modi-current))
(moddecls (verilog-modi-get-decls modi))
sig-list regexp)))
(setq sig-list (verilog-signals-not-matching-regexp
sig-list verilog-auto-inout-ignore-regexp))
- (forward-line 1)
+ (verilog-forward-or-insert-line)
(when v2k (verilog-repair-open-comma))
(when sig-list
(verilog-insert-indent "// Beginning of automatic inouts (from unused autoinst inouts)\n")
(verilog-signals-matching-regexp sig-list-if regexp)
"interface" direction-re))
(when v2k (verilog-repair-open-comma))
- (when (or sig-list-i sig-list-o sig-list-io)
+ (when (or sig-list-i sig-list-o sig-list-io sig-list-if)
(verilog-insert-indent "// Beginning of automatic in/out/inouts (from specific module)\n")
;; Don't sort them so an upper AUTOINST will match the main module
(verilog-insert-definition modi sig-list-o "output" indent-pt v2k t)
/*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/"
(verilog-auto-inout-module nil t))
+(defun verilog-auto-inout-param ()
+ "Expand AUTOINOUTPARAM statements, as part of \\[verilog-auto].
+Take input/output/inout statements from the specified module and insert
+into the current module. This is useful for making null templates and
+shell modules which need to have identical I/O with another module.
+Any I/O which are already defined in this module will not be redefined.
+For the complement of this function, see `verilog-auto-inout-comp',
+and to make monitors with all inputs, see `verilog-auto-inout-in'.
+
+Limitations:
+ If placed inside the parenthesis of a module declaration, it creates
+ Verilog 2001 style, else uses Verilog 1995 style.
+
+ Module names must be resolvable to filenames. See `verilog-auto-inst'.
+
+ Parameters are inserted in the same order as in the original module.
+
+ Parameters do not have values, which is SystemVerilog 2009 syntax.
+
+An example:
+
+ module ExampShell ();
+ /*AUTOINOUTPARAM(\"ExampMain\")*/
+ endmodule
+
+ module ExampMain ();
+ parameter PARAM = 22;
+ endmodule
+
+Typing \\[verilog-auto] will make this into:
+
+ module ExampShell (/*AUTOARG*/i,o,io);
+ /*AUTOINOUTPARAM(\"ExampMain\")*/
+ // Beginning of automatic parameters (from specific module)
+ parameter PARAM;
+ // End of automatics
+ endmodule
+
+You may also provide an optional regular expression, in which case only
+parameters matching the regular expression will be included. For example the
+same expansion will result from only extracting parameters starting with i:
+
+ /*AUTOINOUTPARAM(\"ExampMain\",\"^i\")*/"
+ (save-excursion
+ (let* ((params (verilog-read-auto-params 1 2))
+ (submod (nth 0 params))
+ (regexp (nth 1 params))
+ submodi)
+ ;; Lookup position, etc of co-module
+ ;; Note this may raise an error
+ (when (setq submodi (verilog-modi-lookup submod t))
+ (let* ((indent-pt (current-indentation))
+ (v2k (verilog-in-paren-quick))
+ (modi (verilog-modi-current))
+ (moddecls (verilog-modi-get-decls modi))
+ (submoddecls (verilog-modi-get-decls submodi))
+ (sig-list-p (verilog-signals-not-in
+ (verilog-decls-get-gparams submoddecls)
+ (append (verilog-decls-get-gparams moddecls)))))
+ (forward-line 1)
+ (setq sig-list-p (verilog-signals-matching-regexp sig-list-p regexp))
+ (when v2k (verilog-repair-open-comma))
+ (when sig-list-p
+ (verilog-insert-indent "// Beginning of automatic parameters (from specific module)\n")
+ ;; Don't sort them so an upper AUTOINST will match the main module
+ (verilog-insert-definition modi sig-list-p "parameter" indent-pt v2k t)
+ (verilog-insert-indent "// End of automatics\n"))
+ (when v2k (verilog-repair-close-comma)))))))
+
+(defun verilog-auto-inout-modport ()
+ "Expand AUTOINOUTMODPORT statements, as part of \\[verilog-auto].
+Take input/output/inout statements from the specified interface
+and modport and insert into the current module. This is useful
+for making verification modules that connect to UVM interfaces.
+
+ The first parameter is the name of an interface.
+
+ The second parameter is a regexp of modports to read from in
+ that interface.
+
+ The optional third parameter is a regular expression, and only
+ signals matching the regular expression will be included.
+
+Limitations:
+ If placed inside the parenthesis of a module declaration, it creates
+ Verilog 2001 style, else uses Verilog 1995 style.
+
+ Interface names must be resolvable to filenames. See `verilog-auto-inst'.
+
+As with other autos, any inputs/outputs declared in the module
+will suppress the AUTO from redeclaring an inputs/outputs by
+the same name.
+
+An example:
+
+ interface ExampIf
+ ( input logic clk );
+ logic req_val;
+ logic [7:0] req_dat;
+ clocking mon_clkblk @(posedge clk);
+ input req_val;
+ input req_dat;
+ endclocking
+ modport mp(clocking mon_clkblk);
+ endinterface
+
+ module ExampMain
+ ( input clk,
+ /*AUTOINOUTMODPORT(\"ExampIf\" \"mp\")*/
+ // Beginning of automatic in/out/inouts (from modport)
+ input [7:0] req_dat,
+ input req_val
+ // End of automatics
+ );
+ /*AUTOASSIGNMODPORT(\"ExampIf\" \"mp\")*/
+ endmodule
+
+Typing \\[verilog-auto] will make this into:
+
+ ...
+ module ExampMain
+ ( input clk,
+ /*AUTOINOUTMODPORT(\"ExampIf\" \"mp\")*/
+ // Beginning of automatic in/out/inouts (from modport)
+ input req_dat,
+ input req_val
+ // End of automatics
+ );
+
+If the modport is part of a UVM monitor/driver class, this
+creates a wrapper module that may be used to instantiate the
+driver/monitor using AUTOINST in the testbench."
+ (save-excursion
+ (let* ((params (verilog-read-auto-params 2 3))
+ (submod (nth 0 params))
+ (modport-re (nth 1 params))
+ (regexp (nth 2 params))
+ direction-re submodi) ;; direction argument not supported until requested
+ ;; Lookup position, etc of co-module
+ ;; Note this may raise an error
+ (when (setq submodi (verilog-modi-lookup submod t))
+ (let* ((indent-pt (current-indentation))
+ (v2k (verilog-in-paren-quick))
+ (modi (verilog-modi-current))
+ (moddecls (verilog-modi-get-decls modi))
+ (submoddecls (verilog-modi-get-decls submodi))
+ (submodportdecls (verilog-modi-modport-lookup submodi modport-re))
+ (sig-list-i (verilog-signals-in ;; Decls doesn't have data types, must resolve
+ (verilog-decls-get-vars submoddecls)
+ (verilog-signals-not-in
+ (verilog-decls-get-inputs submodportdecls)
+ (append (verilog-decls-get-ports submoddecls)
+ (verilog-decls-get-ports moddecls)))))
+ (sig-list-o (verilog-signals-in ;; Decls doesn't have data types, must resolve
+ (verilog-decls-get-vars submoddecls)
+ (verilog-signals-not-in
+ (verilog-decls-get-outputs submodportdecls)
+ (append (verilog-decls-get-ports submoddecls)
+ (verilog-decls-get-ports moddecls)))))
+ (sig-list-io (verilog-signals-in ;; Decls doesn't have data types, must resolve
+ (verilog-decls-get-vars submoddecls)
+ (verilog-signals-not-in
+ (verilog-decls-get-inouts submodportdecls)
+ (append (verilog-decls-get-ports submoddecls)
+ (verilog-decls-get-ports moddecls))))))
+ (forward-line 1)
+ (setq sig-list-i (verilog-signals-edit-wire-reg
+ (verilog-signals-matching-dir-re
+ (verilog-signals-matching-regexp sig-list-i regexp)
+ "input" direction-re))
+ sig-list-o (verilog-signals-edit-wire-reg
+ (verilog-signals-matching-dir-re
+ (verilog-signals-matching-regexp sig-list-o regexp)
+ "output" direction-re))
+ sig-list-io (verilog-signals-edit-wire-reg
+ (verilog-signals-matching-dir-re
+ (verilog-signals-matching-regexp sig-list-io regexp)
+ "inout" direction-re)))
+ (when v2k (verilog-repair-open-comma))
+ (when (or sig-list-i sig-list-o sig-list-io)
+ (verilog-insert-indent "// Beginning of automatic in/out/inouts (from modport)\n")
+ ;; Don't sort them so an upper AUTOINST will match the main module
+ (verilog-insert-definition modi sig-list-o "output" indent-pt v2k t)
+ (verilog-insert-definition modi sig-list-io "inout" indent-pt v2k t)
+ (verilog-insert-definition modi sig-list-i "input" indent-pt v2k t)
+ (verilog-insert-indent "// End of automatics\n"))
+ (when v2k (verilog-repair-close-comma)))))))
+
(defun verilog-auto-insert-lisp ()
"Expand AUTOINSERTLISP statements, as part of \\[verilog-auto].
The Lisp code provided is called, and the Lisp code calls
// For this example we declare the function in the
// module's file itself. Often you'd define it instead
- // in a site-start.el or .emacs file.
+ // in a site-start.el or init file.
/*
Local Variables:
eval:
(backward-sexp 1) ;; Inside comment
(point))) ;; Beginning paren
(cmd (buffer-substring-no-properties cmd-beg-pt cmd-end-pt)))
- (forward-line 1)
+ (verilog-forward-or-insert-line)
;; Some commands don't move point (like insert-file) so we always
;; add the begin/end comments, then delete it if not needed
(verilog-insert-indent "// Beginning of automatic insert lisp\n")
By default, AUTORESET will include the width of the signal in the
autos, SystemVerilog designs may want to change this. To control
-this behavior, see `verilog-auto-reset-widths'.
+this behavior, see `verilog-auto-reset-widths'. In some cases
+AUTORESET must use a '0 assignment and it will print NOWIDTH; use
+`verilog-auto-reset-widths' unbased to prevent this.
AUTORESET ties signals to deasserted, which is presumed to be zero.
Signals that match `verilog-active-low-regexp' will be deasserted by tying
them to a one.
+AUTORESET may try to reset arrays or structures that cannot be
+reset by a simple assignment, resulting in compile errors. This
+is a feature to be taken as a hint that you need to reset these
+signals manually (or put them into a \"`ifdef NEVER signal<=`0;
+`endif\" so Verilog-Mode ignores them.)
+
An example:
always @(posedge clk or negedge reset_l) begin
An example of making a stub for another module:
module ExampStub (/*AUTOINST*/);
+ /*AUTOINOUTPARAM(\"Foo\")*/
/*AUTOINOUTMODULE(\"Foo\")*/
/*AUTOTIEOFF*/
// verilator lint_off UNUSED
Typing \\[verilog-auto] will make this into:
module ExampStub (/*AUTOINST*/...);
+ /*AUTOINOUTPARAM(\"Foo\")*/
/*AUTOINOUTMODULE(\"Foo\")*/
// Beginning of autotieoff
output [2:0] foo;
(setq sig-list (verilog-signals-not-matching-regexp
sig-list verilog-auto-tieoff-ignore-regexp))
(when sig-list
- (forward-line 1)
+ (verilog-forward-or-insert-line)
(verilog-insert-indent "// Beginning of automatic tieoffs (for this module's unterminated outputs)\n")
(setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
(verilog-modi-cache-add-vars modi sig-list) ; Before we trash list
;; Insert
(setq defs (sort defs 'string<))
(when defs
- (forward-line 1)
+ (verilog-forward-or-insert-line)
(verilog-insert-indent "// Beginning of automatic undefs\n")
(while defs
(verilog-insert-indent "`undef " (car defs) "\n")
An example of making a stub for another module:
module ExampStub (/*AUTOINST*/);
+ /*AUTOINOUTPARAM(\"Examp\")*/
/*AUTOINOUTMODULE(\"Examp\")*/
/*AUTOTIEOFF*/
// verilator lint_off UNUSED
(setq sig-list (verilog-signals-not-matching-regexp
sig-list verilog-auto-unused-ignore-regexp))
(when sig-list
- (forward-line 1)
+ (verilog-forward-or-insert-line)
(verilog-insert-indent "// Beginning of automatic unused inputs\n")
(setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
(while sig-list
;;
(sig-list-consts (append (verilog-decls-get-consts moddecls)
(verilog-decls-get-gparams moddecls)))
- (sig-list-all (append (verilog-decls-get-vars moddecls)
- (verilog-decls-get-outputs moddecls)
- (verilog-decls-get-inouts moddecls)
- (verilog-decls-get-inputs moddecls)))
+ (sig-list-all (verilog-decls-get-iovars moddecls))
;;
(undecode-sig (or (assoc undecode-name sig-list-all)
(error "%s: Signal %s not found in design" (verilog-point-text) undecode-name)))
;; count(enums) == width(sig)
(equal (number-to-string (length enum-sigs))
(verilog-sig-width undecode-sig)))))
- (enum-chars 0)
+ (enum-chars 0)
(ascii-chars 0))
;;
;; Find number of ascii chars needed
elim-regexp)))
tmp-sigs (cdr tmp-sigs))))
;;
- (forward-line 1)
+ (verilog-forward-or-insert-line)
(verilog-insert-indent "// Beginning of automatic ASCII enum decoding\n")
(let ((decode-sig-list (list (list ascii-name (format "[%d:0]" (- (* ascii-chars 8) 1))
(concat "Decode of " undecode-name) nil nil))))
Use \\[verilog-faq] for a pointer to frequently asked questions.
+For new users, we recommend setting `verilog-case-fold' to nil
+and `verilog-auto-arg-sort' to t.
+
The hooks `verilog-before-auto-hook' and `verilog-auto-hook' are
called before and after this function, respectively.
Using \\[describe-function], see also:
`verilog-auto-arg' for AUTOARG module instantiations
`verilog-auto-ascii-enum' for AUTOASCIIENUM enumeration decoding
+ `verilog-auto-assign-modport' for AUTOASSIGNMODPORT assignment to/from modport
+ `verilog-auto-inout' for AUTOINOUT making hierarchy inouts
`verilog-auto-inout-comp' for AUTOINOUTCOMP copy complemented i/o
`verilog-auto-inout-in' for AUTOINOUTIN inputs for all i/o
+ `verilog-auto-inout-modport' for AUTOINOUTMODPORT i/o from an interface modport
`verilog-auto-inout-module' for AUTOINOUTMODULE copying i/o from elsewhere
- `verilog-auto-inout' for AUTOINOUT making hierarchy inouts
+ `verilog-auto-inout-param' for AUTOINOUTPARAM copying params from elsewhere
`verilog-auto-input' for AUTOINPUT making hierarchy inputs
`verilog-auto-insert-lisp' for AUTOINSERTLISP insert code from lisp function
`verilog-auto-inst' for AUTOINST instantiation pins
`verilog-auto-reg' for AUTOREG registers
`verilog-auto-reg-input' for AUTOREGINPUT instantiation registers
`verilog-auto-reset' for AUTORESET flop resets
- `verilog-auto-sense' for AUTOSENSE always sensitivity lists
+ `verilog-auto-sense' for AUTOSENSE or AS always sensitivity lists
`verilog-auto-tieoff' for AUTOTIEOFF output tieoffs
`verilog-auto-undef' for AUTOUNDEF `undef of local `defines
`verilog-auto-unused' for AUTOUNUSED unused inputs/inouts
(verilog-save-font-mods
(let ((oldbuf (if (not (buffer-modified-p))
(buffer-string)))
+ (case-fold-search verilog-case-fold)
;; Cache directories; we don't write new files, so can't change
(verilog-dir-cache-preserving t)
;; Cache current module
(verilog-auto-re-search-do "/\\*\\(AUTOSENSE\\|AS\\)\\*/" 'verilog-auto-sense)
(verilog-auto-re-search-do "/\\*AUTORESET\\*/" 'verilog-auto-reset)
;; Must be done before autoin/out as creates a reg
- (verilog-auto-re-search-do "/\\*AUTOASCIIENUM([^)]*)\\*/" 'verilog-auto-ascii-enum)
+ (verilog-auto-re-search-do "/\\*AUTOASCIIENUM(.*?)\\*/" 'verilog-auto-ascii-enum)
;;
;; first in/outs from other files
- (verilog-auto-re-search-do "/\\*AUTOINOUTMODULE([^)]*)\\*/" 'verilog-auto-inout-module)
- (verilog-auto-re-search-do "/\\*AUTOINOUTCOMP([^)]*)\\*/" 'verilog-auto-inout-comp)
- (verilog-auto-re-search-do "/\\*AUTOINOUTIN([^)]*)\\*/" 'verilog-auto-inout-in)
+ (verilog-auto-re-search-do "/\\*AUTOINOUTMODPORT(.*?)\\*/" 'verilog-auto-inout-modport)
+ (verilog-auto-re-search-do "/\\*AUTOINOUTMODULE(.*?)\\*/" 'verilog-auto-inout-module)
+ (verilog-auto-re-search-do "/\\*AUTOINOUTCOMP(.*?)\\*/" 'verilog-auto-inout-comp)
+ (verilog-auto-re-search-do "/\\*AUTOINOUTIN(.*?)\\*/" 'verilog-auto-inout-in)
+ (verilog-auto-re-search-do "/\\*AUTOINOUTPARAM(.*?)\\*/" 'verilog-auto-inout-param)
;; next in/outs which need previous sucked inputs first
- (verilog-auto-re-search-do "/\\*AUTOOUTPUT\\((\"[^\"]*\")\\)\\*/"
- (lambda () (verilog-auto-output t)))
- (verilog-auto-re-search-do "/\\*AUTOOUTPUT\\*/" 'verilog-auto-output)
- (verilog-auto-re-search-do "/\\*AUTOINPUT\\((\"[^\"]*\")\\)\\*/"
- (lambda () (verilog-auto-input t)))
- (verilog-auto-re-search-do "/\\*AUTOINPUT\\*/" 'verilog-auto-input)
- (verilog-auto-re-search-do "/\\*AUTOINOUT\\((\"[^\"]*\")\\)\\*/"
- (lambda () (verilog-auto-inout t)))
- (verilog-auto-re-search-do "/\\*AUTOINOUT\\*/" 'verilog-auto-inout)
+ (verilog-auto-re-search-do "/\\*AUTOOUTPUT\\((.*?)\\)?\\*/" 'verilog-auto-output)
+ (verilog-auto-re-search-do "/\\*AUTOINPUT\\((.*?)\\)?\\*/" 'verilog-auto-input)
+ (verilog-auto-re-search-do "/\\*AUTOINOUT\\((.*?)\\)?\\*/" 'verilog-auto-inout)
;; Then tie off those in/outs
(verilog-auto-re-search-do "/\\*AUTOTIEOFF\\*/" 'verilog-auto-tieoff)
;; These can be anywhere after AUTOINSERTLISP
- (verilog-auto-re-search-do "/\\*AUTOUNDEF\\((\"[^\"]*\")\\)?\\*/" 'verilog-auto-undef)
+ (verilog-auto-re-search-do "/\\*AUTOUNDEF\\((.*?)\\)?\\*/" 'verilog-auto-undef)
;; Wires/regs must be after inputs/outputs
+ (verilog-auto-re-search-do "/\\*AUTOASSIGNMODPORT(.*?)\\*/" 'verilog-auto-assign-modport)
(verilog-auto-re-search-do "/\\*AUTOLOGIC\\*/" 'verilog-auto-logic)
(verilog-auto-re-search-do "/\\*AUTOWIRE\\*/" 'verilog-auto-wire)
(verilog-auto-re-search-do "/\\*AUTOREG\\*/" 'verilog-auto-reg)
(define-key map "r" 'verilog-sk-repeat)
(define-key map "s" 'verilog-sk-specify)
(define-key map "t" 'verilog-sk-task)
- (define-key map "u" 'verilog-sk-uvm-class)
+ (define-key map "u" 'verilog-sk-uvm-object)
(define-key map "w" 'verilog-sk-while)
(define-key map "x" 'verilog-sk-casex)
(define-key map "z" 'verilog-sk-casez)
(define-key map "O" 'verilog-sk-output)
(define-key map "S" 'verilog-sk-state-machine)
(define-key map "=" 'verilog-sk-inout)
+ (define-key map "U" 'verilog-sk-uvm-component)
(define-key map "W" 'verilog-sk-wire)
(define-key map "R" 'verilog-sk-reg)
(define-key map "D" 'verilog-sk-define-signal)
;;
;; Place the templates into Verilog Mode. They may be inserted under any key.
;; C-c C-t will be the default. If you use templates a lot, you
-;; may want to consider moving the binding to another key in your .emacs
+;; may want to consider moving the binding to another key in your init
;; file.
;;
;; Note \C-c and letter are reserved for users
> _ \n
> "endclass" (progn (electric-verilog-terminate-line) nil))
-(define-skeleton verilog-sk-uvm-class
+(define-skeleton verilog-sk-uvm-object
"Insert a class definition"
()
> "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n
> _ \n
> "`uvm_object_utils_begin(" name ")" \n
- > (- verilog-indent-level) " `uvm_object_utils_end" \n
+ > (- verilog-indent-level) "`uvm_object_utils_end" \n
> _ \n
> "function new(name=\"" name "\");" \n
> "super.new(name);" \n
> _ \n
> "endclass" (progn (electric-verilog-terminate-line) nil))
+(define-skeleton verilog-sk-uvm-component
+ "Insert a class definition"
+ ()
+ > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n
+ > _ \n
+ > "`uvm_component_utils_begin(" name ")" \n
+ > (- verilog-indent-level) "`uvm_component_utils_end" \n
+ > _ \n
+ > "function new(name=\"\", uvm_component parent);" \n
+ > "super.new(name, parent);" \n
+ > (- verilog-indent-level) "endfunction" \n
+ > _ \n
+ > "endclass" (progn (electric-verilog-terminate-line) nil))
+
(define-skeleton verilog-sk-primitive
"Insert a task definition."
()
()
> "begin" '(verilog-sk-prompt-name) \n
> _ \n
- > (- verilog-indent-level-behavioral) "end"
-)
+ > (- verilog-indent-level-behavioral) "end" )
(define-skeleton verilog-sk-fork
"Insert a fork join block."
"Map containing mouse bindings for `verilog-mode'.")
-(defun verilog-highlight-region (beg end old-len)
+(defun verilog-highlight-region (beg end _old-len)
"Colorize included files and modules in the (changed?) region.
Clicking on the middle-mouse button loads them in a buffer (as in dired)."
(when (or verilog-highlight-includes
verilog-before-getopt-flags-hook
verilog-before-save-font-hook
verilog-cache-enabled
+ verilog-case-fold
verilog-case-indent
verilog-cexp-indent
verilog-compiler
verilog-linter
verilog-minimum-comment-distance
verilog-mode-hook
- verilog-mode-release-date
verilog-mode-release-emacs
verilog-mode-version
verilog-preprocessor