Fix handling of commands containing double quotes in gdb-mi

[gnu-emacs] / lisp / progmodes / verilog-mode.el

diff --git a/lisp/progmodes/verilog-mode.el b/lisp/progmodes/verilog-mode.el
index 52e7b6e2429a2e2ad6ea0e13155f358c63f27862..73e3cd9980f036d929545111a5103297eaf027c0 100644 (file)
--- a/lisp/progmodes/verilog-mode.el
+++ b/lisp/progmodes/verilog-mode.el
@@ -1,6 +1,6 @@
 ;; verilog-mode.el --- major mode for editing verilog source in Emacs
 
-;; Copyright (C) 1996-2011  Free Software Foundation, Inc.
+;; Copyright (C) 1996-2012  Free Software Foundation, Inc.
 
 ;; Author: Michael McNamara (mac@verilog.com),
 ;;    Wilson Snyder (wsnyder@wsnyder.org)
@@ -689,6 +689,7 @@ file referenced.  If false, this is not supported."
 Set this to \"wire\" if the Verilog code uses \"`default_nettype
 none\".  Note using `default_nettype none isn't recommended practice; this
 mode is experimental."
+  :version "24.1"
   :group 'verilog-mode-actions
   :type 'boolean)
 (put 'verilog-auto-declare-nettype 'safe-local-variable `stringp)
@@ -696,6 +697,7 @@ mode is experimental."
 (defcustom verilog-auto-wire-type nil
   "*Non-nil specifies the data type to use with `verilog-auto-wire' etc.
 Set this to \"logic\" for SystemVerilog code, or use `verilog-auto-logic'."
+  :version "24.1"
   :group 'verilog-mode-actions
   :type 'boolean)
 (put 'verilog-auto-wire-type 'safe-local-variable `stringp)
@@ -709,6 +711,7 @@ The name of the function or case will be set between the braces."
 
 (defcustom verilog-auto-delete-trailing-whitespace nil
   "*True means to `delete-trailing-whitespace' in `verilog-auto'."
+  :version "24.1"
   :group 'verilog-mode-actions
   :type 'boolean)
 (put 'verilog-auto-delete-trailing-whitespace 'safe-local-variable 'verilog-booleanp)
@@ -986,6 +989,7 @@ If nil, all blocking assigned signals are ignored when any
 non-blocking assignment is in the AUTORESET block.  This allows
 blocking assignments to be used for temporary values and not have
 those temporaries reset.  See example in `verilog-auto-reset'."
+  :version "24.1"
   :type 'boolean
   :group 'verilog-mode-auto)
 (put 'verilog-auto-reset-blocking-in-non 'safe-local-variable 'verilog-booleanp)
@@ -1073,6 +1077,7 @@ declared together to remain together.  Sorted order reduces
 changes when declarations are moved around in a file.
 
 See also `verilog-auto-arg-sort'."
+  :version "24.1"
   :group 'verilog-mode-auto
   :type 'boolean)
 (put 'verilog-auto-inst-sort 'safe-local-variable 'verilog-booleanp)
@@ -1135,6 +1140,7 @@ See the \\[verilog-faq] for examples on using this."
   "*Data type used for the declaration for AUTOTIEOFF.  If \"wire\" then
 create a wire, if \"assign\" create an assignment, else the data type for
 variable creation."
+  :version "24.1"
   :group 'verilog-mode-auto
   :type 'string)
 (put 'verilog-auto-tieoff-declaration 'safe-local-variable 'stringp)
@@ -1423,7 +1429,7 @@ If set will become buffer local.")
       ["AUTOSENSE"                     (describe-function 'verilog-auto-sense)
        :help           "Help on AUTOSENSE - sensitivity lists for always blocks"]
       ["AUTOTIEOFF"                    (describe-function 'verilog-auto-tieoff)
-       :help           "Help on AUTOTIEOFF - tieing off unused outputs"]
+       :help           "Help on AUTOTIEOFF - tying off unused outputs"]
       ["AUTOUNUSED"                    (describe-function 'verilog-auto-unused)
        :help           "Help on AUTOUNUSED - terminating unused inputs"]
       ["AUTOWIRE"                      (describe-function 'verilog-auto-wire)
@@ -1667,7 +1673,7 @@ This speeds up complicated regexp matches."
   ;; Similar to `delete-trailing-whitespace' but that's not present in XEmacs
   (save-excursion
     (goto-char (point-min))
-    (while (re-search-forward "[ \t]+$" nil t)  ;; Not syntatic WS as no formfeed
+    (while (re-search-forward "[ \t]+$" nil t)  ;; Not syntactic WS as no formfeed
       (replace-match "" nil nil))))
 
 (defvar compile-command)
@@ -11725,7 +11731,7 @@ this is a recent change.  To control this behavior, see
 `verilog-auto-reset-widths'.
 
 AUTORESET ties signals to deasserted, which is presumed to be zero.
-Signals that match `verilog-active-low-regexp' will be deasserted by tieing
+Signals that match `verilog-active-low-regexp' will be deasserted by tying
 them to a one.
 
 An example:
@@ -11816,7 +11822,7 @@ finds all outputs in the module, and if that input is not otherwise declared
 as a register or wire, creates a tieoff.
 
 AUTORESET ties signals to deasserted, which is presumed to be zero.
-Signals that match `verilog-active-low-regexp' will be deasserted by tieing
+Signals that match `verilog-active-low-regexp' will be deasserted by tying
 them to a one.
 
 You can add signals you do not want included in AUTOTIEOFF with