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[refind] / EfiLib / Platform.h
1 /*
2 Headers collection for procedures
3 */
4
5 #ifndef __REFIT_PLATFORM_H__
6 #define __REFIT_PLATFORM_H__
7
8
9 #include <Uefi.h>
10
11 #include <Guid/Acpi.h>
12 #include <Guid/EventGroup.h>
13 #include <Guid/SmBios.h>
14 #include <Guid/Mps.h>
15
16 #include <Library/BaseLib.h>
17 #include <Library/BaseMemoryLib.h>
18 #include <Library/DebugLib.h>
19 #include <Library/HiiLib.h>
20 #include <Library/MemoryAllocationLib.h>
21 #include <Library/PcdLib.h>
22 #include <Library/PerformanceLib.h>
23 #include <Library/PeCoffGetEntryPointLib.h>
24 #include <Library/TimerLib.h>
25 #include <Library/UefiBootServicesTableLib.h>
26 #include <Library/UefiDriverEntryPoint.h>
27 #include <Library/UefiLib.h>
28 #include <Library/UefiRuntimeServicesTableLib.h>
29 #include <Library/UefiRuntimeLib.h>
30
31 #include <Framework/FrameworkInternalFormRepresentation.h>
32
33 #include <IndustryStandard/Acpi10.h>
34 #include <IndustryStandard/Acpi20.h>
35
36 #include <Protocol/Cpu.h>
37 #include <Protocol/CpuIo.h>
38 #include <Protocol/DataHub.h>
39 #include <Protocol/DevicePathToText.h>
40 #include <Protocol/FrameworkHii.h>
41 #include <Protocol/Smbios.h>
42 #include <Protocol/VariableWrite.h>
43 #include <Protocol/Variable.h>
44
45 //#include <Protocol/FSInjectProtocol.h>
46 //#include <Protocol/MsgLog.h>
47
48 //#include "lib.h"
49 //#include "boot.h"
50 //#include "BiosVideo.h"
51 #include "../include/Bmp.h"
52 #include "efiConsoleControl.h"
53 //#include "SmBios.h"
54 #include "EfiLib/GenericBdsLib.h"
55 //#include "device_inject.h"
56 //#include "UsbMass.h"
57
58 #include "../refind/global.h"
59
60 /* Decimal powers: */
61 // #define kilo (1000ULL)
62 // #define Mega (kilo * kilo)
63 // #define Giga (kilo * Mega)
64 // #define Tera (kilo * Giga)
65 // #define Peta (kilo * Tera)
66
67 // #define IS_COMMA(a) ((a) == L',')
68 // #define IS_HYPHEN(a) ((a) == L'-')
69 // #define IS_DOT(a) ((a) == L'.')
70 // #define IS_LEFT_PARENTH(a) ((a) == L'(')
71 // #define IS_RIGHT_PARENTH(a) ((a) == L')')
72 // #define IS_SLASH(a) ((a) == L'/')
73 // #define IS_NULL(a) ((a) == L'\0')
74 // #define IS_DIGIT(a) (((a) >= '0') && ((a) <= '9'))
75 // #define IS_HEX(a) (((a) >= 'a') && ((a) <= 'f'))
76 // #define IS_UPPER(a) (((a) >= 'A') && ((a) <= 'Z'))
77 // #define IS_ALFA(x) (((x >= 'a') && (x <='z')) || ((x >= 'A') && (x <='Z')))
78 // #define IS_ASCII(x) ((x>=0x20) && (x<=0x7F))
79 // #define IS_PUNCT(x) ((x == '.') || (x == '-'))
80
81
82 // #define EBDA_BASE_ADDRESS 0x40E
83 // #define EFI_SYSTEM_TABLE_MAX_ADDRESS 0xFFFFFFFF
84 // #define ROUND_PAGE(x) ((((unsigned)(x)) + EFI_PAGE_SIZE - 1) & ~(EFI_PAGE_SIZE - 1))
85
86 //
87 // Max bytes needed to represent ID of a SCSI device
88 //
89 //#define EFI_SCSI_TARGET_MAX_BYTES (0x10)
90
91 //
92 // bit5..7 are for Logical unit number
93 // 11100000b (0xe0)
94 //
95 //#define EFI_SCSI_LOGICAL_UNIT_NUMBER_MASK 0xe0
96
97 //
98 // Scsi Command Length
99 //
100 //#define EFI_SCSI_OP_LENGTH_SIX 0x6
101 //#define EFI_SCSI_OP_LENGTH_TEN 0xa
102 //#define EFI_SCSI_OP_LENGTH_SIXTEEN 0x10
103
104 // #define SAFE_LOG_SIZE 80
105 //
106 // #define MSG_LOG_SIZE (64 * 1024)
107 // #define MsgLog(x...) {AsciiSPrint(msgCursor, MSG_LOG_SIZE, x); while(*msgCursor){msgCursor++;}}
108 //
109 // #define CPU_MODEL_DOTHAN 0x0D
110 // #define CPU_MODEL_YONAH 0x0E
111 // #define CPU_MODEL_MEROM 0x0F /* same as CONROE but mobile */
112 // #define CPU_MODEL_CONROE 0x0F
113 // #define CPU_MODEL_CELERON 0x16 /* ever see? */
114 // #define CPU_MODEL_PENRYN 0x17
115 // #define CPU_MODEL_WOLFDALE 0x17
116 // #define CPU_MODEL_NEHALEM 0x1A
117 // #define CPU_MODEL_ATOM 0x1C
118 // #define CPU_MODEL_XEON_MP 0x1D /* ever see? */
119 // #define CPU_MODEL_FIELDS 0x1E
120 // #define CPU_MODEL_DALES 0x1F
121 // #define CPU_MODEL_CLARKDALE 0x25
122 // #define CPU_MODEL_LINCROFT 0x27
123 // #define CPU_MODEL_SANDY_BRIDGE 0x2A
124 // #define CPU_MODEL_WESTMERE 0x2C
125 // #define CPU_MODEL_JAKETOWN 0x2D /* ever see? */
126 // #define CPU_MODEL_NEHALEM_EX 0x2E
127 // #define CPU_MODEL_WESTMERE_EX 0x2F
128 //
129 // #define CPU_VENDOR_INTEL 0x756E6547
130 // #define CPU_VENDOR_AMD 0x68747541
131 // /* Unknown CPU */
132 // #define CPU_STRING_UNKNOWN "Unknown CPU Type"
133
134 //definitions from Apple XNU
135
136 /* CPU defines */
137 // #define bit(n) (1UL << (n))
138 // #define _Bit(n) (1ULL << n)
139 // #define _HBit(n) (1ULL << ((n)+32))
140 //
141 // #define bitmask(h,l) ((bit(h)|(bit(h)-1)) & ~(bit(l)-1))
142 // #define bitfield(x,h,l) (((x) & bitmask(h,l)) >> l)
143 // #define quad(hi,lo) (((UINT64)(hi)) << 32 | (lo))
144
145 /*
146 * The CPUID_FEATURE_XXX values define 64-bit values
147 * returned in %ecx:%edx to a CPUID request with %eax of 1:
148 */
149 // #define CPUID_FEATURE_FPU _Bit(0) /* Floating point unit on-chip */
150 // #define CPUID_FEATURE_VME _Bit(1) /* Virtual Mode Extension */
151 // #define CPUID_FEATURE_DE _Bit(2) /* Debugging Extension */
152 // #define CPUID_FEATURE_PSE _Bit(3) /* Page Size Extension */
153 // #define CPUID_FEATURE_TSC _Bit(4) /* Time Stamp Counter */
154 // #define CPUID_FEATURE_MSR _Bit(5) /* Model Specific Registers */
155 // #define CPUID_FEATURE_PAE _Bit(6) /* Physical Address Extension */
156 // #define CPUID_FEATURE_MCE _Bit(7) /* Machine Check Exception */
157 // #define CPUID_FEATURE_CX8 _Bit(8) /* CMPXCHG8B */
158 // #define CPUID_FEATURE_APIC _Bit(9) /* On-chip APIC */
159 // #define CPUID_FEATURE_SEP _Bit(11) /* Fast System Call */
160 // #define CPUID_FEATURE_MTRR _Bit(12) /* Memory Type Range Register */
161 // #define CPUID_FEATURE_PGE _Bit(13) /* Page Global Enable */
162 // #define CPUID_FEATURE_MCA _Bit(14) /* Machine Check Architecture */
163 // #define CPUID_FEATURE_CMOV _Bit(15) /* Conditional Move Instruction */
164 // #define CPUID_FEATURE_PAT _Bit(16) /* Page Attribute Table */
165 // #define CPUID_FEATURE_PSE36 _Bit(17) /* 36-bit Page Size Extension */
166 // #define CPUID_FEATURE_PSN _Bit(18) /* Processor Serial Number */
167 // #define CPUID_FEATURE_CLFSH _Bit(19) /* CLFLUSH Instruction supported */
168 // #define CPUID_FEATURE_DS _Bit(21) /* Debug Store */
169 // #define CPUID_FEATURE_ACPI _Bit(22) /* Thermal monitor and Clock Ctrl */
170 // #define CPUID_FEATURE_MMX _Bit(23) /* MMX supported */
171 // #define CPUID_FEATURE_FXSR _Bit(24) /* Fast floating pt save/restore */
172 // #define CPUID_FEATURE_SSE _Bit(25) /* Streaming SIMD extensions */
173 // #define CPUID_FEATURE_SSE2 _Bit(26) /* Streaming SIMD extensions 2 */
174 // #define CPUID_FEATURE_SS _Bit(27) /* Self-Snoop */
175 // #define CPUID_FEATURE_HTT _Bit(28) /* Hyper-Threading Technology */
176 // #define CPUID_FEATURE_TM _Bit(29) /* Thermal Monitor (TM1) */
177 // #define CPUID_FEATURE_PBE _Bit(31) /* Pend Break Enable */
178 //
179 // #define CPUID_FEATURE_SSE3 _HBit(0) /* Streaming SIMD extensions 3 */
180 // #define CPUID_FEATURE_PCLMULQDQ _HBit(1) /* PCLMULQDQ Instruction */
181 //
182 // #define CPUID_FEATURE_MONITOR _HBit(3) /* Monitor/mwait */
183 // #define CPUID_FEATURE_DSCPL _HBit(4) /* Debug Store CPL */
184 // #define CPUID_FEATURE_VMX _HBit(5) /* VMX */
185 // #define CPUID_FEATURE_SMX _HBit(6) /* SMX */
186 // #define CPUID_FEATURE_EST _HBit(7) /* Enhanced SpeedsTep (GV3) */
187 // #define CPUID_FEATURE_TM2 _HBit(8) /* Thermal Monitor 2 */
188 // #define CPUID_FEATURE_SSSE3 _HBit(9) /* Supplemental SSE3 instructions */
189 // #define CPUID_FEATURE_CID _HBit(10) /* L1 Context ID */
190 //
191 // #define CPUID_FEATURE_CX16 _HBit(13) /* CmpXchg16b instruction */
192 // #define CPUID_FEATURE_xTPR _HBit(14) /* Send Task PRiority msgs */
193 // #define CPUID_FEATURE_PDCM _HBit(15) /* Perf/Debug Capability MSR */
194 //
195 // #define CPUID_FEATURE_DCA _HBit(18) /* Direct Cache Access */
196 // #define CPUID_FEATURE_SSE4_1 _HBit(19) /* Streaming SIMD extensions 4.1 */
197 // #define CPUID_FEATURE_SSE4_2 _HBit(20) /* Streaming SIMD extensions 4.2 */
198 // #define CPUID_FEATURE_xAPIC _HBit(21) /* Extended APIC Mode */
199 // #define CPUID_FEATURE_POPCNT _HBit(23) /* POPCNT instruction */
200 // #define CPUID_FEATURE_AES _HBit(25) /* AES instructions */
201 // #define CPUID_FEATURE_VMM _HBit(31) /* VMM (Hypervisor) present */
202
203 // /*
204 // * The CPUID_EXTFEATURE_XXX values define 64-bit values
205 // * returned in %ecx:%edx to a CPUID request with %eax of 0x80000001:
206 // */
207 // #define CPUID_EXTFEATURE_SYSCALL _Bit(11) /* SYSCALL/sysret */
208 // #define CPUID_EXTFEATURE_XD _Bit(20) /* eXecute Disable */
209 // #define CPUID_EXTFEATURE_1GBPAGE _Bit(26) /* 1G-Byte Page support */
210 // #define CPUID_EXTFEATURE_RDTSCP _Bit(27) /* RDTSCP */
211 // #define CPUID_EXTFEATURE_EM64T _Bit(29) /* Extended Mem 64 Technology */
212 //
213 // //#define CPUID_EXTFEATURE_LAHF _HBit(20) /* LAFH/SAHF instructions */
214 // // New definition with Snow kernel
215 // #define CPUID_EXTFEATURE_LAHF _HBit(0) /* LAHF/SAHF instructions */
216 // /*
217 // * The CPUID_EXTFEATURE_XXX values define 64-bit values
218 // * returned in %ecx:%edx to a CPUID request with %eax of 0x80000007:
219 // */
220 // #define CPUID_EXTFEATURE_TSCI _Bit(8) /* TSC Invariant */
221 //
222 // #define CPUID_CACHE_SIZE 16 /* Number of descriptor values */
223 //
224 // #define CPUID_MWAIT_EXTENSION _Bit(0) /* enumeration of WMAIT extensions */
225 // #define CPUID_MWAIT_BREAK _Bit(1) /* interrupts are break events */
226
227 // /* Known MSR registers */
228 // #define MSR_IA32_PLATFORM_ID 0x0017
229 // #define MSR_CORE_THREAD_COUNT 0x0035 /* limited use - not for Penryn or older */
230 // #define MSR_IA32_BIOS_SIGN_ID 0x008B /* microcode version */
231 // #define MSR_FSB_FREQ 0x00CD /* limited use - not for i7 */
232 // #define MSR_PLATFORM_INFO 0x00CE /* limited use - MinRatio for i7 but Max for Yonah */
233 // /* turbo for penryn */
234 // #define MSR_IA32_EXT_CONFIG 0x00EE /* limited use - not for i7 */
235 // #define MSR_FLEX_RATIO 0x0194 /* limited use - not for Penryn or older */
236 // //see no value on most CPUs
237 // #define MSR_IA32_PERF_STATUS 0x0198
238 // #define MSR_IA32_PERF_CONTROL 0x0199
239 // #define MSR_IA32_CLOCK_MODULATION 0x019A
240 // #define MSR_THERMAL_STATUS 0x019C
241 // #define MSR_IA32_MISC_ENABLE 0x01A0
242 // #define MSR_THERMAL_TARGET 0x01A2 /* limited use - not for Penryn or older */
243 // #define MSR_TURBO_RATIO_LIMIT 0x01AD /* limited use - not for Penryn or older */
244 //
245 //
246 // //Copied from revogirl
247 // #define IA32_ENERGY_PERF_BIAS 0x01B0
248 // //MSR 000001B0 0000-0000-0000-0005
249 // //MSR 000001B1 0000-0000-8838-0000
250 // #define IA32_PLATFORM_DCA_CAP 0x01F8
251 // //MSR 000001FC 0000-0000-0004-005F
252 //
253 //
254 // // Sandy Bridge & JakeTown specific 'Running Average Power Limit' MSR's.
255 // #define MSR_RAPL_POWER_UNIT 0x606
256 // //MSR 00000606 0000-0000-000A-1003
257 // //MSR 0000060B 0000-0000-0000-8854
258 // //MSR 0000060C 0000-0000-0000-8854
259
260 // #define MSR_PKG_RAPL_POWER_LIMIT 0x610
261 // //MSR 00000610 0000-A580-0000-8960
262 // #define MSR_PKG_ENERGY_STATUS 0x611
263 // //MSR 00000611 0000-0000-3212-A857
264 // #define MSR_PKG_PERF_STATUS 0x613
265 // #define MSR_PKG_POWER_INFO 0x614
266 // //MSR 00000614 0000-0000-01E0-02F8
267 // // Sandy Bridge IA (Core) domain MSR's.
268 // #define MSR_PP0_POWER_LIMIT 0x638
269 // #define MSR_PP0_ENERGY_STATUS 0x639
270 // #define MSR_PP0_POLICY 0x63A
271 // #define MSR_PP0_PERF_STATUS 0x63B
272 //
273 // // Sandy Bridge Uncore (IGPU) domain MSR's (Not on JakeTown).
274 // #define MSR_PP1_POWER_LIMIT 0x640
275 // #define MSR_PP1_ENERGY_STATUS 0x641
276 // //MSR 00000641 0000-0000-0000-0000
277 // #define MSR_PP1_POLICY 0x642
278 //
279 // // JakeTown only Memory MSR's.
280 // #define MSR_DRAM_POWER_LIMIT 0x618
281 // #define MSR_DRAM_ENERGY_STATUS 0x619
282 // #define MSR_DRAM_PERF_STATUS 0x61B
283 // #define MSR_DRAM_POWER_INFO 0x61C
284 //
285 //
286 // //AMD
287 // #define K8_FIDVID_STATUS 0xC0010042
288 // #define K10_COFVID_STATUS 0xC0010071
289 // #define DEFAULT_FSB 100000 /* for now, hardcoding 100MHz for old CPUs */
290
291
292 // /* CPUID Index */
293 // #define CPUID_0 0
294 // #define CPUID_1 1
295 // #define CPUID_2 2
296 // #define CPUID_3 3
297 // #define CPUID_4 4
298 // #define CPUID_80 5
299 // #define CPUID_81 6
300 // #define CPUID_87 7
301 // #define CPUID_MAX 8
302 //
303 // #define EAX 0
304 // #define EBX 1
305 // #define ECX 2
306 // #define EDX 3
307 //
308 // /* CPU Cache */
309 // #define MAX_CACHE_COUNT 4
310 // #define CPU_CACHE_LEVEL 3
311 //
312 // /* PCI */
313 // #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
314 // #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
315 // #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
316 // #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
317 // #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
318 // #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
319 //
320 // #define PCI_CLASS_MEDIA_HDA 0x03
321 //
322 // #define GEN_PMCON_1 0xA0
323 //
324 // #define PCIADDR(bus, dev, func) ((1 << 31) | (bus << 16) | (dev << 11) | (func << 8))
325 // #define REG8(base, reg) ((volatile UINT8 *)(UINTN)base)[(reg)]
326 // #define REG16(base, reg) ((volatile UINT16 *)(UINTN)base)[(reg) >> 1]
327 // #define REG32(base, reg) ((volatile UINT32 *)(UINTN)base)[(reg) >> 2]
328 // #define WRITEREG32(base, reg, value) REG32(base, reg) = value
329
330 #define EFI_HANDLE_TYPE_UNKNOWN 0x000
331 #define EFI_HANDLE_TYPE_IMAGE_HANDLE 0x001
332 #define EFI_HANDLE_TYPE_DRIVER_BINDING_HANDLE 0x002
333 #define EFI_HANDLE_TYPE_DEVICE_DRIVER 0x004
334 #define EFI_HANDLE_TYPE_BUS_DRIVER 0x008
335 #define EFI_HANDLE_TYPE_DRIVER_CONFIGURATION_HANDLE 0x010
336 #define EFI_HANDLE_TYPE_DRIVER_DIAGNOSTICS_HANDLE 0x020
337 #define EFI_HANDLE_TYPE_COMPONENT_NAME_HANDLE 0x040
338 #define EFI_HANDLE_TYPE_DEVICE_HANDLE 0x080
339 #define EFI_HANDLE_TYPE_PARENT_HANDLE 0x100
340 #define EFI_HANDLE_TYPE_CONTROLLER_HANDLE 0x200
341 #define EFI_HANDLE_TYPE_CHILD_HANDLE 0x400
342
343 // #define AML_CHUNK_NONE 0xff
344 // #define AML_CHUNK_ZERO 0x00
345 // #define AML_CHUNK_ONE 0x01
346 // #define AML_CHUNK_ALIAS 0x06
347 // #define AML_CHUNK_NAME 0x08
348 // #define AML_CHUNK_BYTE 0x0A
349 // #define AML_CHUNK_WORD 0x0B
350 // #define AML_CHUNK_DWORD 0x0C
351 // #define AML_CHUNK_STRING 0x0D
352 // #define AML_CHUNK_QWORD 0x0E
353 // #define AML_CHUNK_SCOPE 0x10
354 // #define AML_CHUNK_PACKAGE 0x12
355 // #define AML_CHUNK_METHOD 0x14
356 // #define AML_CHUNK_RETURN 0xA4
357 // #define AML_LOCAL0 0x60
358 // #define AML_STORE_OP 0x70
359
360 // struct aml_chunk
361 // {
362 // UINT8 Type;
363 // UINT16 Length;
364 // CHAR8* Buffer;
365 //
366 // UINT16 Size;
367 //
368 // struct aml_chunk* Next;
369 // struct aml_chunk* First;
370 // struct aml_chunk* Last;
371 // };
372 //
373 // typedef struct aml_chunk AML_CHUNK;
374 //
375 // struct p_state
376 // {
377 // union
378 // {
379 // UINT16 Control;
380 // struct
381 // {
382 // UINT8 VID; // Voltage ID
383 // UINT8 FID; // Frequency ID
384 // };
385 // };
386 //
387 // UINT32 CID; // Compare ID
388 // UINT32 Frequency;
389 // };
390 //
391 // typedef struct p_state P_STATE;
392
393 // typedef enum {
394 // kTagTypeNone,
395 // kTagTypeDict,
396 // kTagTypeKey,
397 // kTagTypeString,
398 // kTagTypeInteger,
399 // kTagTypeData,
400 // kTagTypeDate,
401 // kTagTypeFalse,
402 // kTagTypeTrue,
403 // kTagTypeArray
404 // } TAG_TYPE;
405
406 #pragma pack(1)
407
408 // struct Symbol {
409 // UINT32 refCount;
410 // struct Symbol *next;
411 // CHAR8 string[1];
412 // };
413 //
414 // typedef struct Symbol Symbol, *SymbolPtr;
415
416 // typedef struct {
417 //
418 // UINT32 type;
419 // CHAR8 *string;
420 // UINT32 offset;
421 // VOID *tag;
422 // VOID *tagNext;
423 //
424 // }Tag, *TagPtr;
425 //
426 // typedef struct {
427 //
428 // EFI_ACPI_DESCRIPTION_HEADER Header;
429 // UINT32 Entry;
430 //
431 // } RSDT_TABLE;
432 //
433 // typedef struct {
434 //
435 // EFI_ACPI_DESCRIPTION_HEADER Header;
436 // UINT64 Entry;
437 //
438 // } XSDT_TABLE;
439
440 // typedef struct {
441 //
442 // // SMBIOS TYPE0
443 // CHAR8 VendorName[64];
444 // CHAR8 RomVersion[64];
445 // CHAR8 ReleaseDate[64];
446 // // SMBIOS TYPE1
447 // CHAR8 ManufactureName[64];
448 // CHAR8 ProductName[64];
449 // CHAR8 VersionNr[64];
450 // CHAR8 SerialNr[64];
451 // // CHAR8 Uuid[64];
452 // // CHAR8 SKUNumber[64];
453 // CHAR8 FamilyName[64];
454 // CHAR8 OEMProduct[64];
455 // // SMBIOS TYPE2
456 // CHAR8 BoardManufactureName[64];
457 // CHAR8 BoardSerialNumber[64];
458 // CHAR8 BoardNumber[64]; //Board-ID
459 // CHAR8 LocationInChassis[64];
460 // CHAR8 BoardVersion[64];
461 // CHAR8 OEMBoard[64];
462 // // SMBIOS TYPE3
463 // BOOLEAN Mobile;
464 // CHAR8 ChassisManufacturer[64];
465 // CHAR8 ChassisAssetTag[64];
466 // // SMBIOS TYPE4
467 // UINT16 CpuFreqMHz;
468 // UINT32 BusSpeed; //in kHz
469 // BOOLEAN Turbo;
470 //
471 // // SMBIOS TYPE17
472 // CHAR8 MemoryManufacturer[64];
473 // CHAR8 MemorySerialNumber[64];
474 // CHAR8 MemoryPartNumber[64];
475 // CHAR8 MemorySpeed[64];
476 // // SMBIOS TYPE131
477 // UINT16 CpuType;
478 // // SMBIOS TYPE132
479 // UINT16 QPI;
480 //
481 // // OS parameters
482 // CHAR8 Language[16];
483 // CHAR8 BootArgs[256];
484 // CHAR16 CustomUuid[40];
485 // CHAR16 DefaultBoot[40];
486 //
487 // // GUI parameters
488 // BOOLEAN Debug;
489 //
490 // //ACPI
491 // UINT64 ResetAddr;
492 // UINT8 ResetVal;
493 // BOOLEAN UseDSDTmini;
494 // BOOLEAN DropSSDT;
495 // BOOLEAN GeneratePStates;
496 // BOOLEAN GenerateCStates;
497 // UINT8 PLimitDict;
498 // UINT8 UnderVoltStep;
499 // BOOLEAN LpcTune;
500 // BOOLEAN EnableC2;
501 // BOOLEAN EnableC4;
502 // BOOLEAN EnableC6;
503 // BOOLEAN EnableISS;
504 // BOOLEAN smartUPS;
505 // BOOLEAN PatchNMI;
506 // CHAR16 DsdtName[60];
507 //
508 // //Injections
509 // BOOLEAN StringInjector;
510 // BOOLEAN InjectSystemID;
511 // //Graphics
512 // UINT16 PCIRootUID;
513 // BOOLEAN GraphicsInjector;
514 // BOOLEAN LoadVBios;
515 // BOOLEAN PatchVBios;
516 // CHAR16 FBName[16];
517 // UINT16 VideoPorts;
518 // UINT64 VRAM;
519 // UINT8 Dcfg[8];
520 // UINT8 NVCAP[20];
521 //
522 // // HDA
523 // BOOLEAN HDAInjection;
524 // UINTN HDALayoutId;
525 //
526 // } SETTINGS_DATA;
527
528 // typedef struct {
529 // //values from CPUID
530 // UINT32 CPUID[CPUID_MAX][4];
531 // UINT32 Vendor;
532 // UINT32 Signature;
533 // UINT32 Family;
534 // UINT32 Model;
535 // UINT32 Stepping;
536 // UINT32 Type;
537 // UINT32 Extmodel;
538 // UINT32 Extfamily;
539 // UINT64 Features;
540 // UINT64 ExtFeatures;
541 // UINT32 CoresPerPackage;
542 // UINT32 LogicalPerPackage;
543 // CHAR8 BrandString[48];
544 //
545 // //values from BIOS
546 // UINT32 ExternalClock; //keep this values as kHz
547 // UINT32 MaxSpeed; //MHz
548 // UINT32 CurrentSpeed; //MHz
549 // UINT32 Pad;
550 //
551 // //calculated from MSR
552 // UINT64 MicroCode;
553 // UINT64 ProcessorFlag;
554 // UINT32 MaxRatio;
555 // UINT32 SubDivider;
556 // UINT32 MinRatio;
557 // UINT32 DynFSB;
558 // UINT64 ProcessorInterconnectSpeed;
559 // UINT64 FSBFrequency; //Hz
560 // UINT64 CPUFrequency;
561 // UINT64 TSCFrequency;
562 // UINT8 Cores;
563 // UINT8 EnabledCores;
564 // UINT8 Threads;
565 // UINT8 Mobile; //not for i3-i7
566 //
567 // /* Core i7,5,3 */
568 // UINT16 Turbo1; //1 Core
569 // UINT16 Turbo2; //2 Core
570 // UINT16 Turbo3; //3 Core
571 // UINT16 Turbo4; //4 Core
572 //
573 // } CPU_STRUCTURE;
574
575 // typedef enum {
576 //
577 // MacBook11,
578 // MacBook21,
579 // MacBook41,
580 // MacBook52,
581 // MacBookPro51,
582 // MacBookPro81,
583 // MacBookPro83,
584 // MacBookAir31,
585 // MacMini21,
586 // iMac81,
587 // iMac101,
588 // iMac112,
589 // iMac121,
590 // iMac122,
591 // MacPro31,
592 // MacPro41,
593 // MacPro51
594 //
595 // } MACHINE_TYPES;
596
597 // typedef struct {
598 // UINT8 Type;
599 // UINT8 BankConnections;
600 // UINT8 BankConnectionCount;
601 // UINT32 ModuleSize;
602 // UINT32 Frequency;
603 // CHAR8* Vendor;
604 // CHAR8* PartNo;
605 // CHAR8* SerialNo;
606 // UINT8 *spd;
607 // BOOLEAN InUse;
608 // } RAM_SLOT_INFO;
609 //
610 // #define MAX_SLOT_COUNT 8
611 // #define MAX_RAM_SLOTS 16
612 //
613 // typedef struct {
614 //
615 // UINT64 Frequency;
616 // UINT32 Divider;
617 // UINT8 TRC;
618 // UINT8 TRP;
619 // UINT8 RAS;
620 // UINT8 Channels;
621 // UINT8 Slots;
622 // UINT8 Type;
623 //
624 // RAM_SLOT_INFO DIMM[MAX_RAM_SLOTS];
625 //
626 // } MEM_STRUCTURE;
627 //unused
628 // typedef struct {
629 // UINT8 MaxMemorySlots; // number of memory slots polulated by SMBIOS
630 // UINT8 CntMemorySlots; // number of memory slots counted
631 // UINT16 MemoryModules; // number of memory modules installed
632 // UINT32 DIMM[MAX_RAM_SLOTS]; // Information and SPD mapping for each slot
633 // } DMI;
634
635 // typedef enum {
636 // english, //en
637 // russian, //ru
638 // chinese //cn
639 // //something else? add, please
640 // } LANGUAGES;
641 //
642 // typedef enum {
643 // Unknown,
644 // Ati,
645 // Intel,
646 // Nvidia
647 //
648 // } GFX_MANUFACTERER;
649
650 // typedef struct {
651 // GFX_MANUFACTERER Vendor;
652 // UINT8 Ports;
653 // UINT16 DeviceID;
654 // UINT16 Width;
655 // UINT16 Height;
656 // CHAR8 Model[64];
657 // CHAR8 Config[64];
658 // BOOLEAN LoadVBios;
659 // } GFX_PROPERTIES;
660 #pragma pack(0)
661 //extern CHAR8 *msgbuf;
662 //extern CHAR8 *msgCursor;
663 //extern SMBIOS_STRUCTURE_POINTER SmbiosTable;
664 //extern GFX_PROPERTIES gGraphics[];
665 //extern UINTN NGFX;
666 //extern BOOLEAN gMobile;
667 //extern UINT32 gCpuSpeed; //kHz
668 //extern UINT16 gCPUtype;
669 //extern UINT64 TurboMsr;
670 //extern CHAR8* BiosVendor;
671 /*extern UINT32 mPropSize;
672 extern UINT8* mProperties;
673 extern CHAR8 gSelectedUUID[];
674 extern CHAR8* AppleSystemVersion[];
675 extern CHAR8* AppleFirmwareVersion[];
676 extern CHAR8* AppleReleaseDate[];
677 extern CHAR8* AppleManufacturer;
678 extern CHAR8* AppleProductName[];
679 extern CHAR8* AppleSystemVersion[];
680 extern CHAR8* AppleSerialNumber[];
681 extern CHAR8* AppleFamilies[];
682 extern CHAR8* AppleBoardID[];
683 extern CHAR8* AppleChassisAsset[];
684 extern CHAR8* AppleBoardSN;
685 extern CHAR8* AppleBoardLocation; */
686 // extern EFI_SYSTEM_TABLE* gST;
687 // extern EFI_BOOT_SERVICES* gBS;
688 // extern SETTINGS_DATA gSettings;
689 // extern LANGUAGES gLanguage;
690 // //extern BOOLEAN gFirmwareClover;
691 // extern CPU_STRUCTURE gCPUStructure;
692 //extern EFI_GUID gUuid;
693 //extern EFI_EDID_DISCOVERED_PROTOCOL* EdidDiscovered;
694 //extern UINT8 *gEDID;
695 //extern CHAR8* gDeviceProperties;
696 //extern CHAR8* cDeviceProperties;
697 //extern INPUT_ITEM *InputItems;
698 /*
699 extern EFI_GUID gEfiAppleBootGuid;
700 extern EFI_GUID gEfiAppleNvramGuid;
701 extern EFI_GUID AppleSystemInfoProducerName;
702 extern EFI_GUID AppleDevicePropertyProtocolGuid;
703 extern EFI_GUID gEfiAppleScreenInfoGuid;
704 extern EFI_GUID gEfiAppleVendorGuid;
705 extern EFI_GUID gEfiPartTypeSystemPartGuid;
706 extern EFI_GUID gMsgLogProtocolGuid;
707 extern EFI_GUID gEfiLegacy8259ProtocolGuid;
708
709 extern EFI_EVENT mVirtualAddressChangeEvent;
710 extern EFI_EVENT OnReadyToBootEvent;
711 extern EFI_EVENT ExitBootServiceEvent;
712 extern EFI_EVENT mSimpleFileSystemChangeEvent;
713 extern UINTN gEvent;
714
715 VOID WaitForSts(VOID);
716
717 VOID InitBooterLog(VOID);
718 EFI_STATUS SetupBooterLog(VOID);
719 VOID GetDefaultSettings(VOID);
720 VOID FillInputs(VOID);
721 VOID ApplyInputs(VOID);
722 */
723 // EFI_STATUS StrToGuid (IN CHAR16 *Str, OUT EFI_GUID *Guid);
724 // EFI_STATUS StrToGuidLE (IN CHAR16 *Str, OUT EFI_GUID *Guid);
725 // BOOLEAN hex2bin(IN CHAR8 *hex, OUT UINT8 *bin, INT32 len);
726 // UINT8 hexstrtouint8 (CHAR8* buf); //one or two hex letters to one byte
727
728 EFI_STATUS EFIAPI InitializeConsoleSim (VOID);
729 //EFI_STATUS GuiEventsInitialize (VOID);
730 //Settings.c
731 // UINT32 GetCrc32(UINT8 *Buffer, UINTN Size);
732 // VOID GetCPUProperties (VOID);
733 // VOID GetDevices(VOID);
734 // MACHINE_TYPES GetDefaultModel(VOID);
735 // UINT16 GetAdvancedCpuType(VOID);
736 // //EFI_STATUS GetOSVersion(IN REFIT_VOLUME *Volume);
737 // EFI_STATUS GetUserSettings(IN EFI_FILE *RootDir);
738 // EFI_STATUS GetNVRAMSettings(IN EFI_FILE *RootDir, CHAR16* NVRAMPlistPath);
739 // EFI_STATUS GetEdid(VOID);
740 // //EFI_STATUS SetFSInjection(IN LOADER_ENTRY *Entry);
741
742 // EFI_STATUS
743 // LogDataHub(
744 // EFI_GUID *TypeGuid,
745 // CHAR16 *Name,
746 // VOID *Data,
747 // UINT32 DataSize);
748 //
749 // EFI_STATUS SetVariablesForOSX();
750 // VOID SetupDataForOSX();
751 // EFI_STATUS SetPrivateVarProto(VOID);
752 // VOID SetDevices(VOID);
753 // VOID ScanSPD();
754 //BOOLEAN setup_ati_devprop(pci_dt_t *ati_dev);
755 //BOOLEAN setup_gma_devprop(pci_dt_t *gma_dev);
756 //CHAR8* get_gma_model(IN UINT16 DeviceID);
757 //BOOLEAN setup_nvidia_devprop(pci_dt_t *nvda_dev);
758 //CHAR8* get_nvidia_model(IN UINT16 DeviceID);
759
760
761 //EG_IMAGE * egDecodePNG(IN UINT8 *FileData, IN UINTN FileDataLength, IN UINTN IconSize, IN BOOLEAN WantAlpha);
762
763 //EFI_STATUS PatchACPI(IN REFIT_VOLUME *Volume);
764 //EFI_STATUS PatchACPI_OtherOS(CHAR16* OsSubdir, BOOLEAN DropSSDT);
765 //UINT8 Checksum8(VOID * startPtr, UINT32 len);
766 //BOOLEAN tableSign(CHAR8 *table, CONST CHAR8 *sgn);
767 //VOID SaveOemDsdt(VOID);
768
769 //EFI_STATUS EventsInitialize(VOID);
770 //EFI_STATUS EjectVolume(IN REFIT_VOLUME *Volume);
771
772 //EFI_STATUS bootElTorito(IN REFIT_VOLUME* volume);
773 //EFI_STATUS bootMBR(IN REFIT_VOLUME* volume);
774 //EFI_STATUS bootPBR(IN REFIT_VOLUME* volume);
775
776 //CHAR8* XMLDecode(const CHAR8* src);
777 //EFI_STATUS ParseXML(const CHAR8* buffer, TagPtr * dict);
778 //TagPtr GetProperty( TagPtr dict, const CHAR8* key );
779 //EFI_STATUS XMLParseNextTag(CHAR8* buffer, TagPtr * tag, UINT32* lenPtr);
780 //VOID FreeTag( TagPtr tag );
781 //EFI_STATUS GetNextTag( UINT8* buffer, CHAR8** tag, UINT32* start,UINT32* length);
782
783 //EFI_STATUS SaveSettings(VOID);
784
785 // UINTN iStrLen(CHAR8* String, UINTN MaxLen);
786 // EFI_STATUS PrepatchSmbios(VOID);
787 // VOID PatchSmbios(VOID);
788 // VOID FinalizeSmbios(VOID);
789 //
790 // EFI_STATUS DisableUsbLegacySupport(VOID);
791
792 #endif