1 ;;; verilog-mode.el --- major mode for editing verilog source in Emacs
3 ;; Copyright (C) 1996-2015 Free Software Foundation, Inc.
5 ;; Author: Michael McNamara <mac@verilog.com>
6 ;; Wilson Snyder <wsnyder@wsnyder.org>
7 ;; http://www.verilog.com
8 ;; http://www.veripool.org
10 ;; Keywords: languages
12 ;; Yoni Rabkin <yoni@rabkins.net> contacted the maintainer of this
13 ;; file on 19/3/2008, and the maintainer agreed that when a bug is
14 ;; filed in the Emacs bug reporting system against this file, a copy
15 ;; of the bug report be sent to the maintainer's email address.
17 ;; This code supports Emacs 21.1 and later
18 ;; And XEmacs 21.1 and later
19 ;; Please do not make changes that break Emacs 21. Thanks!
23 ;; This file is part of GNU Emacs.
25 ;; GNU Emacs is free software: you can redistribute it and/or modify
26 ;; it under the terms of the GNU General Public License as published by
27 ;; the Free Software Foundation, either version 3 of the License, or
28 ;; (at your option) any later version.
30 ;; GNU Emacs is distributed in the hope that it will be useful,
31 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
32 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 ;; GNU General Public License for more details.
35 ;; You should have received a copy of the GNU General Public License
36 ;; along with GNU Emacs. If not, see <http://www.gnu.org/licenses/>.
43 ;; A major mode for editing Verilog and SystemVerilog HDL source code (IEEE
44 ;; 1364-2005 and IEEE 1800-2012 standards). When you have entered Verilog
45 ;; mode, you may get more info by pressing C-h m. You may also get online
46 ;; help describing various functions by: C-h f <Name of function you want
49 ;; KNOWN BUGS / BUG REPORTS
50 ;; =======================
52 ;; SystemVerilog is a rapidly evolving language, and hence this mode is
53 ;; under continuous development. Please report any issues to the issue
56 ;; http://www.veripool.org/verilog-mode
58 ;; Please use verilog-submit-bug-report to submit a report; type C-c
59 ;; C-b to invoke this and as a result we will have a much easier time
60 ;; of reproducing the bug you find, and hence fixing it.
62 ;; INSTALLING THE MODE
63 ;; ===================
65 ;; An older version of this mode may be already installed as a part of
66 ;; your environment, and one method of updating would be to update
67 ;; your Emacs environment. Sometimes this is difficult for local
68 ;; political/control reasons, and hence you can always install a
69 ;; private copy (or even a shared copy) which overrides the system
72 ;; You can get step by step help in installing this file by going to
73 ;; <http://www.verilog.com/emacs_install.html>
75 ;; The short list of installation instructions are: To set up
76 ;; automatic Verilog mode, put this file in your load path, and put
77 ;; the following in code (please un comment it first!) in your
78 ;; .emacs, or in your site's site-load.el
80 ; (autoload 'verilog-mode "verilog-mode" "Verilog mode" t )
81 ; (add-to-list 'auto-mode-alist '("\\.[ds]?vh?\\'" . verilog-mode))
83 ;; Be sure to examine at the help for verilog-auto, and the other
84 ;; verilog-auto-* functions for some major coding time savers.
86 ;; If you want to customize Verilog mode to fit your needs better,
87 ;; you may add the below lines (the values of the variables presented
88 ;; here are the defaults). Note also that if you use an Emacs that
89 ;; supports custom, it's probably better to use the custom menu to
90 ;; edit these. If working as a member of a large team these settings
91 ;; should be common across all users (in a site-start file), or set
92 ;; in Local Variables in every file. Otherwise, different people's
93 ;; AUTO expansion may result different whitespace changes.
95 ; ;; Enable syntax highlighting of **all** languages
96 ; (global-font-lock-mode t)
98 ; ;; User customization for Verilog mode
99 ; (setq verilog-indent-level 3
100 ; verilog-indent-level-module 3
101 ; verilog-indent-level-declaration 3
102 ; verilog-indent-level-behavioral 3
103 ; verilog-indent-level-directive 1
104 ; verilog-case-indent 2
105 ; verilog-auto-newline t
106 ; verilog-auto-indent-on-newline t
107 ; verilog-tab-always-indent t
108 ; verilog-auto-endcomments t
109 ; verilog-minimum-comment-distance 40
110 ; verilog-indent-begin-after-if t
111 ; verilog-auto-lineup 'declarations
112 ; verilog-highlight-p1800-keywords nil
113 ; verilog-linter "my_lint_shell_command"
120 ;; See commit history at http://www.veripool.org/verilog-mode.html
121 ;; (This section is required to appease checkdoc.)
125 ;; This variable will always hold the version number of the mode
126 (defconst verilog-mode-version "2015-05-14-6232468-vpo-GNU"
127 "Version of this Verilog mode.")
128 (defconst verilog-mode-release-emacs t
129 "If non-nil, this version of Verilog mode was released with Emacs itself.")
131 (defun verilog-version ()
132 "Inform caller of the version of this file."
134 (message "Using verilog-mode version %s" verilog-mode-version))
136 ;; Insure we have certain packages, and deal with it if we don't
137 ;; Be sure to note which Emacs flavor and version added each feature.
139 ;; Provide stuff if we are XEmacs
140 (when (featurep 'xemacs)
145 (require 'regexp-opt)
147 ;; Bug in 19.28 through 19.30 skeleton.el, not provided.
154 (defmacro when (cond &rest body)
155 (list 'if cond (cons 'progn body))))
158 (if (fboundp 'unless)
160 (defmacro unless (cond &rest body)
161 (cons 'if (cons cond (cons nil body)))))
164 (if (fboundp 'store-match-data)
166 (defmacro store-match-data (&rest _args) nil))
169 (if (fboundp 'char-before)
171 (defmacro char-before (&rest _body)
172 (char-after (1- (point)))))
177 (defsubst point-at-bol (&optional N)
178 (save-excursion (beginning-of-line N) (point))))
183 (defsubst point-at-eol (&optional N)
184 (save-excursion (end-of-line N) (point))))
190 (if (fboundp 'match-string-no-properties)
192 (defsubst match-string-no-properties (num &optional string)
193 "Return string of text matched by last search, without text properties.
194 NUM specifies which parenthesized expression in the last regexp.
195 Value is nil if NUMth pair didn't match, or there were less than NUM pairs.
196 Zero means the entire text matched by the whole regexp or whole string.
197 STRING should be given if the last search was by `string-match' on STRING."
198 (if (match-beginning num)
202 (match-beginning num) (match-end num))))
203 (set-text-properties 0 (length result) nil result)
205 (buffer-substring-no-properties (match-beginning num)
210 (if (and (featurep 'custom) (fboundp 'custom-declare-variable))
211 nil ;; We've got what we needed
212 ;; We have the old custom-library, hack around it!
213 (defmacro defgroup (&rest _args) nil)
214 (defmacro customize (&rest _args)
216 "Sorry, Customize is not available with this version of Emacs"))
217 (defmacro defcustom (var value doc &rest _args)
218 `(defvar ,var ,value ,doc))
220 (if (fboundp 'defface)
222 (defmacro defface (var values doc &rest _args)
226 (if (and (featurep 'custom) (fboundp 'customize-group))
227 nil ;; We've got what we needed
228 ;; We have an intermediate custom-library, hack around it!
229 (defmacro customize-group (var &rest _args)
233 (unless (boundp 'inhibit-point-motion-hooks)
234 (defvar inhibit-point-motion-hooks nil))
235 (unless (boundp 'deactivate-mark)
236 (defvar deactivate-mark nil))
239 ;; OK, do this stuff if we are NOT XEmacs:
240 (unless (featurep 'xemacs)
241 (unless (fboundp 'region-active-p)
242 (defmacro region-active-p ()
243 `(and transient-mark-mode mark-active))))
246 ;; Provide a regular expression optimization routine, using regexp-opt
247 ;; if provided by the user's elisp libraries
249 ;; The below were disabled when GNU Emacs 22 was released;
250 ;; perhaps some still need to be there to support Emacs 21.
251 (if (featurep 'xemacs)
252 (if (fboundp 'regexp-opt)
253 ;; regexp-opt is defined, does it take 3 or 2 arguments?
254 (if (fboundp 'function-max-args)
255 (let ((args (function-max-args `regexp-opt)))
257 ((eq args 3) ;; It takes 3
258 (condition-case nil ; Hide this defun from emacses
259 ;with just a two input regexp
260 (defun verilog-regexp-opt (a b)
261 "Deal with differing number of required arguments for `regexp-opt'.
262 Call `regexp-opt' on A and B."
266 ((eq args 2) ;; It takes 2
267 (defun verilog-regexp-opt (a b)
268 "Call `regexp-opt' on A and B."
272 ;; We can't tell; assume it takes 2
273 (defun verilog-regexp-opt (a b)
274 "Call `regexp-opt' on A and B."
277 ;; There is no regexp-opt, provide our own
278 (defun verilog-regexp-opt (strings &optional paren _shy)
279 (let ((open (if paren "\\(" "")) (close (if paren "\\)" "")))
280 (concat open (mapconcat 'regexp-quote strings "\\|") close)))
283 (defalias 'verilog-regexp-opt 'regexp-opt)))
285 ;; emacs >=22 has looking-back, but older emacs and xemacs don't.
286 ;; This function is lifted directly from emacs's subr.el
287 ;; so that it can be used by xemacs.
288 ;; The idea for this was borrowed from org-mode via this link:
289 ;; https://lists.gnu.org/archive/html/emacs-orgmode/2009-12/msg00032.html
292 ((fboundp 'looking-back)
293 (defalias 'verilog-looking-back 'looking-back))
295 (defun verilog-looking-back (regexp limit &optional greedy)
296 "Return non-nil if text before point matches regular expression REGEXP.
297 Like `looking-at' except matches before point, and is slower.
298 LIMIT if non-nil speeds up the search by specifying a minimum
299 starting position, to avoid checking matches that would start
302 If GREEDY is non-nil, extend the match backwards as far as
303 possible, stopping when a single additional previous character
304 cannot be part of a match for REGEXP. When the match is
305 extended, its starting position is allowed to occur before
308 As a general recommendation, try to avoid using `looking-back'
309 wherever possible, since it is slow."
310 (let ((start (point))
313 (and (re-search-backward (concat "\\(?:" regexp "\\)\\=") limit t)
317 (narrow-to-region (point-min) start)
318 (while (and (> pos (point-min))
322 (looking-at (concat "\\(?:" regexp "\\)\\'"))))
326 (looking-at (concat "\\(?:" regexp "\\)\\'")))))
327 (not (null pos)))))))
330 ;; Both xemacs and emacs
332 (require 'diff) ;; diff-command and diff-switches
335 (require 'compile) ;; compilation-error-regexp-alist-alist
338 (unless (fboundp 'buffer-chars-modified-tick) ;; Emacs 22 added
339 (defmacro buffer-chars-modified-tick () (buffer-modified-tick)))
341 ;; Added in Emacs 24.1
343 (unless (fboundp 'prog-mode)
344 (define-derived-mode prog-mode fundamental-mode "Prog"))
348 (defun verilog-regexp-words (a)
349 "Call 'regexp-opt' with word delimiters for the words A."
350 (concat "\\<" (verilog-regexp-opt a t) "\\>")))
351 (defun verilog-regexp-words (a)
352 "Call 'regexp-opt' with word delimiters for the words A."
353 ;; The FAQ references this function, so user LISP sometimes calls it
354 (concat "\\<" (verilog-regexp-opt a t) "\\>"))
356 (defun verilog-easy-menu-filter (menu)
357 "Filter `easy-menu-define' MENU to support new features."
358 (cond ((not (featurep 'xemacs))
359 menu) ;; GNU Emacs - passthru
360 ;; XEmacs doesn't support :help. Strip it.
361 ;; Recursively filter the a submenu
363 (mapcar 'verilog-easy-menu-filter menu))
364 ;; Look for [:help "blah"] and remove
366 (let ((i 0) (out []))
367 (while (< i (length menu))
368 (if (equal `:help (aref menu i))
370 (setq out (vconcat out (vector (aref menu i)))
373 (t menu))) ;; Default - ok
374 ;;(verilog-easy-menu-filter
375 ;; `("Verilog" ("MA" ["SAA" nil :help "Help SAA"] ["SAB" nil :help "Help SAA"])
376 ;; "----" ["MB" nil :help "Help MB"]))
378 (defun verilog-define-abbrev (table name expansion &optional hook)
379 "Filter `define-abbrev' TABLE NAME EXPANSION and call HOOK.
380 Provides SYSTEM-FLAG in newer Emacs."
382 (define-abbrev table name expansion hook 0 t)
384 (define-abbrev table name expansion hook))))
386 (defun verilog-customize ()
387 "Customize variables and other settings used by Verilog-Mode."
389 (customize-group 'verilog-mode))
391 (defun verilog-font-customize ()
392 "Customize fonts used by Verilog-Mode."
394 (if (fboundp 'customize-apropos)
395 (customize-apropos "font-lock-*" 'faces)))
397 (defun verilog-booleanp (value)
398 "Return t if VALUE is boolean.
399 This implements GNU Emacs 22.1's `booleanp' function in earlier Emacs.
400 This function may be removed when Emacs 21 is no longer supported."
401 (or (equal value t) (equal value nil)))
403 (defun verilog-insert-last-command-event ()
404 "Insert the `last-command-event'."
405 (insert (if (featurep 'xemacs)
406 ;; XEmacs 21.5 doesn't like last-command-event
408 ;; And GNU Emacs 22 has obsoleted last-command-char
409 last-command-event)))
411 (defvar verilog-no-change-functions nil
412 "True if `after-change-functions' is disabled.
413 Use of `syntax-ppss' may break, as ppss's cache may get corrupted.")
415 (defvar verilog-in-hooks nil
416 "True when within a `verilog-run-hooks' block.")
418 (defmacro verilog-run-hooks (&rest hooks)
419 "Run each hook in HOOKS using `run-hooks'.
420 Set `verilog-in-hooks' during this time, to assist AUTO caches."
421 `(let ((verilog-in-hooks t))
422 (run-hooks ,@hooks)))
424 (defun verilog-syntax-ppss (&optional pos)
425 (when verilog-no-change-functions
427 (verilog-scan-cache-flush)
428 ;; else don't let the AUTO code itself get away with flushing the cache,
429 ;; as that'll make things very slow
431 (error "%s: Internal problem; use of syntax-ppss when cache may be corrupt"
432 (verilog-point-text))))
433 (if (fboundp 'syntax-ppss)
435 (parse-partial-sexp (point-min) (or pos (point)))))
437 (defgroup verilog-mode nil
438 "Major mode for Verilog source code."
442 ; (defgroup verilog-mode-fonts nil
443 ; "Facilitates easy customization fonts used in Verilog source text"
444 ; :link '(customize-apropos "font-lock-*" 'faces)
445 ; :group 'verilog-mode)
447 (defgroup verilog-mode-indent nil
448 "Customize indentation and highlighting of Verilog source text."
449 :group 'verilog-mode)
451 (defgroup verilog-mode-actions nil
452 "Customize actions on Verilog source text."
453 :group 'verilog-mode)
455 (defgroup verilog-mode-auto nil
456 "Customize AUTO actions when expanding Verilog source text."
457 :group 'verilog-mode)
459 (defvar verilog-debug nil
460 "Non-nil means enable debug messages for `verilog-mode' internals.")
462 (defvar verilog-warn-fatal nil
463 "Non-nil means `verilog-warn-error' warnings are fatal `error's.")
465 (defcustom verilog-linter
466 "echo 'No verilog-linter set, see \"M-x describe-variable verilog-linter\"'"
467 "Unix program and arguments to call to run a lint checker on Verilog source.
468 Depending on the `verilog-set-compile-command', this may be invoked when
469 you type \\[compile]. When the compile completes, \\[next-error] will take
470 you to the next lint error."
472 :group 'verilog-mode-actions)
473 ;; We don't mark it safe, as it's used as a shell command
475 (defcustom verilog-coverage
476 "echo 'No verilog-coverage set, see \"M-x describe-variable verilog-coverage\"'"
477 "Program and arguments to use to annotate for coverage Verilog source.
478 Depending on the `verilog-set-compile-command', this may be invoked when
479 you type \\[compile]. When the compile completes, \\[next-error] will take
480 you to the next lint error."
482 :group 'verilog-mode-actions)
483 ;; We don't mark it safe, as it's used as a shell command
485 (defcustom verilog-simulator
486 "echo 'No verilog-simulator set, see \"M-x describe-variable verilog-simulator\"'"
487 "Program and arguments to use to interpret Verilog source.
488 Depending on the `verilog-set-compile-command', this may be invoked when
489 you type \\[compile]. When the compile completes, \\[next-error] will take
490 you to the next lint error."
492 :group 'verilog-mode-actions)
493 ;; We don't mark it safe, as it's used as a shell command
495 (defcustom verilog-compiler
496 "echo 'No verilog-compiler set, see \"M-x describe-variable verilog-compiler\"'"
497 "Program and arguments to use to compile Verilog source.
498 Depending on the `verilog-set-compile-command', this may be invoked when
499 you type \\[compile]. When the compile completes, \\[next-error] will take
500 you to the next lint error."
502 :group 'verilog-mode-actions)
503 ;; We don't mark it safe, as it's used as a shell command
505 (defcustom verilog-preprocessor
506 ;; Very few tools give preprocessed output, so we'll default to Verilog-Perl
507 "vppreproc __FLAGS__ __FILE__"
508 "Program and arguments to use to preprocess Verilog source.
509 This is invoked with `verilog-preprocess', and depending on the
510 `verilog-set-compile-command', may also be invoked when you type
511 \\[compile]. When the compile completes, \\[next-error] will
512 take you to the next lint error."
514 :group 'verilog-mode-actions)
515 ;; We don't mark it safe, as it's used as a shell command
517 (defvar verilog-preprocess-history nil
518 "History for `verilog-preprocess'.")
520 (defvar verilog-tool 'verilog-linter
521 "Which tool to use for building compiler-command.
522 Either nil, `verilog-linter', `verilog-compiler',
523 `verilog-coverage', `verilog-preprocessor', or `verilog-simulator'.
524 Alternatively use the \"Choose Compilation Action\" menu. See
525 `verilog-set-compile-command' for more information.")
527 (defcustom verilog-highlight-translate-off nil
528 "Non-nil means background-highlight code excluded from translation.
529 That is, all code between \"// synopsys translate_off\" and
530 \"// synopsys translate_on\" is highlighted using a different background color
531 \(face `verilog-font-lock-translate-off-face').
533 Note: This will slow down on-the-fly fontification (and thus editing).
535 Note: Activate the new setting in a Verilog buffer by re-fontifying it (menu
536 entry \"Fontify Buffer\"). XEmacs: turn off and on font locking."
538 :group 'verilog-mode-indent)
539 ;; Note we don't use :safe, as that would break on Emacsen before 22.0.
540 (put 'verilog-highlight-translate-off 'safe-local-variable 'verilog-booleanp)
542 (defcustom verilog-auto-lineup 'declarations
543 "Type of statements to lineup across multiple lines.
544 If 'all' is selected, then all line ups described below are done.
546 If 'declarations', then just declarations are lined up with any
547 preceding declarations, taking into account widths and the like,
548 so or example the code:
555 If 'assignment', then assignments are lined up with any preceding
556 assignments, so for example the code
557 a_long_variable <= b + c;
560 a_long_variable <= b + c;
563 In order to speed up editing, large blocks of statements are lined up
564 only when a \\[verilog-pretty-expr] is typed; and large blocks of declarations
565 are lineup only when \\[verilog-pretty-declarations] is typed."
567 :type '(radio (const :tag "Line up Assignments and Declarations" all)
568 (const :tag "Line up Assignment statements" assignments )
569 (const :tag "Line up Declarations" declarations)
570 (function :tag "Other"))
571 :group 'verilog-mode-indent )
572 (put 'verilog-auto-lineup 'safe-local-variable
573 '(lambda (x) (memq x '(nil all assignments declarations))))
575 (defcustom verilog-indent-level 3
576 "Indentation of Verilog statements with respect to containing block."
577 :group 'verilog-mode-indent
579 (put 'verilog-indent-level 'safe-local-variable 'integerp)
581 (defcustom verilog-indent-level-module 3
582 "Indentation of Module level Verilog statements (eg always, initial).
583 Set to 0 to get initial and always statements lined up on the left side of
585 :group 'verilog-mode-indent
587 (put 'verilog-indent-level-module 'safe-local-variable 'integerp)
589 (defcustom verilog-indent-level-declaration 3
590 "Indentation of declarations with respect to containing block.
591 Set to 0 to get them list right under containing block."
592 :group 'verilog-mode-indent
594 (put 'verilog-indent-level-declaration 'safe-local-variable 'integerp)
596 (defcustom verilog-indent-declaration-macros nil
597 "How to treat macro expansions in a declaration.
602 If non nil, treat as:
606 :group 'verilog-mode-indent
608 (put 'verilog-indent-declaration-macros 'safe-local-variable 'verilog-booleanp)
610 (defcustom verilog-indent-lists t
611 "How to treat indenting items in a list.
612 If t (the default), indent as:
613 always @( posedge a or
617 always @( posedge a or
619 :group 'verilog-mode-indent
621 (put 'verilog-indent-lists 'safe-local-variable 'verilog-booleanp)
623 (defcustom verilog-indent-level-behavioral 3
624 "Absolute indentation of first begin in a task or function block.
625 Set to 0 to get such code to start at the left side of the screen."
626 :group 'verilog-mode-indent
628 (put 'verilog-indent-level-behavioral 'safe-local-variable 'integerp)
630 (defcustom verilog-indent-level-directive 1
631 "Indentation to add to each level of \\=`ifdef declarations.
632 Set to 0 to have all directives start at the left side of the screen."
633 :group 'verilog-mode-indent
635 (put 'verilog-indent-level-directive 'safe-local-variable 'integerp)
637 (defcustom verilog-cexp-indent 2
638 "Indentation of Verilog statements split across lines."
639 :group 'verilog-mode-indent
641 (put 'verilog-cexp-indent 'safe-local-variable 'integerp)
643 (defcustom verilog-case-indent 2
644 "Indentation for case statements."
645 :group 'verilog-mode-indent
647 (put 'verilog-case-indent 'safe-local-variable 'integerp)
649 (defcustom verilog-auto-newline t
650 "Non-nil means automatically newline after semicolons."
651 :group 'verilog-mode-indent
653 (put 'verilog-auto-newline 'safe-local-variable 'verilog-booleanp)
655 (defcustom verilog-auto-indent-on-newline t
656 "Non-nil means automatically indent line after newline."
657 :group 'verilog-mode-indent
659 (put 'verilog-auto-indent-on-newline 'safe-local-variable 'verilog-booleanp)
661 (defcustom verilog-tab-always-indent t
662 "Non-nil means TAB should always re-indent the current line.
663 A nil value means TAB will only reindent when at the beginning of the line."
664 :group 'verilog-mode-indent
666 (put 'verilog-tab-always-indent 'safe-local-variable 'verilog-booleanp)
668 (defcustom verilog-tab-to-comment nil
669 "Non-nil means TAB moves to the right hand column in preparation for a comment."
670 :group 'verilog-mode-actions
672 (put 'verilog-tab-to-comment 'safe-local-variable 'verilog-booleanp)
674 (defcustom verilog-indent-begin-after-if t
675 "Non-nil means indent begin statements following if, else, while, etc.
676 Otherwise, line them up."
677 :group 'verilog-mode-indent
679 (put 'verilog-indent-begin-after-if 'safe-local-variable 'verilog-booleanp)
681 (defcustom verilog-align-ifelse nil
682 "Non-nil means align `else' under matching `if'.
683 Otherwise else is lined up with first character on line holding matching if."
684 :group 'verilog-mode-indent
686 (put 'verilog-align-ifelse 'safe-local-variable 'verilog-booleanp)
688 (defcustom verilog-minimum-comment-distance 10
689 "Minimum distance (in lines) between begin and end required before a comment.
690 Setting this variable to zero results in every end acquiring a comment; the
691 default avoids too many redundant comments in tight quarters."
692 :group 'verilog-mode-indent
694 (put 'verilog-minimum-comment-distance 'safe-local-variable 'integerp)
696 (defcustom verilog-highlight-p1800-keywords nil
697 "Non-nil means highlight words newly reserved by IEEE-1800.
698 These will appear in `verilog-font-lock-p1800-face' in order to gently
699 suggest changing where these words are used as variables to something else.
700 A nil value means highlight these words as appropriate for the SystemVerilog
701 IEEE-1800 standard. Note that changing this will require restarting Emacs
702 to see the effect as font color choices are cached by Emacs."
703 :group 'verilog-mode-indent
705 (put 'verilog-highlight-p1800-keywords 'safe-local-variable 'verilog-booleanp)
707 (defcustom verilog-highlight-grouping-keywords nil
708 "Non-nil means highlight grouping keywords more dramatically.
709 If false, these words are in the `font-lock-type-face'; if True
710 then they are in `verilog-font-lock-grouping-keywords-face'.
711 Some find that special highlighting on these grouping constructs
712 allow the structure of the code to be understood at a glance."
713 :group 'verilog-mode-indent
715 (put 'verilog-highlight-grouping-keywords 'safe-local-variable 'verilog-booleanp)
717 (defcustom verilog-highlight-modules nil
718 "Non-nil means highlight module statements for `verilog-load-file-at-point'.
719 When true, mousing over module names will allow jumping to the
720 module definition. If false, this is not supported. Setting
721 this is experimental, and may lead to bad performance."
722 :group 'verilog-mode-indent
724 (put 'verilog-highlight-modules 'safe-local-variable 'verilog-booleanp)
726 (defcustom verilog-highlight-includes t
727 "Non-nil means highlight module statements for `verilog-load-file-at-point'.
728 When true, mousing over include file names will allow jumping to the
729 file referenced. If false, this is not supported."
730 :group 'verilog-mode-indent
732 (put 'verilog-highlight-includes 'safe-local-variable 'verilog-booleanp)
734 (defcustom verilog-auto-declare-nettype nil
735 "Non-nil specifies the data type to use with `verilog-auto-input' etc.
736 Set this to \"wire\" if the Verilog code uses \"\\=`default_nettype
737 none\". Note using \\=`default_nettype none isn't recommended practice; this
738 mode is experimental."
739 :version "24.1" ;; rev670
740 :group 'verilog-mode-actions
742 (put 'verilog-auto-declare-nettype 'safe-local-variable `stringp)
744 (defcustom verilog-auto-wire-type nil
745 "Non-nil specifies the data type to use with `verilog-auto-wire' etc.
746 Set this to \"logic\" for SystemVerilog code, or use `verilog-auto-logic'."
747 :version "24.1" ;; rev673
748 :group 'verilog-mode-actions
750 (put 'verilog-auto-wire-type 'safe-local-variable `stringp)
752 (defcustom verilog-auto-endcomments t
753 "Non-nil means insert a comment /* ... */ after 'end's.
754 The name of the function or case will be set between the braces."
755 :group 'verilog-mode-actions
757 (put 'verilog-auto-endcomments 'safe-local-variable 'verilog-booleanp)
759 (defcustom verilog-auto-delete-trailing-whitespace nil
760 "Non-nil means to `delete-trailing-whitespace' in `verilog-auto'."
761 :version "24.1" ;; rev703
762 :group 'verilog-mode-actions
764 (put 'verilog-auto-delete-trailing-whitespace 'safe-local-variable 'verilog-booleanp)
766 (defcustom verilog-auto-ignore-concat nil
767 "Non-nil means ignore signals in {...} concatenations for AUTOWIRE etc.
768 This will exclude signals referenced as pin connections in {...}
769 from AUTOWIRE, AUTOOUTPUT and friends. This flag should be set
770 for backward compatibility only and not set in new designs; it
771 may be removed in future versions."
772 :group 'verilog-mode-actions
774 (put 'verilog-auto-ignore-concat 'safe-local-variable 'verilog-booleanp)
776 (defcustom verilog-auto-read-includes nil
777 "Non-nil means to automatically read includes before AUTOs.
778 This will do a `verilog-read-defines' and `verilog-read-includes' before
779 each AUTO expansion. This makes it easier to embed defines and includes,
780 but can result in very slow reading times if there are many or large
782 :group 'verilog-mode-actions
784 (put 'verilog-auto-read-includes 'safe-local-variable 'verilog-booleanp)
786 (defcustom verilog-auto-save-policy nil
787 "Non-nil indicates action to take when saving a Verilog buffer with AUTOs.
788 A value of `force' will always do a \\[verilog-auto] automatically if
789 needed on every save. A value of `detect' will do \\[verilog-auto]
790 automatically when it thinks necessary. A value of `ask' will query the
791 user when it thinks updating is needed.
793 You should not rely on the 'ask or 'detect policies, they are safeguards
794 only. They do not detect when AUTOINSTs need to be updated because a
795 sub-module's port list has changed."
796 :group 'verilog-mode-actions
797 :type '(choice (const nil) (const ask) (const detect) (const force)))
799 (defcustom verilog-auto-star-expand t
800 "Non-nil means to expand SystemVerilog .* instance ports.
801 They will be expanded in the same way as if there was an AUTOINST in the
802 instantiation. See also `verilog-auto-star' and `verilog-auto-star-save'."
803 :group 'verilog-mode-actions
805 (put 'verilog-auto-star-expand 'safe-local-variable 'verilog-booleanp)
807 (defcustom verilog-auto-star-save nil
808 "Non-nil means save to disk SystemVerilog .* instance expansions.
809 A nil value indicates direct connections will be removed before saving.
810 Only meaningful to those created due to `verilog-auto-star-expand' being set.
812 Instead of setting this, you may want to use /*AUTOINST*/, which will
814 :group 'verilog-mode-actions
816 (put 'verilog-auto-star-save 'safe-local-variable 'verilog-booleanp)
818 (defvar verilog-auto-update-tick nil
819 "Modification tick at which autos were last performed.")
821 (defvar verilog-auto-last-file-locals nil
822 "Text from file-local-variables during last evaluation.")
824 (defvar verilog-diff-function 'verilog-diff-report
825 "Function to run when `verilog-diff-auto' detects differences.
826 Function takes three arguments, the original buffer, the
827 difference buffer, and the point in original buffer with the
832 (defvar verilog-error-regexp-added nil)
834 (defvar verilog-error-regexp-emacs-alist
837 "\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 3)
839 "([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 1 3)
841 ".*\\*[WE],[0-9A-Z]+\\(\[[0-9A-Z_,]+\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)" 2 3)
843 "[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 2)
845 "\\(WARNING\\|ERROR\\|INFO\\)[^:]*: \\([^,]+\\),\\s-+\\(line \\)?\\([0-9]+\\):" 2 4 )
848 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
849 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 2 5)
851 "\\(Error\\|Warning\\).*in file (\\([^ \t]+\\) at line *\\([0-9]+\\))" 2 3)
853 "\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 3)
855 "Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 2)
857 "\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 3)
859 "syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 2)
861 "%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4)
863 "^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 1 2)
865 "List of regexps for Verilog compilers.
866 See `compilation-error-regexp-alist' for the formatting. For Emacs 22+.")
868 (defvar verilog-error-regexp-xemacs-alist
869 ;; Emacs form is '((v-tool "re" 1 2) ...)
870 ;; XEmacs form is '(verilog ("re" 1 2) ...)
871 ;; So we can just map from Emacs to XEmacs
872 (cons 'verilog (mapcar 'cdr verilog-error-regexp-emacs-alist))
873 "List of regexps for Verilog compilers.
874 See `compilation-error-regexp-alist-alist' for the formatting. For XEmacs.")
876 (defvar verilog-error-font-lock-keywords
879 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t)
880 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t)
882 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 1 bold t)
883 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 3 bold t)
884 ;; verilog-IES (nc-verilog)
885 (".*\\*[WE],[0-9A-Z]+\\(\[[0-9A-Z_,]+\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)|" 2 bold t)
886 (".*\\*[WE],[0-9A-Z]+\\(\[[0-9A-Z_,]+\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)|" 3 bold t)
887 ;; verilog-surefire-1
888 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 bold t)
889 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 2 bold t)
890 ;; verilog-surefire-2
891 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 2 bold t)
892 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 3 bold t)
895 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
896 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t)
898 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
899 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t)
901 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 bold t)
902 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 3 bold t)
904 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t)
905 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t)
907 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t)
908 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 3 bold t)
910 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 bold t)
911 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t)
913 (".*%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 bold t)
914 (".*%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 4 bold t)
916 ("^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 1 bold t)
917 ("^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 2 bold t)
919 "Keywords to also highlight in Verilog *compilation* buffers.
920 Only used in XEmacs; GNU Emacs uses `verilog-error-regexp-emacs-alist'.")
922 (defcustom verilog-library-flags '("")
923 "List of standard Verilog arguments to use for /*AUTOINST*/.
924 These arguments are used to find files for `verilog-auto', and match
925 the flags accepted by a standard Verilog-XL simulator.
927 -f filename Reads more `verilog-library-flags' from the filename.
928 +incdir+dir Adds the directory to `verilog-library-directories'.
929 -Idir Adds the directory to `verilog-library-directories'.
930 -y dir Adds the directory to `verilog-library-directories'.
931 +libext+.v Adds the extensions to `verilog-library-extensions'.
932 -v filename Adds the filename to `verilog-library-files'.
934 filename Adds the filename to `verilog-library-files'.
935 This is not recommended, -v is a better choice.
937 You might want these defined in each file; put at the *END* of your file
941 // verilog-library-flags:(\"-y dir -y otherdir\")
944 Verilog-mode attempts to detect changes to this local variable, but they
945 are only insured to be correct when the file is first visited. Thus if you
946 have problems, use \\[find-alternate-file] RET to have these take effect.
948 See also the variables mentioned above."
949 :group 'verilog-mode-auto
950 :type '(repeat string))
951 (put 'verilog-library-flags 'safe-local-variable 'listp)
953 (defcustom verilog-library-directories '(".")
954 "List of directories when looking for files for /*AUTOINST*/.
955 The directory may be relative to the current file, or absolute.
956 Environment variables are also expanded in the directory names.
957 Having at least the current directory is a good idea.
959 You might want these defined in each file; put at the *END* of your file
963 // verilog-library-directories:(\".\" \"subdir\" \"subdir2\")
966 Verilog-mode attempts to detect changes to this local variable, but they
967 are only insured to be correct when the file is first visited. Thus if you
968 have problems, use \\[find-alternate-file] RET to have these take effect.
970 See also `verilog-library-flags', `verilog-library-files'
971 and `verilog-library-extensions'."
972 :group 'verilog-mode-auto
973 :type '(repeat file))
974 (put 'verilog-library-directories 'safe-local-variable 'listp)
976 (defcustom verilog-library-files '()
977 "List of files to search for modules.
978 AUTOINST will use this when it needs to resolve a module name.
979 This is a complete path, usually to a technology file with many standard
982 You might want these defined in each file; put at the *END* of your file
986 // verilog-library-files:(\"/some/path/technology.v\" \"/some/path/tech2.v\")
989 Verilog-mode attempts to detect changes to this local variable, but they
990 are only insured to be correct when the file is first visited. Thus if you
991 have problems, use \\[find-alternate-file] RET to have these take effect.
993 See also `verilog-library-flags', `verilog-library-directories'."
994 :group 'verilog-mode-auto
995 :type '(repeat directory))
996 (put 'verilog-library-files 'safe-local-variable 'listp)
998 (defcustom verilog-library-extensions '(".v" ".sv")
999 "List of extensions to use when looking for files for /*AUTOINST*/.
1000 See also `verilog-library-flags', `verilog-library-directories'."
1001 :type '(repeat string)
1002 :group 'verilog-mode-auto)
1003 (put 'verilog-library-extensions 'safe-local-variable 'listp)
1005 (defcustom verilog-active-low-regexp nil
1006 "If true, treat signals matching this regexp as active low.
1007 This is used for AUTORESET and AUTOTIEOFF. For proper behavior,
1008 you will probably also need `verilog-auto-reset-widths' set."
1009 :group 'verilog-mode-auto
1010 :type '(choice (const nil) regexp))
1011 (put 'verilog-active-low-regexp 'safe-local-variable 'stringp)
1013 (defcustom verilog-auto-sense-include-inputs nil
1014 "Non-nil means AUTOSENSE should include all inputs.
1015 If nil, only inputs that are NOT output signals in the same block are
1017 :group 'verilog-mode-auto
1019 (put 'verilog-auto-sense-include-inputs 'safe-local-variable 'verilog-booleanp)
1021 (defcustom verilog-auto-sense-defines-constant nil
1022 "Non-nil means AUTOSENSE should assume all defines represent constants.
1023 When true, the defines will not be included in sensitivity lists. To
1024 maintain compatibility with other sites, this should be set at the bottom
1025 of each Verilog file that requires it, rather than being set globally."
1026 :group 'verilog-mode-auto
1028 (put 'verilog-auto-sense-defines-constant 'safe-local-variable 'verilog-booleanp)
1030 (defcustom verilog-auto-reset-blocking-in-non t
1031 "Non-nil means AUTORESET will reset blocking statements.
1032 When true, AUTORESET will reset in blocking statements those
1033 signals which were assigned with blocking assignments (=) even in
1034 a block with non-blocking assignments (<=).
1036 If nil, all blocking assigned signals are ignored when any
1037 non-blocking assignment is in the AUTORESET block. This allows
1038 blocking assignments to be used for temporary values and not have
1039 those temporaries reset. See example in `verilog-auto-reset'."
1040 :version "24.1" ;; rev718
1042 :group 'verilog-mode-auto)
1043 (put 'verilog-auto-reset-blocking-in-non 'safe-local-variable 'verilog-booleanp)
1045 (defcustom verilog-auto-reset-widths t
1046 "True means AUTORESET should determine the width of signals.
1047 This is then used to set the width of the zero (32'h0 for example). This
1048 is required by some lint tools that aren't smart enough to ignore widths of
1049 the constant zero. This may result in ugly code when parameters determine
1050 the MSB or LSB of a signal inside an AUTORESET.
1052 If nil, AUTORESET uses \"0\" as the constant.
1054 If 'unbased', AUTORESET used the unbased unsized literal \"'0\"
1055 as the constant. This setting is strongly recommended for
1056 SystemVerilog designs."
1058 :group 'verilog-mode-auto)
1059 (put 'verilog-auto-reset-widths 'safe-local-variable
1060 '(lambda (x) (memq x '(nil t unbased))))
1062 (defcustom verilog-assignment-delay ""
1063 "Text used for delays in delayed assignments. Add a trailing space if set."
1064 :group 'verilog-mode-auto
1066 (put 'verilog-assignment-delay 'safe-local-variable 'stringp)
1068 (defcustom verilog-auto-arg-format 'packed
1069 "Formatting to use for AUTOARG signal names.
1070 If 'packed', then as many inputs and outputs that fit within
1071 `fill-column' will be put onto one line.
1073 If 'single', then a single input or output will be put onto each
1076 :type '(radio (const :tag "Line up Assignments and Declarations" packed)
1077 (const :tag "Line up Assignment statements" single))
1078 :group 'verilog-mode-auto)
1079 (put 'verilog-auto-arg-format 'safe-local-variable
1080 '(lambda (x) (memq x '(packed single))))
1082 (defcustom verilog-auto-arg-sort nil
1083 "Non-nil means AUTOARG signal names will be sorted, not in declaration order.
1084 Declaration order is advantageous with order based instantiations
1085 and is the default for backward compatibility. Sorted order
1086 reduces changes when declarations are moved around in a file, and
1087 it's bad practice to rely on order based instantiations anyhow.
1089 See also `verilog-auto-inst-sort'."
1090 :group 'verilog-mode-auto
1092 (put 'verilog-auto-arg-sort 'safe-local-variable 'verilog-booleanp)
1094 (defcustom verilog-auto-inst-dot-name nil
1095 "Non-nil means when creating ports with AUTOINST, use .name syntax.
1096 This will use \".port\" instead of \".port(port)\" when possible.
1097 This is only legal in SystemVerilog files, and will confuse older
1098 simulators. Setting `verilog-auto-inst-vector' to nil may also
1099 be desirable to increase how often .name will be used."
1100 :group 'verilog-mode-auto
1102 (put 'verilog-auto-inst-dot-name 'safe-local-variable 'verilog-booleanp)
1104 (defcustom verilog-auto-inst-param-value nil
1105 "Non-nil means AUTOINST will replace parameters with the parameter value.
1106 If nil, leave parameters as symbolic names.
1108 Parameters must be in Verilog 2001 format #(...), and if a parameter is not
1109 listed as such there (as when the default value is acceptable), it will not
1110 be replaced, and will remain symbolic.
1112 For example, imagine a submodule uses parameters to declare the size of its
1113 inputs. This is then used by an upper module:
1115 module InstModule (o,i);
1117 input [WIDTH-1:0] i;
1127 Note even though PARAM=10, the AUTOINST has left the parameter as a
1128 symbolic name. If `verilog-auto-inst-param-value' is set, this will
1137 :group 'verilog-mode-auto
1139 (put 'verilog-auto-inst-param-value 'safe-local-variable 'verilog-booleanp)
1141 (defcustom verilog-auto-inst-sort nil
1142 "Non-nil means AUTOINST signals will be sorted, not in declaration order.
1143 Also affects AUTOINSTPARAM. Declaration order is the default for
1144 backward compatibility, and as some teams prefer signals that are
1145 declared together to remain together. Sorted order reduces
1146 changes when declarations are moved around in a file.
1148 See also `verilog-auto-arg-sort'."
1149 :version "24.1" ;; rev688
1150 :group 'verilog-mode-auto
1152 (put 'verilog-auto-inst-sort 'safe-local-variable 'verilog-booleanp)
1154 (defcustom verilog-auto-inst-vector t
1155 "Non-nil means when creating default ports with AUTOINST, use bus subscripts.
1156 If nil, skip the subscript when it matches the entire bus as declared in
1157 the module (AUTOWIRE signals always are subscripted, you must manually
1158 declare the wire to have the subscripts removed.) Setting this to nil may
1159 speed up some simulators, but is less general and harder to read, so avoid."
1160 :group 'verilog-mode-auto
1162 (put 'verilog-auto-inst-vector 'safe-local-variable 'verilog-booleanp)
1164 (defcustom verilog-auto-inst-template-numbers nil
1165 "If true, when creating templated ports with AUTOINST, add a comment.
1167 If t, the comment will add the line number of the template that
1168 was used for that port declaration. This setting is suggested
1169 only for debugging use, as regular use may cause a large numbers
1172 If 'lhs', the comment will show the left hand side of the
1173 AUTO_TEMPLATE rule that is matched. This is less precise than
1174 numbering (t) when multiple rules have the same pin name, but
1175 won't merge conflict."
1176 :group 'verilog-mode-auto
1177 :type '(choice (const nil) (const t) (const lhs)))
1178 (put 'verilog-auto-inst-template-numbers 'safe-local-variable
1179 '(lambda (x) (memq x '(nil t lhs))))
1181 (defcustom verilog-auto-inst-column 40
1182 "Indent-to column number for net name part of AUTOINST created pin."
1183 :group 'verilog-mode-indent
1185 (put 'verilog-auto-inst-column 'safe-local-variable 'integerp)
1187 (defcustom verilog-auto-inst-interfaced-ports nil
1188 "Non-nil means include interfaced ports in AUTOINST expansions."
1189 :version "24.3" ;; rev773, default change rev815
1190 :group 'verilog-mode-auto
1192 (put 'verilog-auto-inst-interfaced-ports 'safe-local-variable 'verilog-booleanp)
1194 (defcustom verilog-auto-input-ignore-regexp nil
1195 "If non-nil, when creating AUTOINPUT, ignore signals matching this regexp.
1196 See the \\[verilog-faq] for examples on using this."
1197 :group 'verilog-mode-auto
1198 :type '(choice (const nil) regexp))
1199 (put 'verilog-auto-input-ignore-regexp 'safe-local-variable 'stringp)
1201 (defcustom verilog-auto-inout-ignore-regexp nil
1202 "If non-nil, when creating AUTOINOUT, ignore signals matching this regexp.
1203 See the \\[verilog-faq] for examples on using this."
1204 :group 'verilog-mode-auto
1205 :type '(choice (const nil) regexp))
1206 (put 'verilog-auto-inout-ignore-regexp 'safe-local-variable 'stringp)
1208 (defcustom verilog-auto-output-ignore-regexp nil
1209 "If non-nil, when creating AUTOOUTPUT, ignore signals matching this regexp.
1210 See the \\[verilog-faq] for examples on using this."
1211 :group 'verilog-mode-auto
1212 :type '(choice (const nil) regexp))
1213 (put 'verilog-auto-output-ignore-regexp 'safe-local-variable 'stringp)
1215 (defcustom verilog-auto-template-warn-unused nil
1216 "Non-nil means report warning if an AUTO_TEMPLATE line is not used.
1217 This feature is not supported before Emacs 21.1 or XEmacs 21.4."
1218 :version "24.3" ;;rev787
1219 :group 'verilog-mode-auto
1221 (put 'verilog-auto-template-warn-unused 'safe-local-variable 'verilog-booleanp)
1223 (defcustom verilog-auto-tieoff-declaration "wire"
1224 "Data type used for the declaration for AUTOTIEOFF.
1225 If \"wire\" then create a wire, if \"assign\" create an
1226 assignment, else the data type for variable creation."
1227 :version "24.1" ;; rev713
1228 :group 'verilog-mode-auto
1230 (put 'verilog-auto-tieoff-declaration 'safe-local-variable 'stringp)
1232 (defcustom verilog-auto-tieoff-ignore-regexp nil
1233 "If non-nil, when creating AUTOTIEOFF, ignore signals matching this regexp.
1234 See the \\[verilog-faq] for examples on using this."
1235 :group 'verilog-mode-auto
1236 :type '(choice (const nil) regexp))
1237 (put 'verilog-auto-tieoff-ignore-regexp 'safe-local-variable 'stringp)
1239 (defcustom verilog-auto-unused-ignore-regexp nil
1240 "If non-nil, when creating AUTOUNUSED, ignore signals matching this regexp.
1241 See the \\[verilog-faq] for examples on using this."
1242 :group 'verilog-mode-auto
1243 :type '(choice (const nil) regexp))
1244 (put 'verilog-auto-unused-ignore-regexp 'safe-local-variable 'stringp)
1246 (defcustom verilog-case-fold t
1247 "Non-nil means `verilog-mode' regexps should ignore case.
1248 This variable is t for backward compatibility; nil is suggested."
1250 :group 'verilog-mode
1252 (put 'verilog-case-fold 'safe-local-variable 'verilog-booleanp)
1254 (defcustom verilog-typedef-regexp nil
1255 "If non-nil, regular expression that matches Verilog-2001 typedef names.
1256 For example, \"_t$\" matches typedefs named with _t, as in the C language.
1257 See also `verilog-case-fold'."
1258 :group 'verilog-mode-auto
1259 :type '(choice (const nil) regexp))
1260 (put 'verilog-typedef-regexp 'safe-local-variable 'stringp)
1262 (defcustom verilog-mode-hook 'verilog-set-compile-command
1263 "Hook run after Verilog mode is loaded."
1265 :group 'verilog-mode)
1267 (defcustom verilog-auto-hook nil
1268 "Hook run after `verilog-mode' updates AUTOs."
1269 :group 'verilog-mode-auto
1272 (defcustom verilog-before-auto-hook nil
1273 "Hook run before `verilog-mode' updates AUTOs."
1274 :group 'verilog-mode-auto
1277 (defcustom verilog-delete-auto-hook nil
1278 "Hook run after `verilog-mode' deletes AUTOs."
1279 :group 'verilog-mode-auto
1282 (defcustom verilog-before-delete-auto-hook nil
1283 "Hook run before `verilog-mode' deletes AUTOs."
1284 :group 'verilog-mode-auto
1287 (defcustom verilog-getopt-flags-hook nil
1288 "Hook run after `verilog-getopt-flags' determines the Verilog option lists."
1289 :group 'verilog-mode-auto
1292 (defcustom verilog-before-getopt-flags-hook nil
1293 "Hook run before `verilog-getopt-flags' determines the Verilog option lists."
1294 :group 'verilog-mode-auto
1297 (defcustom verilog-before-save-font-hook nil
1298 "Hook run before `verilog-save-font-mods' removes highlighting."
1299 :version "24.3" ;;rev735
1300 :group 'verilog-mode-auto
1303 (defcustom verilog-after-save-font-hook nil
1304 "Hook run after `verilog-save-font-mods' restores highlighting."
1305 :version "24.3" ;;rev735
1306 :group 'verilog-mode-auto
1309 (defvar verilog-imenu-generic-expression
1310 '((nil "^\\s-*\\(\\(m\\(odule\\|acromodule\\)\\)\\|primitive\\)\\s-+\\([a-zA-Z0-9_.:]+\\)" 4)
1311 ("*Vars*" "^\\s-*\\(reg\\|wire\\)\\s-+\\(\\|\\[[^]]+\\]\\s-+\\)\\([A-Za-z0-9_]+\\)" 3))
1312 "Imenu expression for Verilog mode. See `imenu-generic-expression'.")
1315 ;; provide a verilog-header function.
1316 ;; Customization variables:
1318 (defvar verilog-date-scientific-format nil
1319 "If non-nil, dates are written in scientific format (e.g. 1997/09/17).
1320 If nil, in European format (e.g. 17.09.1997). The brain-dead American
1321 format (e.g. 09/17/1997) is not supported.")
1323 (defvar verilog-company nil
1324 "Default name of Company for Verilog header.
1325 If set will become buffer local.")
1326 (make-variable-buffer-local 'verilog-company)
1328 (defvar verilog-project nil
1329 "Default name of Project for Verilog header.
1330 If set will become buffer local.")
1331 (make-variable-buffer-local 'verilog-project)
1333 (defvar verilog-mode-map
1334 (let ((map (make-sparse-keymap)))
1335 (define-key map ";" 'electric-verilog-semi)
1336 (define-key map [(control 59)] 'electric-verilog-semi-with-comment)
1337 (define-key map ":" 'electric-verilog-colon)
1338 ;;(define-key map "=" 'electric-verilog-equal)
1339 (define-key map "\`" 'electric-verilog-tick)
1340 (define-key map "\t" 'electric-verilog-tab)
1341 (define-key map "\r" 'electric-verilog-terminate-line)
1342 ;; backspace/delete key bindings
1343 (define-key map [backspace] 'backward-delete-char-untabify)
1344 (unless (boundp 'delete-key-deletes-forward) ; XEmacs variable
1345 (define-key map [delete] 'delete-char)
1346 (define-key map [(meta delete)] 'kill-word))
1347 (define-key map "\M-\C-b" 'electric-verilog-backward-sexp)
1348 (define-key map "\M-\C-f" 'electric-verilog-forward-sexp)
1349 (define-key map "\M-\r" `electric-verilog-terminate-and-indent)
1350 (define-key map "\M-\t" 'verilog-complete-word)
1351 (define-key map "\M-?" 'verilog-show-completions)
1352 ;; Note \C-c and letter are reserved for users
1353 (define-key map "\C-c\`" 'verilog-lint-off)
1354 (define-key map "\C-c\*" 'verilog-delete-auto-star-implicit)
1355 (define-key map "\C-c\?" 'verilog-diff-auto)
1356 (define-key map "\C-c\C-r" 'verilog-label-be)
1357 (define-key map "\C-c\C-i" 'verilog-pretty-declarations)
1358 (define-key map "\C-c=" 'verilog-pretty-expr)
1359 (define-key map "\C-c\C-b" 'verilog-submit-bug-report)
1360 (define-key map "\M-*" 'verilog-star-comment)
1361 (define-key map "\C-c\C-c" 'verilog-comment-region)
1362 (define-key map "\C-c\C-u" 'verilog-uncomment-region)
1363 (when (featurep 'xemacs)
1364 (define-key map [(meta control h)] 'verilog-mark-defun)
1365 (define-key map "\M-\C-a" 'verilog-beg-of-defun)
1366 (define-key map "\M-\C-e" 'verilog-end-of-defun))
1367 (define-key map "\C-c\C-d" 'verilog-goto-defun)
1368 (define-key map "\C-c\C-k" 'verilog-delete-auto)
1369 (define-key map "\C-c\C-a" 'verilog-auto)
1370 (define-key map "\C-c\C-s" 'verilog-auto-save-compile)
1371 (define-key map "\C-c\C-p" 'verilog-preprocess)
1372 (define-key map "\C-c\C-z" 'verilog-inject-auto)
1373 (define-key map "\C-c\C-e" 'verilog-expand-vector)
1374 (define-key map "\C-c\C-h" 'verilog-header)
1376 "Keymap used in Verilog mode.")
1380 verilog-menu verilog-mode-map "Menu for Verilog mode"
1381 (verilog-easy-menu-filter
1383 ("Choose Compilation Action"
1386 (setq verilog-tool nil)
1387 (verilog-set-compile-command))
1389 :selected (equal verilog-tool nil)
1390 :help "When invoking compilation, use compile-command"]
1393 (setq verilog-tool 'verilog-linter)
1394 (verilog-set-compile-command))
1396 :selected (equal verilog-tool `verilog-linter)
1397 :help "When invoking compilation, use lint checker"]
1400 (setq verilog-tool 'verilog-coverage)
1401 (verilog-set-compile-command))
1403 :selected (equal verilog-tool `verilog-coverage)
1404 :help "When invoking compilation, annotate for coverage"]
1407 (setq verilog-tool 'verilog-simulator)
1408 (verilog-set-compile-command))
1410 :selected (equal verilog-tool `verilog-simulator)
1411 :help "When invoking compilation, interpret Verilog source"]
1414 (setq verilog-tool 'verilog-compiler)
1415 (verilog-set-compile-command))
1417 :selected (equal verilog-tool `verilog-compiler)
1418 :help "When invoking compilation, compile Verilog source"]
1421 (setq verilog-tool 'verilog-preprocessor)
1422 (verilog-set-compile-command))
1424 :selected (equal verilog-tool `verilog-preprocessor)
1425 :help "When invoking compilation, preprocess Verilog source, see also `verilog-preprocess'"]
1428 ["Beginning of function" verilog-beg-of-defun
1430 :help "Move backward to the beginning of the current function or procedure"]
1431 ["End of function" verilog-end-of-defun
1433 :help "Move forward to the end of the current function or procedure"]
1434 ["Mark function" verilog-mark-defun
1436 :help "Mark the current Verilog function or procedure"]
1437 ["Goto function/module" verilog-goto-defun
1438 :help "Move to specified Verilog module/task/function"]
1439 ["Move to beginning of block" electric-verilog-backward-sexp
1440 :help "Move backward over one balanced expression"]
1441 ["Move to end of block" electric-verilog-forward-sexp
1442 :help "Move forward over one balanced expression"]
1445 ["Comment Region" verilog-comment-region
1446 :help "Put marked area into a comment"]
1447 ["UnComment Region" verilog-uncomment-region
1448 :help "Uncomment an area commented with Comment Region"]
1449 ["Multi-line comment insert" verilog-star-comment
1450 :help "Insert Verilog /* */ comment at point"]
1451 ["Lint error to comment" verilog-lint-off
1452 :help "Convert a Verilog linter warning line into a disable statement"]
1456 :help "Perform compilation-action (above) on the current buffer"]
1457 ["AUTO, Save, Compile" verilog-auto-save-compile
1458 :help "Recompute AUTOs, save buffer, and compile"]
1459 ["Next Compile Error" next-error
1460 :help "Visit next compilation error message and corresponding source code"]
1461 ["Ignore Lint Warning at point" verilog-lint-off
1462 :help "Convert a Verilog linter warning line into a disable statement"]
1464 ["Line up declarations around point" verilog-pretty-declarations
1465 :help "Line up declarations around point"]
1466 ["Line up equations around point" verilog-pretty-expr
1467 :help "Line up expressions around point"]
1468 ["Redo/insert comments on every end" verilog-label-be
1469 :help "Label matching begin ... end statements"]
1470 ["Expand [x:y] vector line" verilog-expand-vector
1471 :help "Take a signal vector on the current line and expand it to multiple lines"]
1472 ["Insert begin-end block" verilog-insert-block
1473 :help "Insert begin ... end"]
1474 ["Complete word" verilog-complete-word
1475 :help "Complete word at point"]
1477 ["Recompute AUTOs" verilog-auto
1478 :help "Expand AUTO meta-comment statements"]
1479 ["Kill AUTOs" verilog-delete-auto
1480 :help "Remove AUTO expansions"]
1481 ["Diff AUTOs" verilog-diff-auto
1482 :help "Show differences in AUTO expansions"]
1483 ["Inject AUTOs" verilog-inject-auto
1484 :help "Inject AUTOs into legacy non-AUTO buffer"]
1486 ["AUTO General" (describe-function 'verilog-auto)
1487 :help "Help introduction on AUTOs"]
1488 ["AUTO Library Flags" (describe-variable 'verilog-library-flags)
1489 :help "Help on verilog-library-flags"]
1490 ["AUTO Library Path" (describe-variable 'verilog-library-directories)
1491 :help "Help on verilog-library-directories"]
1492 ["AUTO Library Files" (describe-variable 'verilog-library-files)
1493 :help "Help on verilog-library-files"]
1494 ["AUTO Library Extensions" (describe-variable 'verilog-library-extensions)
1495 :help "Help on verilog-library-extensions"]
1496 ["AUTO `define Reading" (describe-function 'verilog-read-defines)
1497 :help "Help on reading `defines"]
1498 ["AUTO `include Reading" (describe-function 'verilog-read-includes)
1499 :help "Help on parsing `includes"]
1500 ["AUTOARG" (describe-function 'verilog-auto-arg)
1501 :help "Help on AUTOARG - declaring module port list"]
1502 ["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum)
1503 :help "Help on AUTOASCIIENUM - creating ASCII for enumerations"]
1504 ["AUTOASSIGNMODPORT" (describe-function 'verilog-auto-assign-modport)
1505 :help "Help on AUTOASSIGNMODPORT - creating assignments to/from modports"]
1506 ["AUTOINOUT" (describe-function 'verilog-auto-inout)
1507 :help "Help on AUTOINOUT - adding inouts from cells"]
1508 ["AUTOINOUTCOMP" (describe-function 'verilog-auto-inout-comp)
1509 :help "Help on AUTOINOUTCOMP - copying complemented i/o from another file"]
1510 ["AUTOINOUTIN" (describe-function 'verilog-auto-inout-in)
1511 :help "Help on AUTOINOUTIN - copying i/o from another file as all inputs"]
1512 ["AUTOINOUTMODPORT" (describe-function 'verilog-auto-inout-modport)
1513 :help "Help on AUTOINOUTMODPORT - copying i/o from an interface modport"]
1514 ["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module)
1515 :help "Help on AUTOINOUTMODULE - copying i/o from another file"]
1516 ["AUTOINOUTPARAM" (describe-function 'verilog-auto-inout-param)
1517 :help "Help on AUTOINOUTPARAM - copying parameters from another file"]
1518 ["AUTOINPUT" (describe-function 'verilog-auto-input)
1519 :help "Help on AUTOINPUT - adding inputs from cells"]
1520 ["AUTOINSERTLISP" (describe-function 'verilog-auto-insert-lisp)
1521 :help "Help on AUTOINSERTLISP - insert text from a lisp function"]
1522 ["AUTOINSERTLAST" (describe-function 'verilog-auto-insert-last)
1523 :help "Help on AUTOINSERTLISPLAST - insert text from a lisp function"]
1524 ["AUTOINST" (describe-function 'verilog-auto-inst)
1525 :help "Help on AUTOINST - adding pins for cells"]
1526 ["AUTOINST (.*)" (describe-function 'verilog-auto-star)
1527 :help "Help on expanding Verilog-2001 .* pins"]
1528 ["AUTOINSTPARAM" (describe-function 'verilog-auto-inst-param)
1529 :help "Help on AUTOINSTPARAM - adding parameter pins to cells"]
1530 ["AUTOLOGIC" (describe-function 'verilog-auto-logic)
1531 :help "Help on AUTOLOGIC - declaring logic signals"]
1532 ["AUTOOUTPUT" (describe-function 'verilog-auto-output)
1533 :help "Help on AUTOOUTPUT - adding outputs from cells"]
1534 ["AUTOOUTPUTEVERY" (describe-function 'verilog-auto-output-every)
1535 :help "Help on AUTOOUTPUTEVERY - adding outputs of all signals"]
1536 ["AUTOREG" (describe-function 'verilog-auto-reg)
1537 :help "Help on AUTOREG - declaring registers for non-wires"]
1538 ["AUTOREGINPUT" (describe-function 'verilog-auto-reg-input)
1539 :help "Help on AUTOREGINPUT - declaring inputs for non-wires"]
1540 ["AUTORESET" (describe-function 'verilog-auto-reset)
1541 :help "Help on AUTORESET - resetting always blocks"]
1542 ["AUTOSENSE or AS" (describe-function 'verilog-auto-sense)
1543 :help "Help on AUTOSENSE - sensitivity lists for always blocks"]
1544 ["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff)
1545 :help "Help on AUTOTIEOFF - tying off unused outputs"]
1546 ["AUTOUNDEF" (describe-function 'verilog-auto-undef)
1547 :help "Help on AUTOUNDEF - undefine all local defines"]
1548 ["AUTOUNUSED" (describe-function 'verilog-auto-unused)
1549 :help "Help on AUTOUNUSED - terminating unused inputs"]
1550 ["AUTOWIRE" (describe-function 'verilog-auto-wire)
1551 :help "Help on AUTOWIRE - declaring wires for cells"]
1554 ["Submit bug report" verilog-submit-bug-report
1555 :help "Submit via mail a bug report on verilog-mode.el"]
1556 ["Version and FAQ" verilog-faq
1557 :help "Show the current version, and where to get the FAQ etc"]
1558 ["Customize Verilog Mode..." verilog-customize
1559 :help "Customize variables and other settings used by Verilog-Mode"]
1560 ["Customize Verilog Fonts & Colors" verilog-font-customize
1561 :help "Customize fonts used by Verilog-Mode."])))
1564 verilog-stmt-menu verilog-mode-map "Menu for statement templates in Verilog."
1565 (verilog-easy-menu-filter
1567 ["Header" verilog-sk-header
1568 :help "Insert a header block at the top of file"]
1569 ["Comment" verilog-sk-comment
1570 :help "Insert a comment block"]
1572 ["Module" verilog-sk-module
1573 :help "Insert a module .. (/*AUTOARG*/);.. endmodule block"]
1574 ["OVM Class" verilog-sk-ovm-class
1575 :help "Insert an OVM class block"]
1576 ["UVM Object" verilog-sk-uvm-object
1577 :help "Insert an UVM object block"]
1578 ["UVM Component" verilog-sk-uvm-component
1579 :help "Insert an UVM component block"]
1580 ["Primitive" verilog-sk-primitive
1581 :help "Insert a primitive .. (.. );.. endprimitive block"]
1583 ["Input" verilog-sk-input
1584 :help "Insert an input declaration"]
1585 ["Output" verilog-sk-output
1586 :help "Insert an output declaration"]
1587 ["Inout" verilog-sk-inout
1588 :help "Insert an inout declaration"]
1589 ["Wire" verilog-sk-wire
1590 :help "Insert a wire declaration"]
1591 ["Reg" verilog-sk-reg
1592 :help "Insert a register declaration"]
1593 ["Define thing under point as a register" verilog-sk-define-signal
1594 :help "Define signal under point as a register at the top of the module"]
1596 ["Initial" verilog-sk-initial
1597 :help "Insert an initial begin .. end block"]
1598 ["Always" verilog-sk-always
1599 :help "Insert an always @(AS) begin .. end block"]
1600 ["Function" verilog-sk-function
1601 :help "Insert a function .. begin .. end endfunction block"]
1602 ["Task" verilog-sk-task
1603 :help "Insert a task .. begin .. end endtask block"]
1604 ["Specify" verilog-sk-specify
1605 :help "Insert a specify .. endspecify block"]
1606 ["Generate" verilog-sk-generate
1607 :help "Insert a generate .. endgenerate block"]
1609 ["Begin" verilog-sk-begin
1610 :help "Insert a begin .. end block"]
1612 :help "Insert an if (..) begin .. end block"]
1613 ["(if) else" verilog-sk-else-if
1614 :help "Insert an else if (..) begin .. end block"]
1615 ["For" verilog-sk-for
1616 :help "Insert a for (...) begin .. end block"]
1617 ["While" verilog-sk-while
1618 :help "Insert a while (...) begin .. end block"]
1619 ["Fork" verilog-sk-fork
1620 :help "Insert a fork begin .. end .. join block"]
1621 ["Repeat" verilog-sk-repeat
1622 :help "Insert a repeat (..) begin .. end block"]
1623 ["Case" verilog-sk-case
1624 :help "Insert a case block, prompting for details"]
1625 ["Casex" verilog-sk-casex
1626 :help "Insert a casex (...) item: begin.. end endcase block"]
1627 ["Casez" verilog-sk-casez
1628 :help "Insert a casez (...) item: begin.. end endcase block"])))
1630 (defvar verilog-mode-abbrev-table nil
1631 "Abbrev table in use in Verilog-mode buffers.")
1633 (define-abbrev-table 'verilog-mode-abbrev-table ())
1634 (verilog-define-abbrev verilog-mode-abbrev-table "class" "" 'verilog-sk-ovm-class)
1635 (verilog-define-abbrev verilog-mode-abbrev-table "always" "" 'verilog-sk-always)
1636 (verilog-define-abbrev verilog-mode-abbrev-table "begin" nil `verilog-sk-begin)
1637 (verilog-define-abbrev verilog-mode-abbrev-table "case" "" `verilog-sk-case)
1638 (verilog-define-abbrev verilog-mode-abbrev-table "for" "" `verilog-sk-for)
1639 (verilog-define-abbrev verilog-mode-abbrev-table "generate" "" `verilog-sk-generate)
1640 (verilog-define-abbrev verilog-mode-abbrev-table "initial" "" `verilog-sk-initial)
1641 (verilog-define-abbrev verilog-mode-abbrev-table "fork" "" `verilog-sk-fork)
1642 (verilog-define-abbrev verilog-mode-abbrev-table "module" "" `verilog-sk-module)
1643 (verilog-define-abbrev verilog-mode-abbrev-table "primitive" "" `verilog-sk-primitive)
1644 (verilog-define-abbrev verilog-mode-abbrev-table "repeat" "" `verilog-sk-repeat)
1645 (verilog-define-abbrev verilog-mode-abbrev-table "specify" "" `verilog-sk-specify)
1646 (verilog-define-abbrev verilog-mode-abbrev-table "task" "" `verilog-sk-task)
1647 (verilog-define-abbrev verilog-mode-abbrev-table "while" "" `verilog-sk-while)
1648 (verilog-define-abbrev verilog-mode-abbrev-table "casex" "" `verilog-sk-casex)
1649 (verilog-define-abbrev verilog-mode-abbrev-table "casez" "" `verilog-sk-casez)
1650 (verilog-define-abbrev verilog-mode-abbrev-table "if" "" `verilog-sk-if)
1651 (verilog-define-abbrev verilog-mode-abbrev-table "else if" "" `verilog-sk-else-if)
1652 (verilog-define-abbrev verilog-mode-abbrev-table "assign" "" `verilog-sk-assign)
1653 (verilog-define-abbrev verilog-mode-abbrev-table "function" "" `verilog-sk-function)
1654 (verilog-define-abbrev verilog-mode-abbrev-table "input" "" `verilog-sk-input)
1655 (verilog-define-abbrev verilog-mode-abbrev-table "output" "" `verilog-sk-output)
1656 (verilog-define-abbrev verilog-mode-abbrev-table "inout" "" `verilog-sk-inout)
1657 (verilog-define-abbrev verilog-mode-abbrev-table "wire" "" `verilog-sk-wire)
1658 (verilog-define-abbrev verilog-mode-abbrev-table "reg" "" `verilog-sk-reg)
1664 (defsubst verilog-within-string ()
1665 (nth 3 (parse-partial-sexp (point-at-bol) (point))))
1667 (defsubst verilog-string-match-fold (regexp string &optional start)
1668 "Like `string-match', but use `verilog-case-fold'.
1669 Return index of start of first match for REGEXP in STRING, or nil.
1670 Matching ignores case if `verilog-case-fold' is non-nil.
1671 If third arg START is non-nil, start search at that index in STRING."
1672 (let ((case-fold-search verilog-case-fold))
1673 (string-match regexp string start)))
1675 (defsubst verilog-string-replace-matches (from-string to-string fixedcase literal string)
1676 "Replace occurrences of FROM-STRING with TO-STRING.
1677 FIXEDCASE and LITERAL as in `replace-match'. STRING is what to replace.
1678 The case (verilog-string-replace-matches \"o\" \"oo\" nil nil \"foobar\")
1679 will break, as the o's continuously replace. xa -> x works ok though."
1680 ;; Hopefully soon to an Emacs built-in
1681 ;; Also note \ in the replacement prevent multiple replacements; IE
1682 ;; (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil "wire@_@")
1683 ;; Gives "wire\([0-9]+\)_@" not "wire\([0-9]+\)_\([0-9]+\)"
1685 (while (string-match from-string string start)
1686 (setq string (replace-match to-string fixedcase literal string)
1687 start (min (length string) (+ (match-beginning 0) (length to-string)))))
1690 (defsubst verilog-string-remove-spaces (string)
1691 "Remove spaces surrounding STRING."
1693 (setq string (verilog-string-replace-matches "^\\s-+" "" nil nil string))
1694 (setq string (verilog-string-replace-matches "\\s-+$" "" nil nil string))
1697 (defsubst verilog-re-search-forward (REGEXP BOUND NOERROR)
1698 ;; checkdoc-params: (REGEXP BOUND NOERROR)
1699 "Like `re-search-forward', but skips over match in comments or strings."
1700 (let ((mdata '(nil nil))) ;; So match-end will return nil if no matches found
1702 (re-search-forward REGEXP BOUND NOERROR)
1703 (setq mdata (match-data))
1704 (and (verilog-skip-forward-comment-or-string)
1706 (setq mdata '(nil nil))
1710 (store-match-data mdata)
1713 (defsubst verilog-re-search-backward (REGEXP BOUND NOERROR)
1714 ;; checkdoc-params: (REGEXP BOUND NOERROR)
1715 "Like `re-search-backward', but skips over match in comments or strings."
1716 (let ((mdata '(nil nil))) ;; So match-end will return nil if no matches found
1718 (re-search-backward REGEXP BOUND NOERROR)
1719 (setq mdata (match-data))
1720 (and (verilog-skip-backward-comment-or-string)
1722 (setq mdata '(nil nil))
1726 (store-match-data mdata)
1729 (defsubst verilog-re-search-forward-quick (regexp bound noerror)
1730 "Like `verilog-re-search-forward', including use of REGEXP BOUND and NOERROR,
1731 but trashes match data and is faster for REGEXP that doesn't match often.
1732 This uses `verilog-scan' and text properties to ignore comments,
1733 so there may be a large up front penalty for the first search."
1735 (while (and (not pt)
1736 (re-search-forward regexp bound noerror))
1737 (if (verilog-inside-comment-or-string-p)
1738 (re-search-forward "[/\"\n]" nil t) ;; Only way a comment or quote can end
1739 (setq pt (match-end 0))))
1742 (defsubst verilog-re-search-backward-quick (regexp bound noerror)
1743 ;; checkdoc-params: (REGEXP BOUND NOERROR)
1744 "Like `verilog-re-search-backward', including use of REGEXP BOUND and NOERROR,
1745 but trashes match data and is faster for REGEXP that doesn't match often.
1746 This uses `verilog-scan' and text properties to ignore comments,
1747 so there may be a large up front penalty for the first search."
1749 (while (and (not pt)
1750 (re-search-backward regexp bound noerror))
1751 (if (verilog-inside-comment-or-string-p)
1752 (re-search-backward "[/\"]" nil t) ;; Only way a comment or quote can begin
1753 (setq pt (match-beginning 0))))
1756 (defsubst verilog-re-search-forward-substr (substr regexp bound noerror)
1757 "Like `re-search-forward', but first search for SUBSTR constant.
1758 Then searched for the normal REGEXP (which contains SUBSTR), with given
1759 BOUND and NOERROR. The REGEXP must fit within a single line.
1760 This speeds up complicated regexp matches."
1761 ;; Problem with overlap: search-forward BAR then FOOBARBAZ won't match.
1762 ;; thus require matches to be on one line, and use beginning-of-line.
1764 (while (and (not done)
1765 (search-forward substr bound noerror))
1768 (setq done (re-search-forward regexp (point-at-eol) noerror)))
1769 (unless (and (<= (match-beginning 0) (point))
1770 (>= (match-end 0) (point)))
1772 (when done (goto-char done))
1774 ;;(verilog-re-search-forward-substr "-end" "get-end-of" nil t) ;;-end (test bait)
1776 (defsubst verilog-re-search-backward-substr (substr regexp bound noerror)
1777 "Like `re-search-backward', but first search for SUBSTR constant.
1778 Then searched for the normal REGEXP (which contains SUBSTR), with given
1779 BOUND and NOERROR. The REGEXP must fit within a single line.
1780 This speeds up complicated regexp matches."
1781 ;; Problem with overlap: search-backward BAR then FOOBARBAZ won't match.
1782 ;; thus require matches to be on one line, and use beginning-of-line.
1784 (while (and (not done)
1785 (search-backward substr bound noerror))
1788 (setq done (re-search-backward regexp (point-at-bol) noerror)))
1789 (unless (and (<= (match-beginning 0) (point))
1790 (>= (match-end 0) (point)))
1792 (when done (goto-char done))
1794 ;;(verilog-re-search-backward-substr "-end" "get-end-of" nil t) ;;-end (test bait)
1796 (defun verilog-delete-trailing-whitespace ()
1797 "Delete trailing spaces or tabs, but not newlines nor linefeeds.
1798 Also add missing final newline.
1800 To call this from the command line, see \\[verilog-batch-diff-auto].
1802 To call on \\[verilog-auto], set `verilog-auto-delete-trailing-whitespace'."
1803 ;; Similar to `delete-trailing-whitespace' but that's not present in XEmacs
1805 (goto-char (point-min))
1806 (while (re-search-forward "[ \t]+$" nil t) ;; Not syntactic WS as no formfeed
1807 (replace-match "" nil nil))
1808 (goto-char (point-max))
1809 (unless (bolp) (insert "\n"))))
1811 (defvar compile-command)
1812 (defvar create-lockfiles) ;; Emacs 24
1814 ;; compilation program
1815 (defun verilog-set-compile-command ()
1816 "Function to compute shell command to compile Verilog.
1818 This reads `verilog-tool' and sets `compile-command'. This specifies the
1819 program that executes when you type \\[compile] or
1820 \\[verilog-auto-save-compile].
1822 By default `verilog-tool' uses a Makefile if one exists in the
1823 current directory. If not, it is set to the `verilog-linter',
1824 `verilog-compiler', `verilog-coverage', `verilog-preprocessor',
1825 or `verilog-simulator' variables, as selected with the Verilog ->
1826 \"Choose Compilation Action\" menu.
1828 You should set `verilog-tool' or the other variables to the path and
1829 arguments for your Verilog simulator. For example:
1832 \"(cd /tmp; surecov %s)\".
1834 In the former case, the path to the current buffer is concat'ed to the
1835 value of `verilog-tool'; in the later, the path to the current buffer is
1836 substituted for the %s.
1838 Where __FLAGS__ appears in the string `verilog-current-flags'
1839 will be substituted.
1841 Where __FILE__ appears in the string, the variable
1842 `buffer-file-name' of the current buffer, without the directory
1843 portion, will be substituted."
1846 ((or (file-exists-p "makefile") ;If there is a makefile, use it
1847 (file-exists-p "Makefile"))
1848 (set (make-local-variable 'compile-command) "make "))
1850 (set (make-local-variable 'compile-command)
1852 (if (string-match "%s" (eval verilog-tool))
1853 (format (eval verilog-tool) (or buffer-file-name ""))
1854 (concat (eval verilog-tool) " " (or buffer-file-name "")))
1856 (verilog-modify-compile-command))
1858 (defun verilog-expand-command (command)
1859 "Replace meta-information in COMMAND and return it.
1860 Where __FLAGS__ appears in the string `verilog-current-flags'
1861 will be substituted. Where __FILE__ appears in the string, the
1862 current buffer's file-name, without the directory portion, will
1864 (setq command (verilog-string-replace-matches
1865 ;; Note \\b only works if under verilog syntax table
1866 "\\b__FLAGS__\\b" (verilog-current-flags)
1868 (setq command (verilog-string-replace-matches
1869 "\\b__FILE__\\b" (file-name-nondirectory
1870 (or (buffer-file-name) ""))
1874 (defun verilog-modify-compile-command ()
1875 "Update `compile-command' using `verilog-expand-command'."
1877 (stringp compile-command)
1878 (string-match "\\b\\(__FLAGS__\\|__FILE__\\)\\b" compile-command))
1879 (set (make-local-variable 'compile-command)
1880 (verilog-expand-command compile-command))))
1882 (if (featurep 'xemacs)
1883 ;; Following code only gets called from compilation-mode-hook on XEmacs to add error handling.
1884 (defun verilog-error-regexp-add-xemacs ()
1885 "Teach XEmacs about verilog errors.
1886 Called by `compilation-mode-hook'. This allows \\[next-error] to
1889 (if (boundp 'compilation-error-regexp-systems-alist)
1891 (not (equal compilation-error-regexp-systems-list 'all))
1892 (not (member compilation-error-regexp-systems-list 'verilog)))
1893 (push 'verilog compilation-error-regexp-systems-list)))
1894 (if (boundp 'compilation-error-regexp-alist-alist)
1895 (if (not (assoc 'verilog compilation-error-regexp-alist-alist))
1896 (setcdr compilation-error-regexp-alist-alist
1897 (cons verilog-error-regexp-xemacs-alist
1898 (cdr compilation-error-regexp-alist-alist)))))
1899 (if (boundp 'compilation-font-lock-keywords)
1901 (set (make-local-variable 'compilation-font-lock-keywords)
1902 verilog-error-font-lock-keywords)
1903 (font-lock-set-defaults)))
1904 ;; Need to re-run compilation-error-regexp builder
1905 (if (fboundp 'compilation-build-compilation-error-regexp-alist)
1906 (compilation-build-compilation-error-regexp-alist))
1909 ;; Following code only gets called from compilation-mode-hook on Emacs to add error handling.
1910 (defun verilog-error-regexp-add-emacs ()
1911 "Tell Emacs compile that we are Verilog.
1912 Called by `compilation-mode-hook'. This allows \\[next-error] to
1915 (if (boundp 'compilation-error-regexp-alist-alist)
1917 (if (not (assoc 'verilog-xl-1 compilation-error-regexp-alist-alist))
1920 (push (car item) compilation-error-regexp-alist)
1921 (push item compilation-error-regexp-alist-alist)
1923 verilog-error-regexp-emacs-alist)))))
1925 (if (featurep 'xemacs) (add-hook 'compilation-mode-hook 'verilog-error-regexp-add-xemacs))
1926 (if (featurep 'emacs) (add-hook 'compilation-mode-hook 'verilog-error-regexp-add-emacs))
1928 (defconst verilog-compiler-directives
1930 '( ;; compiler directives, from IEEE 1800-2012 section 22.1
1931 "`__FILE__" "`__LINE" "`begin_keywords" "`celldefine" "`default_nettype"
1932 "`define" "`else" "`elsif" "`end_keywords" "`endcelldefine" "`endif"
1933 "`ifdef" "`ifndef" "`include" "`line" "`nounconnected_drive" "`pragma"
1934 "`resetall" "`timescale" "`unconnected_drive" "`undef" "`undefineall"
1935 ;; compiler directives not covered by IEEE 1800
1936 "`case" "`default" "`endfor" "`endprotect" "`endswitch" "`endwhile" "`for"
1937 "`format" "`if" "`let" "`protect" "`switch" "`timescale" "`time_scale"
1940 "List of Verilog compiler directives.")
1942 (defconst verilog-directive-re
1943 (verilog-regexp-words verilog-compiler-directives))
1945 (defconst verilog-directive-re-1
1946 (concat "[ \t]*" verilog-directive-re))
1948 (defconst verilog-directive-begin
1949 "\\<`\\(for\\|i\\(f\\|fdef\\|fndef\\)\\|switch\\|while\\)\\>")
1951 (defconst verilog-directive-middle
1952 "\\<`\\(else\\|elsif\\|default\\|case\\)\\>")
1954 (defconst verilog-directive-end
1955 "`\\(endfor\\|endif\\|endswitch\\|endwhile\\)\\>")
1957 (defconst verilog-ovm-begin-re
1961 "`ovm_component_utils_begin"
1962 "`ovm_component_param_utils_begin"
1963 "`ovm_field_utils_begin"
1964 "`ovm_object_utils_begin"
1965 "`ovm_object_param_utils_begin"
1966 "`ovm_sequence_utils_begin"
1967 "`ovm_sequencer_utils_begin"
1970 (defconst verilog-ovm-end-re
1974 "`ovm_component_utils_end"
1975 "`ovm_field_utils_end"
1976 "`ovm_object_utils_end"
1977 "`ovm_sequence_utils_end"
1978 "`ovm_sequencer_utils_end"
1981 (defconst verilog-uvm-begin-re
1985 "`uvm_component_utils_begin"
1986 "`uvm_component_param_utils_begin"
1987 "`uvm_field_utils_begin"
1988 "`uvm_object_utils_begin"
1989 "`uvm_object_param_utils_begin"
1990 "`uvm_sequence_utils_begin"
1991 "`uvm_sequencer_utils_begin"
1994 (defconst verilog-uvm-end-re
1998 "`uvm_component_utils_end"
1999 "`uvm_field_utils_end"
2000 "`uvm_object_utils_end"
2001 "`uvm_sequence_utils_end"
2002 "`uvm_sequencer_utils_end"
2005 (defconst verilog-vmm-begin-re
2009 "`vmm_data_member_begin"
2010 "`vmm_env_member_begin"
2011 "`vmm_scenario_member_begin"
2012 "`vmm_subenv_member_begin"
2013 "`vmm_xactor_member_begin"
2016 (defconst verilog-vmm-end-re
2020 "`vmm_data_member_end"
2021 "`vmm_env_member_end"
2022 "`vmm_scenario_member_end"
2023 "`vmm_subenv_member_end"
2024 "`vmm_xactor_member_end"
2027 (defconst verilog-vmm-statement-re
2031 ;; "`vmm_xactor_member_enum_array"
2032 "`vmm_\\(data\\|env\\|scenario\\|subenv\\|xactor\\)_member_\\(scalar\\|string\\|enum\\|vmm_data\\|channel\\|xactor\\|subenv\\|user_defined\\)\\(_array\\)?"
2033 ;; "`vmm_xactor_member_scalar_array"
2034 ;; "`vmm_xactor_member_scalar"
2037 (defconst verilog-ovm-statement-re
2046 "`ovm_analysis_imp_decl"
2047 "`ovm_blocking_get_imp_decl"
2048 "`ovm_blocking_get_peek_imp_decl"
2049 "`ovm_blocking_master_imp_decl"
2050 "`ovm_blocking_peek_imp_decl"
2051 "`ovm_blocking_put_imp_decl"
2052 "`ovm_blocking_slave_imp_decl"
2053 "`ovm_blocking_transport_imp_decl"
2054 "`ovm_component_registry"
2055 "`ovm_component_registry_param"
2056 "`ovm_component_utils"
2059 "`ovm_declare_sequence_lib"
2066 "`ovm_field_aa_int_byte"
2067 "`ovm_field_aa_int_byte_unsigned"
2068 "`ovm_field_aa_int_int"
2069 "`ovm_field_aa_int_int_unsigned"
2070 "`ovm_field_aa_int_integer"
2071 "`ovm_field_aa_int_integer_unsigned"
2072 "`ovm_field_aa_int_key"
2073 "`ovm_field_aa_int_longint"
2074 "`ovm_field_aa_int_longint_unsigned"
2075 "`ovm_field_aa_int_shortint"
2076 "`ovm_field_aa_int_shortint_unsigned"
2077 "`ovm_field_aa_int_string"
2078 "`ovm_field_aa_object_int"
2079 "`ovm_field_aa_object_string"
2080 "`ovm_field_aa_string_int"
2081 "`ovm_field_aa_string_string"
2082 "`ovm_field_array_int"
2083 "`ovm_field_array_object"
2084 "`ovm_field_array_string"
2089 "`ovm_field_queue_int"
2090 "`ovm_field_queue_object"
2091 "`ovm_field_queue_string"
2092 "`ovm_field_sarray_int"
2097 "`ovm_get_peek_imp_decl"
2104 "`ovm_master_imp_decl"
2106 "`ovm_non_blocking_transport_imp_decl"
2107 "`ovm_nonblocking_get_imp_decl"
2108 "`ovm_nonblocking_get_peek_imp_decl"
2109 "`ovm_nonblocking_master_imp_decl"
2110 "`ovm_nonblocking_peek_imp_decl"
2111 "`ovm_nonblocking_put_imp_decl"
2112 "`ovm_nonblocking_slave_imp_decl"
2113 "`ovm_object_registry"
2114 "`ovm_object_registry_param"
2116 "`ovm_peek_imp_decl"
2117 "`ovm_phase_func_decl"
2118 "`ovm_phase_task_decl"
2119 "`ovm_print_aa_int_object"
2120 "`ovm_print_aa_string_int"
2121 "`ovm_print_aa_string_object"
2122 "`ovm_print_aa_string_string"
2123 "`ovm_print_array_int"
2124 "`ovm_print_array_object"
2125 "`ovm_print_array_string"
2126 "`ovm_print_object_queue"
2127 "`ovm_print_queue_int"
2128 "`ovm_print_string_queue"
2131 "`ovm_rand_send_with"
2133 "`ovm_sequence_utils"
2134 "`ovm_slave_imp_decl"
2135 "`ovm_transport_imp_decl"
2136 "`ovm_update_sequence_lib"
2137 "`ovm_update_sequence_lib_and_item"
2140 "`static_message") nil )))
2142 (defconst verilog-uvm-statement-re
2147 "`uvm_analysis_imp_decl"
2148 "`uvm_blocking_get_imp_decl"
2149 "`uvm_blocking_get_peek_imp_decl"
2150 "`uvm_blocking_master_imp_decl"
2151 "`uvm_blocking_peek_imp_decl"
2152 "`uvm_blocking_put_imp_decl"
2153 "`uvm_blocking_slave_imp_decl"
2154 "`uvm_blocking_transport_imp_decl"
2155 "`uvm_component_param_utils"
2156 "`uvm_component_registry"
2157 "`uvm_component_registry_param"
2158 "`uvm_component_utils"
2161 "`uvm_create_seq" ;; Undocumented in 1.1
2162 "`uvm_declare_p_sequencer"
2163 "`uvm_declare_sequence_lib" ;; Deprecated in 1.1
2166 "`uvm_do_callbacks_exit_on"
2167 "`uvm_do_obj_callbacks"
2168 "`uvm_do_obj_callbacks_exit_on"
2171 "`uvm_do_on_pri_with"
2175 "`uvm_do_seq" ;; Undocumented in 1.1
2176 "`uvm_do_seq_with" ;; Undocumented in 1.1
2179 "`uvm_error_context"
2181 "`uvm_fatal_context"
2182 "`uvm_field_aa_int_byte"
2183 "`uvm_field_aa_int_byte_unsigned"
2184 "`uvm_field_aa_int_enum"
2185 "`uvm_field_aa_int_int"
2186 "`uvm_field_aa_int_int_unsigned"
2187 "`uvm_field_aa_int_integer"
2188 "`uvm_field_aa_int_integer_unsigned"
2189 "`uvm_field_aa_int_key"
2190 "`uvm_field_aa_int_longint"
2191 "`uvm_field_aa_int_longint_unsigned"
2192 "`uvm_field_aa_int_shortint"
2193 "`uvm_field_aa_int_shortint_unsigned"
2194 "`uvm_field_aa_int_string"
2195 "`uvm_field_aa_object_int"
2196 "`uvm_field_aa_object_string"
2197 "`uvm_field_aa_string_int"
2198 "`uvm_field_aa_string_string"
2199 "`uvm_field_array_enum"
2200 "`uvm_field_array_int"
2201 "`uvm_field_array_object"
2202 "`uvm_field_array_string"
2207 "`uvm_field_queue_enum"
2208 "`uvm_field_queue_int"
2209 "`uvm_field_queue_object"
2210 "`uvm_field_queue_string"
2212 "`uvm_field_sarray_enum"
2213 "`uvm_field_sarray_int"
2214 "`uvm_field_sarray_object"
2215 "`uvm_field_sarray_string"
2218 "`uvm_file" ;; Undocumented in 1.1, use `__FILE__
2220 "`uvm_get_peek_imp_decl"
2223 "`uvm_line" ;; Undocumented in 1.1, use `__LINE__
2224 "`uvm_master_imp_decl"
2225 "`uvm_non_blocking_transport_imp_decl" ;; Deprecated in 1.1
2226 "`uvm_nonblocking_get_imp_decl"
2227 "`uvm_nonblocking_get_peek_imp_decl"
2228 "`uvm_nonblocking_master_imp_decl"
2229 "`uvm_nonblocking_peek_imp_decl"
2230 "`uvm_nonblocking_put_imp_decl"
2231 "`uvm_nonblocking_slave_imp_decl"
2232 "`uvm_nonblocking_transport_imp_decl"
2233 "`uvm_object_param_utils"
2234 "`uvm_object_registry"
2235 "`uvm_object_registry_param" ;; Undocumented in 1.1
2249 "`uvm_peek_imp_decl"
2252 "`uvm_rand_send_pri"
2253 "`uvm_rand_send_pri_with"
2254 "`uvm_rand_send_with"
2255 "`uvm_record_attribute"
2260 "`uvm_sequence_utils" ;; Deprecated in 1.1
2261 "`uvm_set_super_type"
2262 "`uvm_slave_imp_decl"
2263 "`uvm_transport_imp_decl"
2265 "`uvm_unpack_arrayN"
2271 "`uvm_unpack_queueN"
2273 "`uvm_unpack_sarray"
2274 "`uvm_unpack_sarrayN"
2275 "`uvm_unpack_string"
2276 "`uvm_update_sequence_lib" ;; Deprecated in 1.1
2277 "`uvm_update_sequence_lib_and_item" ;; Deprecated in 1.1
2279 "`uvm_warning_context") nil )))
2283 ;; Regular expressions used to calculate indent, etc.
2285 (defconst verilog-symbol-re "\\<[a-zA-Z_][a-zA-Z_0-9.]*\\>")
2292 (defconst verilog-assignment-operator-re
2296 ;; blocking assignment_operator
2297 "=" "+=" "-=" "*=" "/=" "%=" "&=" "|=" "^=" "<<=" ">>=" "<<<=" ">>>="
2298 ;; non blocking assignment operator
2301 "==" "!=" "===" "!===" "<=" ">=" "==\?" "!=\?"
2306 ;; Is this a legal verilog operator?
2310 (defconst verilog-assignment-operation-re
2312 ; "\\(^\\s-*[A-Za-z0-9_]+\\(\\[\\([A-Za-z0-9_]+\\)\\]\\)*\\s-*\\)"
2313 ; "\\(^\\s-*[^=<>+-*/%&|^:\\s-]+[^=<>+-*/%&|^\n]*?\\)"
2314 "\\(^.*?\\)" "\\B" verilog-assignment-operator-re "\\B" ))
2316 (defconst verilog-label-re (concat verilog-symbol-re "\\s-*:\\s-*"))
2317 (defconst verilog-property-re
2318 (concat "\\(" verilog-label-re "\\)?"
2319 "\\(\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(assert\\)"))
2320 ;; "\\(assert\\|assume\\|cover\\)\\s-+property\\>"
2322 (defconst verilog-no-indent-begin-re
2324 (verilog-regexp-words
2325 '("always" "always_comb" "always_ff" "always_latch" "initial" "final" ;; procedural blocks
2326 "if" "else" ;; conditional statements
2327 "while" "for" "foreach" "repeat" "do" "forever" )))) ;; loop statements
2329 (defconst verilog-ends-re
2330 ;; Parenthesis indicate type of keyword found
2332 "\\(\\<else\\>\\)\\|" ; 1
2333 "\\(\\<if\\>\\)\\|" ; 2
2334 "\\(\\<assert\\>\\)\\|" ; 3
2335 "\\(\\<end\\>\\)\\|" ; 3.1
2336 "\\(\\<endcase\\>\\)\\|" ; 4
2337 "\\(\\<endfunction\\>\\)\\|" ; 5
2338 "\\(\\<endtask\\>\\)\\|" ; 6
2339 "\\(\\<endspecify\\>\\)\\|" ; 7
2340 "\\(\\<endtable\\>\\)\\|" ; 8
2341 "\\(\\<endgenerate\\>\\)\\|" ; 9
2342 "\\(\\<join\\(_any\\|_none\\)?\\>\\)\\|" ; 10
2343 "\\(\\<endclass\\>\\)\\|" ; 11
2344 "\\(\\<endgroup\\>\\)\\|" ; 12
2346 "\\(\\<`vmm_data_member_end\\>\\)\\|"
2347 "\\(\\<`vmm_env_member_end\\>\\)\\|"
2348 "\\(\\<`vmm_scenario_member_end\\>\\)\\|"
2349 "\\(\\<`vmm_subenv_member_end\\>\\)\\|"
2350 "\\(\\<`vmm_xactor_member_end\\>\\)\\|"
2352 "\\(\\<`ovm_component_utils_end\\>\\)\\|"
2353 "\\(\\<`ovm_field_utils_end\\>\\)\\|"
2354 "\\(\\<`ovm_object_utils_end\\>\\)\\|"
2355 "\\(\\<`ovm_sequence_utils_end\\>\\)\\|"
2356 "\\(\\<`ovm_sequencer_utils_end\\>\\)"
2358 "\\(\\<`uvm_component_utils_end\\>\\)\\|"
2359 "\\(\\<`uvm_field_utils_end\\>\\)\\|"
2360 "\\(\\<`uvm_object_utils_end\\>\\)\\|"
2361 "\\(\\<`uvm_sequence_utils_end\\>\\)\\|"
2362 "\\(\\<`uvm_sequencer_utils_end\\>\\)"
2365 (defconst verilog-auto-end-comment-lines-re
2366 ;; Matches to names in this list cause auto-end-commenting
2368 verilog-directive-re "\\)\\|\\("
2370 (verilog-regexp-words
2399 ;;; NOTE: verilog-leap-to-head expects that verilog-end-block-re and
2400 ;;; verilog-end-block-ordered-re matches exactly the same strings.
2401 (defconst verilog-end-block-ordered-re
2402 ;; Parenthesis indicate type of keyword found
2403 (concat "\\(\\<endcase\\>\\)\\|" ; 1
2404 "\\(\\<end\\>\\)\\|" ; 2
2405 "\\(\\<end" ; 3, but not used
2406 "\\(" ; 4, but not used
2407 "\\(function\\)\\|" ; 5
2409 "\\(module\\)\\|" ; 7
2410 "\\(primitive\\)\\|" ; 8
2411 "\\(interface\\)\\|" ; 9
2412 "\\(package\\)\\|" ; 10
2413 "\\(class\\)\\|" ; 11
2414 "\\(group\\)\\|" ; 12
2415 "\\(program\\)\\|" ; 13
2416 "\\(sequence\\)\\|" ; 14
2417 "\\(clocking\\)\\|" ; 15
2418 "\\(property\\)\\|" ; 16
2420 (defconst verilog-end-block-re
2422 (verilog-regexp-words
2424 `("end" ;; closes begin
2425 "endcase" ;; closes any of case, casex casez or randcase
2426 "join" "join_any" "join_none" ;; closes fork
2441 "`ovm_component_utils_end"
2442 "`ovm_field_utils_end"
2443 "`ovm_object_utils_end"
2444 "`ovm_sequence_utils_end"
2445 "`ovm_sequencer_utils_end"
2447 "`uvm_component_utils_end"
2448 "`uvm_field_utils_end"
2449 "`uvm_object_utils_end"
2450 "`uvm_sequence_utils_end"
2451 "`uvm_sequencer_utils_end"
2453 "`vmm_data_member_end"
2454 "`vmm_env_member_end"
2455 "`vmm_scenario_member_end"
2456 "`vmm_subenv_member_end"
2457 "`vmm_xactor_member_end"
2461 (defconst verilog-endcomment-reason-re
2462 ;; Parenthesis indicate type of keyword found
2464 "\\(\\<begin\\>\\)\\|" ; 1
2465 "\\(\\<else\\>\\)\\|" ; 2
2466 "\\(\\<end\\>\\s-+\\<else\\>\\)\\|" ; 3
2467 "\\(\\<always\\(?:_ff\\)?\\>\\(?:\[ \t\]*@\\)\\)\\|" ; 4 (matches always or always_ff w/ @...)
2468 "\\(\\<always\\(?:_comb\\|_latch\\)?\\>\\)\\|" ; 5 (matches always, always_comb, always_latch w/o @...)
2469 "\\(\\<fork\\>\\)\\|" ; 7
2471 verilog-property-re "\\|"
2472 "\\(\\(" verilog-label-re "\\)?\\<assert\\>\\)\\|"
2473 "\\(\\<clocking\\>\\)\\|"
2474 "\\(\\<task\\>\\)\\|"
2475 "\\(\\<function\\>\\)\\|"
2476 "\\(\\<initial\\>\\)\\|"
2477 "\\(\\<interface\\>\\)\\|"
2478 "\\(\\<package\\>\\)\\|"
2479 "\\(\\<final\\>\\)\\|"
2481 "\\(\\<while\\>\\)\\|\\(\\<do\\>\\)\\|"
2482 "\\(\\<for\\(ever\\|each\\)?\\>\\)\\|"
2483 "\\(\\<repeat\\>\\)\\|\\(\\<wait\\>\\)\\|"
2486 (defconst verilog-named-block-re "begin[ \t]*:")
2488 ;; These words begin a block which can occur inside a module which should be indented,
2489 ;; and closed with the respective word from the end-block list
2491 (defconst verilog-beg-block-re
2493 (verilog-regexp-words
2495 "case" "casex" "casez" "randcase"
2505 "`ovm_component_utils_begin"
2506 "`ovm_component_param_utils_begin"
2507 "`ovm_field_utils_begin"
2508 "`ovm_object_utils_begin"
2509 "`ovm_object_param_utils_begin"
2510 "`ovm_sequence_utils_begin"
2511 "`ovm_sequencer_utils_begin"
2513 "`uvm_component_utils_begin"
2514 "`uvm_component_param_utils_begin"
2515 "`uvm_field_utils_begin"
2516 "`uvm_object_utils_begin"
2517 "`uvm_object_param_utils_begin"
2518 "`uvm_sequence_utils_begin"
2519 "`uvm_sequencer_utils_begin"
2521 "`vmm_data_member_begin"
2522 "`vmm_env_member_begin"
2523 "`vmm_scenario_member_begin"
2524 "`vmm_subenv_member_begin"
2525 "`vmm_xactor_member_begin"
2527 ;; These are the same words, in a specific order in the regular
2528 ;; expression so that matching will work nicely for
2529 ;; verilog-forward-sexp and verilog-calc-indent
2530 (defconst verilog-beg-block-re-ordered
2531 ( concat "\\(\\<begin\\>\\)" ;1
2532 "\\|\\(\\<randcase\\>\\|\\(\\<unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\>\\)" ; 2,3
2533 "\\|\\(\\(\\<disable\\>\\s-+\\|\\<wait\\>\\s-+\\)?fork\\>\\)" ;4,5
2534 "\\|\\(\\<class\\>\\)" ;6
2535 "\\|\\(\\<table\\>\\)" ;7
2536 "\\|\\(\\<specify\\>\\)" ;8
2537 "\\|\\(\\<function\\>\\)" ;9
2538 "\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)*\\<function\\>\\)" ;10
2539 "\\|\\(\\<task\\>\\)" ;14
2540 "\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)*\\<task\\>\\)" ;15
2541 "\\|\\(\\<generate\\>\\)" ;18
2542 "\\|\\(\\<covergroup\\>\\)" ;16 20
2543 "\\|\\(\\(\\(\\<cover\\>\\s-+\\)\\|\\(\\<assert\\>\\s-+\\)\\)*\\<property\\>\\)" ;17 21
2544 "\\|\\(\\<\\(rand\\)?sequence\\>\\)" ;21 25
2545 "\\|\\(\\<clocking\\>\\)" ;22 27
2546 "\\|\\(\\<`[ou]vm_[a-z_]+_begin\\>\\)" ;28
2547 "\\|\\(\\<`vmm_[a-z_]+_member_begin\\>\\)"
2551 (defconst verilog-end-block-ordered-rry
2552 [ "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
2553 "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)"
2554 "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
2555 "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)"
2556 "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)"
2557 "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)"
2558 "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)"
2559 "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)"
2560 "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)"
2561 "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)"
2562 "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)"
2563 "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)"
2564 "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)"
2567 (defconst verilog-nameable-item-re
2569 (verilog-regexp-words
2572 "join" "join_any" "join_none"
2594 (defconst verilog-declaration-opener
2596 (verilog-regexp-words
2597 `("module" "begin" "task" "function"))))
2599 (defconst verilog-declaration-prefix-re
2601 (verilog-regexp-words
2604 "inout" "input" "output" "ref"
2606 "const" "static" "protected" "local"
2608 "localparam" "parameter" "var"
2612 (defconst verilog-declaration-core-re
2614 (verilog-regexp-words
2616 ;; port direction (by themselves)
2617 "inout" "input" "output"
2618 ;; integer_atom_type
2619 "byte" "shortint" "int" "longint" "integer" "time"
2620 ;; integer_vector_type
2623 "shortreal" "real" "realtime"
2625 "supply0" "supply1" "tri" "triand" "trior" "trireg" "tri0" "tri1" "uwire" "wire" "wand" "wor"
2627 "string" "event" "chandle" "virtual" "enum" "genvar"
2630 "mailbox" "semaphore"
2632 (defconst verilog-declaration-re
2633 (concat "\\(" verilog-declaration-prefix-re "\\s-*\\)?" verilog-declaration-core-re))
2634 (defconst verilog-range-re "\\(\\[[^]]*\\]\\s-*\\)+")
2635 (defconst verilog-optional-signed-re "\\s-*\\(\\(un\\)?signed\\)?")
2636 (defconst verilog-optional-signed-range-re
2638 "\\s-*\\(\\<\\(reg\\|wire\\)\\>\\s-*\\)?\\(\\<\\(un\\)?signed\\>\\s-*\\)?\\(" verilog-range-re "\\)?"))
2639 (defconst verilog-macroexp-re "`\\sw+")
2641 (defconst verilog-delay-re "#\\s-*\\(\\([0-9_]+\\('s?[hdxbo][0-9a-fA-F_xz]+\\)?\\)\\|\\(([^()]*)\\)\\|\\(\\sw+\\)\\)")
2642 (defconst verilog-declaration-re-2-no-macro
2643 (concat "\\s-*" verilog-declaration-re
2644 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
2646 (defconst verilog-declaration-re-2-macro
2647 (concat "\\s-*" verilog-declaration-re
2648 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
2649 "\\|\\(" verilog-macroexp-re "\\)"
2651 (defconst verilog-declaration-re-1-macro
2652 (concat "^" verilog-declaration-re-2-macro))
2654 (defconst verilog-declaration-re-1-no-macro (concat "^" verilog-declaration-re-2-no-macro))
2656 (defconst verilog-defun-re
2657 (eval-when-compile (verilog-regexp-words `("macromodule" "module" "class" "program" "interface" "package" "primitive" "config"))))
2658 (defconst verilog-end-defun-re
2659 (eval-when-compile (verilog-regexp-words `("endmodule" "endclass" "endprogram" "endinterface" "endpackage" "endprimitive" "endconfig"))))
2660 (defconst verilog-zero-indent-re
2661 (concat verilog-defun-re "\\|" verilog-end-defun-re))
2662 (defconst verilog-inst-comment-re
2663 (eval-when-compile (verilog-regexp-words `("Outputs" "Inouts" "Inputs" "Interfaces" "Interfaced"))))
2665 (defconst verilog-behavioral-block-beg-re
2666 (eval-when-compile (verilog-regexp-words `("initial" "final" "always" "always_comb" "always_latch" "always_ff"
2667 "function" "task"))))
2668 (defconst verilog-coverpoint-re "\\w+\\s*:\\s*\\(coverpoint\\|cross\\constraint\\)" )
2669 (defconst verilog-in-constraint-re ;; keywords legal in constraint blocks starting a statement/block
2670 (eval-when-compile (verilog-regexp-words `("if" "else" "solve" "foreach"))))
2672 (defconst verilog-indent-re
2674 (verilog-regexp-words
2677 "always" "always_latch" "always_ff" "always_comb"
2679 ; "unique" "priority"
2680 "case" "casex" "casez" "randcase" "endcase"
2682 "clocking" "endclocking"
2683 "config" "endconfig"
2684 "covergroup" "endgroup"
2685 "fork" "join" "join_any" "join_none"
2686 "function" "endfunction"
2688 "generate" "endgenerate"
2690 "interface" "endinterface"
2691 "module" "macromodule" "endmodule"
2692 "package" "endpackage"
2693 "primitive" "endprimitive"
2694 "program" "endprogram"
2695 "property" "endproperty"
2696 "sequence" "randsequence" "endsequence"
2697 "specify" "endspecify"
2704 "`if" "`ifdef" "`ifndef" "`else" "`elsif" "`endif"
2705 "`while" "`endwhile"
2710 "`protect" "`endprotect"
2711 "`switch" "`endswitch"
2715 "`ovm_component_utils_begin"
2716 "`ovm_component_param_utils_begin"
2717 "`ovm_field_utils_begin"
2718 "`ovm_object_utils_begin"
2719 "`ovm_object_param_utils_begin"
2720 "`ovm_sequence_utils_begin"
2721 "`ovm_sequencer_utils_begin"
2723 "`ovm_component_utils_end"
2724 "`ovm_field_utils_end"
2725 "`ovm_object_utils_end"
2726 "`ovm_sequence_utils_end"
2727 "`ovm_sequencer_utils_end"
2729 "`uvm_component_utils_begin"
2730 "`uvm_component_param_utils_begin"
2731 "`uvm_field_utils_begin"
2732 "`uvm_object_utils_begin"
2733 "`uvm_object_param_utils_begin"
2734 "`uvm_sequence_utils_begin"
2735 "`uvm_sequencer_utils_begin"
2737 "`uvm_component_utils_end" ;; Typo in spec, it's not uvm_component_end
2738 "`uvm_field_utils_end"
2739 "`uvm_object_utils_end"
2740 "`uvm_sequence_utils_end"
2741 "`uvm_sequencer_utils_end"
2743 "`vmm_data_member_begin"
2744 "`vmm_env_member_begin"
2745 "`vmm_scenario_member_begin"
2746 "`vmm_subenv_member_begin"
2747 "`vmm_xactor_member_begin"
2749 "`vmm_data_member_end"
2750 "`vmm_env_member_end"
2751 "`vmm_scenario_member_end"
2752 "`vmm_subenv_member_end"
2753 "`vmm_xactor_member_end"
2756 (defconst verilog-defun-level-not-generate-re
2758 (verilog-regexp-words
2759 `( "module" "macromodule" "primitive" "class" "program"
2760 "interface" "package" "config"))))
2762 (defconst verilog-defun-level-re
2764 (verilog-regexp-words
2766 `( "module" "macromodule" "primitive" "class" "program"
2767 "interface" "package" "config")
2768 `( "initial" "final" "always" "always_comb" "always_ff"
2769 "always_latch" "endtask" "endfunction" )))))
2771 (defconst verilog-defun-level-generate-only-re
2773 (verilog-regexp-words
2774 `( "initial" "final" "always" "always_comb" "always_ff"
2775 "always_latch" "endtask" "endfunction" ))))
2777 (defconst verilog-cpp-level-re
2779 (verilog-regexp-words
2781 "endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass"
2783 (defconst verilog-disable-fork-re "\\(disable\\|wait\\)\\s-+fork\\>")
2784 (defconst verilog-extended-case-re "\\(\\(unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
2785 (defconst verilog-extended-complete-re
2786 (concat "\\(\\(\\<extern\\s-+\\|\\<\\(\\<\\(pure\\|context\\)\\>\\s-+\\)?virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)\\)"
2787 "\\|\\(\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)\\)"
2788 "\\|\\(\\(\\<import\\>\\s-+\\)?\\(\"DPI-C\"\\s-+\\)?\\(\\<\\(pure\\|context\\)\\>\\s-+\\)?\\([A-Za-z_][A-Za-z0-9_]*\\s-+=\\s-+\\)?\\(function\\>\\|task\\>\\)\\)"
2789 "\\|" verilog-extended-case-re ))
2790 (defconst verilog-basic-complete-re
2792 (verilog-regexp-words
2794 "always" "assign" "always_latch" "always_ff" "always_comb" "constraint"
2795 "import" "initial" "final" "module" "macromodule" "repeat" "randcase" "while"
2796 "if" "for" "forever" "foreach" "else" "parameter" "do" "localparam" "assert"
2798 (defconst verilog-complete-reg
2800 verilog-extended-complete-re "\\|\\(" verilog-basic-complete-re "\\)"))
2802 (defconst verilog-end-statement-re
2803 (concat "\\(" verilog-beg-block-re "\\)\\|\\("
2804 verilog-end-block-re "\\)"))
2806 (defconst verilog-endcase-re
2807 (concat verilog-extended-case-re "\\|"
2812 (defconst verilog-exclude-str-start "/* -----\\/----- EXCLUDED -----\\/-----"
2813 "String used to mark beginning of excluded text.")
2814 (defconst verilog-exclude-str-end " -----/\\----- EXCLUDED -----/\\----- */"
2815 "String used to mark end of excluded text.")
2816 (defconst verilog-preprocessor-re
2821 (verilog-regexp-words
2829 "`nounconnected_drive"
2831 "`unconnected_drive"
2834 ;; two words: i.e. `ifdef DEFINE
2835 "\\<\\(`elsif\\|`ifn?def\\|`undef\\|`default_nettype\\|`begin_keywords\\)\\>\\s-"
2837 ;; `line number "filename" level
2838 "\\<\\(`line\\)\\>\\s-+[0-9]+\\s-+\"[^\"]+\"\\s-+[012]"
2840 ;;`include "file" or `include <file>
2841 "\\<\\(`include\\)\\>\\s-+\\(?:\"[^\"]+\"\\|<[^>]+>\\)"
2843 ;; `pragma <stuff> (no mention in IEEE 1800-2012 that pragma can span multiple lines
2844 "\\<\\(`pragma\\)\\>\\s-+.+$"
2846 ;; `timescale time_unit / time_precision
2847 "\\<\\(`timescale\\)\\>\\s-+10\\{0,2\\}\\s-*[munpf]?s\\s-*\\/\\s-*10\\{0,2\\}\\s-*[munpf]?s"
2849 ;; `define and `if can span multiple lines if line ends in '\'. NOTE: `if is not IEEE 1800-2012
2850 ;; from http://www.emacswiki.org/emacs/MultilineRegexp
2851 (concat "\\<\\(`define\\|`if\\)\\>" ;; directive
2852 "\\s-+" ;; separator
2853 "\\(?:.*?\\(?:\n.*\\)*?\\)" ;; definition: to end of line, then maybe more lines (excludes any trailing \n)
2854 "\\(?:\n\\s-*\n\\|\\'\\)") ;; blank line or EOF
2856 ;; `<macro>() : i.e. `uvm_info(a,b,c) or any other pre-defined macro
2857 ;; Since parameters inside the macro can have parentheses, and
2858 ;; the macro can span multiple lines, just look for the opening
2859 ;; parentheses and then continue to the end of the first
2861 (concat "\\<`\\w+\\>\\s-*("
2862 "\\(?:.*?\\(?:\n.*\\)*?\\)" ;; definition: to end of line, then maybe more lines (excludes any trailing \n)
2863 "\\(?:\n\\s-*\n\\|\\'\\)") ;; blank line or EOF
2867 (defconst verilog-keywords
2868 (append verilog-compiler-directives
2870 "after" "alias" "always" "always_comb" "always_ff" "always_latch" "and"
2871 "assert" "assign" "assume" "automatic" "before" "begin" "bind"
2872 "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte"
2873 "case" "casex" "casez" "cell" "chandle" "class" "clocking" "cmos"
2874 "config" "const" "constraint" "context" "continue" "cover"
2875 "covergroup" "coverpoint" "cross" "deassign" "default" "defparam"
2876 "design" "disable" "dist" "do" "edge" "else" "end" "endcase"
2877 "endclass" "endclocking" "endconfig" "endfunction" "endgenerate"
2878 "endgroup" "endinterface" "endmodule" "endpackage" "endprimitive"
2879 "endprogram" "endproperty" "endspecify" "endsequence" "endtable"
2880 "endtask" "enum" "event" "expect" "export" "extends" "extern"
2881 "final" "first_match" "for" "force" "foreach" "forever" "fork"
2882 "forkjoin" "function" "generate" "genvar" "highz0" "highz1" "if"
2883 "iff" "ifnone" "ignore_bins" "illegal_bins" "import" "incdir"
2884 "include" "initial" "inout" "input" "inside" "instance" "int"
2885 "integer" "interface" "intersect" "join" "join_any" "join_none"
2886 "large" "liblist" "library" "local" "localparam" "logic"
2887 "longint" "macromodule" "mailbox" "matches" "medium" "modport" "module"
2888 "nand" "negedge" "new" "nmos" "nor" "noshowcancelled" "not"
2889 "notif0" "notif1" "null" "or" "output" "package" "packed"
2890 "parameter" "pmos" "posedge" "primitive" "priority" "program"
2891 "property" "protected" "pull0" "pull1" "pulldown" "pullup"
2892 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
2893 "randcase" "randsequence" "rcmos" "real" "realtime" "ref" "reg"
2894 "release" "repeat" "return" "rnmos" "rpmos" "rtran" "rtranif0"
2895 "rtranif1" "scalared" "semaphore" "sequence" "shortint" "shortreal"
2896 "showcancelled" "signed" "small" "solve" "specify" "specparam"
2897 "static" "string" "strong0" "strong1" "struct" "super" "supply0"
2898 "supply1" "table" "tagged" "task" "this" "throughout" "time"
2899 "timeprecision" "timeunit" "tran" "tranif0" "tranif1" "tri"
2900 "tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union"
2901 "unique" "unsigned" "use" "uwire" "var" "vectored" "virtual" "void"
2902 "wait" "wait_order" "wand" "weak0" "weak1" "while" "wildcard"
2903 "wire" "with" "within" "wor" "xnor" "xor"
2905 "accept_on" "checker" "endchecker" "eventually" "global" "implies"
2906 "let" "nexttime" "reject_on" "restrict" "s_always" "s_eventually"
2907 "s_nexttime" "s_until" "s_until_with" "strong" "sync_accept_on"
2908 "sync_reject_on" "unique0" "until" "until_with" "untyped" "weak"
2910 "implements" "interconnect" "nettype" "soft"
2912 "List of Verilog keywords.")
2914 (defconst verilog-comment-start-regexp "//\\|/\\*"
2915 "Dual comment value for `comment-start-regexp'.")
2917 (defvar verilog-mode-syntax-table
2918 (let ((table (make-syntax-table)))
2919 ;; Populate the syntax TABLE.
2920 (modify-syntax-entry ?\\ "\\" table)
2921 (modify-syntax-entry ?+ "." table)
2922 (modify-syntax-entry ?- "." table)
2923 (modify-syntax-entry ?= "." table)
2924 (modify-syntax-entry ?% "." table)
2925 (modify-syntax-entry ?< "." table)
2926 (modify-syntax-entry ?> "." table)
2927 (modify-syntax-entry ?& "." table)
2928 (modify-syntax-entry ?| "." table)
2929 ;; FIXME: This goes against Emacs conventions. Use "_" syntax instead and
2930 ;; then use regexps with things like "\\_<...\\_>".
2931 (modify-syntax-entry ?` "w" table) ;; ` is part of definition symbols in Verilog
2932 (modify-syntax-entry ?_ "w" table)
2933 (modify-syntax-entry ?\' "." table)
2935 ;; Set up TABLE to handle block and line style comments.
2936 (if (featurep 'xemacs)
2938 ;; XEmacs (formerly Lucid) has the best implementation
2939 (modify-syntax-entry ?/ ". 1456" table)
2940 (modify-syntax-entry ?* ". 23" table)
2941 (modify-syntax-entry ?\n "> b" table))
2942 ;; Emacs does things differently, but we can work with it
2943 (modify-syntax-entry ?/ ". 124b" table)
2944 (modify-syntax-entry ?* ". 23" table)
2945 (modify-syntax-entry ?\n "> b" table))
2947 "Syntax table used in Verilog mode buffers.")
2949 (defvar verilog-font-lock-keywords nil
2950 "Default highlighting for Verilog mode.")
2952 (defvar verilog-font-lock-keywords-1 nil
2953 "Subdued level highlighting for Verilog mode.")
2955 (defvar verilog-font-lock-keywords-2 nil
2956 "Medium level highlighting for Verilog mode.
2957 See also `verilog-font-lock-extra-types'.")
2959 (defvar verilog-font-lock-keywords-3 nil
2960 "Gaudy level highlighting for Verilog mode.
2961 See also `verilog-font-lock-extra-types'.")
2963 (defvar verilog-font-lock-translate-off-face
2964 'verilog-font-lock-translate-off-face
2965 "Font to use for translated off regions.")
2966 (defface verilog-font-lock-translate-off-face
2969 (:background "gray90" :italic t ))
2972 (:background "gray10" :italic t ))
2973 (((class grayscale) (background light))
2974 (:foreground "DimGray" :italic t))
2975 (((class grayscale) (background dark))
2976 (:foreground "LightGray" :italic t))
2978 "Font lock mode face used to background highlight translate-off regions."
2979 :group 'font-lock-highlighting-faces)
2981 (defvar verilog-font-lock-p1800-face
2982 'verilog-font-lock-p1800-face
2983 "Font to use for p1800 keywords.")
2984 (defface verilog-font-lock-p1800-face
2987 (:foreground "DarkOrange3" :bold t ))
2990 (:foreground "orange1" :bold t ))
2992 "Font lock mode face used to highlight P1800 keywords."
2993 :group 'font-lock-highlighting-faces)
2995 (defvar verilog-font-lock-ams-face
2996 'verilog-font-lock-ams-face
2997 "Font to use for Analog/Mixed Signal keywords.")
2998 (defface verilog-font-lock-ams-face
3001 (:foreground "Purple" :bold t ))
3004 (:foreground "orange1" :bold t ))
3006 "Font lock mode face used to highlight AMS keywords."
3007 :group 'font-lock-highlighting-faces)
3009 (defvar verilog-font-grouping-keywords-face
3010 'verilog-font-lock-grouping-keywords-face
3011 "Font to use for Verilog Grouping Keywords (such as begin..end).")
3012 (defface verilog-font-lock-grouping-keywords-face
3015 (:foreground "Purple" :bold t ))
3018 (:foreground "orange1" :bold t ))
3020 "Font lock mode face used to highlight verilog grouping keywords."
3021 :group 'font-lock-highlighting-faces)
3023 (let* ((verilog-type-font-keywords
3027 "and" "bit" "buf" "bufif0" "bufif1" "cmos" "defparam"
3028 "event" "genvar" "inout" "input" "integer" "localparam"
3029 "logic" "mailbox" "nand" "nmos" "nor" "not" "notif0" "notif1" "or"
3030 "output" "parameter" "pmos" "pull0" "pull1" "pulldown" "pullup"
3031 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran"
3032 "rtranif0" "rtranif1" "semaphore" "signed" "struct" "supply"
3033 "supply0" "supply1" "time" "tran" "tranif0" "tranif1"
3034 "tri" "tri0" "tri1" "triand" "trior" "trireg" "typedef"
3035 "uwire" "vectored" "wand" "wire" "wor" "xnor" "xor"
3038 (verilog-pragma-keywords
3041 '("surefire" "auto" "synopsys" "rtl_synthesis" "verilint" "leda" "0in"
3044 (verilog-1800-2005-keywords
3047 '("alias" "assert" "assume" "automatic" "before" "bind"
3048 "bins" "binsof" "break" "byte" "cell" "chandle" "class"
3049 "clocking" "config" "const" "constraint" "context" "continue"
3050 "cover" "covergroup" "coverpoint" "cross" "deassign" "design"
3051 "dist" "do" "edge" "endclass" "endclocking" "endconfig"
3052 "endgroup" "endprogram" "endproperty" "endsequence" "enum"
3053 "expect" "export" "extends" "extern" "first_match" "foreach"
3054 "forkjoin" "genvar" "highz0" "highz1" "ifnone" "ignore_bins"
3055 "illegal_bins" "import" "incdir" "include" "inside" "instance"
3056 "int" "intersect" "large" "liblist" "library" "local" "longint"
3057 "matches" "medium" "modport" "new" "noshowcancelled" "null"
3058 "packed" "program" "property" "protected" "pull0" "pull1"
3059 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
3060 "randcase" "randsequence" "ref" "release" "return" "scalared"
3061 "sequence" "shortint" "shortreal" "showcancelled" "small" "solve"
3062 "specparam" "static" "string" "strong0" "strong1" "struct"
3063 "super" "tagged" "this" "throughout" "timeprecision" "timeunit"
3064 "type" "union" "unsigned" "use" "var" "virtual" "void"
3065 "wait_order" "weak0" "weak1" "wildcard" "with" "within"
3068 (verilog-1800-2009-keywords
3071 '("accept_on" "checker" "endchecker" "eventually" "global"
3072 "implies" "let" "nexttime" "reject_on" "restrict" "s_always"
3073 "s_eventually" "s_nexttime" "s_until" "s_until_with" "strong"
3074 "sync_accept_on" "sync_reject_on" "unique0" "until"
3075 "until_with" "untyped" "weak" ) nil )))
3077 (verilog-1800-2012-keywords
3080 '("implements" "interconnect" "nettype" "soft" ) nil )))
3082 (verilog-ams-keywords
3085 '("above" "abs" "absdelay" "acos" "acosh" "ac_stim"
3086 "aliasparam" "analog" "analysis" "asin" "asinh" "atan" "atan2" "atanh"
3087 "branch" "ceil" "connectmodule" "connectrules" "cos" "cosh" "ddt"
3088 "ddx" "discipline" "driver_update" "enddiscipline" "endconnectrules"
3089 "endnature" "endparamset" "exclude" "exp" "final_step" "flicker_noise"
3090 "floor" "flow" "from" "ground" "hypot" "idt" "idtmod" "inf"
3091 "initial_step" "laplace_nd" "laplace_np" "laplace_zd" "laplace_zp"
3092 "last_crossing" "limexp" "ln" "log" "max" "min" "nature"
3093 "net_resolution" "noise_table" "paramset" "potential" "pow" "sin"
3094 "sinh" "slew" "sqrt" "tan" "tanh" "timer" "transition" "white_noise"
3095 "wreal" "zi_nd" "zi_np" "zi_zd" ) nil )))
3097 (verilog-font-keywords
3101 "assign" "case" "casex" "casez" "randcase" "deassign"
3102 "default" "disable" "else" "endcase" "endfunction"
3103 "endgenerate" "endinterface" "endmodule" "endprimitive"
3104 "endspecify" "endtable" "endtask" "final" "for" "force" "return" "break"
3105 "continue" "forever" "fork" "function" "generate" "if" "iff" "initial"
3106 "interface" "join" "join_any" "join_none" "macromodule" "module" "negedge"
3107 "package" "endpackage" "always" "always_comb" "always_ff"
3108 "always_latch" "posedge" "primitive" "priority" "release"
3109 "repeat" "specify" "table" "task" "unique" "wait" "while"
3110 "class" "program" "endclass" "endprogram"
3113 (verilog-font-grouping-keywords
3116 '( "begin" "end" ) nil ))))
3118 (setq verilog-font-lock-keywords
3120 ;; Fontify all builtin keywords
3121 (concat "\\<\\(" verilog-font-keywords "\\|"
3122 ;; And user/system tasks and functions
3123 "\\$[a-zA-Z][a-zA-Z0-9_\\$]*"
3125 ;; Fontify all types
3126 (if verilog-highlight-grouping-keywords
3127 (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
3128 'verilog-font-lock-grouping-keywords-face)
3129 (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
3130 'font-lock-type-face))
3131 (cons (concat "\\<\\(" verilog-type-font-keywords "\\)\\>")
3132 'font-lock-type-face)
3133 ;; Fontify IEEE-1800-2005 keywords appropriately
3134 (if verilog-highlight-p1800-keywords
3135 (cons (concat "\\<\\(" verilog-1800-2005-keywords "\\)\\>")
3136 'verilog-font-lock-p1800-face)
3137 (cons (concat "\\<\\(" verilog-1800-2005-keywords "\\)\\>")
3138 'font-lock-type-face))
3139 ;; Fontify IEEE-1800-2009 keywords appropriately
3140 (if verilog-highlight-p1800-keywords
3141 (cons (concat "\\<\\(" verilog-1800-2009-keywords "\\)\\>")
3142 'verilog-font-lock-p1800-face)
3143 (cons (concat "\\<\\(" verilog-1800-2009-keywords "\\)\\>")
3144 'font-lock-type-face))
3145 ;; Fontify IEEE-1800-2012 keywords appropriately
3146 (if verilog-highlight-p1800-keywords
3147 (cons (concat "\\<\\(" verilog-1800-2012-keywords "\\)\\>")
3148 'verilog-font-lock-p1800-face)
3149 (cons (concat "\\<\\(" verilog-1800-2012-keywords "\\)\\>")
3150 'font-lock-type-face))
3151 ;; Fontify Verilog-AMS keywords
3152 (cons (concat "\\<\\(" verilog-ams-keywords "\\)\\>")
3153 'verilog-font-lock-ams-face)))
3155 (setq verilog-font-lock-keywords-1
3156 (append verilog-font-lock-keywords
3158 ;; Fontify module definitions
3160 "\\<\\(\\(macro\\)?module\\|primitive\\|class\\|program\\|interface\\|package\\|task\\)\\>\\s-*\\(\\sw+\\)"
3161 '(1 font-lock-keyword-face)
3162 '(3 font-lock-function-name-face 'prepend))
3163 ;; Fontify function definitions
3165 (concat "\\<function\\>\\s-+\\(integer\\|real\\(time\\)?\\|time\\)\\s-+\\(\\sw+\\)" )
3166 '(1 font-lock-keyword-face)
3167 '(3 font-lock-constant-face prepend))
3168 '("\\<function\\>\\s-+\\(\\[[^]]+\\]\\)\\s-+\\(\\sw+\\)"
3169 (1 font-lock-keyword-face)
3170 (2 font-lock-constant-face append))
3171 '("\\<function\\>\\s-+\\(\\sw+\\)"
3172 1 'font-lock-constant-face append))))
3174 (setq verilog-font-lock-keywords-2
3175 (append verilog-font-lock-keywords-1
3178 (concat "\\(//\\s-*\\(" verilog-pragma-keywords "\\)\\s-.*\\)")
3179 ;; Fontify escaped names
3180 '("\\(\\\\\\S-*\\s-\\)" 0 font-lock-function-name-face)
3181 ;; Fontify macro definitions/ uses
3182 '("`\\s-*[A-Za-z][A-Za-z0-9_]*" 0 (if (boundp 'font-lock-preprocessor-face)
3183 'font-lock-preprocessor-face
3184 'font-lock-type-face))
3185 ;; Fontify delays/numbers
3186 '("\\(@\\)\\|\\(#\\s-*\\(\\(\[0-9_.\]+\\('s?[hdxbo][0-9a-fA-F_xz]*\\)?\\)\\|\\(([^()]+)\\|\\sw+\\)\\)\\)"
3187 0 font-lock-type-face append)
3188 ;; Fontify instantiation names
3189 '("\\([A-Za-z][A-Za-z0-9_]*\\)\\s-*(" 1 font-lock-function-name-face)
3192 (setq verilog-font-lock-keywords-3
3193 (append verilog-font-lock-keywords-2
3194 (when verilog-highlight-translate-off
3196 ;; Fontify things in translate off regions
3197 '(verilog-match-translate-off
3198 (0 'verilog-font-lock-translate-off-face prepend))
3202 ;; Buffer state preservation
3204 (defmacro verilog-save-buffer-state (&rest body)
3205 "Execute BODY forms, saving state around insignificant change.
3206 Changes in text properties like `face' or `syntax-table' are
3207 considered insignificant. This macro allows text properties to
3208 be changed, even in a read-only buffer.
3210 A change is considered significant if it affects the buffer text
3211 in any way that isn't completely restored again. Any
3212 user-visible changes to the buffer must not be within a
3213 `verilog-save-buffer-state'."
3214 ;; From c-save-buffer-state
3215 `(let* ((modified (buffer-modified-p))
3216 (buffer-undo-list t)
3217 (inhibit-read-only t)
3218 (inhibit-point-motion-hooks t)
3219 (verilog-no-change-functions t)
3220 before-change-functions
3221 after-change-functions
3223 buffer-file-name ; Prevent primitives checking
3224 buffer-file-truename) ; for file modification
3229 (set-buffer-modified-p nil)))))
3231 (defmacro verilog-save-no-change-functions (&rest body)
3232 "Execute BODY forms, disabling all change hooks in BODY.
3233 For insignificant changes, see instead `verilog-save-buffer-state'."
3234 `(let* ((inhibit-point-motion-hooks t)
3235 (verilog-no-change-functions t)
3236 before-change-functions
3237 after-change-functions)
3240 (defvar verilog-save-font-mod-hooked nil
3241 "Local variable when inside a `verilog-save-font-mods' block.")
3242 (make-variable-buffer-local 'verilog-save-font-mod-hooked)
3244 (defmacro verilog-save-font-mods (&rest body)
3245 "Execute BODY forms, disabling text modifications to allow performing BODY.
3246 Includes temporary disabling of `font-lock' to restore the buffer
3247 to full text form for parsing. Additional actions may be specified with
3248 `verilog-before-save-font-hook' and `verilog-after-save-font-hook'."
3249 ;; Before version 20, match-string with font-lock returns a
3250 ;; vector that is not equal to the string. IE if on "input"
3251 ;; nil==(equal "input" (progn (looking-at "input") (match-string 0)))
3252 `(let* ((hooked (unless verilog-save-font-mod-hooked
3253 (verilog-run-hooks 'verilog-before-save-font-hook)
3255 (verilog-save-font-mod-hooked t)
3256 (fontlocked (when (and (boundp 'font-lock-mode) font-lock-mode)
3262 (when fontlocked (font-lock-mode t))
3263 (when hooked (verilog-run-hooks 'verilog-after-save-font-hook)))))
3266 ;; Comment detection and caching
3268 (defvar verilog-scan-cache-preserving nil
3269 "If true, the specified buffer's comment properties are static.
3270 Buffer changes will be ignored. See `verilog-inside-comment-or-string-p'
3271 and `verilog-scan'.")
3273 (defvar verilog-scan-cache-tick nil
3274 "Modification tick at which `verilog-scan' was last completed.")
3275 (make-variable-buffer-local 'verilog-scan-cache-tick)
3277 (defun verilog-scan-cache-flush ()
3278 "Flush the `verilog-scan' cache."
3279 (setq verilog-scan-cache-tick nil))
3281 (defun verilog-scan-cache-ok-p ()
3282 "Return t if the scan cache is up to date."
3283 (or (and verilog-scan-cache-preserving
3284 (eq verilog-scan-cache-preserving (current-buffer))
3285 verilog-scan-cache-tick)
3286 (equal verilog-scan-cache-tick (buffer-chars-modified-tick))))
3288 (defmacro verilog-save-scan-cache (&rest body)
3289 "Execute the BODY forms, allowing scan cache preservation within BODY.
3290 This requires that insertions must use `verilog-insert'."
3291 ;; If the buffer is out of date, trash it, as we'll not check later the tick
3292 ;; Note this must work properly if there's multiple layers of calls
3293 ;; to verilog-save-scan-cache even with differing ticks.
3295 (unless (verilog-scan-cache-ok-p) ;; Must be before let
3296 (setq verilog-scan-cache-tick nil))
3297 (let* ((verilog-scan-cache-preserving (current-buffer)))
3300 (defun verilog-scan-region (beg end)
3301 "Parse between BEG and END for `verilog-inside-comment-or-string-p'.
3302 This creates v-cmts properties where comments are in force."
3303 ;; Why properties and not overlays? Overlays have much slower non O(1)
3305 ;; This function is warm - called on every verilog-insert
3308 (verilog-save-buffer-state
3311 (while (< (point) end)
3312 (cond ((looking-at "//")
3314 (or (search-forward "\n" end t)
3316 ;; "1+": The leading // or /* itself isn't considered as
3317 ;; being "inside" the comment, so that a (search-backward)
3318 ;; that lands at the start of the // won't mis-indicate
3319 ;; it's inside a comment. Also otherwise it would be
3320 ;; hard to find a commented out /*AS*/ vs one that isn't
3321 (put-text-property (1+ pt) (point) 'v-cmts t))
3322 ((looking-at "/\\*")
3324 (or (search-forward "*/" end t)
3325 ;; No error - let later code indicate it so we can
3326 ;; use inside functions on-the-fly
3327 ;;(error "%s: Unmatched /* */, at char %d"
3328 ;; (verilog-point-text) (point))
3330 (put-text-property (1+ pt) (point) 'v-cmts t))
3333 (or (re-search-forward "[^\\]\"" end t) ;; don't forward-char first, since we look for a non backslash first
3334 ;; No error - let later code indicate it so we can
3336 (put-text-property (1+ pt) (point) 'v-cmts t))
3339 (if (re-search-forward "[/\"]" end t)
3341 (goto-char end))))))))))
3343 (defun verilog-scan ()
3344 "Parse the buffer, marking all comments with properties.
3345 Also assumes any text inserted since `verilog-scan-cache-tick'
3346 either is ok to parse as a non-comment, or `verilog-insert' was used."
3347 ;; See also `verilog-scan-debug' and `verilog-scan-and-debug'
3348 (unless (verilog-scan-cache-ok-p)
3350 (verilog-save-buffer-state
3352 (message "Scanning %s cache=%s cachetick=%S tick=%S" (current-buffer)
3353 verilog-scan-cache-preserving verilog-scan-cache-tick
3354 (buffer-chars-modified-tick)))
3355 (remove-text-properties (point-min) (point-max) '(v-cmts nil))
3356 (verilog-scan-region (point-min) (point-max))
3357 (setq verilog-scan-cache-tick (buffer-chars-modified-tick))
3358 (when verilog-debug (message "Scanning... done"))))))
3360 (defun verilog-scan-debug ()
3361 "For debugging, show with display face results of `verilog-scan'."
3363 ;;(if dbg (setq dbg (concat dbg (format "verilog-scan-debug\n"))))
3365 (goto-char (point-min))
3366 (remove-text-properties (point-min) (point-max) '(face nil))
3368 (cond ((get-text-property (point) 'v-cmts)
3369 (put-text-property (point) (1+ (point)) `face 'underline)
3370 ;;(if dbg (setq dbg (concat dbg (format " v-cmts at %S\n" (point)))))
3373 (goto-char (or (next-property-change (point)) (point-max))))))))
3375 (defun verilog-scan-and-debug ()
3376 "For debugging, run `verilog-scan' and `verilog-scan-debug'."
3377 (let (verilog-scan-cache-preserving
3378 verilog-scan-cache-tick)
3379 (goto-char (point-min))
3381 (verilog-scan-debug)))
3383 (defun verilog-inside-comment-or-string-p (&optional pos)
3384 "Check if optional point POS is inside a comment.
3385 This may require a slow pre-parse of the buffer with `verilog-scan'
3386 to establish comment properties on all text."
3387 ;; This function is very hot
3390 (and (>= pos (point-min))
3391 (get-text-property pos 'v-cmts))
3392 (get-text-property (point) 'v-cmts)))
3394 (defun verilog-insert (&rest stuff)
3395 "Insert STUFF arguments, tracking for `verilog-inside-comment-or-string-p'.
3396 Any insert that includes a comment must have the entire comment
3397 inserted using a single call to `verilog-insert'."
3400 (insert (car stuff))
3401 (setq stuff (cdr stuff)))
3402 (verilog-scan-region pt (point))))
3406 (defun verilog-declaration-end ()
3407 (search-forward ";"))
3409 (defun verilog-point-text (&optional pointnum)
3410 "Return text describing where POINTNUM or current point is (for errors).
3411 Use filename, if current buffer being edited shorten to just buffer name."
3412 (concat (or (and (equal (window-buffer) (current-buffer))
3416 ":" (int-to-string (1+ (count-lines (point-min) (or pointnum (point)))))))
3418 (defun electric-verilog-backward-sexp ()
3419 "Move backward over one balanced expression."
3421 ;; before that see if we are in a comment
3422 (verilog-backward-sexp))
3424 (defun electric-verilog-forward-sexp ()
3425 "Move forward over one balanced expression."
3427 ;; before that see if we are in a comment
3428 (verilog-forward-sexp))
3430 ;;;used by hs-minor-mode
3431 (defun verilog-forward-sexp-function (arg)
3433 (verilog-backward-sexp)
3434 (verilog-forward-sexp)))
3437 (defun verilog-backward-sexp ()
3442 (if (not (looking-at "\\<"))
3445 ((verilog-skip-backward-comment-or-string))
3446 ((looking-at "\\<else\\>")
3448 verilog-end-block-re
3449 "\\|\\(\\<else\\>\\)"
3450 "\\|\\(\\<if\\>\\)"))
3451 (while (and (not found)
3452 (verilog-re-search-backward reg nil 'move))
3454 ((match-end 1) ; matched verilog-end-block-re
3455 ;; try to leap back to matching outward block by striding across
3456 ;; indent level changing tokens then immediately
3457 ;; previous line governs indentation.
3458 (verilog-leap-to-head))
3459 ((match-end 2) ; else, we're in deep
3460 (setq elsec (1+ elsec)))
3461 ((match-end 3) ; found it
3462 (setq elsec (1- elsec))
3464 ;; Now previous line describes syntax
3465 (setq found 't))))))
3466 ((looking-at verilog-end-block-re)
3467 (verilog-leap-to-head))
3468 ((looking-at "\\(endmodule\\>\\)\\|\\(\\<endprimitive\\>\\)\\|\\(\\<endclass\\>\\)\\|\\(\\<endprogram\\>\\)\\|\\(\\<endinterface\\>\\)\\|\\(\\<endpackage\\>\\)")
3471 (verilog-re-search-backward "\\<\\(macro\\)?module\\>" nil 'move))
3473 (verilog-re-search-backward "\\<primitive\\>" nil 'move))
3475 (verilog-re-search-backward "\\<class\\>" nil 'move))
3477 (verilog-re-search-backward "\\<program\\>" nil 'move))
3479 (verilog-re-search-backward "\\<interface\\>" nil 'move))
3481 (verilog-re-search-backward "\\<package\\>" nil 'move))
3484 (backward-sexp 1))))
3489 (defun verilog-forward-sexp ()
3494 (if (not (looking-at "\\<"))
3497 ((verilog-skip-forward-comment-or-string)
3498 (verilog-forward-syntactic-ws))
3499 ((looking-at verilog-beg-block-re-ordered)
3502 ;; Search forward for matching end
3503 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
3505 ;; Search forward for matching endcase
3506 (setq reg "\\(\\<randcase\\>\\|\\(\\<unique0?\\>\\s-+\\|\\<priority\\>\\s-+\\)?\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )
3507 (setq md 3) ;; ender is third item in regexp
3510 ;; might be "disable fork" or "wait fork"
3514 (looking-at verilog-disable-fork-re)
3515 (and (looking-at "fork")
3517 (setq here (point)) ;; sometimes a fork is just a fork
3519 (looking-at verilog-disable-fork-re))))
3520 (progn ;; it is a disable fork; ignore it
3521 (goto-char (match-end 0))
3524 (progn ;; it is a nice simple fork
3525 (goto-char here) ;; return from looking for "disable fork"
3526 ;; Search forward for matching join
3527 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))))
3529 ;; Search forward for matching endclass
3530 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
3533 ;; Search forward for matching endtable
3534 (setq reg "\\<endtable\\>" )
3537 ;; Search forward for matching endspecify
3538 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
3540 ;; Search forward for matching endfunction
3541 (setq reg "\\<endfunction\\>" )
3544 ;; Search forward for matching endfunction
3545 (setq reg "\\<endfunction\\>" )
3548 ;; Search forward for matching endtask
3549 (setq reg "\\<endtask\\>" )
3552 ;; Search forward for matching endtask
3553 (setq reg "\\<endtask\\>" )
3556 ;; Search forward for matching endgenerate
3557 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
3559 ;; Search forward for matching endgroup
3560 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
3562 ;; Search forward for matching endproperty
3563 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
3565 ;; Search forward for matching endsequence
3566 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" )
3567 (setq md 3)) ; 3 to get to endsequence in the reg above
3569 ;; Search forward for matching endclocking
3570 (setq reg "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)" )))
3577 (while (verilog-re-search-forward reg nil 'move)
3579 ((match-end md) ; a closer in regular expression, so we are climbing out
3580 (setq depth (1- depth))
3581 (if (= 0 depth) ; we are out!
3583 ((match-end 1) ; an opener in the r-e, so we are in deeper now
3584 (setq here (point)) ; remember where we started
3585 (goto-char (match-beginning 1))
3588 (looking-at verilog-disable-fork-re)
3589 (and (looking-at "fork")
3592 (looking-at verilog-disable-fork-re))))
3593 (progn ;; it is a disable fork; another false alarm
3594 (goto-char (match-end 0)))
3595 (progn ;; it is a simple fork (or has nothing to do with fork)
3597 (setq depth (1+ depth))))))))))
3598 (if (verilog-re-search-forward reg nil 'move)
3599 (throw 'skip 1))))))
3601 ((looking-at (concat
3602 "\\(\\<\\(macro\\)?module\\>\\)\\|"
3603 "\\(\\<primitive\\>\\)\\|"
3604 "\\(\\<class\\>\\)\\|"
3605 "\\(\\<program\\>\\)\\|"
3606 "\\(\\<interface\\>\\)\\|"
3607 "\\(\\<package\\>\\)"))
3610 (verilog-re-search-forward "\\<endmodule\\>" nil 'move))
3612 (verilog-re-search-forward "\\<endprimitive\\>" nil 'move))
3614 (verilog-re-search-forward "\\<endclass\\>" nil 'move))
3616 (verilog-re-search-forward "\\<endprogram\\>" nil 'move))
3618 (verilog-re-search-forward "\\<endinterface\\>" nil 'move))
3620 (verilog-re-search-forward "\\<endpackage\\>" nil 'move))
3623 (if (= (following-char) ?\) )
3625 (forward-sexp 1)))))
3628 (if (= (following-char) ?\) )
3630 (forward-sexp 1))))))
3632 (defun verilog-declaration-beg ()
3633 (verilog-re-search-backward verilog-declaration-re (bobp) t))
3639 (defvar verilog-which-tool 1)
3641 (define-derived-mode verilog-mode prog-mode "Verilog"
3642 "Major mode for editing Verilog code.
3643 \\<verilog-mode-map>
3644 See \\[describe-function] verilog-auto (\\[verilog-auto]) for details on how
3645 AUTOs can improve coding efficiency.
3647 Use \\[verilog-faq] for a pointer to frequently asked questions.
3649 NEWLINE, TAB indents for Verilog code.
3650 Delete converts tabs to spaces as it moves back.
3652 Supports highlighting.
3654 Turning on Verilog mode calls the value of the variable `verilog-mode-hook'
3655 with no args, if that value is non-nil.
3657 Variables controlling indentation/edit style:
3659 variable `verilog-indent-level' (default 3)
3660 Indentation of Verilog statements with respect to containing block.
3661 `verilog-indent-level-module' (default 3)
3662 Absolute indentation of Module level Verilog statements.
3663 Set to 0 to get initial and always statements lined up
3664 on the left side of your screen.
3665 `verilog-indent-level-declaration' (default 3)
3666 Indentation of declarations with respect to containing block.
3667 Set to 0 to get them list right under containing block.
3668 `verilog-indent-level-behavioral' (default 3)
3669 Indentation of first begin in a task or function block
3670 Set to 0 to get such code to lined up underneath the task or
3672 `verilog-indent-level-directive' (default 1)
3673 Indentation of \\=`ifdef/\\=`endif blocks.
3674 `verilog-cexp-indent' (default 1)
3675 Indentation of Verilog statements broken across lines i.e.:
3678 `verilog-case-indent' (default 2)
3679 Indentation for case statements.
3680 `verilog-auto-newline' (default nil)
3681 Non-nil means automatically newline after semicolons and the punctuation
3683 `verilog-auto-indent-on-newline' (default t)
3684 Non-nil means automatically indent line after newline.
3685 `verilog-tab-always-indent' (default t)
3686 Non-nil means TAB in Verilog mode should always reindent the current line,
3687 regardless of where in the line point is when the TAB command is used.
3688 `verilog-indent-begin-after-if' (default t)
3689 Non-nil means to indent begin statements following a preceding
3690 if, else, while, for and repeat statements, if any. Otherwise,
3691 the begin is lined up with the preceding token. If t, you get:
3693 begin // amount of indent based on `verilog-cexp-indent'
3697 `verilog-auto-endcomments' (default t)
3698 Non-nil means a comment /* ... */ is set after the ends which ends
3699 cases, tasks, functions and modules.
3700 The type and name of the object will be set between the braces.
3701 `verilog-minimum-comment-distance' (default 10)
3702 Minimum distance (in lines) between begin and end required before a comment
3703 will be inserted. Setting this variable to zero results in every
3704 end acquiring a comment; the default avoids too many redundant
3705 comments in tight quarters.
3706 `verilog-auto-lineup' (default 'declarations)
3707 List of contexts where auto lineup of code should be done.
3709 Variables controlling other actions:
3711 `verilog-linter' (default surelint)
3712 Unix program to call to run the lint checker. This is the default
3713 command for \\[compile-command] and \\[verilog-auto-save-compile].
3715 See \\[customize] for the complete list of variables.
3717 AUTO expansion functions are, in part:
3719 \\[verilog-auto] Expand AUTO statements.
3720 \\[verilog-delete-auto] Remove the AUTOs.
3721 \\[verilog-inject-auto] Insert AUTOs for the first time.
3723 Some other functions are:
3725 \\[verilog-complete-word] Complete word with appropriate possibilities.
3726 \\[verilog-mark-defun] Mark function.
3727 \\[verilog-beg-of-defun] Move to beginning of current function.
3728 \\[verilog-end-of-defun] Move to end of current function.
3729 \\[verilog-label-be] Label matching begin ... end, fork ... join, etc statements.
3731 \\[verilog-comment-region] Put marked area in a comment.
3732 \\[verilog-uncomment-region] Uncomment an area commented with \\[verilog-comment-region].
3733 \\[verilog-insert-block] Insert begin ... end.
3734 \\[verilog-star-comment] Insert /* ... */.
3736 \\[verilog-sk-always] Insert an always @(AS) begin .. end block.
3737 \\[verilog-sk-begin] Insert a begin .. end block.
3738 \\[verilog-sk-case] Insert a case block, prompting for details.
3739 \\[verilog-sk-for] Insert a for (...) begin .. end block, prompting for details.
3740 \\[verilog-sk-generate] Insert a generate .. endgenerate block.
3741 \\[verilog-sk-header] Insert a header block at the top of file.
3742 \\[verilog-sk-initial] Insert an initial begin .. end block.
3743 \\[verilog-sk-fork] Insert a fork begin .. end .. join block.
3744 \\[verilog-sk-module] Insert a module .. (/*AUTOARG*/);.. endmodule block.
3745 \\[verilog-sk-ovm-class] Insert an OVM Class block.
3746 \\[verilog-sk-uvm-object] Insert an UVM Object block.
3747 \\[verilog-sk-uvm-component] Insert an UVM Component block.
3748 \\[verilog-sk-primitive] Insert a primitive .. (.. );.. endprimitive block.
3749 \\[verilog-sk-repeat] Insert a repeat (..) begin .. end block.
3750 \\[verilog-sk-specify] Insert a specify .. endspecify block.
3751 \\[verilog-sk-task] Insert a task .. begin .. end endtask block.
3752 \\[verilog-sk-while] Insert a while (...) begin .. end block, prompting for details.
3753 \\[verilog-sk-casex] Insert a casex (...) item: begin.. end endcase block, prompting for details.
3754 \\[verilog-sk-casez] Insert a casez (...) item: begin.. end endcase block, prompting for details.
3755 \\[verilog-sk-if] Insert an if (..) begin .. end block.
3756 \\[verilog-sk-else-if] Insert an else if (..) begin .. end block.
3757 \\[verilog-sk-comment] Insert a comment block.
3758 \\[verilog-sk-assign] Insert an assign .. = ..; statement.
3759 \\[verilog-sk-function] Insert a function .. begin .. end endfunction block.
3760 \\[verilog-sk-input] Insert an input declaration, prompting for details.
3761 \\[verilog-sk-output] Insert an output declaration, prompting for details.
3762 \\[verilog-sk-state-machine] Insert a state machine definition, prompting for details.
3763 \\[verilog-sk-inout] Insert an inout declaration, prompting for details.
3764 \\[verilog-sk-wire] Insert a wire declaration, prompting for details.
3765 \\[verilog-sk-reg] Insert a register declaration, prompting for details.
3766 \\[verilog-sk-define-signal] Define signal under point as a register at the top of the module.
3768 All key bindings can be seen in a Verilog-buffer with \\[describe-bindings].
3769 Key bindings specific to `verilog-mode-map' are:
3771 \\{verilog-mode-map}"
3772 :abbrev-table verilog-mode-abbrev-table
3773 (set (make-local-variable 'beginning-of-defun-function)
3774 'verilog-beg-of-defun)
3775 (set (make-local-variable 'end-of-defun-function)
3776 'verilog-end-of-defun)
3777 (set-syntax-table verilog-mode-syntax-table)
3778 (set (make-local-variable 'indent-line-function)
3779 #'verilog-indent-line-relative)
3780 (set (make-local-variable 'comment-indent-function) 'verilog-comment-indent)
3781 (set (make-local-variable 'parse-sexp-ignore-comments) nil)
3782 (set (make-local-variable 'comment-start) "// ")
3783 (set (make-local-variable 'comment-end) "")
3784 (set (make-local-variable 'comment-start-skip) "/\\*+ *\\|// *")
3785 (set (make-local-variable 'comment-multi-line) nil)
3786 ;; Set up for compilation
3787 (setq verilog-which-tool 1)
3788 (setq verilog-tool 'verilog-linter)
3789 (verilog-set-compile-command)
3790 (when (boundp 'hack-local-variables-hook) ;; Also modify any file-local-variables
3791 (add-hook 'hack-local-variables-hook 'verilog-modify-compile-command t))
3794 (when (featurep 'xemacs)
3795 (easy-menu-add verilog-stmt-menu)
3796 (easy-menu-add verilog-menu)
3797 (setq mode-popup-menu (cons "Verilog Mode" verilog-stmt-menu)))
3799 ;; Stuff for GNU Emacs
3800 (set (make-local-variable 'font-lock-defaults)
3801 `((verilog-font-lock-keywords
3802 verilog-font-lock-keywords-1
3803 verilog-font-lock-keywords-2
3804 verilog-font-lock-keywords-3)
3806 ,(if (functionp 'syntax-ppss)
3807 ;; verilog-beg-of-defun uses syntax-ppss, and syntax-ppss uses
3808 ;; font-lock-beginning-of-syntax-function, so
3809 ;; font-lock-beginning-of-syntax-function, can't use
3810 ;; verilog-beg-of-defun.
3812 'verilog-beg-of-defun)))
3813 ;;------------------------------------------------------------
3814 ;; now hook in 'verilog-highlight-include-files (eldo-mode.el&spice-mode.el)
3815 ;; all buffer local:
3816 (unless noninteractive ;; Else can't see the result, and change hooks are slow
3817 (when (featurep 'xemacs)
3818 (make-local-hook 'font-lock-mode-hook)
3819 (make-local-hook 'font-lock-after-fontify-buffer-hook); doesn't exist in Emacs
3820 (make-local-hook 'after-change-functions))
3821 (add-hook 'font-lock-mode-hook 'verilog-highlight-buffer t t)
3822 (add-hook 'font-lock-after-fontify-buffer-hook 'verilog-highlight-buffer t t) ; not in Emacs
3823 (add-hook 'after-change-functions 'verilog-highlight-region t t))
3825 ;; Tell imenu how to handle Verilog.
3826 (set (make-local-variable 'imenu-generic-expression)
3827 verilog-imenu-generic-expression)
3828 ;; Tell which-func-modes that imenu knows about verilog
3829 (when (and (boundp 'which-func-modes) (listp which-func-modes))
3830 (add-to-list 'which-func-modes 'verilog-mode))
3832 (when (boundp 'hs-special-modes-alist)
3833 (unless (assq 'verilog-mode hs-special-modes-alist)
3834 (setq hs-special-modes-alist
3835 (cons '(verilog-mode-mode "\\<begin\\>" "\\<end\\>" nil
3836 verilog-forward-sexp-function)
3837 hs-special-modes-alist))))
3840 (add-hook 'write-contents-hooks 'verilog-auto-save-check nil 'local)
3841 ;; verilog-mode-hook call added by define-derived-mode
3846 ;; Electric functions
3848 (defun electric-verilog-terminate-line (&optional arg)
3849 "Terminate line and indent next line.
3850 With optional ARG, remove existing end of line comments."
3852 ;; before that see if we are in a comment
3853 (let ((state (save-excursion (verilog-syntax-ppss))))
3855 ((nth 7 state) ; Inside // comment
3858 (delete-horizontal-space)
3863 (beginning-of-line)))
3864 (verilog-indent-line))
3865 ((nth 4 state) ; Inside any comment (hence /**/)
3867 (verilog-more-comment))
3869 ;; First, check if current line should be indented
3871 (delete-horizontal-space)
3873 (skip-chars-forward " \t")
3874 (if (looking-at verilog-auto-end-comment-lines-re)
3875 (let ((indent-str (verilog-indent-line)))
3876 ;; Maybe we should set some endcomments
3877 (if verilog-auto-endcomments
3878 (verilog-set-auto-endcomments indent-str arg))
3880 (delete-horizontal-space)
3887 (delete-horizontal-space)
3889 ;; see if we should line up assignments
3891 (if (or (eq 'all verilog-auto-lineup)
3892 (eq 'assignments verilog-auto-lineup))
3893 (verilog-pretty-expr t "\\(<\\|:\\)?=" ))
3897 (if verilog-auto-indent-on-newline
3898 (verilog-indent-line)))
3902 (defun electric-verilog-terminate-and-indent ()
3903 "Insert a newline and indent for the next statement."
3905 (electric-verilog-terminate-line 1))
3907 (defun electric-verilog-semi ()
3908 "Insert `;' character and reindent the line."
3910 (verilog-insert-last-command-event)
3912 (if (or (verilog-in-comment-or-string-p)
3913 (verilog-in-escaped-name-p))
3917 (verilog-forward-ws&directives)
3918 (verilog-indent-line))
3919 (if (and verilog-auto-newline
3920 (not (verilog-parenthesis-depth)))
3921 (electric-verilog-terminate-line))))
3923 (defun electric-verilog-semi-with-comment ()
3924 "Insert `;' character, reindent the line and indent for comment."
3929 (verilog-indent-line))
3930 (indent-for-comment))
3932 (defun electric-verilog-colon ()
3933 "Insert `:' and do all indentations except line indent on this line."
3935 (verilog-insert-last-command-event)
3936 ;; Do nothing if within string.
3938 (verilog-within-string)
3939 (not (verilog-in-case-region-p)))
3943 (lim (progn (verilog-beg-of-statement) (point))))
3945 (verilog-backward-case-item lim)
3946 (verilog-indent-line)))
3947 ;; (let ((verilog-tab-always-indent nil))
3948 ;; (verilog-indent-line))
3951 ;;(defun electric-verilog-equal ()
3952 ;; "Insert `=', and do indentation if within block."
3954 ;; (verilog-insert-last-command-event)
3955 ;; Could auto line up expressions, but not yet
3956 ;; (if (eq (car (verilog-calculate-indent)) 'block)
3957 ;; (let ((verilog-tab-always-indent nil))
3958 ;; (verilog-indent-command)))
3961 (defun electric-verilog-tick ()
3962 "Insert back-tick, and indent to column 0 if this is a CPP directive."
3964 (verilog-insert-last-command-event)
3966 (if (verilog-in-directive-p)
3967 (verilog-indent-line))))
3969 (defun electric-verilog-tab ()
3970 "Function called when TAB is pressed in Verilog mode."
3972 ;; If verilog-tab-always-indent, indent the beginning of the line.
3974 ;; The region is active, indent it.
3975 ((and (region-active-p)
3976 (not (eq (region-beginning) (region-end))))
3977 (indent-region (region-beginning) (region-end) nil))
3978 ((or verilog-tab-always-indent
3980 (skip-chars-backward " \t")
3982 (let* ((oldpnt (point))
3986 (skip-chars-forward " \t")
3987 (verilog-indent-line)
3988 (back-to-indentation)
3990 (if (< (point) boi-point)
3991 (back-to-indentation)
3992 (cond ((not verilog-tab-to-comment))
3996 (indent-for-comment)
3997 (when (and (eolp) (= oldpnt (point)))
3998 ; kill existing comment
4000 (re-search-forward comment-start-skip oldpnt 'move)
4001 (goto-char (match-beginning 0))
4002 (skip-chars-backward " \t")
4003 (kill-region (point) oldpnt)))))))
4004 (t (progn (insert "\t")))))
4009 ;; Interactive functions
4012 (defun verilog-indent-buffer ()
4013 "Indent-region the entire buffer as Verilog code.
4014 To call this from the command line, see \\[verilog-batch-indent]."
4017 (indent-region (point-min) (point-max) nil))
4019 (defun verilog-insert-block ()
4020 "Insert Verilog begin ... end; block in the code with right indentation."
4022 (verilog-indent-line)
4024 (electric-verilog-terminate-line)
4026 (electric-verilog-terminate-line)
4029 (verilog-indent-line)))
4031 (defun verilog-star-comment ()
4032 "Insert Verilog star comment at point."
4034 (verilog-indent-line)
4042 (defun verilog-insert-1 (fmt max)
4043 "Use format string FMT to insert integers 0 to MAX - 1.
4044 Inserts one integer per line, at the current column. Stops early
4045 if it reaches the end of the buffer."
4046 (let ((col (current-column))
4050 (insert (format fmt n))
4052 ;; Note that this function does not bother to check for lines
4053 ;; shorter than col.
4057 (move-to-column col))))))
4059 (defun verilog-insert-indices (max)
4060 "Insert a set of indices into a rectangle.
4061 The upper left corner is defined by point. Indices begin with 0
4062 and extend to the MAX - 1. If no prefix arg is given, the user
4063 is prompted for a value. The indices are surrounded by square
4064 brackets \[]. For example, the following code with the point
4065 located after the first 'a' gives:
4071 a = b ==> insert-indices ==> a[ 4] = b
4077 (interactive "NMAX: ")
4078 (verilog-insert-1 "[%3d]" max))
4080 (defun verilog-generate-numbers (max)
4081 "Insert a set of generated numbers into a rectangle.
4082 The upper left corner is defined by point. The numbers are padded to three
4083 digits, starting with 000 and extending to (MAX - 1). If no prefix argument
4084 is supplied, then the user is prompted for the MAX number. Consider the
4085 following code fragment:
4091 buf buf ==> generate-numbers ==> buf buf004
4097 (interactive "NMAX: ")
4098 (verilog-insert-1 "%3.3d" max))
4100 (defun verilog-mark-defun ()
4101 "Mark the current Verilog function (or procedure).
4102 This puts the mark at the end, and point at the beginning."
4104 (if (featurep 'xemacs)
4107 (verilog-end-of-defun)
4109 (verilog-beg-of-defun)
4110 (if (fboundp 'zmacs-activate-region)
4111 (zmacs-activate-region)))
4114 (defun verilog-comment-region (start end)
4115 ;; checkdoc-params: (start end)
4116 "Put the region into a Verilog comment.
4117 The comments that are in this area are \"deformed\":
4118 `*)' becomes `!(*' and `}' becomes `!{'.
4119 These deformed comments are returned to normal if you use
4120 \\[verilog-uncomment-region] to undo the commenting.
4122 The commented area starts with `verilog-exclude-str-start', and ends with
4123 `verilog-exclude-str-end'. But if you change these variables,
4124 \\[verilog-uncomment-region] won't recognize the comments."
4127 ;; Insert start and endcomments
4129 (if (and (save-excursion (skip-chars-forward " \t") (eolp))
4130 (not (save-excursion (skip-chars-backward " \t") (bolp))))
4132 (beginning-of-line))
4133 (insert verilog-exclude-str-end)
4138 (insert verilog-exclude-str-start)
4140 ;; Replace end-comments within commented area
4143 (while (re-search-backward "\\*/" start t)
4144 (replace-match "*-/" t t)))
4146 (let ((s+1 (1+ start)))
4147 (while (re-search-backward "/\\*" s+1 t)
4148 (replace-match "/-*" t t))))))
4150 (defun verilog-uncomment-region ()
4151 "Uncomment a commented area; change deformed comments back to normal.
4152 This command does nothing if the pointer is not in a commented
4153 area. See also `verilog-comment-region'."
4156 (let ((start (point))
4158 ;; Find the boundaries of the comment
4160 (setq start (progn (search-backward verilog-exclude-str-start nil t)
4162 (setq end (progn (search-forward verilog-exclude-str-end nil t)
4164 ;; Check if we're really inside a comment
4165 (if (or (equal start (point)) (<= end (point)))
4166 (message "Not standing within commented area.")
4168 ;; Remove endcomment
4171 (let ((pos (point)))
4173 (delete-region pos (1+ (point))))
4174 ;; Change comments back to normal
4176 (while (re-search-backward "\\*-/" start t)
4177 (replace-match "*/" t t)))
4179 (while (re-search-backward "/-\\*" start t)
4180 (replace-match "/*" t t)))
4181 ;; Remove start comment
4184 (let ((pos (point)))
4186 (delete-region pos (1+ (point)))))))))
4188 (defun verilog-beg-of-defun ()
4189 "Move backward to the beginning of the current function or procedure."
4191 (verilog-re-search-backward verilog-defun-re nil 'move))
4193 (defun verilog-beg-of-defun-quick ()
4194 "Move backward to the beginning of the current function or procedure.
4195 Uses `verilog-scan' cache."
4197 (verilog-re-search-backward-quick verilog-defun-re nil 'move))
4199 (defun verilog-end-of-defun ()
4200 "Move forward to the end of the current function or procedure."
4202 (verilog-re-search-forward verilog-end-defun-re nil 'move))
4204 (defun verilog-get-end-of-defun ()
4206 (cond ((verilog-re-search-forward-quick verilog-end-defun-re nil t)
4209 (error "%s: Can't find endmodule" (verilog-point-text))
4212 (defun verilog-label-be ()
4213 "Label matching begin ... end, fork ... join and case ... endcase statements."
4218 (verilog-beg-of-defun)
4221 (verilog-end-of-defun)
4223 (goto-char (marker-position b))
4225 (message "Relabeling module..."))
4227 (> (marker-position e) (point))
4228 (verilog-re-search-forward
4229 verilog-auto-end-comment-lines-re
4231 (goto-char (match-beginning 0))
4232 (let ((indent-str (verilog-indent-line)))
4233 (verilog-set-auto-endcomments indent-str 't)
4235 (delete-horizontal-space))
4237 (if (= 9 (% cnt 10))
4238 (message "%d..." cnt)))
4243 (message "%d lines auto commented" cnt))))
4245 (defun verilog-beg-of-statement ()
4246 "Move backward to beginning of statement."
4248 ;; Move back token by token until we see the end
4249 ;; of some earlier line.
4252 ;; If the current point does not begin a new
4253 ;; statement, as in the character ahead of us is a ';', or SOF
4254 ;; or the string after us unambiguously starts a statement,
4255 ;; or the token before us unambiguously ends a statement,
4256 ;; then move back a token and test again.
4258 ;; stop if beginning of buffer
4260 ;; stop if looking at a pre-processor directive
4261 (looking-at "`\\w+")
4262 ;; stop if we find a ;
4263 (= (preceding-char) ?\;)
4264 ;; stop if we see a named coverpoint
4265 (looking-at "\\w+\\W*:\\W*\\(coverpoint\\|cross\\|constraint\\)")
4266 ;; keep going if we are in the middle of a word
4267 (not (or (looking-at "\\<") (forward-word -1)))
4268 ;; stop if we see an assertion (perhaps labeled)
4270 (looking-at "\\(\\w+\\W*:\\W*\\)?\\(\\<\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(\\<assert\\>\\)")
4274 (verilog-backward-token)
4275 (if (and (looking-at verilog-label-re)
4276 (not (looking-at verilog-end-block-re)))
4279 ;; stop if we see an extended complete reg, perhaps a complete one
4281 (looking-at verilog-complete-reg)
4283 (while (and (looking-at verilog-extended-complete-re)
4284 (progn (setq p (point))
4285 (verilog-backward-token)
4288 ;; stop if we see a complete reg (previous found extended ones)
4289 (looking-at verilog-basic-complete-re)
4290 ;; stop if previous token is an ender
4292 (verilog-backward-token)
4293 (looking-at verilog-end-block-re))))
4294 (verilog-backward-syntactic-ws)
4295 (verilog-backward-token))
4296 ;; Now point is where the previous line ended.
4297 (verilog-forward-syntactic-ws)
4298 ;; Skip forward over any preprocessor directives, as they have wacky indentation
4299 (if (looking-at verilog-preprocessor-re)
4300 (progn (goto-char (match-end 0))
4301 (verilog-forward-syntactic-ws)))))
4303 (defun verilog-beg-of-statement-1 ()
4304 "Move backward to beginning of statement."
4306 (if (verilog-in-comment-p)
4307 (verilog-backward-syntactic-ws))
4310 (while (not (looking-at verilog-complete-reg))
4312 (verilog-backward-syntactic-ws)
4314 (= (preceding-char) ?\;)
4316 (verilog-backward-token)
4317 (looking-at verilog-ends-re)))
4321 (verilog-forward-syntactic-ws)))
4324 ; (not (looking-at verilog-complete-reg))
4326 ; (not (= (preceding-char) ?\;)))
4327 ; (verilog-backward-token)
4328 ; (verilog-backward-syntactic-ws)
4329 ; (setq pt (point)))
4331 ; ;(verilog-forward-syntactic-ws)
4333 (defun verilog-end-of-statement ()
4334 "Move forward to end of current statement."
4338 ((verilog-in-directive-p)
4342 ((looking-at verilog-beg-block-re)
4343 (verilog-forward-sexp))
4345 ((equal (char-after) ?\})
4348 ;; Skip to end of statement
4349 ((condition-case nil
4354 (verilog-skip-forward-comment-or-string)
4357 (cond ((looking-at "[ \t]*;")
4358 (skip-chars-forward "^;")
4360 (throw 'found (point)))
4363 (looking-at verilog-beg-block-re))
4364 (goto-char (match-beginning 0))
4366 ((looking-at "[ \t]*)")
4367 (throw 'found (point)))
4369 (throw 'found (point)))
4375 ;; Skip a whole block
4378 (verilog-re-search-forward verilog-end-statement-re nil 'move)
4379 (setq nest (if (match-end 1)
4383 (throw 'found (point)))
4385 (throw 'found (verilog-end-of-statement))))))
4388 (defun verilog-in-case-region-p ()
4389 "Return true if in a case region.
4390 More specifically, point @ in the line foo : @ begin"
4394 (progn (verilog-forward-syntactic-ws)
4395 (looking-at "\\<begin\\>"))
4396 (progn (verilog-backward-syntactic-ws)
4397 (= (preceding-char) ?\:)))
4401 (verilog-re-search-backward
4402 (concat "\\(\\<module\\>\\)\\|\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|"
4403 "\\(\\<endcase\\>\\)\\>")
4407 (setq nest (1+ nest)))
4411 (setq nest (1- nest)))
4413 (throw 'found (= nest 0)))))))
4416 (defun verilog-backward-up-list (arg)
4417 "Call `backward-up-list' ARG, ignoring comments."
4418 (let ((parse-sexp-ignore-comments t))
4419 (backward-up-list arg)))
4421 (defun verilog-forward-sexp-cmt (arg)
4422 "Call `forward-sexp' ARG, inside comments."
4423 (let ((parse-sexp-ignore-comments nil))
4424 (forward-sexp arg)))
4426 (defun verilog-forward-sexp-ign-cmt (arg)
4427 "Call `forward-sexp' ARG, ignoring comments."
4428 (let ((parse-sexp-ignore-comments t))
4429 (forward-sexp arg)))
4431 (defun verilog-in-generate-region-p ()
4432 "Return true if in a generate region.
4433 More specifically, after a generate and before an endgenerate."
4440 (verilog-re-search-backward
4441 "\\<\\(module\\)\\|\\(generate\\)\\|\\(endgenerate\\)\\>" nil 'move)
4443 ((match-end 1) ; module - we have crawled out
4445 ((match-end 2) ; generate
4446 (setq nest (1- nest)))
4447 ((match-end 3) ; endgenerate
4448 (setq nest (1+ nest))))))))
4449 (= nest 0) )) ; return nest
4451 (defun verilog-in-fork-region-p ()
4452 "Return true if between a fork and join."
4454 (let ((lim (save-excursion (verilog-beg-of-defun) (point)))
4459 (verilog-re-search-backward "\\<\\(fork\\)\\|\\(join\\(_any\\|_none\\)?\\)\\>" lim 'move)
4461 ((match-end 1) ; fork
4462 (setq nest (1- nest)))
4463 ((match-end 2) ; join
4464 (setq nest (1+ nest)))))))
4465 (= nest 0) )) ; return nest
4467 (defun verilog-backward-case-item (lim)
4468 "Skip backward to nearest enclosing case item.
4469 Limit search to point LIM."
4475 (verilog-re-search-backward verilog-endcomment-reason-re
4478 ;; Try to find the real :
4479 (if (save-excursion (search-backward ":" lim1 t))
4485 (verilog-re-search-backward "\\(\\[\\)\\|\\(\\]\\)\\|\\(:\\)"
4489 (setq colon (1+ colon))
4491 (error "%s: unbalanced [" (verilog-point-text))))
4493 (setq colon (1- colon)))
4496 (setq colon (1+ colon)))))
4497 ;; Skip back to beginning of case item
4498 (skip-chars-backward "\t ")
4499 (verilog-skip-backward-comment-or-string)
4504 (verilog-re-search-backward
4505 "\\<\\(case[zx]?\\)\\>\\|;\\|\\<end\\>" nil 'move)
4509 (goto-char (match-end 1))
4510 (verilog-forward-ws&directives)
4511 (if (looking-at "(")
4514 (verilog-forward-ws&directives)))
4517 (goto-char (match-end 0))
4518 (verilog-forward-ws&directives)
4520 (error "Malformed case item"))))
4521 (setq str (buffer-substring b e))
4525 "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
4526 (setq str (concat (substring str 0 e) "...")))
4535 (defun verilog-kill-existing-comment ()
4536 "Kill auto comment on this line."
4544 (search-forward "//" e t))))
4546 (delete-region (- b 2) e)))))
4548 (defconst verilog-directive-nest-re
4549 (concat "\\(`else\\>\\)\\|"
4550 "\\(`endif\\>\\)\\|"
4552 "\\(`ifdef\\>\\)\\|"
4553 "\\(`ifndef\\>\\)\\|"
4556 (defun verilog-set-auto-endcomments (indent-str kill-existing-comment)
4557 "Add ending comment with given INDENT-STR.
4558 With KILL-EXISTING-COMMENT, remove what was there before.
4559 Insert `// case: 7 ' or `// NAME ' on this line if appropriate.
4560 Insert `// case expr ' if this line ends a case block.
4561 Insert `// ifdef FOO ' if this line ends code conditional on FOO.
4562 Insert `// NAME ' if this line ends a function, task, module,
4563 primitive or interface named NAME."
4566 (; Comment close preprocessor directives
4568 (looking-at "\\(`endif\\)\\|\\(`else\\)")
4569 (or kill-existing-comment
4570 (not (save-excursion
4572 (search-backward "//" (point-at-bol) t)))))
4575 (else (if (match-end 2) "!" " ")))
4577 (if kill-existing-comment
4578 (verilog-kill-existing-comment))
4579 (delete-horizontal-space)
4582 (while (and (/= nest 0)
4583 (verilog-re-search-backward verilog-directive-nest-re nil 'move))
4585 ((match-end 1) ; `else
4588 ((match-end 2) ; `endif
4589 (setq nest (1+ nest)))
4590 ((match-end 3) ; `if
4591 (setq nest (1- nest)))
4592 ((match-end 4) ; `ifdef
4593 (setq nest (1- nest)))
4594 ((match-end 5) ; `ifndef
4595 (setq nest (1- nest)))
4596 ((match-end 6) ; `elsif
4607 (skip-chars-forward "^ \t")
4608 (verilog-forward-syntactic-ws)
4611 (skip-chars-forward "a-zA-Z0-9_")
4614 (if (> (count-lines (point) b) verilog-minimum-comment-distance)
4615 (insert (concat " // " else m " " (buffer-substring b e))))
4617 (insert " // unmatched `else, `elsif or `endif")
4620 (; Comment close case/class/function/task/module and named block
4621 (and (looking-at "\\<end")
4622 (or kill-existing-comment
4623 (not (save-excursion
4625 (search-backward "//" (point-at-bol) t)))))
4626 (let ((type (car indent-str)))
4627 (unless (eq type 'declaration)
4628 (unless (looking-at (concat "\\(" verilog-end-block-ordered-re "\\)[ \t]*:")) ;; ignore named ends
4629 (if (looking-at verilog-end-block-ordered-re)
4631 (;- This is a case block; search back for the start of this case
4632 (match-end 1) ;; of verilog-end-block-ordered-re
4635 (str "UNMATCHED!!"))
4637 (verilog-leap-to-head)
4639 ((looking-at "\\<randcase\\>")
4640 (setq str "randcase")
4642 ((looking-at "\\(\\(unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
4643 (goto-char (match-end 0))
4644 (setq str (concat (match-string 0) " " (verilog-get-expr)))
4648 (if kill-existing-comment
4649 (verilog-kill-existing-comment))
4650 (delete-horizontal-space)
4651 (insert (concat " // " str ))
4652 (if err (ding 't))))
4654 (;- This is a begin..end block
4655 (match-end 2) ;; of verilog-end-block-ordered-re
4656 (let ((str " // UNMATCHED !!")
4662 (verilog-leap-to-head)
4663 (setq there (point))
4664 (if (not (match-end 0))
4668 (if kill-existing-comment
4669 (verilog-kill-existing-comment))
4670 (delete-horizontal-space)
4674 (save-excursion (verilog-beg-of-defun) (point)))
4677 (;-- handle named block differently
4678 (looking-at verilog-named-block-re)
4679 (search-forward ":")
4680 (setq there (point))
4681 (setq str (verilog-get-expr))
4683 (setq str (concat " // block: " str )))
4685 ((verilog-in-case-region-p) ;-- handle case item differently
4687 (setq str (verilog-backward-case-item lim))
4688 (setq there (point))
4690 (setq str (concat " // case: " str )))
4692 (;- try to find "reason" for this begin
4696 ;; (verilog-backward-token)
4697 (verilog-beg-of-statement)
4701 ((looking-at verilog-endcomment-reason-re)
4702 (setq there (match-end 0))
4703 (setq cntx (concat (match-string 0) " "))
4709 (if (and (verilog-continued-line)
4710 (looking-at "\\<repeat\\>\\|\\<wait\\>\\|\\<always\\>"))
4712 (goto-char (match-end 0))
4713 (setq there (point))
4715 (concat " // " (match-string 0) " " (verilog-get-expr))))
4721 ( reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)\\|\\(assert\\)"))
4723 (while (verilog-re-search-backward reg nil 'move)
4725 ((match-end 1) ; begin
4726 (setq nest (1- nest)))
4727 ((match-end 2) ; end
4728 (setq nest (1+ nest)))
4732 (goto-char (match-end 0))
4733 (setq there (point))
4735 (setq str (verilog-get-expr))
4736 (setq str (concat " // else: !if" str ))
4741 (goto-char (match-end 0))
4742 (setq there (point))
4744 (setq str (verilog-get-expr))
4745 (setq str (concat " // else: !assert " str ))
4746 (throw 'skip 1)))))))))
4751 (reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)\\|\\(assert\\)"))
4753 (while (verilog-re-search-backward reg nil 'move)
4755 ((match-end 1) ; begin
4756 (setq nest (1- nest)))
4757 ((match-end 2) ; end
4758 (setq nest (1+ nest)))
4762 (goto-char (match-end 0))
4763 (setq there (point))
4765 (setq str (verilog-get-expr))
4766 (setq str (concat " // else: !if" str ))
4771 (goto-char (match-end 0))
4772 (setq there (point))
4774 (setq str (verilog-get-expr))
4775 (setq str (concat " // else: !assert " str ))
4776 (throw 'skip 1)))))))))
4778 (; always, always_comb, always_latch w/o @...
4780 (goto-char (match-end 0))
4781 (setq there (point))
4783 (setq str (concat " // " cntx )))
4785 (;- task/function/initial et cetera
4788 (goto-char (match-end 0))
4789 (setq there (point))
4791 (setq str (concat " // " cntx (verilog-get-expr))))
4794 (setq str " // auto-endcomment confused "))))
4797 (verilog-in-case-region-p) ;-- handle case item differently
4799 (setq there (point))
4801 (setq str (verilog-backward-case-item lim))))
4803 (setq str (concat " // case: " str )))
4805 ((verilog-in-fork-region-p)
4807 (setq str " // fork branch" ))
4809 ((looking-at "\\<end\\>")
4812 (verilog-forward-syntactic-ws)
4814 (setq str (verilog-get-expr))
4815 (setq str (concat " // " cntx str )))
4820 (if kill-existing-comment
4821 (verilog-kill-existing-comment))
4822 (delete-horizontal-space)
4824 (> (count-lines here there) verilog-minimum-comment-distance))
4828 (;- this is endclass, which can be nested
4829 (match-end 11) ;; of verilog-end-block-ordered-re
4832 (reg "\\<\\(class\\)\\|\\(endclass\\)\\|\\(package\\|primitive\\|\\(macro\\)?module\\)\\>")
4836 (while (verilog-re-search-backward reg nil 'move)
4838 ((match-end 3) ; endclass
4840 (setq string "unmatched endclass")
4843 ((match-end 2) ; endclass
4844 (setq nest (1+ nest)))
4846 ((match-end 1) ; class
4847 (setq nest (1- nest))
4850 (goto-char (match-end 0))
4853 (skip-chars-forward "^ \t")
4854 (verilog-forward-ws&directives)
4857 (skip-chars-forward "a-zA-Z0-9_")
4859 (setq string (buffer-substring b e)))
4863 (if kill-existing-comment
4864 (verilog-kill-existing-comment))
4865 (delete-horizontal-space)
4866 (insert (concat " // " string ))))
4868 (;- this is end{function,generate,task,module,primitive,table,generate}
4869 ;- which can not be nested.
4871 (let (string reg (name-re nil))
4873 (if kill-existing-comment
4875 (verilog-kill-existing-comment)))
4876 (delete-horizontal-space)
4879 ((match-end 5) ;; of verilog-end-block-ordered-re
4880 (setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
4881 (setq name-re "\\w+\\(?:\n\\|\\s-\\)*[(;]"))
4882 ((match-end 6) ;; of verilog-end-block-ordered-re
4883 (setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
4884 (setq name-re "\\w+\\(?:\n\\|\\s-\\)*[(;]"))
4885 ((match-end 7) ;; of verilog-end-block-ordered-re
4886 (setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\<endmodule\\>"))
4887 ((match-end 8) ;; of verilog-end-block-ordered-re
4888 (setq reg "\\(\\<primitive\\>\\)\\|\\(\\<\\(endprimitive\\|package\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4889 ((match-end 9) ;; of verilog-end-block-ordered-re
4890 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<\\(endinterface\\|package\\|primitive\\|\\(macro\\)?module\\)\\>\\)"))
4891 ((match-end 10) ;; of verilog-end-block-ordered-re
4892 (setq reg "\\(\\<package\\>\\)\\|\\(\\<\\(endpackage\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4893 ((match-end 11) ;; of verilog-end-block-ordered-re
4894 (setq reg "\\(\\<class\\>\\)\\|\\(\\<\\(endclass\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4895 ((match-end 12) ;; of verilog-end-block-ordered-re
4896 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<\\(endcovergroup\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4897 ((match-end 13) ;; of verilog-end-block-ordered-re
4898 (setq reg "\\(\\<program\\>\\)\\|\\(\\<\\(endprogram\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4899 ((match-end 14) ;; of verilog-end-block-ordered-re
4900 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<\\(endsequence\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4901 ((match-end 15) ;; of verilog-end-block-ordered-re
4902 (setq reg "\\(\\<clocking\\>\\)\\|\\<endclocking\\>"))
4903 ((match-end 16) ;; of verilog-end-block-ordered-re
4904 (setq reg "\\(\\<property\\>\\)\\|\\<endproperty\\>"))
4906 (t (error "Problem in verilog-set-auto-endcomments")))
4909 (verilog-re-search-backward reg nil 'move)
4913 (skip-chars-forward "^ \t")
4914 (verilog-forward-ws&directives)
4915 (if (looking-at "static\\|automatic")
4917 (goto-char (match-end 0))
4918 (verilog-forward-ws&directives)))
4919 (if (and name-re (verilog-re-search-forward name-re nil 'move))
4921 (goto-char (match-beginning 0))
4922 (verilog-forward-ws&directives)))
4925 (skip-chars-forward "a-zA-Z0-9_")
4927 (setq string (buffer-substring b e)))
4930 (setq string "unmatched end(function|task|module|primitive|interface|package|class|clocking)")))))
4932 (insert (concat " // " string )))
4935 (defun verilog-get-expr()
4936 "Grab expression at point, e.g., case ( a | b & (c ^d))."
4938 (verilog-forward-syntactic-ws)
4939 (skip-chars-forward " \t")
4945 (verilog-forward-syntactic-ws)
4946 (if (looking-at "(")
4949 (while (and (/= par 0)
4950 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
4953 (setq par (1+ par)))
4955 (setq par (1- par)))))))
4959 (while (and (/= par 0)
4960 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
4963 (setq par (1+ par)))
4965 (setq par (1- par)))))
4969 (while (and (/= par 0)
4970 (verilog-re-search-forward "\\(\\[\\)\\|\\(\\]\\)" nil 'move))
4973 (setq par (1+ par)))
4975 (setq par (1- par)))))
4976 (verilog-forward-syntactic-ws)
4977 (skip-chars-forward "^ \t\n\f")
4979 ((looking-at "/[/\\*]")
4982 (skip-chars-forward "^: \t\n\f")
4984 (str (buffer-substring b e)))
4985 (if (setq e (string-match "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
4986 (setq str (concat (substring str 0 e) "...")))
4989 (defun verilog-expand-vector ()
4990 "Take a signal vector on the current line and expand it to multiple lines.
4991 Useful for creating tri's and other expanded fields."
4993 (verilog-expand-vector-internal "[" "]"))
4995 (defun verilog-expand-vector-internal (bra ket)
4996 "Given BRA, the start brace and KET, the end brace, expand one line into many lines."
4999 (let ((signal-string (buffer-substring (point)
5001 (end-of-line) (point)))))
5005 "\\([0-9]*\\)\\(:[0-9]*\\|\\)\\(::[0-9---]*\\|\\)"
5007 "\\(.*\\)$") signal-string)
5008 (let* ((sig-head (match-string 1 signal-string))
5009 (vec-start (string-to-number (match-string 2 signal-string)))
5010 (vec-end (if (= (match-beginning 3) (match-end 3))
5013 (substring signal-string (1+ (match-beginning 3))
5016 (if (= (match-beginning 4) (match-end 4))
5019 (substring signal-string (+ 2 (match-beginning 4))
5021 (sig-tail (match-string 5 signal-string))
5026 (let ((tmp vec-start))
5027 (setq vec-start vec-end
5029 vec-range (- vec-range))))
5030 (if (< vec-end vec-start)
5031 (while (<= vec-end vec-start)
5032 (setq vec (append vec (list vec-start)))
5033 (setq vec-start (- vec-start vec-range)))
5034 (while (<= vec-start vec-end)
5035 (setq vec (append vec (list vec-start)))
5036 (setq vec-start (+ vec-start vec-range))))
5038 ;; Delete current line
5039 (delete-region (point) (progn (forward-line 0) (point)))
5043 (insert (concat sig-head bra
5044 (int-to-string (car vec)) ket sig-tail "\n"))
5045 (setq vec (cdr vec)))
5050 (defun verilog-strip-comments ()
5051 "Strip all comments from the Verilog code."
5053 (goto-char (point-min))
5054 (while (re-search-forward "//" nil t)
5055 (if (verilog-within-string)
5056 (re-search-forward "\"" nil t)
5057 (if (verilog-in-star-comment-p)
5058 (re-search-forward "\*/" nil t)
5059 (let ((bpt (- (point) 2)))
5061 (delete-region bpt (point))))))
5063 (goto-char (point-min))
5064 (while (re-search-forward "/\\*" nil t)
5065 (if (verilog-within-string)
5066 (re-search-forward "\"" nil t)
5067 (let ((bpt (- (point) 2)))
5068 (re-search-forward "\\*/")
5069 (delete-region bpt (point))))))
5071 (defun verilog-one-line ()
5072 "Convert structural Verilog instances to occupy one line."
5074 (goto-char (point-min))
5075 (while (re-search-forward "\\([^;]\\)[ \t]*\n[ \t]*" nil t)
5076 (replace-match "\\1 " nil nil)))
5078 (defun verilog-linter-name ()
5079 "Return name of linter, either surelint or verilint."
5080 (let ((compile-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
5082 (lint-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
5084 (cond ((equal compile-word1 "surelint") `surelint)
5085 ((equal compile-word1 "verilint") `verilint)
5086 ((equal lint-word1 "surelint") `surelint)
5087 ((equal lint-word1 "verilint") `verilint)
5088 (t `surelint)))) ;; back compatibility
5090 (defun verilog-lint-off ()
5091 "Convert a Verilog linter warning line into a disable statement.
5093 pci_bfm_null.v, line 46: Unused input: pci_rst_
5094 becomes a comment for the appropriate tool.
5096 The first word of the `compile-command' or `verilog-linter'
5097 variables is used to determine which product is being used.
5099 See \\[verilog-surelint-off] and \\[verilog-verilint-off]."
5101 (let ((linter (verilog-linter-name)))
5102 (cond ((equal linter `surelint)
5103 (verilog-surelint-off))
5104 ((equal linter `verilint)
5105 (verilog-verilint-off))
5106 (t (error "Linter name not set")))))
5108 (defvar compilation-last-buffer)
5109 (defvar next-error-last-buffer)
5111 (defun verilog-surelint-off ()
5112 "Convert a SureLint warning line into a disable statement.
5113 Run from Verilog source window; assumes there is a *compile* buffer
5114 with point set appropriately.
5117 WARNING [STD-UDDONX]: xx.v, line 8: output out is never assigned.
5119 // surefire lint_line_off UDDONX"
5121 (let ((buff (if (boundp 'next-error-last-buffer)
5122 next-error-last-buffer
5123 compilation-last-buffer)))
5124 (when (buffer-live-p buff)
5126 (switch-to-buffer buff)
5129 (looking-at "\\(INFO\\|WARNING\\|ERROR\\) \\[[^-]+-\\([^]]+\\)\\]: \\([^,]+\\), line \\([0-9]+\\): \\(.*\\)$")
5130 (let* ((code (match-string 2))
5131 (file (match-string 3))
5132 (line (match-string 4))
5133 (buffer (get-file-buffer file))
5138 (and (file-exists-p file)
5139 (find-file-noselect file)))
5141 (let* ((pop-up-windows t))
5142 (let ((name (expand-file-name
5144 (format "Find this error in: (default %s) "
5147 (if (file-directory-p name)
5148 (setq name (expand-file-name filename name)))
5150 (and (file-exists-p name)
5151 (find-file-noselect name))))))))
5152 (switch-to-buffer buffer)
5153 (goto-char (point-min))
5154 (forward-line (- (string-to-number line)))
5158 ((verilog-in-slash-comment-p)
5159 (re-search-backward "//")
5161 ((looking-at "// surefire lint_off_line ")
5162 (goto-char (match-end 0))
5163 (let ((lim (point-at-eol)))
5164 (if (re-search-forward code lim 'move)
5166 (insert (concat " " code)))))
5169 ((verilog-in-star-comment-p)
5170 (re-search-backward "/\*")
5171 (insert (format " // surefire lint_off_line %6s" code )))
5173 (insert (format " // surefire lint_off_line %6s" code ))
5176 (defun verilog-verilint-off ()
5177 "Convert a Verilint warning line into a disable statement.
5180 (W240) pci_bfm_null.v, line 46: Unused input: pci_rst_
5182 //Verilint 240 off // WARNING: Unused input"
5186 (when (looking-at "\\(.*\\)([WE]\\([0-9A-Z]+\\)).*,\\s +line\\s +[0-9]+:\\s +\\([^:\n]+\\):?.*$")
5187 (replace-match (format
5188 ;; %3s makes numbers 1-999 line up nicely
5189 "\\1//Verilint %3s off // WARNING: \\3"
5192 (verilog-indent-line))))
5194 (defun verilog-auto-save-compile ()
5195 "Update automatics with \\[verilog-auto], save the buffer, and compile."
5197 (verilog-auto) ; Always do it for safety
5199 (compile compile-command))
5201 (defun verilog-preprocess (&optional command filename)
5202 "Preprocess the buffer, similar to `compile', but put output in Verilog-Mode.
5203 Takes optional COMMAND or defaults to `verilog-preprocessor', and
5204 FILENAME to find directory to run in, or defaults to `buffer-file-name'."
5207 (let ((default (verilog-expand-command verilog-preprocessor)))
5208 (set (make-local-variable `verilog-preprocessor)
5209 (read-from-minibuffer "Run Preprocessor (like this): "
5211 'verilog-preprocess-history default)))))
5212 (unless command (setq command (verilog-expand-command verilog-preprocessor)))
5213 (let* ((fontlocked (and (boundp 'font-lock-mode) font-lock-mode))
5214 (dir (file-name-directory (or filename buffer-file-name)))
5215 (cmd (concat "cd " dir "; " command)))
5216 (with-output-to-temp-buffer "*Verilog-Preprocessed*"
5217 (with-current-buffer (get-buffer "*Verilog-Preprocessed*")
5218 (insert (concat "// " cmd "\n"))
5219 (call-process shell-file-name nil t nil shell-command-switch cmd)
5221 ;; Without this force, it takes a few idle seconds
5222 ;; to get the color, which is very jarring
5223 (unless (fboundp 'font-lock-ensure)
5224 ;; We should use font-lock-ensure in preference to
5225 ;; font-lock-fontify-buffer, but IIUC the problem this is supposed to
5226 ;; solve only appears in Emacsen older than font-lock-ensure anyway.
5227 ;; So avoid bytecomp's interactive-only by going through intern.
5228 (when fontlocked (funcall (intern "font-lock-fontify-buffer"))))))))
5235 (defun verilog-warn (string &rest args)
5236 "Print a warning with `format' using STRING and optional ARGS."
5237 (apply 'message (concat "%%Warning: " string) args))
5239 (defun verilog-warn-error (string &rest args)
5240 "Call `error' using STRING and optional ARGS.
5241 If `verilog-warn-fatal' is non-nil, call `verilog-warn' instead."
5242 (if verilog-warn-fatal
5243 (apply 'error string args)
5244 (apply 'verilog-warn string args)))
5246 (defmacro verilog-batch-error-wrapper (&rest body)
5247 "Execute BODY and add error prefix to any errors found.
5248 This lets programs calling batch mode to easily extract error messages."
5249 `(let ((verilog-warn-fatal nil))
5253 (error "%%Error: %s%s" (error-message-string err)
5254 (if (featurep 'xemacs) "\n" "")))))) ;; XEmacs forgets to add a newline
5256 (defun verilog-batch-execute-func (funref &optional no-save)
5257 "Internal processing of a batch command.
5258 Runs FUNREF on all command arguments.
5259 Save the result unless optional NO-SAVE is t."
5260 (verilog-batch-error-wrapper
5261 ;; Setting global variables like that is *VERY NASTY* !!! --Stef
5262 ;; However, this function is called only when Emacs is being used as
5263 ;; a standalone language instead of as an editor, so we'll live.
5265 ;; General globals needed
5266 (setq make-backup-files nil)
5267 (setq-default make-backup-files nil)
5268 (setq enable-local-variables t)
5269 (setq enable-local-eval t)
5270 (setq create-lockfiles nil)
5271 ;; Make sure any sub-files we read get proper mode
5272 (setq-default major-mode 'verilog-mode)
5273 ;; Ditto files already read in
5274 ;; Remember buffer list, so don't later pickup any verilog-getopt files
5275 (let ((orig-buffer-list (buffer-list)))
5277 (when (buffer-file-name buf)
5278 (with-current-buffer buf
5280 (verilog-auto-reeval-locals)
5281 (verilog-getopt-flags))))
5283 ;; Process the files
5284 (mapcar (lambda (buf)
5285 (when (buffer-file-name buf)
5287 (if (not (file-exists-p (buffer-file-name buf)))
5289 (concat "File not found: " (buffer-file-name buf))))
5290 (message (concat "Processing " (buffer-file-name buf)))
5293 (when (and (not no-save)
5294 (buffer-modified-p)) ;; Avoid "no changes to be saved"
5296 orig-buffer-list))))
5298 (defun verilog-batch-auto ()
5299 "For use with --batch, perform automatic expansions as a stand-alone tool.
5300 This sets up the appropriate Verilog mode environment, updates automatics
5301 with \\[verilog-auto] on all command-line files, and saves the buffers.
5302 For proper results, multiple filenames need to be passed on the command
5303 line in bottom-up order."
5304 (unless noninteractive
5305 (error "Use verilog-batch-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
5306 (verilog-batch-execute-func `verilog-auto))
5308 (defun verilog-batch-delete-auto ()
5309 "For use with --batch, perform automatic deletion as a stand-alone tool.
5310 This sets up the appropriate Verilog mode environment, deletes automatics
5311 with \\[verilog-delete-auto] on all command-line files, and saves the buffers."
5312 (unless noninteractive
5313 (error "Use verilog-batch-delete-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
5314 (verilog-batch-execute-func `verilog-delete-auto))
5316 (defun verilog-batch-delete-trailing-whitespace ()
5317 "For use with --batch, perform whitespace deletion as a stand-alone tool.
5318 This sets up the appropriate Verilog mode environment, removes
5319 whitespace with \\[verilog-delete-trailing-whitespace] on all
5320 command-line files, and saves the buffers."
5321 (unless noninteractive
5322 (error "Use verilog-batch-delete-trailing-whitespace only with --batch")) ;; Otherwise we'd mess up buffer modes
5323 (verilog-batch-execute-func `verilog-delete-trailing-whitespace))
5325 (defun verilog-batch-diff-auto ()
5326 "For use with --batch, perform automatic differences as a stand-alone tool.
5327 This sets up the appropriate Verilog mode environment, expand automatics
5328 with \\[verilog-diff-auto] on all command-line files, and reports an error
5329 if any differences are observed. This is appropriate for adding to regressions
5330 to insure automatics are always properly maintained."
5331 (unless noninteractive
5332 (error "Use verilog-batch-diff-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
5333 (verilog-batch-execute-func `verilog-diff-auto t))
5335 (defun verilog-batch-inject-auto ()
5336 "For use with --batch, perform automatic injection as a stand-alone tool.
5337 This sets up the appropriate Verilog mode environment, injects new automatics
5338 with \\[verilog-inject-auto] on all command-line files, and saves the buffers.
5339 For proper results, multiple filenames need to be passed on the command
5340 line in bottom-up order."
5341 (unless noninteractive
5342 (error "Use verilog-batch-inject-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
5343 (verilog-batch-execute-func `verilog-inject-auto))
5345 (defun verilog-batch-indent ()
5346 "For use with --batch, reindent an entire file as a stand-alone tool.
5347 This sets up the appropriate Verilog mode environment, calls
5348 \\[verilog-indent-buffer] on all command-line files, and saves the buffers."
5349 (unless noninteractive
5350 (error "Use verilog-batch-indent only with --batch")) ;; Otherwise we'd mess up buffer modes
5351 (verilog-batch-execute-func `verilog-indent-buffer))
5357 (defconst verilog-indent-alist
5358 '((block . (+ ind verilog-indent-level))
5359 (case . (+ ind verilog-case-indent))
5360 (cparenexp . (+ ind verilog-indent-level))
5361 (cexp . (+ ind verilog-cexp-indent))
5362 (defun . verilog-indent-level-module)
5363 (declaration . verilog-indent-level-declaration)
5364 (directive . (verilog-calculate-indent-directive))
5365 (tf . verilog-indent-level)
5366 (behavioral . (+ verilog-indent-level-behavioral verilog-indent-level-module))
5369 (comment . (verilog-comment-indent))
5373 (defun verilog-continued-line-1 (lim)
5374 "Return true if this is a continued line.
5375 Set point to where line starts. Limit search to point LIM."
5376 (let ((continued 't))
5377 (if (eq 0 (forward-line -1))
5380 (verilog-backward-ws&directives lim)
5382 (setq continued nil)
5383 (setq continued (verilog-backward-token))))
5384 (setq continued nil))
5387 (defun verilog-calculate-indent ()
5388 "Calculate the indent of the current Verilog line.
5389 Examine previous lines. Once a line is found that is definitive as to the
5390 type of the current line, return that lines' indent level and its type.
5391 Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
5393 (let* ((starting_position (point))
5395 (begin (looking-at "[ \t]*begin\\>"))
5396 (lim (save-excursion (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)" nil t)))
5398 (type (catch 'nesting
5399 ;; Keep working backwards until we can figure out
5400 ;; what type of statement this is.
5401 ;; Basically we need to figure out
5402 ;; 1) if this is a continuation of the previous line;
5403 ;; 2) are we in a block scope (begin..end)
5405 ;; if we are in a comment, done.
5406 (if (verilog-in-star-comment-p)
5407 (throw 'nesting 'comment))
5409 ;; if we have a directive, done.
5410 (if (save-excursion (beginning-of-line)
5411 (and (looking-at verilog-directive-re-1)
5412 (not (or (looking-at "[ \t]*`[ou]vm_")
5413 (looking-at "[ \t]*`vmm_")))))
5414 (throw 'nesting 'directive))
5415 ;; indent structs as if there were module level
5416 (setq structres (verilog-in-struct-nested-p))
5417 (cond ((not structres) nil)
5418 ;;((and structres (equal (char-after) ?\})) (throw 'nesting 'struct-close))
5419 ((> structres 0) (throw 'nesting 'nested-struct))
5420 ((= structres 0) (throw 'nesting 'block))
5423 ;; if we are in a parenthesized list, and the user likes to indent these, return.
5424 ;; unless we are in the newfangled coverpoint or constraint blocks
5426 verilog-indent-lists
5428 (not (verilog-in-coverage-p))
5431 (throw 'nesting 'block)))
5433 ;; See if we are continuing a previous line
5435 ;; trap out if we crawl off the top of the buffer
5436 (if (bobp) (throw 'nesting 'cpp))
5438 (if (and (verilog-continued-line-1 lim)
5439 (or (not (verilog-in-coverage-p))
5440 (looking-at verilog-in-constraint-re) )) ;; may still get hosed if concat in constraint
5443 (not (looking-at verilog-complete-reg))
5444 (verilog-continued-line-1 lim))
5445 (progn (goto-char sp)
5446 (throw 'nesting 'cexp))
5449 (if (and (verilog-in-coverage-p)
5450 (looking-at verilog-in-constraint-re))
5453 (skip-chars-forward " \t")
5454 (throw 'nesting 'constraint)))
5456 (not verilog-indent-begin-after-if)
5457 (looking-at verilog-no-indent-begin-re))
5460 (skip-chars-forward " \t")
5461 (throw 'nesting 'statement))
5463 (throw 'nesting 'cexp))))
5464 ;; not a continued line
5465 (goto-char starting_position))
5467 (if (looking-at "\\<else\\>")
5468 ;; search back for governing if, striding across begin..end pairs
5471 (while (verilog-re-search-backward verilog-ends-re nil 'move)
5473 ((match-end 1) ; else, we're in deep
5474 (setq elsec (1+ elsec)))
5476 (setq elsec (1- elsec))
5478 (if verilog-align-ifelse
5479 (throw 'nesting 'statement)
5480 (progn ;; back up to first word on this line
5482 (verilog-forward-syntactic-ws)
5483 (throw 'nesting 'statement)))))
5484 ((match-end 3) ; assert block
5485 (setq elsec (1- elsec))
5486 (verilog-beg-of-statement) ;; doesn't get to beginning
5487 (if (looking-at verilog-property-re)
5488 (throw 'nesting 'statement) ; We don't need an endproperty for these
5489 (throw 'nesting 'block) ;We still need an endproperty
5492 ; try to leap back to matching outward block by striding across
5493 ; indent level changing tokens then immediately
5494 ; previous line governs indentation.
5495 (let (( reg) (nest 1))
5496 ;; verilog-ends => else|if|end|join(_any|_none|)|endcase|endclass|endtable|endspecify|endfunction|endtask|endgenerate|endgroup
5498 ((match-end 4) ; end
5499 ;; Search back for matching begin
5500 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
5501 ((match-end 5) ; endcase
5502 ;; Search back for matching case
5503 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
5504 ((match-end 6) ; endfunction
5505 ;; Search back for matching function
5506 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
5507 ((match-end 7) ; endtask
5508 ;; Search back for matching task
5509 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
5510 ((match-end 8) ; endspecify
5511 ;; Search back for matching specify
5512 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
5513 ((match-end 9) ; endtable
5514 ;; Search back for matching table
5515 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
5516 ((match-end 10) ; endgenerate
5517 ;; Search back for matching generate
5518 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
5519 ((match-end 11) ; joins
5520 ;; Search back for matching fork
5521 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|none\\)?\\>\\)" ))
5522 ((match-end 12) ; class
5523 ;; Search back for matching class
5524 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
5525 ((match-end 13) ; covergroup
5526 ;; Search back for matching covergroup
5527 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" )))
5529 (while (verilog-re-search-backward reg nil 'move)
5531 ((match-end 1) ; begin
5532 (setq nest (1- nest))
5535 ((match-end 2) ; end
5536 (setq nest (1+ nest)))))
5538 (throw 'nesting (verilog-calc-1)))
5542 ;; Return type of block and indent level.
5545 (if (> par 0) ; Unclosed Parenthesis
5546 (list 'cparenexp par)
5549 (list type (verilog-case-indent-level)))
5550 ((eq type 'statement)
5551 (list type (current-column)))
5554 ((eq type 'constraint)
5555 (list 'block (current-column)))
5556 ((eq type 'nested-struct)
5557 (list 'block structres))
5559 (list type (verilog-current-indent-level))))))))
5561 (defun verilog-wai ()
5562 "Show matching nesting block for debugging."
5565 (let* ((type (verilog-calc-1))
5567 ;; Return type of block and indent level.
5571 verilog-indent-lists
5572 (not(or (verilog-in-coverage-p)
5573 (verilog-in-struct-p)))
5578 (setq depth (verilog-case-indent-level)))
5579 ((eq type 'statement)
5580 (setq depth (current-column)))
5584 (setq depth (verilog-current-indent-level)))))
5585 (message "You are at nesting %s depth %d" type depth))))
5587 (defun verilog-calc-1 ()
5589 (let ((re (concat "\\({\\|}\\|" verilog-indent-re "\\)"))
5590 (inconstraint (verilog-in-coverage-p)))
5591 (while (verilog-re-search-backward re nil 'move)
5594 ((equal (char-after) ?\{)
5595 ;; block type returned based on outer constraint { or inner
5596 (if (verilog-at-constraint-p)
5598 (beginning-of-line nil)
5599 (skip-chars-forward " \t")
5600 (throw 'nesting 'constraint))
5602 (throw 'nesting 'statement)))))
5603 ((equal (char-after) ?\})
5605 (there (verilog-at-close-constraint-p)))
5606 (if there ;; we are at the } that closes a constraint. Find the { that opens it
5608 (if (> (verilog-in-paren-count) 0)
5610 (setq par-pos (verilog-parenthesis-depth))
5615 (backward-char 1)))))))
5617 ((looking-at verilog-beg-block-re-ordered)
5619 ((match-end 2) ; *sigh* could be "unique case" or "priority casex"
5620 (let ((here (point)))
5621 (verilog-beg-of-statement)
5622 (if (looking-at verilog-extended-case-re)
5623 (throw 'nesting 'case)
5625 (throw 'nesting 'case))
5627 ((match-end 4) ; *sigh* could be "disable fork"
5628 (let ((here (point)))
5629 (verilog-beg-of-statement)
5630 (if (looking-at verilog-disable-fork-re)
5631 t ; this is a normal statement
5632 (progn ; or is fork, starts a new block
5634 (throw 'nesting 'block)))))
5636 ((match-end 27) ; *sigh* might be a clocking declaration
5637 (let ((here (point)))
5638 (if (verilog-in-paren)
5639 t ; this is a normal statement
5640 (progn ; or is fork, starts a new block
5642 (throw 'nesting 'block)))))
5644 ;; need to consider typedef struct here...
5645 ((looking-at "\\<class\\|struct\\|function\\|task\\>")
5646 ; *sigh* These words have an optional prefix:
5647 ; extern {virtual|protected}? function a();
5648 ; typedef class foo;
5649 ; and we don't want to confuse this with
5654 (verilog-beg-of-statement)
5655 (if (looking-at verilog-beg-block-re-ordered)
5656 (throw 'nesting 'block)
5657 (throw 'nesting 'defun)))
5660 ((looking-at "\\<property\\>")
5662 ; {assert|assume|cover} property (); are complete
5663 ; and could also be labeled: - foo: assert property
5665 ; property ID () ... needs end_property
5666 (verilog-beg-of-statement)
5667 (if (looking-at verilog-property-re)
5668 (throw 'continue 'statement) ; We don't need an endproperty for these
5669 (throw 'nesting 'block) ;We still need an endproperty
5672 (t (throw 'nesting 'block))))
5674 ((looking-at verilog-end-block-re)
5675 (verilog-leap-to-head)
5676 (if (verilog-in-case-region-p)
5678 (verilog-leap-to-case-head)
5679 (if (looking-at verilog-extended-case-re)
5680 (throw 'nesting 'case)))))
5682 ((looking-at verilog-defun-level-re)
5683 (if (looking-at verilog-defun-level-generate-only-re)
5684 (if (verilog-in-generate-region-p)
5685 (throw 'continue 'foo) ; always block in a generate - keep looking
5686 (throw 'nesting 'defun))
5687 (throw 'nesting 'defun)))
5689 ((looking-at verilog-cpp-level-re)
5690 (throw 'nesting 'cpp))
5693 (throw 'nesting 'cpp)))))
5695 (throw 'nesting 'cpp))))
5697 (defun verilog-calculate-indent-directive ()
5698 "Return indentation level for directive.
5699 For speed, the searcher looks at the last directive, not the indent
5700 of the appropriate enclosing block."
5701 (let ((base -1) ;; Indent of the line that determines our indentation
5702 (ind 0)) ;; Relative offset caused by other directives (like `endif on same line as `else)
5703 ;; Start at current location, scan back for another directive
5707 (while (and (< base 0)
5708 (verilog-re-search-backward verilog-directive-re nil t))
5709 (cond ((save-excursion (skip-chars-backward " \t") (bolp))
5710 (setq base (current-indentation))))
5711 (cond ((and (looking-at verilog-directive-end) (< base 0)) ;; Only matters when not at BOL
5712 (setq ind (- ind verilog-indent-level-directive)))
5713 ((and (looking-at verilog-directive-middle) (>= base 0)) ;; Only matters when at BOL
5714 (setq ind (+ ind verilog-indent-level-directive)))
5715 ((looking-at verilog-directive-begin)
5716 (setq ind (+ ind verilog-indent-level-directive)))))
5717 ;; Adjust indent to starting indent of critical line
5718 (setq ind (max 0 (+ ind base))))
5722 (skip-chars-forward " \t")
5723 (cond ((or (looking-at verilog-directive-middle)
5724 (looking-at verilog-directive-end))
5725 (setq ind (max 0 (- ind verilog-indent-level-directive))))))
5728 (defun verilog-leap-to-case-head ()
5731 (verilog-re-search-backward
5733 "\\(\\<randcase\\>\\|\\(\\<unique0?\\s-+\\|priority\\s-+\\)?\\<case[xz]?\\>\\)"
5734 "\\|\\(\\<endcase\\>\\)" )
5738 (let ((here (point)))
5739 (verilog-beg-of-statement)
5740 (unless (looking-at verilog-extended-case-re)
5742 (setq nest (1- nest)))
5744 (setq nest (1+ nest)))
5749 (defun verilog-leap-to-head ()
5750 "Move point to the head of this block.
5751 Jump from end to matching begin, from endcase to matching case, and so on."
5757 ((looking-at "\\<end\\>")
5758 ;; 1: Search back for matching begin
5759 (setq reg (concat "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|"
5760 "\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))
5761 ((looking-at "\\<endtask\\>")
5762 ;; 2: Search back for matching task
5763 (setq reg "\\(\\<task\\>\\)\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)+\\<task\\>\\)")
5765 ((looking-at "\\<endcase\\>")
5767 (verilog-leap-to-case-head) )
5768 (setq reg nil) ; to force skip
5771 ((looking-at "\\<join\\(_any\\|_none\\)?\\>")
5772 ;; 4: Search back for matching fork
5773 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
5774 ((looking-at "\\<endclass\\>")
5775 ;; 5: Search back for matching class
5776 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
5777 ((looking-at "\\<endtable\\>")
5778 ;; 6: Search back for matching table
5779 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
5780 ((looking-at "\\<endspecify\\>")
5781 ;; 7: Search back for matching specify
5782 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
5783 ((looking-at "\\<endfunction\\>")
5784 ;; 8: Search back for matching function
5785 (setq reg "\\(\\<function\\>\\)\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)+\\<function\\>\\)")
5787 ;;(setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
5788 ((looking-at "\\<endgenerate\\>")
5789 ;; 8: Search back for matching generate
5790 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
5791 ((looking-at "\\<endgroup\\>")
5792 ;; 10: Search back for matching covergroup
5793 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
5794 ((looking-at "\\<endproperty\\>")
5795 ;; 11: Search back for matching property
5796 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
5797 ((looking-at verilog-uvm-end-re)
5798 ;; 12: Search back for matching sequence
5799 (setq reg (concat "\\(" verilog-uvm-begin-re "\\|" verilog-uvm-end-re "\\)")))
5800 ((looking-at verilog-ovm-end-re)
5801 ;; 12: Search back for matching sequence
5802 (setq reg (concat "\\(" verilog-ovm-begin-re "\\|" verilog-ovm-end-re "\\)")))
5803 ((looking-at verilog-vmm-end-re)
5804 ;; 12: Search back for matching sequence
5805 (setq reg (concat "\\(" verilog-vmm-begin-re "\\|" verilog-vmm-end-re "\\)")))
5806 ((looking-at "\\<endinterface\\>")
5807 ;; 12: Search back for matching interface
5808 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<endinterface\\>\\)" ))
5809 ((looking-at "\\<endsequence\\>")
5810 ;; 12: Search back for matching sequence
5811 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" ))
5812 ((looking-at "\\<endclocking\\>")
5813 ;; 12: Search back for matching clocking
5814 (setq reg "\\(\\<clocking\\)\\|\\(\\<endclocking\\>\\)" )))
5817 (if (eq nesting 'yes)
5819 (while (verilog-re-search-backward reg nil 'move)
5821 ((match-end 1) ; begin
5822 (if (looking-at "fork")
5823 (let ((here (point)))
5824 (verilog-beg-of-statement)
5825 (unless (looking-at verilog-disable-fork-re)
5827 (setq nest (1- nest))))
5828 (setq nest (1- nest)))
5830 ;; Now previous line describes syntax
5835 ((match-end 2) ; end
5836 (setq nest (1+ nest)))
5838 ;; endcase, jump to case
5840 (setq nest (1+ nest))
5842 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
5844 ;; join, jump to fork
5846 (setq nest (1+ nest))
5848 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
5852 (verilog-re-search-backward reg nil 'move)
5853 (match-end 1)) ; task -> could be virtual and/or protected
5855 (verilog-beg-of-statement)
5857 (throw 'skip 1)))))))
5859 (defun verilog-continued-line ()
5860 "Return true if this is a continued line.
5861 Set point to where line starts."
5862 (let ((continued 't))
5863 (if (eq 0 (forward-line -1))
5866 (verilog-backward-ws&directives)
5868 (setq continued nil)
5869 (while (and continued
5871 (skip-chars-backward " \t")
5873 (setq continued (verilog-backward-token)))))
5874 (setq continued nil))
5877 (defun verilog-backward-token ()
5878 "Step backward token, returning true if this is a continued line."
5880 (verilog-backward-syntactic-ws)
5884 (;-- Anything ending in a ; is complete
5885 (= (preceding-char) ?\;)
5887 (; If a "}" is prefixed by a ";", then this is a complete statement
5888 ; i.e.: constraint foo { a = b; }
5889 (= (preceding-char) ?\})
5892 (not(verilog-at-close-constraint-p))))
5893 (;-- constraint foo { a = b }
5894 ; is a complete statement. *sigh*
5895 (= (preceding-char) ?\{)
5898 (not (verilog-at-constraint-p))))
5900 (= (preceding-char) ?\")
5902 (verilog-skip-backward-comment-or-string)
5906 (= (preceding-char) ?\])
5908 (verilog-backward-open-bracket)
5911 (;-- Could be 'case (foo)' or 'always @(bar)' which is complete
5912 ; also could be simply '@(foo)'
5914 ; (b, ... which ISN'T complete
5915 ;;;; Do we need this???
5916 (= (preceding-char) ?\))
5919 (verilog-backward-up-list 1)
5920 (verilog-backward-syntactic-ws)
5921 (let ((back (point)))
5925 ((looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|case\\(\\|[xz]\\)\\|for\\(\\|each\\|ever\\)\\|i\\(f\\|nitial\\)\\|repeat\\|while\\)\\>")
5926 (not (looking-at "\\<randcase\\>\\|\\<case[xz]?\\>[^:]")))
5927 ((looking-at verilog-uvm-statement-re)
5929 ((looking-at verilog-uvm-begin-re)
5931 ((looking-at verilog-uvm-end-re)
5933 ((looking-at verilog-ovm-statement-re)
5935 ((looking-at verilog-ovm-begin-re)
5937 ((looking-at verilog-ovm-end-re)
5939 ;; JBA find VMM macros
5940 ((looking-at verilog-vmm-statement-re)
5942 ((looking-at verilog-vmm-begin-re)
5944 ((looking-at verilog-vmm-end-re)
5946 ;; JBA trying to catch macro lines with no ; at end
5947 ((looking-at "\\<`")
5952 ((= (preceding-char) ?\@)
5955 (verilog-backward-token)
5956 (not (looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|initial\\|while\\)\\>"))))
5957 ((= (preceding-char) ?\#)
5961 (;-- any of begin|initial|while are complete statements; 'begin : foo' is also complete
5964 (while (or (= (preceding-char) ?\_)
5965 (= (preceding-char) ?\@)
5966 (= (preceding-char) ?\.))
5969 ((looking-at "\\<else\\>")
5971 ((looking-at verilog-behavioral-block-beg-re)
5973 ((looking-at verilog-indent-re)
5978 (verilog-backward-syntactic-ws)
5980 ((= (preceding-char) ?\:)
5982 (verilog-backward-syntactic-ws)
5984 (if (looking-at verilog-nameable-item-re )
5987 ((= (preceding-char) ?\#)
5990 ((= (preceding-char) ?\`)
5998 (defun verilog-backward-syntactic-ws ()
5999 "Move backwards putting point after first non-whitespace non-comment."
6000 (verilog-skip-backward-comments)
6001 (forward-comment (- (buffer-size))))
6003 (defun verilog-backward-syntactic-ws-quick ()
6004 "As with `verilog-backward-syntactic-ws' but use `verilog-scan' cache."
6005 (while (cond ((bobp)
6007 ((> (skip-syntax-backward " ") 0)
6009 ((eq (preceding-char) ?\n) ;; \n's terminate // so aren't space syntax
6012 ((or (verilog-inside-comment-or-string-p (1- (point)))
6013 (verilog-inside-comment-or-string-p (point)))
6014 (re-search-backward "[/\"]" nil t) ;; Only way a comment or quote can begin
6017 (defun verilog-forward-syntactic-ws ()
6018 (verilog-skip-forward-comment-p)
6019 (forward-comment (buffer-size)))
6021 (defun verilog-backward-ws&directives (&optional bound)
6022 "Backward skip over syntactic whitespace and compiler directives for Emacs 19.
6023 Optional BOUND limits search."
6025 (let* ((bound (or bound (point-min)))
6028 (if (< bound (point))
6030 (let ((state (save-excursion (verilog-syntax-ppss))))
6032 ((nth 7 state) ;; in // comment
6033 (verilog-re-search-backward "//" nil 'move)
6034 (skip-chars-backward "/"))
6035 ((nth 4 state) ;; in /* */ comment
6036 (verilog-re-search-backward "/\*" nil 'move))))
6037 (narrow-to-region bound (point))
6038 (while (/= here (point))
6040 (verilog-skip-backward-comments)
6045 ((and verilog-highlight-translate-off
6046 (verilog-within-translate-off))
6047 (verilog-back-to-start-translate-off (point-min)))
6048 ((looking-at verilog-directive-re-1)
6052 (if p (goto-char p))))))))
6054 (defun verilog-forward-ws&directives (&optional bound)
6055 "Forward skip over syntactic whitespace and compiler directives for Emacs 19.
6056 Optional BOUND limits search."
6058 (let* ((bound (or bound (point-max)))
6061 (if (> bound (point))
6063 (let ((state (save-excursion (verilog-syntax-ppss))))
6065 ((nth 7 state) ;; in // comment
6068 (skip-chars-forward " \t\n\f")
6070 ((nth 4 state) ;; in /* */ comment
6071 (verilog-re-search-forward "\*\/\\s-*" nil 'move))))
6072 (narrow-to-region (point) bound)
6073 (while (/= here (point))
6076 (forward-comment (buffer-size))
6077 (and (looking-at "\\s-*(\\*.*\\*)\\s-*") ;; Attribute
6078 (goto-char (match-end 0)))
6081 (if (looking-at verilog-directive-re-1)
6084 (beginning-of-line 2))))))))
6086 (defun verilog-in-comment-p ()
6087 "Return true if in a star or // comment."
6088 (let ((state (save-excursion (verilog-syntax-ppss))))
6089 (or (nth 4 state) (nth 7 state))))
6091 (defun verilog-in-star-comment-p ()
6092 "Return true if in a star comment."
6093 (let ((state (save-excursion (verilog-syntax-ppss))))
6095 (nth 4 state) ; t if in a comment of style a // or b /**/
6097 (nth 7 state) ; t if in a comment of style b /**/
6100 (defun verilog-in-slash-comment-p ()
6101 "Return true if in a slash comment."
6102 (let ((state (save-excursion (verilog-syntax-ppss))))
6105 (defun verilog-in-comment-or-string-p ()
6106 "Return true if in a string or comment."
6107 (let ((state (save-excursion (verilog-syntax-ppss))))
6108 (or (nth 3 state) (nth 4 state) (nth 7 state)))) ; Inside string or comment)
6110 (defun verilog-in-attribute-p ()
6111 "Return true if point is in an attribute (* [] attribute *)."
6114 (verilog-re-search-backward "\\((\\*\\)\\|\\(\\*)\\)" nil 'move)
6117 (progn (goto-char (match-end 1))
6118 (not (looking-at "\\s-*)")))
6121 (progn (goto-char (match-beginning 2))
6122 (not (looking-at "(\\s-*")))
6126 (defun verilog-in-parameter-p ()
6127 "Return true if point is in a parameter assignment #( p1=1, p2=5)."
6130 (verilog-re-search-backward "\\(#(\\)\\|\\()\\)" nil 'move)
6131 (numberp (match-beginning 1)))))
6133 (defun verilog-in-escaped-name-p ()
6134 "Return true if in an escaped name."
6137 (skip-chars-backward "^ \t\n\f")
6138 (if (equal (char-after (point) ) ?\\ )
6141 (defun verilog-in-directive-p ()
6142 "Return true if in a directive."
6145 (looking-at verilog-directive-re-1)))
6147 (defun verilog-in-parenthesis-p ()
6148 "Return true if in a ( ) expression (but not { } or [ ])."
6151 (verilog-re-search-backward "\\((\\)\\|\\()\\)" nil 'move)
6152 (numberp (match-beginning 1)))))
6154 (defun verilog-in-paren ()
6155 "Return true if in a parenthetical expression.
6156 May cache result using `verilog-syntax-ppss'."
6157 (let ((state (save-excursion (verilog-syntax-ppss))))
6158 (> (nth 0 state) 0 )))
6160 (defun verilog-in-paren-count ()
6161 "Return paren depth, floor to 0.
6162 May cache result using `verilog-syntax-ppss'."
6163 (let ((state (save-excursion (verilog-syntax-ppss))))
6164 (if (> (nth 0 state) 0)
6168 (defun verilog-in-paren-quick ()
6169 "Return true if in a parenthetical expression.
6170 Always starts from `point-min', to allow inserts with hooks disabled."
6171 ;; The -quick refers to its use alongside the other -quick functions,
6172 ;; not that it's likely to be faster than verilog-in-paren.
6173 (let ((state (save-excursion (parse-partial-sexp (point-min) (point)))))
6174 (> (nth 0 state) 0 )))
6176 (defun verilog-in-struct-p ()
6177 "Return true if in a struct declaration."
6180 (if (verilog-in-paren)
6182 (verilog-backward-up-list 1)
6183 (verilog-at-struct-p)
6187 (defun verilog-in-struct-nested-p ()
6188 "Return nil for not in struct.
6189 Return 0 for in non-nested struct.
6190 Return >0 for nested struct."
6194 (if (verilog-in-paren)
6196 (verilog-backward-up-list 1)
6197 (setq col (verilog-at-struct-mv-p))
6199 (if (verilog-in-struct-p) (current-column) 0)))
6202 (defun verilog-in-coverage-p ()
6203 "Return true if in a constraint or coverpoint expression."
6206 (if (verilog-in-paren)
6208 (verilog-backward-up-list 1)
6209 (verilog-at-constraint-p)
6212 (defun verilog-at-close-constraint-p ()
6213 "If at the } that closes a constraint or covergroup, return true."
6215 (equal (char-after) ?\})
6216 (verilog-in-coverage-p))
6219 (verilog-backward-ws&directives)
6220 (if (or (equal (char-before) ?\;)
6221 (equal (char-before) ?\}) ;; can end with inner constraint { } block or ;
6222 (equal (char-before) ?\{)) ;; empty constraint block
6226 (defun verilog-at-constraint-p ()
6227 "If at the { of a constraint or coverpoint definition, return true, moving point to constraint."
6231 (equal (char-after) ?\{)
6233 (progn (backward-char 1)
6234 (verilog-backward-ws&directives)
6236 (or (equal (char-before) ?\{) ;; empty case
6237 (equal (char-before) ?\;)
6238 (equal (char-before) ?\}))
6239 ;; skip what looks like bus repetition operator {#{
6240 (not (string-match "^{\\s-*[0-9]+\\s-*{" (buffer-substring p (point)))))))))
6242 (let ( (pt (point)) (pass 0))
6243 (verilog-backward-ws&directives)
6244 (verilog-backward-token)
6245 (if (looking-at (concat "\\<constraint\\|coverpoint\\|cross\\|with\\>\\|" verilog-in-constraint-re))
6246 (progn (setq pass 1)
6247 (if (looking-at "\\<with\\>")
6248 (progn (verilog-backward-ws&directives)
6249 (beginning-of-line) ;; 1
6250 (verilog-forward-ws&directives)
6252 (verilog-beg-of-statement)
6254 ;; if first word token not keyword, it maybe the instance name
6255 ;; check next word token
6256 (if (looking-at "\\<\\w+\\>\\|\\s-*(\\s-*\\S-+")
6257 (progn (verilog-beg-of-statement)
6258 (if (looking-at (concat "\\<\\(constraint\\|"
6259 "\\(?:\\w+\\s-*:\\s-*\\)?\\(coverpoint\\|cross\\)"
6260 "\\|with\\)\\>\\|" verilog-in-constraint-re))
6263 (progn (goto-char pt) nil) 1)))
6267 (defun verilog-at-struct-p ()
6268 "If at the { of a struct, return true, not moving point."
6270 (if (and (equal (char-after) ?\{)
6271 (verilog-backward-token))
6272 (looking-at "\\<struct\\|union\\|packed\\|\\(un\\)?signed\\>")
6275 (defun verilog-at-struct-mv-p ()
6276 "If at the { of a struct, return true, moving point to struct."
6278 (if (and (equal (char-after) ?\{)
6279 (verilog-backward-token))
6280 (if (looking-at "\\<struct\\|union\\|packed\\|\\(un\\)?signed\\>")
6281 (progn (verilog-beg-of-statement) (point))
6282 (progn (goto-char pt) nil))
6283 (progn (goto-char pt) nil))))
6285 (defun verilog-at-close-struct-p ()
6286 "If at the } that closes a struct, return true."
6288 (equal (char-after) ?\})
6289 (verilog-in-struct-p))
6292 (if (looking-at "}\\(?:\\s-*\\w+\\s-*\\)?;") 1))
6296 (defun verilog-parenthesis-depth ()
6297 "Return non zero if in parenthetical-expression."
6298 (save-excursion (nth 1 (verilog-syntax-ppss))))
6301 (defun verilog-skip-forward-comment-or-string ()
6302 "Return true if in a string or comment."
6303 (let ((state (save-excursion (verilog-syntax-ppss))))
6305 ((nth 3 state) ;Inside string
6306 (search-forward "\"")
6308 ((nth 7 state) ;Inside // comment
6311 ((nth 4 state) ;Inside any comment (hence /**/)
6312 (search-forward "*/"))
6316 (defun verilog-skip-backward-comment-or-string ()
6317 "Return true if in a string or comment."
6318 (let ((state (save-excursion (verilog-syntax-ppss))))
6320 ((nth 3 state) ;Inside string
6321 (search-backward "\"")
6323 ((nth 7 state) ;Inside // comment
6324 (search-backward "//")
6325 (skip-chars-backward "/")
6327 ((nth 4 state) ;Inside /* */ comment
6328 (search-backward "/*")
6333 (defun verilog-skip-backward-comments ()
6334 "Return true if a comment was skipped."
6338 (let ((state (save-excursion (verilog-syntax-ppss))))
6340 ((nth 7 state) ;Inside // comment
6341 (search-backward "//")
6342 (skip-chars-backward "/")
6343 (skip-chars-backward " \t\n\f")
6345 ((nth 4 state) ;Inside /* */ comment
6346 (search-backward "/*")
6347 (skip-chars-backward " \t\n\f")
6350 (= (char-before) ?\/)
6351 (= (char-before (1- (point))) ?\*))
6352 (goto-char (- (point) 2))
6353 t) ;; Let nth 4 state handle the rest
6355 (verilog-looking-back "\\*)" nil)
6356 (not (verilog-looking-back "(\\s-*\\*)" nil)))
6357 (goto-char (- (point) 2))
6358 (if (search-backward "(*" nil t)
6360 (skip-chars-backward " \t\n\f")
6363 (goto-char (+ (point) 2))
6366 (/= (skip-chars-backward " \t\n\f") 0))))))))
6368 (defun verilog-skip-forward-comment-p ()
6369 "If in comment, move to end and return true."
6371 (state (save-excursion (verilog-syntax-ppss)))
6373 ((nth 3 state) ;Inside string
6375 ((nth 7 state) ;Inside // comment
6379 ((nth 4 state) ;Inside /* comment
6380 (search-forward "*/")
6382 ((verilog-in-attribute-p) ;Inside (* attribute
6383 (search-forward "*)" nil t)
6386 (skip-chars-forward " \t\n\f")
6389 ((looking-at "\\/\\*")
6392 (goto-char (match-end 0))
6393 (if (search-forward "*/" nil t)
6395 (skip-chars-forward " \t\n\f")
6400 ((and (looking-at "(\\*") ;; attribute start, but not an event (*) or (* )
6401 (not (looking-at "(\\*\\s-*)")))
6404 (goto-char (match-end 0))
6405 (if (search-forward "*)" nil t)
6407 (skip-chars-forward " \t\n\f")
6415 (defun verilog-indent-line-relative ()
6416 "Cheap version of indent line.
6417 Only look at a few lines to determine indent level."
6421 (if (looking-at "^[ \t]*$")
6422 (cond ;- A blank line; No need to be too smart.
6424 (setq indent-str (list 'cpp 0)))
6425 ((verilog-continued-line)
6426 (let ((sp1 (point)))
6427 (if (verilog-continued-line)
6431 (list 'statement (verilog-current-indent-level))))
6433 (setq indent-str (list 'block (verilog-current-indent-level)))))
6436 (setq indent-str (verilog-calculate-indent))))
6437 (progn (skip-chars-forward " \t")
6438 (setq indent-str (verilog-calculate-indent))))
6439 (verilog-do-indent indent-str)))
6441 (defun verilog-indent-line ()
6442 "Indent for special part of code."
6443 (verilog-do-indent (verilog-calculate-indent)))
6445 (defun verilog-do-indent (indent-str)
6446 (let ((type (car indent-str))
6447 (ind (car (cdr indent-str))))
6449 (; handle continued exp
6451 (let ((here (point)))
6452 (verilog-backward-syntactic-ws)
6455 (= (preceding-char) ?\,)
6457 (verilog-beg-of-statement-1)
6458 (looking-at verilog-declaration-re)))
6463 (verilog-beg-of-statement-1)
6465 (if (looking-at verilog-declaration-re)
6466 (progn ;; we have multiple words
6467 (goto-char (match-end 0))
6468 (skip-chars-forward " \t")
6470 ((and verilog-indent-declaration-macros
6471 (= (following-char) ?\`))
6475 (skip-chars-forward " \t")))
6476 ((= (following-char) ?\[)
6479 (verilog-backward-up-list -1)
6480 (skip-chars-forward " \t"))))
6484 (+ (current-column) verilog-cexp-indent))))))
6486 (indent-line-to val)
6487 (if (and (not verilog-indent-lists)
6489 (verilog-pretty-declarations-auto))
6491 ((= (preceding-char) ?\) )
6493 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
6494 (indent-line-to val)))
6498 (verilog-beg-of-statement-1)
6499 (if (and (< (point) here)
6500 (verilog-re-search-forward "=[ \\t]*" here 'move))
6501 (setq val (current-column))
6502 (setq val (eval (cdr (assoc type verilog-indent-alist)))))
6504 (indent-line-to val))))))
6506 (; handle inside parenthetical expressions
6507 (eq type 'cparenexp)
6509 (val (save-excursion
6510 (verilog-backward-up-list 1)
6512 (if verilog-indent-lists
6513 (skip-chars-forward " \t")
6514 (verilog-forward-syntactic-ws))
6518 (decl (save-excursion
6520 (verilog-forward-syntactic-ws)
6522 (looking-at verilog-declaration-re))))
6523 (indent-line-to val)
6525 (verilog-pretty-declarations-auto))))
6527 (;-- Handle the ends
6529 (looking-at verilog-end-block-re)
6530 (verilog-at-close-constraint-p)
6531 (verilog-at-close-struct-p))
6532 (let ((val (if (eq type 'statement)
6533 (- ind verilog-indent-level)
6535 (indent-line-to val)))
6537 (;-- Case -- maybe line 'em up
6538 (and (eq type 'case) (not (looking-at "^[ \t]*$")))
6541 ((looking-at "\\<endcase\\>")
6542 (indent-line-to ind))
6544 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
6545 (indent-line-to val))))))
6548 (and (eq type 'defun)
6549 (looking-at verilog-zero-indent-re))
6556 (looking-at verilog-declaration-re))
6557 (verilog-indent-declaration ind))
6559 (;-- form feeds - ignored as bug in indent-line-to in < 24.5
6562 (;-- Everything else
6564 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
6565 (indent-line-to val))))
6567 (if (looking-at "[ \t]+$")
6568 (skip-chars-forward " \t"))
6569 indent-str ; Return indent data
6572 (defun verilog-current-indent-level ()
6573 "Return the indent-level of the current statement."
6577 (setq par-pos (verilog-parenthesis-depth))
6581 (setq par-pos (verilog-parenthesis-depth)))
6582 (skip-chars-forward " \t")
6585 (defun verilog-case-indent-level ()
6586 "Return the indent-level of the current statement.
6587 Do not count named blocks or case-statements."
6589 (skip-chars-forward " \t")
6591 ((looking-at verilog-named-block-re)
6593 ((and (not (looking-at verilog-extended-case-re))
6594 (looking-at "^[^:;]+[ \t]*:"))
6595 (verilog-re-search-forward ":" nil t)
6596 (skip-chars-forward " \t")
6599 (current-column)))))
6601 (defun verilog-indent-comment ()
6602 "Indent current line as comment."
6605 ((verilog-in-star-comment-p)
6607 (re-search-backward "/\\*" nil t)
6608 (1+(current-column))))
6613 (re-search-backward "//" nil t)
6614 (current-column))))))
6615 (indent-line-to stcol)
6618 (defun verilog-more-comment ()
6619 "Make more comment lines like the previous."
6623 ((verilog-in-star-comment-p)
6626 (re-search-backward "/\\*" nil t)
6627 (1+(current-column))))
6632 (re-search-backward "//" nil t)
6633 (current-column))))))
6639 (skip-chars-forward " \t")
6643 (defun verilog-comment-indent (&optional _arg)
6644 "Return the column number the line should be indented to.
6645 _ARG is ignored, for `comment-indent-function' compatibility."
6647 ((verilog-in-star-comment-p)
6649 (re-search-backward "/\\*" nil t)
6650 (1+(current-column))))
6655 (re-search-backward "//" nil t)
6656 (current-column)))))
6660 (defun verilog-pretty-declarations-auto (&optional quiet)
6661 "Call `verilog-pretty-declarations' QUIET based on `verilog-auto-lineup'."
6662 (when (or (eq 'all verilog-auto-lineup)
6663 (eq 'declarations verilog-auto-lineup))
6664 (verilog-pretty-declarations quiet)))
6666 (defun verilog-pretty-declarations (&optional quiet)
6667 "Line up declarations around point.
6668 Be verbose about progress unless optional QUIET set."
6670 (let* ((m1 (make-marker))
6684 ; (verilog-beg-of-statement-1)
6686 (verilog-forward-syntactic-ws)
6687 (and (not (verilog-in-directive-p)) ;; could have `define input foo
6688 (looking-at verilog-declaration-re)))
6690 (if (verilog-parenthesis-depth)
6691 ;; in an argument list or parameter block
6692 (setq el (verilog-backward-up-list -1)
6695 (verilog-backward-up-list 1)
6696 (forward-line) ;; ignore ( input foo,
6697 (verilog-re-search-forward verilog-declaration-re el 'move)
6698 (goto-char (match-beginning 0))
6699 (skip-chars-backward " \t")
6701 startpos (set-marker (make-marker) start)
6704 (verilog-backward-up-list -1)
6706 (verilog-backward-syntactic-ws)
6708 endpos (set-marker (make-marker) end)
6712 (skip-chars-forward " \t")
6714 ;; in a declaration block (not in argument list)
6717 (verilog-beg-of-statement-1)
6718 (while (and (looking-at verilog-declaration-re)
6720 (skip-chars-backward " \t")
6723 (verilog-backward-syntactic-ws)
6725 (verilog-beg-of-statement-1))
6727 startpos (set-marker (make-marker) start)
6730 (verilog-end-of-statement)
6731 (setq e (point)) ;Might be on last line
6732 (verilog-forward-syntactic-ws)
6733 (while (looking-at verilog-declaration-re)
6734 (verilog-end-of-statement)
6736 (verilog-forward-syntactic-ws))
6738 endpos (set-marker (make-marker) end)
6741 (verilog-do-indent (verilog-calculate-indent))
6742 (verilog-forward-ws&directives)
6744 ;; OK, start and end are set
6745 (goto-char (marker-position startpos))
6746 (if (and (not quiet)
6747 (> (- end start) 100))
6748 (message "Lining up declarations..(please stand by)"))
6749 ;; Get the beginning of line indent first
6750 (while (progn (setq e (marker-position endpos))
6753 ((save-excursion (skip-chars-backward " \t")
6755 (verilog-forward-ws&directives)
6756 (indent-line-to base-ind)
6757 (verilog-forward-ws&directives)
6759 (verilog-re-search-forward "[ \t\n\f]" e 'move)))
6762 (verilog-re-search-forward "[ \t\n\f]" e 'move)))
6765 ;; Now find biggest prefix
6766 (setq ind (verilog-get-lineup-indent (marker-position startpos) endpos))
6767 ;; Now indent each line.
6768 (goto-char (marker-position startpos))
6769 (while (progn (setq e (marker-position endpos))
6770 (setq r (- e (point)))
6773 (unless quiet (message "%d" r))
6774 ;;(verilog-do-indent (verilog-calculate-indent)))
6775 (verilog-forward-ws&directives)
6777 ((or (and verilog-indent-declaration-macros
6778 (looking-at verilog-declaration-re-2-macro))
6779 (looking-at verilog-declaration-re-2-no-macro))
6780 (let ((p (match-end 0)))
6782 (if (verilog-re-search-forward "[[#`]" p 'move)
6786 (goto-char (marker-position m1))
6792 ((verilog-continued-line-1 (marker-position startpos))
6794 (indent-line-to ind))
6795 ((verilog-in-struct-p)
6796 ;; could have a declaration of a user defined item
6798 (verilog-end-of-statement))
6799 (t ; Must be comment or white space
6801 (verilog-forward-ws&directives)
6804 (unless quiet (message "")))))))
6806 (defun verilog-pretty-expr (&optional quiet _myre)
6807 "Line up expressions around point, optionally QUIET with regexp _MYRE ignored."
6809 (if (not (verilog-in-comment-or-string-p))
6811 (let ( (rexp (concat "^\\s-*" verilog-complete-reg))
6812 (rexp1 (concat "^\\s-*" verilog-basic-complete-re)))
6814 (if (and (not (looking-at rexp ))
6815 (looking-at verilog-assignment-operation-re)
6817 (goto-char (match-end 2))
6818 (and (not (verilog-in-attribute-p))
6819 (not (verilog-in-parameter-p))
6820 (not (verilog-in-comment-or-string-p)))))
6821 (let* ((here (point))
6827 (verilog-backward-syntactic-ws)
6829 (while (and (not (looking-at rexp1))
6830 (looking-at verilog-assignment-operation-re)
6834 (verilog-backward-syntactic-ws)
6836 ) ;Ack, need to grok `define
6842 (setq e (point)) ;Might be on last line
6843 (verilog-forward-syntactic-ws)
6846 (not (looking-at rexp1 ))
6847 (looking-at verilog-assignment-operation-re)
6850 (not (eq e (point)))))
6852 (verilog-forward-syntactic-ws)
6856 (endpos (set-marker (make-marker) end))
6860 (verilog-do-indent (verilog-calculate-indent))
6861 (if (and (not quiet)
6862 (> (- end start) 100))
6863 (message "Lining up expressions..(please stand by)"))
6865 ;; Set indent to minimum throughout region
6866 (while (< (point) (marker-position endpos))
6868 (verilog-just-one-space verilog-assignment-operation-re)
6870 (verilog-do-indent (verilog-calculate-indent))
6872 (verilog-forward-syntactic-ws)
6875 ;; Now find biggest prefix
6876 (setq ind (verilog-get-lineup-indent-2 verilog-assignment-operation-re start endpos))
6878 ;; Now indent each line.
6880 (while (progn (setq e (marker-position endpos))
6881 (setq r (- e (point)))
6884 (if (not quiet) (message "%d" r))
6886 ((looking-at verilog-assignment-operation-re)
6887 (goto-char (match-beginning 2))
6888 (if (not (or (verilog-in-parenthesis-p) ;; leave attributes and comparisons alone
6889 (verilog-in-coverage-p)))
6890 (if (eq (char-after) ?=)
6891 (indent-to (1+ ind)) ; line up the = of the <= with surrounding =
6895 ((verilog-continued-line-1 start)
6897 (indent-line-to ind))
6898 (t ; Must be comment or white space
6900 (verilog-forward-ws&directives)
6904 (unless quiet (message ""))
6907 (defun verilog-just-one-space (myre)
6908 "Remove extra spaces around regular expression MYRE."
6910 (if (and (not(looking-at verilog-complete-reg))
6912 (let ((p1 (match-end 1))
6918 (just-one-space)))))
6920 (defun verilog-indent-declaration (baseind)
6921 "Indent current lines as declaration.
6922 Line up the variable names based on previous declaration's indentation.
6923 BASEIND is the base indent to offset everything."
6925 (let ((pos (point-marker))
6926 (lim (save-excursion
6927 ;; (verilog-re-search-backward verilog-declaration-opener nil 'move)
6928 (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)\\|\\(\\<task\\>\\)" nil 'move)
6934 (+ baseind (eval (cdr (assoc 'declaration verilog-indent-alist)))))
6935 (indent-line-to val)
6937 ;; Use previous declaration (in this module) as template.
6938 (if (or (eq 'all verilog-auto-lineup)
6939 (eq 'declarations verilog-auto-lineup))
6940 (if (verilog-re-search-backward
6941 (or (and verilog-indent-declaration-macros
6942 verilog-declaration-re-1-macro)
6943 verilog-declaration-re-1-no-macro) lim t)
6945 (goto-char (match-end 0))
6946 (skip-chars-forward " \t")
6947 (setq ind (current-column))
6951 (eval (cdr (assoc 'declaration verilog-indent-alist)))))
6952 (indent-line-to val)
6953 (if (and verilog-indent-declaration-macros
6954 (looking-at verilog-declaration-re-2-macro))
6955 (let ((p (match-end 0)))
6957 (if (verilog-re-search-forward "[[#`]" p 'move)
6961 (goto-char (marker-position m1))
6964 (if (/= (current-column) ind)
6968 (if (looking-at verilog-declaration-re-2-no-macro)
6969 (let ((p (match-end 0)))
6971 (if (verilog-re-search-forward "[[`#]" p 'move)
6975 (goto-char (marker-position m1))
6978 (if (/= (current-column) ind)
6981 (indent-to ind))))))))))
6984 (defun verilog-get-lineup-indent (b edpos)
6985 "Return the indent level that will line up several lines within the region.
6986 Region is defined by B and EDPOS."
6990 ;; Get rightmost position
6991 (while (progn (setq e (marker-position edpos))
6993 (if (verilog-re-search-forward
6994 (or (and verilog-indent-declaration-macros
6995 verilog-declaration-re-1-macro)
6996 verilog-declaration-re-1-no-macro) e 'move)
6998 (goto-char (match-end 0))
6999 (verilog-backward-syntactic-ws)
7000 (if (> (current-column) ind)
7001 (setq ind (current-column)))
7002 (goto-char (match-end 0)))))
7005 ;; No lineup-string found
7008 (verilog-backward-syntactic-ws)
7009 ;;(skip-chars-backward " \t")
7010 (1+ (current-column))))))
7012 (defun verilog-get-lineup-indent-2 (myre b edpos)
7013 "Return the indent level that will line up several lines within the region."
7017 ;; Get rightmost position
7018 (while (progn (setq e (marker-position edpos))
7020 (if (and (verilog-re-search-forward myre e 'move)
7021 (not (verilog-in-attribute-p))) ;; skip attribute exprs
7023 (goto-char (match-beginning 2))
7024 (verilog-backward-syntactic-ws)
7025 (if (> (current-column) ind)
7026 (setq ind (current-column)))
7027 (goto-char (match-end 0)))
7031 ;; No lineup-string found
7034 (skip-chars-backward " \t")
7035 (1+ (current-column))))))
7037 (defun verilog-comment-depth (type val)
7038 "A useful mode debugging aide. TYPE and VAL are comments for insertion."
7045 (if (re-search-backward " /\\* \[#-\]# \[a-zA-Z\]+ \[0-9\]+ ## \\*/" b t)
7047 (replace-match " /* -# ## */")
7051 (insert " /* ## ## */"))))
7054 (format "%s %d" type val))))
7060 (defvar verilog-str nil)
7061 (defvar verilog-all nil)
7062 (defvar verilog-pred nil)
7063 (defvar verilog-buffer-to-use nil)
7064 (defvar verilog-flag nil)
7065 (defvar verilog-toggle-completions nil
7066 "True means \\<verilog-mode-map>\\[verilog-complete-word] should try all possible completions one by one.
7067 Repeated use of \\[verilog-complete-word] will show you all of them.
7068 Normally, when there is more than one possible completion,
7069 it displays a list of all possible completions.")
7072 (defvar verilog-type-keywords
7074 "and" "buf" "bufif0" "bufif1" "cmos" "defparam" "inout" "input"
7075 "integer" "localparam" "logic" "mailbox" "nand" "nmos" "nor" "not" "notif0"
7076 "notif1" "or" "output" "parameter" "pmos" "pull0" "pull1" "pulldown" "pullup"
7077 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran" "rtranif0"
7078 "rtranif1" "semaphore" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1"
7079 "triand" "trior" "trireg" "wand" "wire" "wor" "xnor" "xor"
7081 "Keywords for types used when completing a word in a declaration or parmlist.
7082 \(integer, real, reg...)")
7084 (defvar verilog-cpp-keywords
7085 '("module" "macromodule" "primitive" "timescale" "define" "ifdef" "ifndef" "else"
7087 "Keywords to complete when at first word of a line in declarative scope.
7088 \(initial, always, begin, assign...)
7089 The procedures and variables defined within the Verilog program
7090 will be completed at runtime and should not be added to this list.")
7092 (defvar verilog-defun-keywords
7095 "always" "always_comb" "always_ff" "always_latch" "assign"
7096 "begin" "end" "generate" "endgenerate" "module" "endmodule"
7097 "specify" "endspecify" "function" "endfunction" "initial" "final"
7098 "task" "endtask" "primitive" "endprimitive"
7100 verilog-type-keywords)
7101 "Keywords to complete when at first word of a line in declarative scope.
7102 \(initial, always, begin, assign...)
7103 The procedures and variables defined within the Verilog program
7104 will be completed at runtime and should not be added to this list.")
7106 (defvar verilog-block-keywords
7108 "begin" "break" "case" "continue" "else" "end" "endfunction"
7109 "endgenerate" "endinterface" "endpackage" "endspecify" "endtask"
7110 "for" "fork" "if" "join" "join_any" "join_none" "repeat" "return"
7112 "Keywords to complete when at first word of a line in behavioral scope.
7113 \(begin, if, then, else, for, fork...)
7114 The procedures and variables defined within the Verilog program
7115 will be completed at runtime and should not be added to this list.")
7117 (defvar verilog-tf-keywords
7118 '("begin" "break" "fork" "join" "join_any" "join_none" "case" "end" "endtask" "endfunction" "if" "else" "for" "while" "repeat")
7119 "Keywords to complete when at first word of a line in a task or function.
7120 \(begin, if, then, else, for, fork.)
7121 The procedures and variables defined within the Verilog program
7122 will be completed at runtime and should not be added to this list.")
7124 (defvar verilog-case-keywords
7125 '("begin" "fork" "join" "join_any" "join_none" "case" "end" "endcase" "if" "else" "for" "repeat")
7126 "Keywords to complete when at first word of a line in case scope.
7127 \(begin, if, then, else, for, fork...)
7128 The procedures and variables defined within the Verilog program
7129 will be completed at runtime and should not be added to this list.")
7131 (defvar verilog-separator-keywords
7132 '("else" "then" "begin")
7133 "Keywords to complete when NOT standing at the first word of a statement.
7134 \(else, then, begin...)
7135 Variables and function names defined within the Verilog program
7136 will be completed at runtime and should not be added to this list.")
7138 (defvar verilog-gate-ios
7139 ;; All these have an implied {"input"...} at the end
7153 ("pulldown" "output")
7158 ("rtran" "inout" "inout")
7159 ("rtranif0" "inout" "inout")
7160 ("rtranif1" "inout" "inout")
7161 ("tran" "inout" "inout")
7162 ("tranif0" "inout" "inout")
7163 ("tranif1" "inout" "inout")
7166 "Map of direction for each positional argument to each gate primitive.")
7168 (defvar verilog-gate-keywords (mapcar `car verilog-gate-ios)
7169 "Keywords for gate primitives.")
7171 (defun verilog-string-diff (str1 str2)
7172 "Return index of first letter where STR1 and STR2 differs."
7176 (if (or (> (1+ diff) (length str1))
7177 (> (1+ diff) (length str2)))
7179 (or (equal (aref str1 diff) (aref str2 diff))
7181 (setq diff (1+ diff))))))
7183 ;; Calculate all possible completions for functions if argument is `function',
7184 ;; completions for procedures if argument is `procedure' or both functions and
7185 ;; procedures otherwise.
7187 (defun verilog-func-completion (type)
7188 "Build regular expression for module/task/function names.
7189 TYPE is 'module, 'tf for task or function, or t if unknown."
7190 (if (string= verilog-str "")
7191 (setq verilog-str "[a-zA-Z_]"))
7192 (let ((verilog-str (concat (cond
7193 ((eq type 'module) "\\<\\(module\\)\\s +")
7194 ((eq type 'tf) "\\<\\(task\\|function\\)\\s +")
7195 (t "\\<\\(task\\|function\\|module\\)\\s +"))
7196 "\\<\\(" verilog-str "[a-zA-Z0-9_.]*\\)\\>"))
7199 (if (not (looking-at verilog-defun-re))
7200 (verilog-re-search-backward verilog-defun-re nil t))
7203 ;; Search through all reachable functions
7204 (goto-char (point-min))
7205 (while (verilog-re-search-forward verilog-str (point-max) t)
7206 (progn (setq match (buffer-substring (match-beginning 2)
7208 (if (or (null verilog-pred)
7209 (funcall verilog-pred match))
7210 (setq verilog-all (cons match verilog-all)))))
7211 (if (match-beginning 0)
7212 (goto-char (match-beginning 0)))))
7214 (defun verilog-get-completion-decl (end)
7215 "Macro for searching through current declaration (var, type or const)
7216 for matches of `str' and adding the occurrence tp `all' through point END."
7217 (let ((re (or (and verilog-indent-declaration-macros
7218 verilog-declaration-re-2-macro)
7219 verilog-declaration-re-2-no-macro))
7222 (while (and (< (point) end)
7223 (verilog-re-search-forward re end t))
7224 ;; Traverse current line
7225 (setq decl-end (save-excursion (verilog-declaration-end)))
7226 (while (and (verilog-re-search-forward verilog-symbol-re decl-end t)
7227 (not (match-end 1)))
7228 (setq match (buffer-substring (match-beginning 0) (match-end 0)))
7229 (if (string-match (concat "\\<" verilog-str) match)
7230 (if (or (null verilog-pred)
7231 (funcall verilog-pred match))
7232 (setq verilog-all (cons match verilog-all)))))
7236 (defun verilog-var-completion ()
7237 "Calculate all possible completions for variables (or constants)."
7238 (let ((start (point)))
7239 ;; Search for all reachable var declarations
7240 (verilog-beg-of-defun)
7242 ;; Check var declarations
7243 (verilog-get-completion-decl start))))
7245 (defun verilog-keyword-completion (keyword-list)
7246 "Give list of all possible completions of keywords in KEYWORD-LIST."
7248 (if (string-match (concat "\\<" verilog-str) s)
7249 (if (or (null verilog-pred)
7250 (funcall verilog-pred s))
7251 (setq verilog-all (cons s verilog-all)))))
7255 (defun verilog-completion (verilog-str verilog-pred verilog-flag)
7256 "Function passed to `completing-read', `try-completion' or `all-completions'.
7257 Called to get completion on VERILOG-STR. If VERILOG-PRED is non-nil, it
7258 must be a function to be called for every match to check if this should
7259 really be a match. If VERILOG-FLAG is t, the function returns a list of
7260 all possible completions. If VERILOG-FLAG is nil it returns a string,
7261 the longest possible completion, or t if VERILOG-STR is an exact match.
7262 If VERILOG-FLAG is 'lambda, the function returns t if VERILOG-STR is an
7263 exact match, nil otherwise."
7265 (let ((verilog-all nil))
7266 ;; Set buffer to use for searching labels. This should be set
7267 ;; within functions which use verilog-completions
7268 (set-buffer verilog-buffer-to-use)
7270 ;; Determine what should be completed
7271 (let ((state (car (verilog-calculate-indent))))
7272 (cond ((eq state 'defun)
7273 (save-excursion (verilog-var-completion))
7274 (verilog-func-completion 'module)
7275 (verilog-keyword-completion verilog-defun-keywords))
7277 ((eq state 'behavioral)
7278 (save-excursion (verilog-var-completion))
7279 (verilog-func-completion 'module)
7280 (verilog-keyword-completion verilog-defun-keywords))
7283 (save-excursion (verilog-var-completion))
7284 (verilog-func-completion 'tf)
7285 (verilog-keyword-completion verilog-block-keywords))
7288 (save-excursion (verilog-var-completion))
7289 (verilog-func-completion 'tf)
7290 (verilog-keyword-completion verilog-case-keywords))
7293 (save-excursion (verilog-var-completion))
7294 (verilog-func-completion 'tf)
7295 (verilog-keyword-completion verilog-tf-keywords))
7298 (save-excursion (verilog-var-completion))
7299 (verilog-keyword-completion verilog-cpp-keywords))
7301 ((eq state 'cparenexp)
7302 (save-excursion (verilog-var-completion)))
7305 (save-excursion (verilog-var-completion))
7306 (verilog-func-completion 'both)
7307 (verilog-keyword-completion verilog-separator-keywords))))
7309 ;; Now we have built a list of all matches. Give response to caller
7310 (verilog-completion-response))))
7312 (defun verilog-completion-response ()
7313 (cond ((or (equal verilog-flag 'lambda) (null verilog-flag))
7314 ;; This was not called by all-completions
7315 (if (null verilog-all)
7316 ;; Return nil if there was no matching label
7318 ;; Get longest string common in the labels
7319 ;; FIXME: Why not use `try-completion'?
7320 (let* ((elm (cdr verilog-all))
7321 (match (car verilog-all))
7322 (min (length match))
7324 (if (string= match verilog-str)
7325 ;; Return t if first match was an exact match
7327 (while (not (null elm))
7328 ;; Find longest common string
7329 (if (< (setq tmp (verilog-string-diff match (car elm))) min)
7332 (setq match (substring match 0 min))))
7333 ;; Terminate with match=t if this is an exact match
7334 (if (string= (car elm) verilog-str)
7338 (setq elm (cdr elm)))))
7339 ;; If this is a test just for exact match, return nil ot t
7340 (if (and (equal verilog-flag 'lambda) (not (equal match 't)))
7343 ;; If flag is t, this was called by all-completions. Return
7344 ;; list of all possible completions
7348 (defvar verilog-last-word-numb 0)
7349 (defvar verilog-last-word-shown nil)
7350 (defvar verilog-last-completions nil)
7352 (defun verilog-complete-word ()
7353 "Complete word at current point.
7354 \(See also `verilog-toggle-completions', `verilog-type-keywords',
7355 and `verilog-separator-keywords'.)"
7356 ;; FIXME: Provide completion-at-point-function.
7358 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
7359 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
7360 (verilog-str (buffer-substring b e))
7361 ;; The following variable is used in verilog-completion
7362 (verilog-buffer-to-use (current-buffer))
7363 (allcomp (if (and verilog-toggle-completions
7364 (string= verilog-last-word-shown verilog-str))
7365 verilog-last-completions
7366 (all-completions verilog-str 'verilog-completion)))
7367 (match (if verilog-toggle-completions
7369 verilog-str (mapcar (lambda (elm)
7370 (cons elm 0)) allcomp)))))
7371 ;; Delete old string
7374 ;; Toggle-completions inserts whole labels
7375 (if verilog-toggle-completions
7377 ;; Update entry number in list
7378 (setq verilog-last-completions allcomp
7379 verilog-last-word-numb
7380 (if (>= verilog-last-word-numb (1- (length allcomp)))
7382 (1+ verilog-last-word-numb)))
7383 (setq verilog-last-word-shown (elt allcomp verilog-last-word-numb))
7384 ;; Display next match or same string if no match was found
7385 (if (not (null allcomp))
7386 (insert "" verilog-last-word-shown)
7387 (insert "" verilog-str)
7388 (message "(No match)")))
7389 ;; The other form of completion does not necessarily do that.
7391 ;; Insert match if found, or the original string if no match
7392 (if (or (null match) (equal match 't))
7393 (progn (insert "" verilog-str)
7394 (message "(No match)"))
7396 ;; Give message about current status of completion
7397 (cond ((equal match 't)
7398 (if (not (null (cdr allcomp)))
7399 (message "(Complete but not unique)")
7400 (message "(Sole completion)")))
7401 ;; Display buffer if the current completion didn't help
7402 ;; on completing the label.
7403 ((and (not (null (cdr allcomp))) (= (length verilog-str)
7405 (with-output-to-temp-buffer "*Completions*"
7406 (display-completion-list allcomp))
7407 ;; Wait for a key press. Then delete *Completion* window
7408 (momentary-string-display "" (point))
7409 (delete-window (get-buffer-window (get-buffer "*Completions*")))
7412 (defun verilog-show-completions ()
7413 "Show all possible completions at current point."
7415 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
7416 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
7417 (verilog-str (buffer-substring b e))
7418 ;; The following variable is used in verilog-completion
7419 (verilog-buffer-to-use (current-buffer))
7420 (allcomp (if (and verilog-toggle-completions
7421 (string= verilog-last-word-shown verilog-str))
7422 verilog-last-completions
7423 (all-completions verilog-str 'verilog-completion))))
7424 ;; Show possible completions in a temporary buffer.
7425 (with-output-to-temp-buffer "*Completions*"
7426 (display-completion-list allcomp))
7427 ;; Wait for a key press. Then delete *Completion* window
7428 (momentary-string-display "" (point))
7429 (delete-window (get-buffer-window (get-buffer "*Completions*")))))
7432 (defun verilog-get-default-symbol ()
7433 "Return symbol around current point as a string."
7435 (buffer-substring (progn
7436 (skip-chars-backward " \t")
7437 (skip-chars-backward "a-zA-Z0-9_")
7440 (skip-chars-forward "a-zA-Z0-9_")
7443 (defun verilog-build-defun-re (str &optional arg)
7444 "Return function/task/module starting with STR as regular expression.
7445 With optional second ARG non-nil, STR is the complete name of the instruction."
7447 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "\\)\\>")
7448 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "[a-zA-Z0-9_]*\\)\\>")))
7450 (defun verilog-comp-defun (verilog-str verilog-pred verilog-flag)
7451 "Function passed to `completing-read', `try-completion' or `all-completions'.
7452 Returns a completion on any function name based on VERILOG-STR prefix. If
7453 VERILOG-PRED is non-nil, it must be a function to be called for every match
7454 to check if this should really be a match. If VERILOG-FLAG is t, the
7455 function returns a list of all possible completions. If it is nil it
7456 returns a string, the longest possible completion, or t if VERILOG-STR is
7457 an exact match. If VERILOG-FLAG is 'lambda, the function returns t if
7458 VERILOG-STR is an exact match, nil otherwise."
7460 (let ((verilog-all nil)
7463 ;; Set buffer to use for searching labels. This should be set
7464 ;; within functions which use verilog-completions
7465 (set-buffer verilog-buffer-to-use)
7467 (let ((verilog-str verilog-str))
7468 ;; Build regular expression for functions
7469 (if (string= verilog-str "")
7470 (setq verilog-str (verilog-build-defun-re "[a-zA-Z_]"))
7471 (setq verilog-str (verilog-build-defun-re verilog-str)))
7472 (goto-char (point-min))
7474 ;; Build a list of all possible completions
7475 (while (verilog-re-search-forward verilog-str nil t)
7476 (setq match (buffer-substring (match-beginning 2) (match-end 2)))
7477 (if (or (null verilog-pred)
7478 (funcall verilog-pred match))
7479 (setq verilog-all (cons match verilog-all)))))
7481 ;; Now we have built a list of all matches. Give response to caller
7482 (verilog-completion-response))))
7484 (defun verilog-goto-defun ()
7485 "Move to specified Verilog module/interface/task/function.
7486 The default is a name found in the buffer around point.
7487 If search fails, other files are checked based on
7488 `verilog-library-flags'."
7490 (let* ((default (verilog-get-default-symbol))
7491 ;; The following variable is used in verilog-comp-function
7492 (verilog-buffer-to-use (current-buffer))
7493 (label (if (not (string= default ""))
7494 ;; Do completion with default
7495 (completing-read (concat "Goto-Label: (default "
7497 'verilog-comp-defun nil nil "")
7498 ;; There is no default value. Complete without it
7499 (completing-read "Goto-Label: "
7500 'verilog-comp-defun nil nil "")))
7502 ;; Make sure library paths are correct, in case need to resolve module
7503 (verilog-auto-reeval-locals)
7504 (verilog-getopt-flags)
7505 ;; If there was no response on prompt, use default value
7506 (if (string= label "")
7507 (setq label default))
7508 ;; Goto right place in buffer if label is not an empty string
7509 (or (string= label "")
7512 (goto-char (point-min))
7514 (re-search-forward (verilog-build-defun-re label t) nil t)))
7517 (beginning-of-line))
7519 (verilog-goto-defun-file label))))
7521 ;; Eliminate compile warning
7522 (defvar occur-pos-list)
7524 (defun verilog-showscopes ()
7525 "List all scopes in this module."
7527 (let ((buffer (current-buffer))
7531 (prevpos (point-min))
7532 (final-context-start (make-marker))
7533 (regexp "\\(module\\s-+\\w+\\s-*(\\)\\|\\(\\w+\\s-+\\w+\\s-*(\\)"))
7534 (with-output-to-temp-buffer "*Occur*"
7536 (message (format "Searching for %s ..." regexp))
7537 ;; Find next match, but give up if prev match was at end of buffer.
7538 (while (and (not (= prevpos (point-max)))
7539 (verilog-re-search-forward regexp nil t))
7540 (goto-char (match-beginning 0))
7543 (setq linenum (+ linenum (count-lines prevpos (point)))))
7544 (setq prevpos (point))
7545 (goto-char (match-end 0))
7546 (let* ((start (save-excursion
7547 (goto-char (match-beginning 0))
7548 (forward-line (if (< nlines 0) nlines (- nlines)))
7550 (end (save-excursion
7551 (goto-char (match-end 0))
7553 (forward-line (1+ nlines))
7556 (tag (format "%3d" linenum))
7557 (empty (make-string (length tag) ?\ ))
7560 (setq tem (make-marker))
7561 (set-marker tem (point))
7562 (set-buffer standard-output)
7563 (setq occur-pos-list (cons tem occur-pos-list))
7564 (or first (zerop nlines)
7565 (insert "--------\n"))
7567 (insert-buffer-substring buffer start end)
7568 (backward-char (- end start))
7569 (setq tem (if (< nlines 0) (- nlines) nlines))
7573 (setq tem (1- tem)))
7574 (let ((this-linenum linenum))
7575 (set-marker final-context-start
7576 (+ (point) (- (match-end 0) (match-beginning 0))))
7577 (while (< (point) final-context-start)
7579 (setq tag (format "%3d" this-linenum)))
7580 (insert tag ?:)))))))
7581 (set-buffer-modified-p nil))))
7584 ;; Highlight helper functions
7585 (defconst verilog-directive-regexp "\\(translate\\|coverage\\|lint\\)_")
7586 (defun verilog-within-translate-off ()
7587 "Return point if within translate-off region, else nil."
7588 (and (save-excursion
7590 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "\\(on\\|off\\)\\>")
7592 (equal "off" (match-string 2))
7595 (defun verilog-start-translate-off (limit)
7596 "Return point before translate-off directive if before LIMIT, else nil."
7597 (when (re-search-forward
7598 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
7600 (match-beginning 0)))
7602 (defun verilog-back-to-start-translate-off (limit)
7603 "Return point before translate-off directive if before LIMIT, else nil."
7604 (when (re-search-backward
7605 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
7607 (match-beginning 0)))
7609 (defun verilog-end-translate-off (limit)
7610 "Return point after translate-on directive if before LIMIT, else nil."
7612 (re-search-forward (concat
7613 "//\\s-*.*\\s-*" verilog-directive-regexp "on\\>") limit t))
7615 (defun verilog-match-translate-off (limit)
7616 "Match a translate-off block, setting `match-data' and returning t, else nil.
7617 Bound search by LIMIT."
7618 (when (< (point) limit)
7619 (let ((start (or (verilog-within-translate-off)
7620 (verilog-start-translate-off limit)))
7621 (case-fold-search t))
7623 (let ((end (or (verilog-end-translate-off limit) limit)))
7624 (set-match-data (list start end))
7625 (goto-char end))))))
7627 (defun verilog-font-lock-match-item (limit)
7628 "Match, and move over, any declaration item after point.
7629 Bound search by LIMIT. Adapted from
7630 `font-lock-match-c-style-declaration-item-and-skip-to-next'."
7633 (narrow-to-region (point-min) limit)
7635 (when (looking-at "\\s-*\\([a-zA-Z]\\w*\\)")
7637 (goto-char (match-end 1))
7638 ;; move to next item
7639 (if (looking-at "\\(\\s-*,\\)")
7640 (goto-char (match-end 1))
7645 ;; Added by Subbu Meiyappan for Header
7647 (defun verilog-header ()
7648 "Insert a standard Verilog file header.
7649 See also `verilog-sk-header' for an alternative format."
7651 (let ((start (point)))
7653 //-----------------------------------------------------------------------------
7655 // Project : <project>
7656 //-----------------------------------------------------------------------------
7657 // File : <filename>
7658 // Author : <author>
7659 // Created : <credate>
7660 // Last modified : <moddate>
7661 //-----------------------------------------------------------------------------
7664 //-----------------------------------------------------------------------------
7665 // Copyright (c) <copydate> by <company> This model is the confidential and
7666 // proprietary property of <company> and the possession or use of this
7667 // file requires a written license from <company>.
7668 //------------------------------------------------------------------------------
7669 // Modification history :
7671 //-----------------------------------------------------------------------------
7675 (search-forward "<filename>")
7676 (replace-match (buffer-name) t t)
7677 (search-forward "<author>") (replace-match "" t t)
7678 (insert (user-full-name))
7679 (insert " <" (user-login-name) "@" (system-name) ">")
7680 (search-forward "<credate>") (replace-match "" t t)
7681 (verilog-insert-date)
7682 (search-forward "<moddate>") (replace-match "" t t)
7683 (verilog-insert-date)
7684 (search-forward "<copydate>") (replace-match "" t t)
7685 (verilog-insert-year)
7686 (search-forward "<modhist>") (replace-match "" t t)
7687 (verilog-insert-date)
7688 (insert " : created")
7691 (setq string (read-string "title: "))
7692 (search-forward "<title>")
7693 (replace-match string t t)
7694 (setq string (read-string "project: " verilog-project))
7695 (setq verilog-project string)
7696 (search-forward "<project>")
7697 (replace-match string t t)
7698 (setq string (read-string "Company: " verilog-company))
7699 (setq verilog-company string)
7700 (search-forward "<company>")
7701 (replace-match string t t)
7702 (search-forward "<company>")
7703 (replace-match string t t)
7704 (search-forward "<company>")
7705 (replace-match string t t)
7706 (search-backward "<description>")
7707 (replace-match "" t t))))
7709 ;; verilog-header Uses the verilog-insert-date function
7711 (defun verilog-insert-date ()
7712 "Insert date from the system."
7714 (if verilog-date-scientific-format
7715 (insert (format-time-string "%Y/%m/%d"))
7716 (insert (format-time-string "%d.%m.%Y"))))
7718 (defun verilog-insert-year ()
7719 "Insert year from the system."
7721 (insert (format-time-string "%Y")))
7725 ;; Signal list parsing
7728 ;; Elements of a signal list
7729 ;; Unfortunately we use 'assoc' on this, so can't be a vector
7730 (defsubst verilog-sig-new (name bits comment mem enum signed type multidim modport)
7731 (list name bits comment mem enum signed type multidim modport))
7732 (defsubst verilog-sig-name (sig)
7734 (defsubst verilog-sig-bits (sig) ;; First element of packed array (pre signal-name)
7736 (defsubst verilog-sig-comment (sig)
7738 (defsubst verilog-sig-memory (sig) ;; Unpacked array (post signal-name)
7740 (defsubst verilog-sig-enum (sig)
7742 (defsubst verilog-sig-signed (sig)
7744 (defsubst verilog-sig-type (sig)
7746 (defsubst verilog-sig-type-set (sig type)
7747 (setcar (nthcdr 6 sig) type))
7748 (defsubst verilog-sig-multidim (sig) ;; Second and additional elements of packed array
7750 (defsubst verilog-sig-multidim-string (sig)
7751 (if (verilog-sig-multidim sig)
7752 (let ((str "") (args (verilog-sig-multidim sig)))
7754 (setq str (concat str (car args)))
7755 (setq args (cdr args)))
7757 (defsubst verilog-sig-modport (sig)
7759 (defsubst verilog-sig-width (sig)
7760 (verilog-make-width-expression (verilog-sig-bits sig)))
7762 (defsubst verilog-alw-new (outputs-del outputs-imm temps inputs)
7763 (vector outputs-del outputs-imm temps inputs))
7764 (defsubst verilog-alw-get-outputs-delayed (sigs)
7766 (defsubst verilog-alw-get-outputs-immediate (sigs)
7768 (defsubst verilog-alw-get-temps (sigs)
7770 (defsubst verilog-alw-get-inputs (sigs)
7772 (defsubst verilog-alw-get-uses-delayed (sigs)
7775 (defsubst verilog-modport-new (name clockings decls)
7776 (list name clockings decls))
7777 (defsubst verilog-modport-name (sig)
7779 (defsubst verilog-modport-clockings (sig)
7780 (nth 1 sig)) ;; Returns list of names
7781 (defsubst verilog-modport-clockings-add (sig val)
7782 (setcar (nthcdr 1 sig) (cons val (nth 1 sig))))
7783 (defsubst verilog-modport-decls (sig)
7784 (nth 2 sig)) ;; Returns verilog-decls-* structure
7785 (defsubst verilog-modport-decls-set (sig val)
7786 (setcar (nthcdr 2 sig) val))
7788 (defsubst verilog-modi-new (name fob pt type)
7789 (vector name fob pt type))
7790 (defsubst verilog-modi-name (modi)
7792 (defsubst verilog-modi-file-or-buffer (modi)
7794 (defsubst verilog-modi-get-point (modi)
7796 (defsubst verilog-modi-get-type (modi) ;; "module" or "interface"
7798 (defsubst verilog-modi-get-decls (modi)
7799 (verilog-modi-cache-results modi 'verilog-read-decls))
7800 (defsubst verilog-modi-get-sub-decls (modi)
7801 (verilog-modi-cache-results modi 'verilog-read-sub-decls))
7803 ;; Signal reading for given module
7804 ;; Note these all take modi's - as returned from verilog-modi-current
7805 (defsubst verilog-decls-new (out inout in vars modports assigns consts gparams interfaces)
7806 (vector out inout in vars modports assigns consts gparams interfaces))
7807 (defsubst verilog-decls-append (a b)
7808 (cond ((not a) b) ((not b) a)
7809 (t (vector (append (aref a 0) (aref b 0)) (append (aref a 1) (aref b 1))
7810 (append (aref a 2) (aref b 2)) (append (aref a 3) (aref b 3))
7811 (append (aref a 4) (aref b 4)) (append (aref a 5) (aref b 5))
7812 (append (aref a 6) (aref b 6)) (append (aref a 7) (aref b 7))
7813 (append (aref a 8) (aref b 8))))))
7814 (defsubst verilog-decls-get-outputs (decls)
7816 (defsubst verilog-decls-get-inouts (decls)
7818 (defsubst verilog-decls-get-inputs (decls)
7820 (defsubst verilog-decls-get-vars (decls)
7822 (defsubst verilog-decls-get-modports (decls) ;; Also for clocking blocks; contains another verilog-decls struct
7823 (aref decls 4)) ;; Returns verilog-modport* structure
7824 (defsubst verilog-decls-get-assigns (decls)
7826 (defsubst verilog-decls-get-consts (decls)
7828 (defsubst verilog-decls-get-gparams (decls)
7830 (defsubst verilog-decls-get-interfaces (decls)
7834 (defsubst verilog-subdecls-new (out inout in intf intfd)
7835 (vector out inout in intf intfd))
7836 (defsubst verilog-subdecls-get-outputs (subdecls)
7838 (defsubst verilog-subdecls-get-inouts (subdecls)
7840 (defsubst verilog-subdecls-get-inputs (subdecls)
7842 (defsubst verilog-subdecls-get-interfaces (subdecls)
7844 (defsubst verilog-subdecls-get-interfaced (subdecls)
7847 (defun verilog-signals-from-signame (signame-list)
7848 "Return signals in standard form from SIGNAME-LIST, a simple list of names."
7849 (mapcar (lambda (name) (verilog-sig-new name nil nil nil nil nil nil nil nil))
7852 (defun verilog-signals-in (in-list not-list)
7853 "Return list of signals in IN-LIST that are also in NOT-LIST.
7854 Also remove any duplicates in IN-LIST.
7855 Signals must be in standard (base vector) form."
7856 ;; This function is hot, so implemented as O(1)
7857 (cond ((eval-when-compile (fboundp 'make-hash-table))
7858 (let ((ht (make-hash-table :test 'equal :rehash-size 4.0))
7859 (ht-not (make-hash-table :test 'equal :rehash-size 4.0))
7862 (puthash (car (car not-list)) t ht-not)
7863 (setq not-list (cdr not-list)))
7865 (when (and (gethash (verilog-sig-name (car in-list)) ht-not)
7866 (not (gethash (verilog-sig-name (car in-list)) ht)))
7867 (setq out-list (cons (car in-list) out-list))
7868 (puthash (verilog-sig-name (car in-list)) t ht))
7869 (setq in-list (cdr in-list)))
7870 (nreverse out-list)))
7871 ;; Slower Fallback if no hash tables (pre Emacs 21.1/XEmacs 21.4)
7875 (if (and (assoc (verilog-sig-name (car in-list)) not-list)
7876 (not (assoc (verilog-sig-name (car in-list)) out-list)))
7877 (setq out-list (cons (car in-list) out-list)))
7878 (setq in-list (cdr in-list)))
7879 (nreverse out-list)))))
7880 ;;(verilog-signals-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("C" "")))
7882 (defun verilog-signals-not-in (in-list not-list)
7883 "Return list of signals in IN-LIST that aren't also in NOT-LIST.
7884 Also remove any duplicates in IN-LIST.
7885 Signals must be in standard (base vector) form."
7886 ;; This function is hot, so implemented as O(1)
7887 (cond ((eval-when-compile (fboundp 'make-hash-table))
7888 (let ((ht (make-hash-table :test 'equal :rehash-size 4.0))
7891 (puthash (car (car not-list)) t ht)
7892 (setq not-list (cdr not-list)))
7894 (when (not (gethash (verilog-sig-name (car in-list)) ht))
7895 (setq out-list (cons (car in-list) out-list))
7896 (puthash (verilog-sig-name (car in-list)) t ht))
7897 (setq in-list (cdr in-list)))
7898 (nreverse out-list)))
7899 ;; Slower Fallback if no hash tables (pre Emacs 21.1/XEmacs 21.4)
7903 (if (and (not (assoc (verilog-sig-name (car in-list)) not-list))
7904 (not (assoc (verilog-sig-name (car in-list)) out-list)))
7905 (setq out-list (cons (car in-list) out-list)))
7906 (setq in-list (cdr in-list)))
7907 (nreverse out-list)))))
7908 ;;(verilog-signals-not-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" "")))
7910 (defun verilog-signals-not-in-struct (in-list not-list)
7911 "Return list of signals in IN-LIST that aren't also in NOT-LIST.
7912 Also remove any duplicates in IN-LIST.
7913 Any structure in not-list will remove all members in in-list.
7914 Signals must be in standard (base vector) form."
7915 (cond ((eval-when-compile (fboundp 'make-hash-table))
7916 (let ((ht (make-hash-table :test 'equal :rehash-size 4.0))
7919 (puthash (car (car not-list)) t ht)
7920 (setq not-list (cdr not-list)))
7922 (setq nm (verilog-sig-name (car in-list)))
7923 (when (not (gethash nm ht))
7925 (while (string-match "^\\([^\\].*\\)\\.[^.]+$" nm)
7926 (setq nm (match-string 1 nm))
7927 (setq addit (and addit
7928 (not (gethash nm ht)))))
7930 (setq out-list (cons (car in-list) out-list))
7931 (puthash (verilog-sig-name (car in-list)) t ht)))
7932 (setq in-list (cdr in-list)))
7933 (nreverse out-list)))
7934 ;; Slower Fallback if no hash tables (pre Emacs 21.1/XEmacs 21.4)
7936 (let (out-list addit nm)
7938 (setq nm (verilog-sig-name (car in-list)))
7939 (when (and (not (assoc nm not-list))
7940 (not (assoc nm out-list)))
7942 (while (string-match "^\\([^\\].*\\)\\.[^.]+$" nm)
7943 (setq nm (match-string 1 nm))
7944 (setq addit (and addit
7945 (not (assoc nm not-list)))))
7947 (setq out-list (cons (car in-list) out-list))))
7948 (setq in-list (cdr in-list)))
7949 (nreverse out-list)))))
7950 ;;(verilog-signals-not-in-struct '(("A" "") ("B" "") ("DEL.SUB.A" "[2:3]")) '(("DEL.SUB" "") ("EXT" "")))
7952 (defun verilog-signals-memory (in-list)
7953 "Return list of signals in IN-LIST that are memorized (multidimensional)."
7956 (if (nth 3 (car in-list))
7957 (setq out-list (cons (car in-list) out-list)))
7958 (setq in-list (cdr in-list)))
7960 ;;(verilog-signals-memory '(("A" nil nil "[3:0]")) '(("B" nil nil nil)))
7962 (defun verilog-signals-sort-compare (a b)
7963 "Compare signal A and B for sorting."
7964 (string< (verilog-sig-name a) (verilog-sig-name b)))
7966 (defun verilog-signals-not-params (in-list)
7967 "Return list of signals in IN-LIST that aren't parameters or numeric constants."
7970 ;; Namespace intentionally short for AUTOs and compatibility
7971 (unless (boundp (intern (concat "vh-" (verilog-sig-name (car in-list)))))
7972 (setq out-list (cons (car in-list) out-list)))
7973 (setq in-list (cdr in-list)))
7974 (nreverse out-list)))
7976 (defun verilog-signals-with (func in-list)
7977 "Return list of signals where FUNC is true executed on each signal in IN-LIST."
7980 (when (funcall func (car in-list))
7981 (setq out-list (cons (car in-list) out-list)))
7982 (setq in-list (cdr in-list)))
7983 (nreverse out-list)))
7985 (defun verilog-signals-combine-bus (in-list)
7986 "Return a list of signals in IN-LIST, with buses combined.
7987 Duplicate signals are also removed. For example A[2] and A[1] become A[2:1]."
7990 sig highbit lowbit ; Temp information about current signal
7991 sv-name sv-highbit sv-lowbit ; Details about signal we are forming
7992 sv-comment sv-memory sv-enum sv-signed sv-type sv-multidim sv-busstring
7995 ;; Shove signals so duplicated signals will be adjacent
7996 (setq in-list (sort in-list `verilog-signals-sort-compare))
7998 (setq sig (car in-list))
7999 ;; No current signal; form from existing details
8001 (setq sv-name (verilog-sig-name sig)
8004 sv-comment (verilog-sig-comment sig)
8005 sv-memory (verilog-sig-memory sig)
8006 sv-enum (verilog-sig-enum sig)
8007 sv-signed (verilog-sig-signed sig)
8008 sv-type (verilog-sig-type sig)
8009 sv-multidim (verilog-sig-multidim sig)
8010 sv-modport (verilog-sig-modport sig)
8013 ;; Extract bus details
8014 (setq bus (verilog-sig-bits sig))
8015 (setq bus (and bus (verilog-simplify-range-expression bus)))
8017 (or (and (string-match "\\[\\([0-9]+\\):\\([0-9]+\\)\\]" bus)
8018 (setq highbit (string-to-number (match-string 1 bus))
8019 lowbit (string-to-number
8020 (match-string 2 bus))))
8021 (and (string-match "\\[\\([0-9]+\\)\\]" bus)
8022 (setq highbit (string-to-number (match-string 1 bus))
8024 ;; Combine bits in bus
8026 (setq sv-highbit (max highbit sv-highbit)
8027 sv-lowbit (min lowbit sv-lowbit))
8028 (setq sv-highbit highbit
8031 ;; String, probably something like `preproc:0
8032 (setq sv-busstring bus)))
8033 ;; Peek ahead to next signal
8034 (setq in-list (cdr in-list))
8035 (setq sig (car in-list))
8036 (cond ((and sig (equal sv-name (verilog-sig-name sig)))
8037 ;; Combine with this signal
8038 (when (and sv-busstring
8039 (not (equal sv-busstring (verilog-sig-bits sig))))
8040 (when nil ;; Debugging
8041 (message (concat "Warning, can't merge into single bus "
8043 ", the AUTOs may be wrong")))
8044 (setq buswarn ", Couldn't Merge"))
8045 (if (verilog-sig-comment sig) (setq combo ", ..."))
8046 (setq sv-memory (or sv-memory (verilog-sig-memory sig))
8047 sv-enum (or sv-enum (verilog-sig-enum sig))
8048 sv-signed (or sv-signed (verilog-sig-signed sig))
8049 sv-type (or sv-type (verilog-sig-type sig))
8050 sv-multidim (or sv-multidim (verilog-sig-multidim sig))
8051 sv-modport (or sv-modport (verilog-sig-modport sig))))
8052 ;; Doesn't match next signal, add to queue, zero in prep for next
8053 ;; Note sig may also be nil for the last signal in the list
8056 (cons (verilog-sig-new
8060 (concat "[" (int-to-string sv-highbit) ":"
8061 (int-to-string sv-lowbit) "]")))
8062 (concat sv-comment combo buswarn)
8063 sv-memory sv-enum sv-signed sv-type sv-multidim sv-modport)
8069 (defun verilog-sig-tieoff (sig)
8070 "Return tieoff expression for given SIG, with appropriate width.
8071 Tieoff value uses `verilog-active-low-regexp' and
8072 `verilog-auto-reset-widths'."
8074 (if (and verilog-active-low-regexp
8075 (verilog-string-match-fold verilog-active-low-regexp (verilog-sig-name sig)))
8077 (cond ((not verilog-auto-reset-widths)
8079 ((equal verilog-auto-reset-widths 'unbased)
8081 ;; Else presume verilog-auto-reset-widths is true
8083 (let* ((width (verilog-sig-width sig)))
8086 ((string-match "^[0-9]+$" width)
8087 (concat width (if (verilog-sig-signed sig) "'sh0" "'h0")))
8089 (concat "{" width "{1'b0}}"))))))))
8095 (defun verilog-decls-princ (decls &optional header prefix)
8096 "For debug, dump the `verilog-read-decls' structure DECLS."
8098 (if header (princ header))
8099 (setq prefix (or prefix ""))
8100 (verilog-signals-princ (verilog-decls-get-outputs decls)
8101 (concat prefix "Outputs:\n") (concat prefix " "))
8102 (verilog-signals-princ (verilog-decls-get-inouts decls)
8103 (concat prefix "Inout:\n") (concat prefix " "))
8104 (verilog-signals-princ (verilog-decls-get-inputs decls)
8105 (concat prefix "Inputs:\n") (concat prefix " "))
8106 (verilog-signals-princ (verilog-decls-get-vars decls)
8107 (concat prefix "Vars:\n") (concat prefix " "))
8108 (verilog-signals-princ (verilog-decls-get-assigns decls)
8109 (concat prefix "Assigns:\n") (concat prefix " "))
8110 (verilog-signals-princ (verilog-decls-get-consts decls)
8111 (concat prefix "Consts:\n") (concat prefix " "))
8112 (verilog-signals-princ (verilog-decls-get-gparams decls)
8113 (concat prefix "Gparams:\n") (concat prefix " "))
8114 (verilog-signals-princ (verilog-decls-get-interfaces decls)
8115 (concat prefix "Interfaces:\n") (concat prefix " "))
8116 (verilog-modport-princ (verilog-decls-get-modports decls)
8117 (concat prefix "Modports:\n") (concat prefix " "))
8120 (defun verilog-signals-princ (signals &optional header prefix)
8121 "For debug, dump internal SIGNALS structures, with HEADER and PREFIX."
8123 (if header (princ header))
8125 (let ((sig (car signals)))
8126 (setq signals (cdr signals))
8128 (princ "\"") (princ (verilog-sig-name sig)) (princ "\"")
8129 (princ " bits=") (princ (verilog-sig-bits sig))
8130 (princ " cmt=") (princ (verilog-sig-comment sig))
8131 (princ " mem=") (princ (verilog-sig-memory sig))
8132 (princ " enum=") (princ (verilog-sig-enum sig))
8133 (princ " sign=") (princ (verilog-sig-signed sig))
8134 (princ " type=") (princ (verilog-sig-type sig))
8135 (princ " dim=") (princ (verilog-sig-multidim sig))
8136 (princ " modp=") (princ (verilog-sig-modport sig))
8139 (defun verilog-modport-princ (modports &optional header prefix)
8140 "For debug, dump internal MODPORT structures, with HEADER and PREFIX."
8142 (if header (princ header))
8144 (let ((sig (car modports)))
8145 (setq modports (cdr modports))
8147 (princ "\"") (princ (verilog-modport-name sig)) (princ "\"")
8148 (princ " clockings=") (princ (verilog-modport-clockings sig))
8150 (verilog-decls-princ (verilog-modport-decls sig)
8151 (concat prefix " syms:\n")
8152 (concat prefix " "))))))
8155 ;; Port/Wire/Etc Reading
8158 (defun verilog-read-inst-backward-name ()
8159 "Internal. Move point back to beginning of inst-name."
8160 (verilog-backward-open-paren)
8163 (verilog-re-search-backward-quick "\\()\\|\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil) ; ] isn't word boundary
8164 (cond ((looking-at ")")
8165 (verilog-backward-open-paren))
8166 (t (setq done t)))))
8167 (while (looking-at "\\]")
8168 (verilog-backward-open-bracket)
8169 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil))
8170 (skip-chars-backward "a-zA-Z0-9`_$"))
8172 (defun verilog-read-inst-module-matcher ()
8173 "Set match data 0 with module_name when point is inside instantiation."
8174 (verilog-read-inst-backward-name)
8175 ;; Skip over instantiation name
8176 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary
8177 ;; Check for parameterized instantiations
8178 (when (looking-at ")")
8179 (verilog-backward-open-paren)
8180 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil))
8181 (skip-chars-backward "a-zA-Z0-9'_$")
8182 ;; #1 is legal syntax for gate primitives
8183 (when (save-excursion
8184 (verilog-backward-syntactic-ws-quick)
8185 (eq ?# (char-before)))
8186 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil)
8187 (skip-chars-backward "a-zA-Z0-9'_$"))
8188 (looking-at "[a-zA-Z0-9`_\$]+")
8189 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
8190 (buffer-substring-no-properties (match-beginning 0) (match-end 0))
8191 ;; Caller assumes match-beginning/match-end is still set
8194 (defun verilog-read-inst-module ()
8195 "Return module_name when point is inside instantiation."
8197 (verilog-read-inst-module-matcher)))
8199 (defun verilog-read-inst-name ()
8200 "Return instance_name when point is inside instantiation."
8202 (verilog-read-inst-backward-name)
8203 (looking-at "[a-zA-Z0-9`_\$]+")
8204 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
8205 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
8207 (defun verilog-read-module-name ()
8208 "Return module name when after its ( or ;."
8210 (re-search-backward "[(;]")
8211 ;; Due to "module x import y (" we must search for declaration begin
8212 (verilog-re-search-backward-quick verilog-defun-re nil nil)
8213 (goto-char (match-end 0))
8214 (verilog-re-search-forward-quick "\\b[a-zA-Z0-9`_\$]+" nil nil)
8215 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
8216 (verilog-symbol-detick
8217 (buffer-substring-no-properties (match-beginning 0) (match-end 0)) t)))
8219 (defun verilog-read-inst-param-value ()
8220 "Return list of parameters and values when point is inside instantiation."
8222 (verilog-read-inst-backward-name)
8223 ;; Skip over instantiation name
8224 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary
8225 ;; If there are parameterized instantiations
8226 (when (looking-at ")")
8227 (let ((end-pt (point))
8229 param-name paren-beg-pt param-value)
8230 (verilog-backward-open-paren)
8231 (while (verilog-re-search-forward-quick "\\." end-pt t)
8232 (verilog-re-search-forward-quick "\\([a-zA-Z0-9`_\$]\\)" nil nil)
8233 (skip-chars-backward "a-zA-Z0-9'_$")
8234 (looking-at "[a-zA-Z0-9`_\$]+")
8235 (setq param-name (buffer-substring-no-properties
8236 (match-beginning 0) (match-end 0)))
8237 (verilog-re-search-forward-quick "(" nil nil)
8238 (setq paren-beg-pt (point))
8239 (verilog-forward-close-paren)
8240 (setq param-value (verilog-string-remove-spaces
8241 (buffer-substring-no-properties
8242 paren-beg-pt (1- (point)))))
8243 (setq params (cons (list param-name param-value) params)))
8246 (defun verilog-read-auto-params (num-param &optional max-param)
8247 "Return parameter list inside auto.
8248 Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters."
8251 ;; /*AUTOPUNT("parameter", "parameter")*/
8253 (while (looking-at "(?\\s *\"\\([^\"]*\\)\"\\s *,?")
8254 (setq olist (cons (match-string 1) olist))
8255 (goto-char (match-end 0))))
8256 (or (eq nil num-param)
8257 (<= num-param (length olist))
8258 (error "%s: Expected %d parameters" (verilog-point-text) num-param))
8259 (if (eq max-param nil) (setq max-param num-param))
8260 (or (eq nil max-param)
8261 (>= max-param (length olist))
8262 (error "%s: Expected <= %d parameters" (verilog-point-text) max-param))
8265 (defun verilog-read-decls ()
8266 "Compute signal declaration information for the current module at point.
8267 Return an array of [outputs inouts inputs wire reg assign const]."
8268 (let ((end-mod-point (or (verilog-get-end-of-defun) (point-max)))
8269 (functask 0) (paren 0) (sig-paren 0) (v2kargs-ok t)
8270 in-modport in-clocking in-ign-to-semi ptype ign-prop
8271 sigs-in sigs-out sigs-inout sigs-var sigs-assign sigs-const
8272 sigs-gparam sigs-intf sigs-modports
8273 vec expect-signal keywd newsig rvalue enum io signed typedefed multidim
8276 ;;(if dbg (setq dbg (concat dbg (format "\n\nverilog-read-decls START PT %s END %s\n" (point) end-mod-point))))
8278 (verilog-beg-of-defun-quick)
8279 (setq sigs-const (verilog-read-auto-constants (point) end-mod-point))
8280 (while (< (point) end-mod-point)
8281 ;;(if dbg (setq dbg (concat dbg (format "Pt %s Vec %s C%c Kwd'%s'\n" (point) vec (following-char) keywd))))
8284 (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
8285 (setq enum (match-string 2)))
8286 (search-forward "\n"))
8287 ((looking-at "/\\*")
8289 (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
8290 (setq enum (match-string 2)))
8291 (or (search-forward "*/")
8292 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8293 ((looking-at "(\\*")
8294 ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
8296 (or (search-forward "*)")
8297 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
8298 ((eq ?\" (following-char))
8299 (or (re-search-forward "[^\\]\"" nil t) ;; don't forward-char first, since we look for a non backslash first
8300 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
8301 ((eq ?\; (following-char))
8302 (cond (in-ign-to-semi ;; Such as inside a "import ...;" in a module header
8303 (setq in-ign-to-semi nil))
8304 ((and in-modport (not (eq in-modport t))) ;; end of a modport declaration
8305 (verilog-modport-decls-set
8307 (verilog-decls-new sigs-out sigs-inout sigs-in
8308 nil nil nil nil nil nil))
8309 ;; Pop from varstack to restore state to pre-clocking
8310 (setq tmp (car varstack)
8311 varstack (cdr varstack)
8312 sigs-out (aref tmp 0)
8313 sigs-inout (aref tmp 1)
8314 sigs-in (aref tmp 2))
8315 (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil
8316 v2kargs-ok nil in-modport nil ign-prop nil))
8318 (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil
8319 v2kargs-ok nil in-modport nil ign-prop nil)))
8321 ((eq ?= (following-char))
8322 (setq rvalue t newsig nil)
8324 ((and (eq ?, (following-char))
8325 (eq paren sig-paren))
8328 ;; ,'s can occur inside {} & funcs
8329 ((looking-at "[{(]")
8330 (setq paren (1+ paren))
8332 ((looking-at "[})]")
8333 (setq paren (1- paren))
8335 (when (< paren sig-paren)
8336 (setq expect-signal nil rvalue nil))) ; ) that ends variables inside v2k arg list
8337 ((looking-at "\\s-*\\(\\[[^]]+\\]\\)")
8338 (goto-char (match-end 0))
8339 (cond (newsig ; Memory, not just width. Patch last signal added's memory (nth 3)
8340 (setcar (cdr (cdr (cdr newsig)))
8341 (if (verilog-sig-memory newsig)
8342 (concat (verilog-sig-memory newsig) (match-string 1))
8344 (vec ;; Multidimensional
8345 (setq multidim (cons vec multidim))
8346 (setq vec (verilog-string-replace-matches
8347 "\\s-+" "" nil nil (match-string 1))))
8349 (setq vec (verilog-string-replace-matches
8350 "\\s-+" "" nil nil (match-string 1))))))
8351 ;; Normal or escaped identifier -- note we remember the \ if escaped
8352 ((looking-at "\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
8353 (goto-char (match-end 0))
8354 (setq keywd (match-string 1))
8355 (when (string-match "^\\\\" (match-string 1))
8356 (setq keywd (concat keywd " "))) ;; Escaped ID needs space at end
8357 ;; Add any :: package names to same identifier
8358 (while (looking-at "\\s-*::\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
8359 (goto-char (match-end 0))
8360 (setq keywd (concat keywd "::" (match-string 1)))
8361 (when (string-match "^\\\\" (match-string 1))
8362 (setq keywd (concat keywd " ")))) ;; Escaped ID needs space at end
8363 (cond ((equal keywd "input")
8364 (setq vec nil enum nil rvalue nil newsig nil signed nil
8365 typedefed nil multidim nil ptype nil modport nil
8366 expect-signal 'sigs-in io t sig-paren paren))
8367 ((equal keywd "output")
8368 (setq vec nil enum nil rvalue nil newsig nil signed nil
8369 typedefed nil multidim nil ptype nil modport nil
8370 expect-signal 'sigs-out io t sig-paren paren))
8371 ((equal keywd "inout")
8372 (setq vec nil enum nil rvalue nil newsig nil signed nil
8373 typedefed nil multidim nil ptype nil modport nil
8374 expect-signal 'sigs-inout io t sig-paren paren))
8375 ((equal keywd "parameter")
8376 (setq vec nil enum nil rvalue nil signed nil
8377 typedefed nil multidim nil ptype nil modport nil
8378 expect-signal 'sigs-gparam io t sig-paren paren))
8379 ((member keywd '("wire" "reg" ; Fast
8381 "tri" "tri0" "tri1" "triand" "trior" "trireg"
8382 "uwire" "wand" "wor"
8383 ;; integer_atom_type
8384 "byte" "shortint" "int" "longint" "integer" "time"
8386 ;; integer_vector_type - "reg" above
8389 "shortreal" "real" "realtime"
8391 "string" "event" "chandle"))
8394 (if typedefed (concat typedefed " " keywd) keywd)))
8395 (t (setq vec nil enum nil rvalue nil signed nil
8396 typedefed nil multidim nil sig-paren paren
8397 expect-signal 'sigs-var modport nil))))
8398 ((equal keywd "assign")
8399 (setq vec nil enum nil rvalue nil signed nil
8400 typedefed nil multidim nil ptype nil modport nil
8401 expect-signal 'sigs-assign sig-paren paren))
8402 ((member keywd '("localparam" "genvar"))
8403 (setq vec nil enum nil rvalue nil signed nil
8404 typedefed nil multidim nil ptype nil modport nil
8405 expect-signal 'sigs-const sig-paren paren))
8406 ((member keywd '("signed" "unsigned"))
8407 (setq signed keywd))
8408 ((member keywd '("assert" "assume" "cover" "expect" "restrict"))
8410 ((member keywd '("class" "covergroup" "function"
8411 "property" "randsequence" "sequence" "task"))
8413 (setq functask (1+ functask))))
8414 ((member keywd '("endclass" "endgroup" "endfunction"
8415 "endproperty" "endsequence" "endtask"))
8416 (setq functask (1- functask)))
8417 ((equal keywd "modport")
8418 (setq in-modport t))
8419 ((equal keywd "clocking")
8420 (setq in-clocking t))
8421 ((equal keywd "import")
8422 (if v2kargs-ok ;; import in module header, not a modport import
8423 (setq in-ign-to-semi t rvalue t)))
8424 ((equal keywd "type")
8426 ((equal keywd "var"))
8427 ;; Ifdef? Ignore name of define
8428 ((member keywd '("`ifdef" "`ifndef" "`elsif"))
8432 (verilog-typedef-name-p keywd))
8435 (if typedefed (concat typedefed " " keywd) keywd)))
8436 (t (setq vec nil enum nil rvalue nil signed nil
8437 typedefed keywd ; Have a type
8438 multidim nil sig-paren paren
8439 expect-signal 'sigs-var modport nil))))
8440 ;; Interface with optional modport in v2k arglist?
8441 ;; Skip over parsing modport, and take the interface name as the type
8445 (looking-at "\\s-*\\(\\.\\(\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*\\)\\|\\)\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*"))
8446 (when (match-end 2) (goto-char (match-end 2)))
8447 (setq vec nil enum nil rvalue nil signed nil
8448 typedefed keywd multidim nil ptype nil modport (match-string 2)
8449 newsig nil sig-paren paren
8450 expect-signal 'sigs-intf io t ))
8451 ;; Ignore dotted LHS assignments: "assign foo.bar = z;"
8452 ((looking-at "\\s-*\\.")
8453 (goto-char (match-end 0))
8455 (setq expect-signal nil)))
8456 ;; "modport <keywd>"
8457 ((and (eq in-modport t)
8458 (not (member keywd verilog-keywords)))
8459 (setq in-modport (verilog-modport-new keywd nil nil))
8460 (setq sigs-modports (cons in-modport sigs-modports))
8461 ;; Push old sig values to stack and point to new signal list
8462 (setq varstack (cons (vector sigs-out sigs-inout sigs-in)
8464 (setq sigs-in nil sigs-inout nil sigs-out nil))
8465 ;; "modport x (clocking <keywd>)"
8466 ((and in-modport in-clocking)
8467 (verilog-modport-clockings-add in-modport keywd)
8468 (setq in-clocking nil))
8471 (equal keywd "endclocking"))
8472 (unless (eq in-clocking t)
8473 (verilog-modport-decls-set
8475 (verilog-decls-new sigs-out sigs-inout sigs-in
8476 nil nil nil nil nil nil))
8477 ;; Pop from varstack to restore state to pre-clocking
8478 (setq tmp (car varstack)
8479 varstack (cdr varstack)
8480 sigs-out (aref tmp 0)
8481 sigs-inout (aref tmp 1)
8482 sigs-in (aref tmp 2)))
8483 (setq in-clocking nil))
8484 ;; "clocking <keywd>"
8485 ((and (eq in-clocking t)
8486 (not (member keywd verilog-keywords)))
8487 (setq in-clocking (verilog-modport-new keywd nil nil))
8488 (setq sigs-modports (cons in-clocking sigs-modports))
8489 ;; Push old sig values to stack and point to new signal list
8490 (setq varstack (cons (vector sigs-out sigs-inout sigs-in)
8492 (setq sigs-in nil sigs-inout nil sigs-out nil))
8493 ;; New signal, maybe?
8497 (not (member keywd verilog-keywords)))
8498 ;; Add new signal to expect-signal's variable
8499 ;;(if dbg (setq dbg (concat dbg (format "Pt %s New sig %s'\n" (point) keywd))))
8500 (setq newsig (verilog-sig-new keywd vec nil nil enum signed typedefed multidim modport))
8501 (set expect-signal (cons newsig
8502 (symbol-value expect-signal))))))
8505 (skip-syntax-forward " "))
8507 (setq tmp (verilog-decls-new (nreverse sigs-out)
8508 (nreverse sigs-inout)
8511 (nreverse sigs-modports)
8512 (nreverse sigs-assign)
8513 (nreverse sigs-const)
8514 (nreverse sigs-gparam)
8515 (nreverse sigs-intf)))
8516 ;;(if dbg (verilog-decls-princ tmp))
8519 (defvar verilog-read-sub-decls-in-interfaced nil
8520 "For `verilog-read-sub-decls', process next signal as under interfaced block.")
8522 (defvar verilog-read-sub-decls-gate-ios nil
8523 "For `verilog-read-sub-decls', gate IO pins remaining, nil if non-primitive.")
8526 ;; Prevent compile warnings; these are let's, not globals
8527 ;; Do not remove the eval-when-compile
8528 ;; - we want an error when we are debugging this code if they are refed.
8536 (defvar sigs-out-unk)
8538 ;; These are known to be from other packages and may not be defined
8539 (defvar diff-command nil)
8540 ;; There are known to be from newer versions of Emacs
8541 (defvar create-lockfiles))
8543 (defun verilog-read-sub-decls-sig (submoddecls comment port sig vec multidim)
8544 "For `verilog-read-sub-decls-line', add a signal."
8545 ;; sig eq t to indicate .name syntax
8546 ;;(message "vrsds: %s(%S)" port sig)
8547 (let ((dotname (eq sig t))
8550 (setq port (verilog-symbol-detick-denumber port))
8551 (setq sig (if dotname port (verilog-symbol-detick-denumber sig)))
8552 (if vec (setq vec (verilog-symbol-detick-denumber vec)))
8553 (if multidim (setq multidim (mapcar `verilog-symbol-detick-denumber multidim)))
8554 (unless (or (not sig)
8555 (equal sig "")) ;; Ignore .foo(1'b1) assignments
8556 (cond ((or (setq portdata (assoc port (verilog-decls-get-inouts submoddecls)))
8557 (equal "inout" verilog-read-sub-decls-gate-ios))
8559 (cons (verilog-sig-new
8561 (if dotname (verilog-sig-bits portdata) vec)
8562 (concat "To/From " comment)
8563 (verilog-sig-memory portdata)
8565 (verilog-sig-signed portdata)
8566 (unless (member (verilog-sig-type portdata) '("wire" "reg"))
8567 (verilog-sig-type portdata))
8570 ((or (setq portdata (assoc port (verilog-decls-get-outputs submoddecls)))
8571 (equal "output" verilog-read-sub-decls-gate-ios))
8573 (cons (verilog-sig-new
8575 (if dotname (verilog-sig-bits portdata) vec)
8576 (concat "From " comment)
8577 (verilog-sig-memory portdata)
8579 (verilog-sig-signed portdata)
8580 ;; Though ok in SV, in V2K code, propagating the
8581 ;; "reg" in "output reg" upwards isn't legal.
8582 ;; Also for backwards compatibility we don't propagate
8583 ;; "input wire" upwards.
8584 ;; See also `verilog-signals-edit-wire-reg'.
8585 (unless (member (verilog-sig-type portdata) '("wire" "reg"))
8586 (verilog-sig-type portdata))
8589 ((or (setq portdata (assoc port (verilog-decls-get-inputs submoddecls)))
8590 (equal "input" verilog-read-sub-decls-gate-ios))
8592 (cons (verilog-sig-new
8594 (if dotname (verilog-sig-bits portdata) vec)
8595 (concat "To " comment)
8596 (verilog-sig-memory portdata)
8598 (verilog-sig-signed portdata)
8599 (unless (member (verilog-sig-type portdata) '("wire" "reg"))
8600 (verilog-sig-type portdata))
8603 ((setq portdata (assoc port (verilog-decls-get-interfaces submoddecls)))
8605 (cons (verilog-sig-new
8607 (if dotname (verilog-sig-bits portdata) vec)
8608 (concat "To/From " comment)
8609 (verilog-sig-memory portdata)
8611 (verilog-sig-signed portdata)
8612 (verilog-sig-type portdata)
8615 ((setq portdata (and verilog-read-sub-decls-in-interfaced
8616 (assoc port (verilog-decls-get-vars submoddecls))))
8618 (cons (verilog-sig-new
8620 (if dotname (verilog-sig-bits portdata) vec)
8621 (concat "To/From " comment)
8622 (verilog-sig-memory portdata)
8624 (verilog-sig-signed portdata)
8625 (verilog-sig-type portdata)
8628 ;; (t -- warning pin isn't defined.) ; Leave for lint tool
8631 (defun verilog-read-sub-decls-expr (submoddecls comment port expr)
8632 "For `verilog-read-sub-decls-line', parse a subexpression and add signals."
8633 ;;(message "vrsde: '%s'" expr)
8634 ;; Replace special /*[....]*/ comments inserted by verilog-auto-inst-port
8635 (setq expr (verilog-string-replace-matches "/\\*\\(\\[[^*]+\\]\\)\\*/" "\\1" nil nil expr))
8636 ;; Remove front operators
8637 (setq expr (verilog-string-replace-matches "^\\s-*[---+~!|&]+\\s-*" "" nil nil expr))
8640 ;; {..., a, b} requires us to recurse on a,b
8641 ;; To support {#{},{#{a,b}} we'll just split everything on [{},]
8642 ((string-match "^\\s-*{\\(.*\\)}\\s-*$" expr)
8643 (unless verilog-auto-ignore-concat
8644 (let ((mlst (split-string (match-string 1 expr) "[{},]"))
8646 (while (setq mstr (pop mlst))
8647 (verilog-read-sub-decls-expr submoddecls comment port mstr)))))
8649 (let (sig vec multidim)
8650 ;; Remove leading reduction operators, etc
8651 (setq expr (verilog-string-replace-matches "^\\s-*[---+~!|&]+\\s-*" "" nil nil expr))
8652 ;;(message "vrsde-ptop: '%s'" expr)
8653 (cond ;; Find \signal. Final space is part of escaped signal name
8654 ((string-match "^\\s-*\\(\\\\[^ \t\n\f]+\\s-\\)" expr)
8655 ;;(message "vrsde-s: '%s'" (match-string 1 expr))
8656 (setq sig (match-string 1 expr)
8657 expr (substring expr (match-end 0))))
8659 ((string-match "^\\s-*\\([a-zA-Z_][a-zA-Z_0-9]*\\)" expr)
8660 ;;(message "vrsde-s: '%s'" (match-string 1 expr))
8661 (setq sig (verilog-string-remove-spaces (match-string 1 expr))
8662 expr (substring expr (match-end 0)))))
8663 ;; Find [vector] or [multi][multi][multi][vector]
8664 (while (string-match "^\\s-*\\(\\[[^]]+\\]\\)" expr)
8665 ;;(message "vrsde-v: '%s'" (match-string 1 expr))
8666 (when vec (setq multidim (cons vec multidim)))
8667 (setq vec (match-string 1 expr)
8668 expr (substring expr (match-end 0))))
8669 ;; If found signal, and nothing unrecognized, add the signal
8670 ;;(message "vrsde-rem: '%s'" expr)
8671 (when (and sig (string-match "^\\s-*$" expr))
8672 (verilog-read-sub-decls-sig submoddecls comment port sig vec multidim))))))
8674 (defun verilog-read-sub-decls-line (submoddecls comment)
8675 "For `verilog-read-sub-decls', read lines of port defs until none match.
8676 Inserts the list of signals found, using submodi to look up each port."
8682 (cond ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*(\\s-*")
8683 (setq port (match-string 1))
8684 (goto-char (match-end 0)))
8686 ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*(\\s-*")
8687 (setq port (concat (match-string 1) " ")) ;; escaped id's need trailing space
8688 (goto-char (match-end 0)))
8690 ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*[,)/]")
8691 (verilog-read-sub-decls-sig
8692 submoddecls comment (match-string 1) t ; sig==t for .name
8693 nil nil) ; vec multidim
8696 ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*[,)/]")
8697 (verilog-read-sub-decls-sig
8698 submoddecls comment (concat (match-string 1) " ") t ; sig==t for .name
8699 nil nil) ; vec multidim
8702 ((looking-at "\\s-*\\.[^(]*(")
8703 (setq port nil) ;; skip this line
8704 (goto-char (match-end 0)))
8706 (setq port nil done t))) ;; Unknown, ignore rest of line
8707 ;; Get signal name. Point is at the first-non-space after (
8708 ;; We intentionally ignore (non-escaped) signals with .s in them
8709 ;; this prevents AUTOWIRE etc from noticing hierarchical sigs.
8711 (cond ((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*)")
8712 (verilog-read-sub-decls-sig
8713 submoddecls comment port
8714 (verilog-string-remove-spaces (match-string 1)) ; sig
8715 nil nil)) ; vec multidim
8717 ((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*)")
8718 (verilog-read-sub-decls-sig
8719 submoddecls comment port
8720 (verilog-string-remove-spaces (match-string 1)) ; sig
8721 (match-string 2) nil)) ; vec multidim
8722 ;; Fastpath was above looking-at's.
8723 ;; For something more complicated invoke a parser
8724 ((looking-at "[^)]+")
8725 (verilog-read-sub-decls-expr
8726 submoddecls comment port
8728 (point) (1- (progn (search-backward "(") ; start at (
8729 (verilog-forward-sexp-ign-cmt 1)
8730 (point)))))))) ; expr
8732 (forward-line 1)))))
8734 (defun verilog-read-sub-decls-gate (submoddecls comment submod end-inst-point)
8735 "For `verilog-read-sub-decls', read lines of UDP gate decl until none match.
8736 Inserts the list of signals found."
8738 (let ((iolist (cdr (assoc submod verilog-gate-ios))))
8739 (while (< (point) end-inst-point)
8740 ;; Get primitive's signal name, as will never have port, and no trailing )
8741 (cond ((looking-at "//")
8742 (search-forward "\n"))
8743 ((looking-at "/\\*")
8744 (or (search-forward "*/")
8745 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8746 ((looking-at "(\\*")
8747 ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
8749 (or (search-forward "*)")
8750 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
8751 ;; On pins, parse and advance to next pin
8752 ;; Looking at pin, but *not* an // Output comment, or ) to end the inst
8753 ((looking-at "\\s-*[a-zA-Z0-9`_$({}\\\\][^,]*")
8754 (goto-char (match-end 0))
8755 (setq verilog-read-sub-decls-gate-ios (or (car iolist) "input")
8756 iolist (cdr iolist))
8757 (verilog-read-sub-decls-expr
8758 submoddecls comment "primitive_port"
8762 (skip-syntax-forward " ")))))))
8764 (defun verilog-read-sub-decls ()
8765 "Internally parse signals going to modules under this module.
8766 Return an array of [ outputs inouts inputs ] signals for modules that are
8767 instantiated in this module. For example if declare A A (.B(SIG)) and SIG
8768 is an output, then SIG will be included in the list.
8770 This only works on instantiations created with /*AUTOINST*/ converted by
8771 \\[verilog-auto-inst]. Otherwise, it would have to read in the whole
8772 component library to determine connectivity of the design.
8774 One work around for this problem is to manually create // Inputs and //
8775 Outputs comments above subcell signals, for example:
8783 (let ((end-mod-point (verilog-get-end-of-defun))
8784 st-point end-inst-point
8785 ;; below 3 modified by verilog-read-sub-decls-line
8786 sigs-out sigs-inout sigs-in sigs-intf sigs-intfd)
8787 (verilog-beg-of-defun-quick)
8788 (while (verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-mod-point t)
8790 (goto-char (match-beginning 0))
8791 (unless (verilog-inside-comment-or-string-p)
8792 ;; Attempt to snarf a comment
8793 (let* ((submod (verilog-read-inst-module))
8794 (inst (verilog-read-inst-name))
8795 (subprim (member submod verilog-gate-keywords))
8796 (comment (concat inst " of " submod ".v"))
8797 submodi submoddecls)
8800 (setq submodi `primitive
8801 submoddecls (verilog-decls-new nil nil nil nil nil nil nil nil nil)
8802 comment (concat inst " of " submod))
8803 (verilog-backward-open-paren)
8804 (setq end-inst-point (save-excursion (verilog-forward-sexp-ign-cmt 1)
8808 (verilog-read-sub-decls-gate submoddecls comment submod end-inst-point))
8811 (when (setq submodi (verilog-modi-lookup submod t))
8812 (setq submoddecls (verilog-modi-get-decls submodi)
8813 verilog-read-sub-decls-gate-ios nil)
8814 (verilog-backward-open-paren)
8815 (setq end-inst-point (save-excursion (verilog-forward-sexp-ign-cmt 1)
8818 ;; This could have used a list created by verilog-auto-inst
8819 ;; However I want it to be runnable even on user's manually added signals
8820 (let ((verilog-read-sub-decls-in-interfaced t))
8821 (while (re-search-forward "\\s *(?\\s *// Interfaced" end-inst-point t)
8822 (verilog-read-sub-decls-line submoddecls comment))) ;; Modifies sigs-ifd
8823 (goto-char st-point)
8824 (while (re-search-forward "\\s *(?\\s *// Interfaces" end-inst-point t)
8825 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-out
8826 (goto-char st-point)
8827 (while (re-search-forward "\\s *(?\\s *// Outputs" end-inst-point t)
8828 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-out
8829 (goto-char st-point)
8830 (while (re-search-forward "\\s *(?\\s *// Inouts" end-inst-point t)
8831 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-inout
8832 (goto-char st-point)
8833 (while (re-search-forward "\\s *(?\\s *// Inputs" end-inst-point t)
8834 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-in
8836 ;; Combine duplicate bits
8837 ;;(setq rr (vector sigs-out sigs-inout sigs-in))
8838 (verilog-subdecls-new
8839 (verilog-signals-combine-bus (nreverse sigs-out))
8840 (verilog-signals-combine-bus (nreverse sigs-inout))
8841 (verilog-signals-combine-bus (nreverse sigs-in))
8842 (verilog-signals-combine-bus (nreverse sigs-intf))
8843 (verilog-signals-combine-bus (nreverse sigs-intfd))))))
8845 (defun verilog-read-inst-pins ()
8846 "Return an array of [ pins ] for the current instantiation at point.
8847 For example if declare A A (.B(SIG)) then B will be included in the list."
8849 (let ((end-mod-point (point)) ;; presume at /*AUTOINST*/ point
8851 (verilog-backward-open-paren)
8852 (while (re-search-forward "\\.\\([^(,) \t\n\f]*\\)\\s-*" end-mod-point t)
8853 (setq pin (match-string 1))
8854 (unless (verilog-inside-comment-or-string-p)
8855 (setq pins (cons (list pin) pins))
8856 (when (looking-at "(")
8857 (verilog-forward-sexp-ign-cmt 1))))
8860 (defun verilog-read-arg-pins ()
8861 "Return an array of [ pins ] for the current argument declaration at point."
8863 (let ((end-mod-point (point)) ;; presume at /*AUTOARG*/ point
8865 (verilog-backward-open-paren)
8866 (while (re-search-forward "\\([a-zA-Z0-9$_.%`]+\\)" end-mod-point t)
8867 (setq pin (match-string 1))
8868 (unless (verilog-inside-comment-or-string-p)
8869 (setq pins (cons (list pin) pins))))
8872 (defun verilog-read-auto-constants (beg end-mod-point)
8873 "Return a list of AUTO_CONSTANTs used in the region from BEG to END-MOD-POINT."
8876 (let (sig-list tpl-end-pt)
8878 (while (re-search-forward "\\<AUTO_CONSTANT" end-mod-point t)
8879 (if (not (looking-at "\\s *("))
8880 (error "%s: Missing () after AUTO_CONSTANT" (verilog-point-text)))
8881 (search-forward "(" end-mod-point)
8882 (setq tpl-end-pt (save-excursion
8884 (verilog-forward-sexp-cmt 1) ;; Moves to paren that closes argdecl's
8887 (while (re-search-forward "\\s-*\\([\"a-zA-Z0-9$_.%`]+\\)\\s-*,*" tpl-end-pt t)
8888 (setq sig-list (cons (list (match-string 1) nil nil) sig-list))))
8891 (defvar verilog-cache-has-lisp nil "True if any AUTO_LISP in buffer.")
8892 (make-variable-buffer-local 'verilog-cache-has-lisp)
8894 (defun verilog-read-auto-lisp-present ()
8895 "Set `verilog-cache-has-lisp' if any AUTO_LISP in this buffer."
8897 (goto-char (point-min))
8898 (setq verilog-cache-has-lisp (re-search-forward "\\<AUTO_LISP(" nil t))))
8900 (defun verilog-read-auto-lisp (start end)
8901 "Look for and evaluate an AUTO_LISP between START and END.
8902 Must call `verilog-read-auto-lisp-present' before this function."
8903 ;; This function is expensive for large buffers, so we cache if any AUTO_LISP exists
8904 (when verilog-cache-has-lisp
8907 (while (re-search-forward "\\<AUTO_LISP(" end t)
8909 (let* ((beg-pt (prog1 (point)
8910 (verilog-forward-sexp-cmt 1))) ;; Closing paren
8912 (verilog-in-hooks t))
8913 (eval-region beg-pt end-pt nil))))))
8915 (defun verilog-read-always-signals-recurse
8916 (exit-keywd rvalue temp-next)
8917 "Recursive routine for parentheses/bracket matching.
8918 EXIT-KEYWD is expression to stop at, nil if top level.
8919 RVALUE is true if at right hand side of equal.
8920 IGNORE-NEXT is true to ignore next token, fake from inside case statement."
8921 (let* ((semi-rvalue (equal "endcase" exit-keywd)) ;; true if after a ; we are looking for rvalue
8922 keywd last-keywd sig-tolk sig-last-tolk gotend got-sig got-list end-else-check
8924 ;;(if dbg (setq dbg (concat dbg (format "Recursion %S %S %S\n" exit-keywd rvalue temp-next))))
8925 (while (not (or (eobp) gotend))
8928 (search-forward "\n"))
8929 ((looking-at "/\\*")
8930 (or (search-forward "*/")
8931 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8932 ((looking-at "(\\*")
8933 ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
8935 (or (search-forward "*)")
8936 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
8937 (t (setq keywd (buffer-substring-no-properties
8939 (save-excursion (when (eq 0 (skip-chars-forward "a-zA-Z0-9$_.%`"))
8942 sig-last-tolk sig-tolk
8944 ;;(if dbg (setq dbg (concat dbg (format "\tPt=%S %S\trv=%S in=%S ee=%S gs=%S\n" (point) keywd rvalue ignore-next end-else-check got-sig))))
8947 (or (re-search-forward "[^\\]\"" nil t)
8948 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
8949 ;; else at top level loop, keep parsing
8950 ((and end-else-check (equal keywd "else"))
8951 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else %s\n" keywd))))
8952 ;; no forward movement, want to see else in lower loop
8953 (setq end-else-check nil))
8954 ;; End at top level loop
8955 ((and end-else-check (looking-at "[^ \t\n\f]"))
8956 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else-other %s\n" keywd))))
8959 ((and exit-keywd (equal keywd exit-keywd))
8961 (forward-char (length keywd)))
8962 ;; Standard tokens...
8964 (setq ignore-next nil rvalue semi-rvalue)
8965 ;; Final statement at top level loop?
8966 (when (not exit-keywd)
8967 ;;(if dbg (setq dbg (concat dbg (format "\ttop-end-check %s\n" keywd))))
8968 (setq end-else-check t))
8971 (if (looking-at "'[sS]?[hdxboHDXBO]?[ \t]*[0-9a-fA-F_xzXZ?]+")
8972 (goto-char (match-end 0))
8974 ((equal keywd ":") ;; Case statement, begin/end label, x?y:z
8975 (cond ((equal "endcase" exit-keywd) ;; case x: y=z; statement next
8976 (setq ignore-next nil rvalue nil))
8977 ((equal "?" exit-keywd) ;; x?y:z rvalue
8979 ((equal "]" exit-keywd) ;; [x:y] rvalue
8981 (got-sig ;; label: statement
8982 (setq ignore-next nil rvalue semi-rvalue got-sig nil))
8983 ((not rvalue) ;; begin label
8984 (setq ignore-next t rvalue nil)))
8988 ;;(if dbg (setq dbg (concat dbg (format "\t\tequal got-sig=%S got-list=%s\n" got-sig got-list))))
8989 (set got-list (cons got-sig (symbol-value got-list)))
8992 (if (eq (char-before) ?< )
8993 (setq sigs-out-d (append sigs-out-d sigs-out-unk)
8995 (setq sigs-out-i (append sigs-out-i sigs-out-unk)
8997 (setq ignore-next nil rvalue t)
9001 (verilog-read-always-signals-recurse ":" rvalue nil))
9004 (verilog-read-always-signals-recurse "]" t nil))
9007 (cond (sig-last-tolk ;; Function call; zap last signal
9008 (setq got-sig nil)))
9009 (cond ((equal last-keywd "for")
9010 ;; temp-next: Variables on LHS are lvalues, but generally we want
9011 ;; to ignore them, assuming they are loop increments
9012 (verilog-read-always-signals-recurse ";" nil t)
9013 (verilog-read-always-signals-recurse ";" t nil)
9014 (verilog-read-always-signals-recurse ")" nil nil))
9015 (t (verilog-read-always-signals-recurse ")" t nil))))
9016 ((equal keywd "begin")
9017 (skip-syntax-forward "w_")
9018 (verilog-read-always-signals-recurse "end" nil nil)
9019 ;;(if dbg (setq dbg (concat dbg (format "\tgot-end %s\n" exit-keywd))))
9020 (setq ignore-next nil rvalue semi-rvalue)
9021 (if (not exit-keywd) (setq end-else-check t)))
9022 ((member keywd '("case" "casex" "casez"))
9023 (skip-syntax-forward "w_")
9024 (verilog-read-always-signals-recurse "endcase" t nil)
9025 (setq ignore-next nil rvalue semi-rvalue)
9026 (if (not exit-keywd) (setq gotend t))) ;; top level begin/end
9027 ((string-match "^[$`a-zA-Z_]" keywd) ;; not exactly word constituent
9028 (cond ((member keywd '("`ifdef" "`ifndef" "`elsif"))
9029 (setq ignore-next t))
9031 (member keywd verilog-keywords)
9032 (string-match "^\\$" keywd)) ;; PLI task
9033 (setq ignore-next nil))
9035 (setq keywd (verilog-symbol-detick-denumber keywd))
9037 (set got-list (cons got-sig (symbol-value got-list)))
9038 ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S got-list=%S\n" got-sig got-list))))
9040 (setq got-list (cond (temp-next 'sigs-temp)
9043 got-sig (if (or (not keywd)
9044 (assoc keywd (symbol-value got-list)))
9045 nil (list keywd nil nil))
9048 (skip-chars-forward "a-zA-Z0-9$_.%`"))
9051 ;; End of non-comment token
9052 (setq last-keywd keywd)))
9053 (skip-syntax-forward " "))
9054 ;; Append the final pending signal
9056 ;;(if dbg (setq dbg (concat dbg (format "\t\tfinal got-sig=%S got-list=%s\n" got-sig got-list))))
9057 (set got-list (cons got-sig (symbol-value got-list)))
9059 ;;(if dbg (setq dbg (concat dbg (format "ENDRecursion %s\n" exit-keywd))))
9062 (defun verilog-read-always-signals ()
9063 "Parse always block at point and return list of (outputs inout inputs)."
9066 sigs-out-d sigs-out-i sigs-out-unk sigs-temp sigs-in)
9067 (verilog-read-always-signals-recurse nil nil nil)
9068 (setq sigs-out-i (append sigs-out-i sigs-out-unk)
9070 ;;(if dbg (with-current-buffer (get-buffer-create "*vl-dbg*")) (delete-region (point-min) (point-max)) (insert dbg) (setq dbg ""))
9071 ;; Return what was found
9072 (verilog-alw-new sigs-out-d sigs-out-i sigs-temp sigs-in))))
9074 (defun verilog-read-instants ()
9075 "Parse module at point and return list of ( ( file instance ) ... )."
9076 (verilog-beg-of-defun-quick)
9077 (let* ((end-mod-point (verilog-get-end-of-defun))
9079 (instants-list nil))
9081 (while (< (point) end-mod-point)
9082 ;; Stay at level 0, no comments
9084 (setq state (parse-partial-sexp (point) end-mod-point 0 t nil))
9085 (or (> (car state) 0) ; in parens
9086 (nth 5 state) ; comment
9090 (if (looking-at "^\\s-*\\([a-zA-Z0-9`_$]+\\)\\s-+\\([a-zA-Z0-9`_$]+\\)\\s-*(")
9091 ;;(if (looking-at "^\\(.+\\)$")
9092 (let ((module (match-string 1))
9093 (instant (match-string 2)))
9094 (if (not (member module verilog-keywords))
9095 (setq instants-list (cons (list module instant) instants-list)))))
9100 (defun verilog-read-auto-template-middle ()
9101 "With point in middle of an AUTO_TEMPLATE, parse it.
9102 Returns REGEXP and list of ( (signal_name connection_name)... )."
9105 (let ((tpl-regexp "\\([0-9]+\\)")
9106 (lineno -1) ; -1 to offset for the AUTO_TEMPLATE's newline
9108 tpl-sig-list tpl-wild-list tpl-end-pt rep)
9110 ;; We reserve @"..." for future lisp expressions that evaluate
9111 ;; once-per-AUTOINST
9112 (when (looking-at "\\s-*\"\\([^\"]*\\)\"")
9113 (setq tpl-regexp (match-string 1))
9114 (goto-char (match-end 0)))
9115 (search-forward "(")
9116 ;; Parse lines in the template
9117 (when (or verilog-auto-inst-template-numbers
9118 verilog-auto-template-warn-unused)
9120 (let ((pre-pt (point)))
9121 (goto-char (point-min))
9122 (while (search-forward "AUTO_TEMPLATE" pre-pt t)
9123 (setq templateno (1+ templateno)))
9124 (while (< (point) pre-pt)
9126 (setq lineno (1+ lineno))))))
9127 (setq tpl-end-pt (save-excursion
9129 (verilog-forward-sexp-cmt 1) ;; Moves to paren that closes argdecl's
9133 (while (< (point) tpl-end-pt)
9134 (cond ((looking-at "\\s-*\\.\\([a-zA-Z0-9`_$]+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
9137 (match-string-no-properties 1)
9138 (match-string-no-properties 2)
9141 (goto-char (match-end 0)))
9144 ;; Regexp bug in XEmacs disallows ][ inside [], and wants + last
9145 "\\s-*\\.\\(\\([a-zA-Z0-9`_$+@^.*?|---]+\\|[][]\\|\\\\[()|]\\)+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
9146 (setq rep (match-string-no-properties 3))
9147 (goto-char (match-end 0))
9151 (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil
9157 ((looking-at "[ \t\f]+")
9158 (goto-char (match-end 0)))
9160 (setq lineno (1+ lineno))
9161 (goto-char (match-end 0)))
9163 (search-forward "\n")
9164 (setq lineno (1+ lineno)))
9165 ((looking-at "/\\*")
9167 (or (search-forward "*/")
9168 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
9170 (error "%s: AUTO_TEMPLATE parsing error: %s"
9171 (verilog-point-text)
9172 (progn (looking-at ".*$") (match-string 0))))))
9175 (list tpl-sig-list tpl-wild-list)))))
9177 (defun verilog-read-auto-template (module)
9178 "Look for an auto_template for the instantiation of the given MODULE.
9179 If found returns `verilog-read-auto-template-inside' structure."
9183 ;; Note this search is expensive, as we hunt from mod-begin to point
9184 ;; for every instantiation. Likewise in verilog-read-auto-lisp.
9185 ;; So, we look first for an exact string rather than a slow regexp.
9186 ;; Someday we may keep a cache of every template, but this would also
9187 ;; need to record the relative position of each AUTOINST, as multiple
9188 ;; templates exist for each module, and we're inserting lines.
9190 ;; See also regexp in `verilog-auto-template-lint'
9191 (verilog-re-search-backward-substr
9193 (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)
9194 ;; Also try forward of this AUTOINST
9195 ;; This is for historical support; this isn't speced as working
9198 (verilog-re-search-forward-substr
9200 (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)))
9201 (goto-char (match-end 0))
9202 (verilog-read-auto-template-middle))
9203 ;; If no template found
9204 (t (vector "" nil))))))
9205 ;;(progn (find-file "auto-template.v") (verilog-read-auto-template "ptl_entry"))
9207 (defvar verilog-auto-template-hits nil "Successful lookups with `verilog-read-auto-template-hit'.")
9208 (make-variable-buffer-local 'verilog-auto-template-hits)
9210 (defun verilog-read-auto-template-hit (tpl-ass)
9211 "Record that TPL-ASS template from `verilog-read-auto-template' was used."
9212 (when (eval-when-compile (fboundp 'make-hash-table)) ;; else feature not allowed
9213 (when verilog-auto-template-warn-unused
9214 (unless verilog-auto-template-hits
9215 (setq verilog-auto-template-hits
9216 (make-hash-table :test 'equal :rehash-size 4.0)))
9217 (puthash (vector (nth 2 tpl-ass) (nth 3 tpl-ass)) t
9218 verilog-auto-template-hits))))
9220 (defun verilog-set-define (defname defvalue &optional buffer enumname)
9221 "Set the definition DEFNAME to the DEFVALUE in the given BUFFER.
9222 Optionally associate it with the specified enumeration ENUMNAME."
9223 (with-current-buffer (or buffer (current-buffer))
9224 ;; Namespace intentionally short for AUTOs and compatibility
9225 (let ((mac (intern (concat "vh-" defname))))
9226 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
9227 ;; Need to define to a constant if no value given
9228 (set (make-local-variable mac)
9229 (if (equal defvalue "") "1" defvalue)))
9231 ;; Namespace intentionally short for AUTOs and compatibility
9232 (let ((enumvar (intern (concat "venum-" enumname))))
9233 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
9234 (unless (boundp enumvar) (set enumvar nil))
9235 (add-to-list (make-local-variable enumvar) defname)))))
9237 (defun verilog-read-defines (&optional filename recurse subcall)
9238 "Read \\=`defines and parameters for the current file, or optional FILENAME.
9239 If the filename is provided, `verilog-library-flags' will be used to
9240 resolve it. If optional RECURSE is non-nil, recurse through \\=`includes.
9242 Parameters must be simple assignments to constants, or have their own
9243 \"parameter\" label rather than a list of parameters. Thus:
9245 parameter X = 5, Y = 10; // Ok
9246 parameter X = {1'b1, 2'h2}; // Ok
9247 parameter X = {1'b1, 2'h2}, Y = 10; // Bad, make into 2 parameter lines
9249 Defines must be simple text substitutions, one on a line, starting
9250 at the beginning of the line. Any ifdefs or multiline comments around the
9253 Defines are stored inside Emacs variables using the name vh-{definename}.
9255 This function is useful for setting vh-* variables. The file variables
9256 feature can be used to set defines that `verilog-mode' can see; put at the
9257 *END* of your file something like:
9260 // vh-macro:\"macro_definition\"
9263 If macros are defined earlier in the same file and you want their values,
9264 you can read them automatically (provided `enable-local-eval' is on):
9267 // eval:(verilog-read-defines)
9268 // eval:(verilog-read-defines \"group_standard_includes.v\")
9271 Note these are only read when the file is first visited, you must use
9272 \\[find-alternate-file] RET to have these take effect after editing them!
9274 If you want to disable the \"Process `eval' or hook local variables\"
9275 warning message, you need to add to your init file:
9277 (setq enable-local-eval t)"
9278 (let ((origbuf (current-buffer)))
9280 (unless subcall (verilog-getopt-flags))
9282 (let ((fns (verilog-library-filenames filename (buffer-file-name))))
9284 (set-buffer (find-file-noselect (car fns)))
9285 (error (concat (verilog-point-text)
9286 ": Can't find verilog-read-defines file: " filename)))))
9288 (goto-char (point-min))
9289 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
9290 (let ((inc (verilog-string-replace-matches
9291 "\"" "" nil nil (match-string-no-properties 1))))
9292 (unless (verilog-inside-comment-or-string-p)
9293 (verilog-read-defines inc recurse t)))))
9295 ;; note we don't use verilog-re... it's faster this way, and that
9296 ;; function has problems when comments are at the end of the define
9297 (goto-char (point-min))
9298 (while (re-search-forward "^\\s-*`define\\s-+\\([a-zA-Z0-9_$]+\\)\\s-+\\(.*\\)$" nil t)
9299 (let ((defname (match-string-no-properties 1))
9300 (defvalue (match-string-no-properties 2)))
9301 (unless (verilog-inside-comment-or-string-p (match-beginning 0))
9302 (setq defvalue (verilog-string-replace-matches "\\s-*/[/*].*$" "" nil nil defvalue))
9303 (verilog-set-define defname defvalue origbuf))))
9304 ;; Hack: Read parameters
9305 (goto-char (point-min))
9306 (while (re-search-forward
9307 "^\\s-*\\(parameter\\|localparam\\)\\(\\s-*\\[[^]]*\\]\\)?\\s-*" nil t)
9309 ;; The primary way of getting defines is verilog-read-decls
9310 ;; However, that isn't called yet for included files, so we'll add another scheme
9311 (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
9312 (setq enumname (match-string-no-properties 2)))
9313 (forward-comment 99999)
9314 (while (looking-at (concat "\\s-*,?\\s-*\\(?:/[/*].*?$\\)?\\s-*\\([a-zA-Z0-9_$]+\\)"
9315 "\\s-*=\\s-*\\([^;,]*\\),?\\s-*\\(/[/*].*?$\\)?\\s-*"))
9316 (unless (verilog-inside-comment-or-string-p (match-beginning 0))
9317 (verilog-set-define (match-string-no-properties 1)
9318 (match-string-no-properties 2) origbuf enumname))
9319 (goto-char (match-end 0))
9320 (forward-comment 99999)))))))
9322 (defun verilog-read-includes ()
9323 "Read \\=`includes for the current file.
9324 This will find all of the \\=`includes which are at the beginning of lines,
9325 ignoring any ifdefs or multiline comments around them.
9326 `verilog-read-defines' is then performed on the current and each included
9329 It is often useful put at the *END* of your file something like:
9332 // eval:(verilog-read-defines)
9333 // eval:(verilog-read-includes)
9336 Note includes are only read when the file is first visited, you must use
9337 \\[find-alternate-file] RET to have these take effect after editing them!
9339 It is good to get in the habit of including all needed files in each .v
9340 file that needs it, rather than waiting for compile time. This will aid
9341 this process, Verilint, and readability. To prevent defining the same
9342 variable over and over when many modules are compiled together, put a test
9343 around the inside each include file:
9345 foo.v (an include file):
9346 \\=`ifdef _FOO_V // include if not already included
9349 ... contents of file
9350 \\=`endif // _FOO_V"
9351 ;;slow: (verilog-read-defines nil t)
9353 (verilog-getopt-flags)
9354 (goto-char (point-min))
9355 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
9356 (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string 1))))
9357 (verilog-read-defines inc nil t)))))
9359 (defun verilog-read-signals (&optional start end)
9360 "Return a simple list of all possible signals in the file.
9361 Bounded by optional region from START to END. Overly aggressive but fast.
9362 Some macros and such are also found and included. For dinotrace.el."
9363 (let (sigs-all keywd)
9364 (progn;save-excursion
9365 (goto-char (or start (point-min)))
9366 (setq end (or end (point-max)))
9367 (while (re-search-forward "[\"/a-zA-Z_.%`]" end t)
9371 (search-forward "\n"))
9372 ((looking-at "/\\*")
9373 (search-forward "*/"))
9374 ((looking-at "(\\*")
9375 (or (looking-at "(\\*\\s-*)") ; It's a "always @ (*)"
9376 (search-forward "*)")))
9377 ((eq ?\" (following-char))
9378 (re-search-forward "[^\\]\"")) ;; don't forward-char first, since we look for a non backslash first
9379 ((looking-at "\\s-*\\([a-zA-Z0-9$_.%`]+\\)")
9380 (goto-char (match-end 0))
9381 (setq keywd (match-string-no-properties 1))
9382 (or (member keywd verilog-keywords)
9383 (member keywd sigs-all)
9384 (setq sigs-all (cons keywd sigs-all))))
9385 (t (forward-char 1))))
9390 ;; Argument file parsing
9393 (defun verilog-getopt (arglist)
9394 "Parse -f, -v etc arguments in ARGLIST list or string."
9395 (unless (listp arglist) (setq arglist (list arglist)))
9396 (let ((space-args '())
9398 ;; Split on spaces, so users can pass whole command lines
9400 (setq arg (car arglist)
9401 arglist (cdr arglist))
9402 (while (string-match "^\\([^ \t\n\f]+\\)[ \t\n\f]*\\(.*$\\)" arg)
9403 (setq space-args (append space-args
9404 (list (match-string-no-properties 1 arg))))
9405 (setq arg (match-string 2 arg))))
9408 (setq arg (car space-args)
9409 space-args (cdr space-args))
9413 (setq next-param arg))
9415 (setq next-param arg))
9417 (setq next-param arg))
9418 ;; +libext+(ext1)+(ext2)...
9419 ((string-match "^\\+libext\\+\\(.*\\)" arg)
9420 (setq arg (match-string 1 arg))
9421 (while (string-match "\\([^+]+\\)\\+?\\(.*\\)" arg)
9422 (verilog-add-list-unique `verilog-library-extensions
9423 (match-string 1 arg))
9424 (setq arg (match-string 2 arg))))
9426 ((or (string-match "^-D\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; -Ddefine=val
9427 (string-match "^-D\\([^+=]*\\)\\(\\)" arg) ;; -Ddefine
9428 (string-match "^\\+define\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; +define+val
9429 (string-match "^\\+define\\([^+=]*\\)\\(\\)" arg)) ;; +define+define
9430 (verilog-set-define (match-string 1 arg) (match-string 2 arg)))
9432 ((or (string-match "^\\+incdir\\+\\(.*\\)" arg) ;; +incdir+dir
9433 (string-match "^-I\\(.*\\)" arg)) ;; -Idir
9434 (verilog-add-list-unique `verilog-library-directories
9435 (match-string 1 (substitute-in-file-name arg))))
9437 ((equal "+librescan" arg))
9438 ((string-match "^-U\\(.*\\)" arg)) ;; -Udefine
9439 ;; Second parameters
9440 ((equal next-param "-f")
9441 (setq next-param nil)
9442 (verilog-getopt-file (substitute-in-file-name arg)))
9443 ((equal next-param "-v")
9444 (setq next-param nil)
9445 (verilog-add-list-unique `verilog-library-files
9446 (substitute-in-file-name arg)))
9447 ((equal next-param "-y")
9448 (setq next-param nil)
9449 (verilog-add-list-unique `verilog-library-directories
9450 (substitute-in-file-name arg)))
9452 ((string-match "^[^-+]" arg)
9453 (verilog-add-list-unique `verilog-library-files
9454 (substitute-in-file-name arg)))
9455 ;; Default - ignore; no warning
9457 ;;(verilog-getopt (list "+libext+.a+.b" "+incdir+foodir" "+define+a+aval" "-f" "otherf" "-v" "library" "-y" "dir"))
9459 (defun verilog-getopt-file (filename)
9460 "Read Verilog options from the specified FILENAME."
9462 (let ((fns (verilog-library-filenames filename (buffer-file-name)))
9463 (orig-buffer (current-buffer))
9466 (set-buffer (find-file-noselect (car fns)))
9467 (error (concat (verilog-point-text)
9468 ": Can't find verilog-getopt-file -f file: " filename)))
9469 (goto-char (point-min))
9471 (setq line (buffer-substring (point) (point-at-eol)))
9473 (when (string-match "//" line)
9474 (setq line (substring line 0 (match-beginning 0))))
9475 (with-current-buffer orig-buffer ; Variables are buffer-local, so need right context.
9476 (verilog-getopt line))))))
9478 (defun verilog-getopt-flags ()
9479 "Convert `verilog-library-flags' into standard library variables."
9480 ;; If the flags are local, then all the outputs should be local also
9481 (when (local-variable-p `verilog-library-flags (current-buffer))
9482 (mapc 'make-local-variable '(verilog-library-extensions
9483 verilog-library-directories
9484 verilog-library-files
9485 verilog-library-flags)))
9486 ;; Allow user to customize
9487 (verilog-run-hooks 'verilog-before-getopt-flags-hook)
9488 ;; Process arguments
9489 (verilog-getopt verilog-library-flags)
9490 ;; Allow user to customize
9491 (verilog-run-hooks 'verilog-getopt-flags-hook))
9493 (defun verilog-add-list-unique (varref object)
9494 "Append to VARREF list the given OBJECT,
9495 unless it is already a member of the variable's list."
9496 (unless (member object (symbol-value varref))
9497 (set varref (append (symbol-value varref) (list object))))
9499 ;;(progn (setq l '()) (verilog-add-list-unique `l "a") (verilog-add-list-unique `l "a") l)
9501 (defun verilog-current-flags ()
9502 "Convert `verilog-library-flags' and similar variables to command line.
9503 Used for __FLAGS__ in `verilog-expand-command'."
9504 (let ((cmd (mapconcat `concat verilog-library-flags " ")))
9505 (when (equal cmd "")
9507 "+libext+" (mapconcat `concat verilog-library-extensions "+")
9508 (mapconcat (lambda (i) (concat " -y " i " +incdir+" i))
9509 verilog-library-directories "")
9510 (mapconcat (lambda (i) (concat " -v " i))
9511 verilog-library-files ""))))
9513 ;;(verilog-current-flags)
9517 ;; Cached directory support
9520 (defvar verilog-dir-cache-preserving nil
9521 "If true, the directory cache is enabled, and file system changes are ignored.
9522 See `verilog-dir-exists-p' and `verilog-dir-files'.")
9524 ;; If adding new cached variable, add also to verilog-preserve-dir-cache
9525 (defvar verilog-dir-cache-list nil
9526 "Alist of (((Cwd Dirname) Results)...) for caching `verilog-dir-files'.")
9527 (defvar verilog-dir-cache-lib-filenames nil
9528 "Cached data for `verilog-library-filenames'.")
9530 (defmacro verilog-preserve-dir-cache (&rest body)
9531 "Execute the BODY forms, allowing directory cache preservation within BODY.
9532 This means that changes inside BODY made to the file system will not be
9533 seen by the `verilog-dir-files' and related functions."
9534 `(let ((verilog-dir-cache-preserving (current-buffer))
9535 verilog-dir-cache-list
9536 verilog-dir-cache-lib-filenames)
9539 (defun verilog-dir-files (dirname)
9540 "Return all filenames in the DIRNAME directory.
9541 Relative paths depend on the `default-directory'.
9542 Results are cached if inside `verilog-preserve-dir-cache'."
9543 (unless verilog-dir-cache-preserving
9544 (setq verilog-dir-cache-list nil)) ;; Cache disabled
9545 ;; We don't use expand-file-name on the dirname to make key, as it's slow
9546 (let* ((cache-key (list dirname default-directory))
9547 (fass (assoc cache-key verilog-dir-cache-list))
9549 (cond (fass ;; Return data from cache hit
9552 (setq exp-dirname (expand-file-name dirname)
9553 data (and (file-directory-p exp-dirname)
9554 (directory-files exp-dirname nil nil nil)))
9555 ;; Note we also encache nil for non-existing dirs.
9556 (setq verilog-dir-cache-list (cons (list cache-key data)
9557 verilog-dir-cache-list))
9559 ;; Miss-and-hit test:
9560 ;;(verilog-preserve-dir-cache (prin1 (verilog-dir-files "."))
9561 ;; (prin1 (verilog-dir-files ".")) nil)
9563 (defun verilog-dir-file-exists-p (filename)
9564 "Return true if FILENAME exists.
9565 Like `file-exists-p' but results are cached if inside
9566 `verilog-preserve-dir-cache'."
9567 (let* ((dirname (file-name-directory filename))
9568 ;; Correct for file-name-nondirectory returning same if no slash.
9569 (dirnamed (if (or (not dirname) (equal dirname filename))
9570 default-directory dirname))
9571 (flist (verilog-dir-files dirnamed)))
9573 (member (file-name-nondirectory filename) flist)
9575 ;;(verilog-dir-file-exists-p "verilog-mode.el")
9576 ;;(verilog-dir-file-exists-p "../verilog-mode/verilog-mode.el")
9580 ;; Module name lookup
9583 (defun verilog-module-inside-filename-p (module filename)
9584 "Return modi if MODULE is specified inside FILENAME, else nil.
9585 Allows version control to check out the file if need be."
9586 (and (or (file-exists-p filename)
9587 (and (fboundp 'vc-backend)
9588 (vc-backend filename)))
9590 (with-current-buffer (find-file-noselect filename)
9592 (goto-char (point-min))
9594 ;; It may be tempting to look for verilog-defun-re,
9595 ;; don't, it slows things down a lot!
9596 (verilog-re-search-forward-quick "\\<\\(module\\|interface\\|program\\)\\>" nil t)
9597 (setq type (match-string-no-properties 0))
9598 (verilog-re-search-forward-quick "[(;]" nil t))
9599 (if (equal module (verilog-read-module-name))
9600 (setq modi (verilog-modi-new module filename (point) type))))
9603 (defun verilog-is-number (symbol)
9604 "Return true if SYMBOL is number-like."
9605 (or (string-match "^[0-9 \t:]+$" symbol)
9606 (string-match "^[---]*[0-9]+$" symbol)
9607 (string-match "^[0-9 \t]+'s?[hdxbo][0-9a-fA-F_xz? \t]*$" symbol)))
9609 (defun verilog-symbol-detick (symbol wing-it)
9610 "Return an expanded SYMBOL name without any defines.
9611 If the variable vh-{symbol} is defined, return that value.
9612 If undefined, and WING-IT, return just SYMBOL without the tick, else nil."
9613 (while (and symbol (string-match "^`" symbol))
9614 (setq symbol (substring symbol 1))
9616 ;; Namespace intentionally short for AUTOs and compatibility
9617 (if (boundp (intern (concat "vh-" symbol)))
9618 ;; Emacs has a bug where boundp on a buffer-local
9619 ;; variable in only one buffer returns t in another.
9620 ;; This can confuse, so check for nil.
9621 ;; Namespace intentionally short for AUTOs and compatibility
9622 (let ((val (eval (intern (concat "vh-" symbol)))))
9624 (if wing-it symbol nil)
9626 (if wing-it symbol nil))))
9628 ;;(verilog-symbol-detick "`mod" nil)
9630 (defun verilog-symbol-detick-denumber (symbol)
9631 "Return SYMBOL with defines converted and any numbers dropped to nil."
9632 (when (string-match "^`" symbol)
9633 ;; This only will work if the define is a simple signal, not
9634 ;; something like a[b]. Sorry, it should be substituted into the parser
9636 (verilog-string-replace-matches
9637 "\[[^0-9: \t]+\]" "" nil nil
9638 (or (verilog-symbol-detick symbol nil)
9639 (if verilog-auto-sense-defines-constant
9642 (if (verilog-is-number symbol)
9646 (defun verilog-symbol-detick-text (text)
9647 "Return TEXT without any known defines.
9648 If the variable vh-{symbol} is defined, substitute that value."
9649 (let ((ok t) symbol val)
9650 (while (and ok (string-match "`\\([a-zA-Z0-9_]+\\)" text))
9651 (setq symbol (match-string 1 text))
9654 ;; Namespace intentionally short for AUTOs and compatibility
9655 (boundp (intern (concat "vh-" symbol)))
9656 ;; Emacs has a bug where boundp on a buffer-local
9657 ;; variable in only one buffer returns t in another.
9658 ;; This can confuse, so check for nil.
9659 ;; Namespace intentionally short for AUTOs and compatibility
9660 (setq val (eval (intern (concat "vh-" symbol)))))
9661 (setq text (replace-match val nil nil text)))
9662 (t (setq ok nil)))))
9664 ;;(progn (setq vh-mod "`foo" vh-foo "bar") (verilog-symbol-detick-text "bar `mod `undefed"))
9666 (defun verilog-expand-dirnames (&optional dirnames)
9667 "Return a list of existing directories given a list of wildcarded DIRNAMES.
9668 Or, just the existing dirnames themselves if there are no wildcards."
9669 ;; Note this function is performance critical.
9670 ;; Do not call anything that requires disk access that cannot be cached.
9672 (unless dirnames (error "`verilog-library-directories' should include at least '.'"))
9673 (setq dirnames (reverse dirnames)) ; not nreverse
9675 pattern dirfile dirfiles dirname root filename rest basefile)
9677 (setq dirname (substitute-in-file-name (car dirnames))
9678 dirnames (cdr dirnames))
9679 (cond ((string-match (concat "^\\(\\|[/\\]*[^*?]*[/\\]\\)" ;; root
9680 "\\([^/\\]*[*?][^/\\]*\\)" ;; filename with *?
9683 (setq root (match-string 1 dirname)
9684 filename (match-string 2 dirname)
9685 rest (match-string 3 dirname)
9687 ;; now replace those * and ? with .+ and .
9688 ;; use ^ and /> to get only whole file names
9689 (setq pattern (verilog-string-replace-matches "[*]" ".+" nil nil pattern)
9690 pattern (verilog-string-replace-matches "[?]" "." nil nil pattern)
9691 pattern (concat "^" pattern "$")
9692 dirfiles (verilog-dir-files root))
9694 (setq basefile (car dirfiles)
9695 dirfile (expand-file-name (concat root basefile rest))
9696 dirfiles (cdr dirfiles))
9697 (if (and (string-match pattern basefile)
9698 ;; Don't allow abc/*/rtl to match abc/rtl via ..
9699 (not (equal basefile "."))
9700 (not (equal basefile ".."))
9701 (file-directory-p dirfile))
9702 (setq dirlist (cons dirfile dirlist)))))
9705 (if (file-directory-p dirname)
9706 (setq dirlist (cons dirname dirlist))))))
9708 ;;(verilog-expand-dirnames (list "." ".." "nonexist" "../*" "/home/wsnyder/*/v"))
9710 (defun verilog-library-filenames (filename &optional current check-ext)
9711 "Return a search path to find the given FILENAME or module name.
9712 Uses the optional CURRENT filename or variable `buffer-file-name', plus
9713 `verilog-library-directories' and `verilog-library-extensions'
9714 variables to build the path. With optional CHECK-EXT also check
9715 `verilog-library-extensions'."
9716 (unless current (setq current (buffer-file-name)))
9717 (unless verilog-dir-cache-preserving
9718 (setq verilog-dir-cache-lib-filenames nil))
9719 (let* ((cache-key (list filename current check-ext))
9720 (fass (assoc cache-key verilog-dir-cache-lib-filenames))
9721 chkdirs chkdir chkexts fn outlist)
9722 (cond (fass ;; Return data from cache hit
9725 ;; Note this expand can't be easily cached, as we need to
9726 ;; pick up buffer-local variables for newly read sub-module files
9727 (setq chkdirs (verilog-expand-dirnames verilog-library-directories))
9729 (setq chkdir (expand-file-name (car chkdirs)
9730 (file-name-directory current))
9731 chkexts (if check-ext verilog-library-extensions `("")))
9733 (setq fn (expand-file-name (concat filename (car chkexts))
9735 ;;(message "Check for %s" fn)
9736 (if (verilog-dir-file-exists-p fn)
9737 (setq outlist (cons (expand-file-name
9738 fn (file-name-directory current))
9740 (setq chkexts (cdr chkexts)))
9741 (setq chkdirs (cdr chkdirs)))
9742 (setq outlist (nreverse outlist))
9743 (setq verilog-dir-cache-lib-filenames
9744 (cons (list cache-key outlist)
9745 verilog-dir-cache-lib-filenames))
9748 (defun verilog-module-filenames (module current)
9749 "Return a search path to find the given MODULE name.
9750 Uses the CURRENT filename, `verilog-library-extensions',
9751 `verilog-library-directories' and `verilog-library-files'
9752 variables to build the path."
9753 ;; Return search locations for it
9754 (append (list current) ; first, current buffer
9755 (verilog-library-filenames module current t)
9756 verilog-library-files)) ; finally, any libraries
9759 ;; Module Information
9761 ;; Many of these functions work on "modi" a module information structure
9762 ;; A modi is: [module-name-string file-name begin-point]
9764 (defvar verilog-cache-enabled t
9765 "Non-nil enables caching of signals, etc. Set to nil for debugging to make things SLOW!")
9767 (defvar verilog-modi-cache-list nil
9768 "Cache of ((Module Function) Buf-Tick Buf-Modtime Func-Returns)...
9769 For speeding up verilog-modi-get-* commands.
9771 (make-variable-buffer-local 'verilog-modi-cache-list)
9773 (defvar verilog-modi-cache-preserve-tick nil
9774 "Modification tick after which the cache is still considered valid.
9775 Use `verilog-preserve-modi-cache' to set it.")
9776 (defvar verilog-modi-cache-preserve-buffer nil
9777 "Modification tick after which the cache is still considered valid.
9778 Use `verilog-preserve-modi-cache' to set it.")
9779 (defvar verilog-modi-cache-current-enable nil
9780 "Non-nil means allow caching `verilog-modi-current', set by let().")
9781 (defvar verilog-modi-cache-current nil
9782 "Currently active `verilog-modi-current', if any, set by let().")
9783 (defvar verilog-modi-cache-current-max nil
9784 "Current endmodule point for `verilog-modi-cache-current', if any.")
9786 (defun verilog-modi-current ()
9787 "Return the modi structure for the module currently at point, possibly cached."
9788 (cond ((and verilog-modi-cache-current
9789 (>= (point) (verilog-modi-get-point verilog-modi-cache-current))
9790 (<= (point) verilog-modi-cache-current-max))
9791 ;; Slow assertion, for debugging the cache:
9792 ;;(or (equal verilog-modi-cache-current (verilog-modi-current-get)) (debug))
9793 verilog-modi-cache-current)
9794 (verilog-modi-cache-current-enable
9795 (setq verilog-modi-cache-current (verilog-modi-current-get)
9796 verilog-modi-cache-current-max
9797 ;; The cache expires when we pass "endmodule" as then the
9798 ;; current modi may change to the next module
9799 ;; This relies on the AUTOs generally inserting, not deleting text
9801 (verilog-re-search-forward-quick verilog-end-defun-re nil nil)))
9802 verilog-modi-cache-current)
9804 (verilog-modi-current-get))))
9806 (defun verilog-modi-current-get ()
9807 "Return the modi structure for the module currently at point."
9808 (let* (name type pt)
9809 ;; read current module's name
9811 (verilog-re-search-backward-quick verilog-defun-re nil nil)
9812 (setq type (match-string-no-properties 0))
9813 (verilog-re-search-forward-quick "(" nil nil)
9814 (setq name (verilog-read-module-name))
9816 ;; return modi - note this vector built two places
9817 (verilog-modi-new name (or (buffer-file-name) (current-buffer)) pt type)))
9819 (defvar verilog-modi-lookup-cache nil "Hash of (modulename modi).")
9820 (make-variable-buffer-local 'verilog-modi-lookup-cache)
9821 (defvar verilog-modi-lookup-last-current nil "Cache of `current-buffer' at last lookup.")
9822 (defvar verilog-modi-lookup-last-tick nil "Cache of `buffer-chars-modified-tick' at last lookup.")
9824 (defun verilog-modi-lookup (module allow-cache &optional ignore-error)
9825 "Find the file and point at which MODULE is defined.
9826 If ALLOW-CACHE is set, check and remember cache of previous lookups.
9827 Return modi if successful, else print message unless IGNORE-ERROR is true."
9828 (let* ((current (or (buffer-file-name) (current-buffer)))
9831 ;;(message "verilog-modi-lookup: %s" module)
9832 (cond ((and verilog-modi-lookup-cache
9833 verilog-cache-enabled
9835 (setq modi (gethash module verilog-modi-lookup-cache))
9836 (equal verilog-modi-lookup-last-current current)
9837 ;; If hit is in current buffer, then tick must match
9838 (or (equal verilog-modi-lookup-last-tick (buffer-chars-modified-tick))
9839 (not (equal current (verilog-modi-file-or-buffer modi)))))
9840 ;;(message "verilog-modi-lookup: HIT %S" modi)
9843 (t (let* ((realname (verilog-symbol-detick module t))
9844 (orig-filenames (verilog-module-filenames realname current))
9845 (filenames orig-filenames)
9847 (while (and filenames (not mif))
9848 (if (not (setq mif (verilog-module-inside-filename-p realname (car filenames))))
9849 (setq filenames (cdr filenames))))
9850 ;; mif has correct form to become later elements of modi
9851 (cond (mif (setq modi mif))
9854 (error (concat (verilog-point-text)
9855 ": Can't locate " module " module definition"
9856 (if (not (equal module realname))
9857 (concat " (Expanded macro to " realname ")")
9859 "\n Check the verilog-library-directories variable."
9860 "\n I looked in (if not listed, doesn't exist):\n\t"
9861 (mapconcat 'concat orig-filenames "\n\t"))))))
9862 (when (eval-when-compile (fboundp 'make-hash-table))
9863 (unless verilog-modi-lookup-cache
9864 (setq verilog-modi-lookup-cache
9865 (make-hash-table :test 'equal :rehash-size 4.0)))
9866 (puthash module modi verilog-modi-lookup-cache))
9867 (setq verilog-modi-lookup-last-current current
9868 verilog-modi-lookup-last-tick (buffer-chars-modified-tick)))))
9871 (defun verilog-modi-filename (modi)
9872 "Filename of MODI, or name of buffer if it's never been saved."
9873 (if (bufferp (verilog-modi-file-or-buffer modi))
9874 (or (buffer-file-name (verilog-modi-file-or-buffer modi))
9875 (buffer-name (verilog-modi-file-or-buffer modi)))
9876 (verilog-modi-file-or-buffer modi)))
9878 (defun verilog-modi-goto (modi)
9879 "Move point/buffer to specified MODI."
9880 (or modi (error "Passed unfound modi to goto, check earlier"))
9881 (set-buffer (if (bufferp (verilog-modi-file-or-buffer modi))
9882 (verilog-modi-file-or-buffer modi)
9883 (find-file-noselect (verilog-modi-file-or-buffer modi))))
9884 (or (equal major-mode `verilog-mode) ;; Put into Verilog mode to get syntax
9886 (goto-char (verilog-modi-get-point modi)))
9888 (defun verilog-goto-defun-file (module)
9889 "Move point to the file at which a given MODULE is defined."
9890 (interactive "sGoto File for Module: ")
9891 (let* ((modi (verilog-modi-lookup module nil)))
9893 (verilog-modi-goto modi)
9894 (switch-to-buffer (current-buffer)))))
9896 (defun verilog-modi-cache-results (modi function)
9897 "Run on MODI the given FUNCTION. Locate the module in a file.
9898 Cache the output of function so next call may have faster access."
9900 (save-excursion ;; Cache is buffer-local so can't avoid this.
9901 (verilog-modi-goto modi)
9902 (if (and (setq fass (assoc (list modi function)
9903 verilog-modi-cache-list))
9904 ;; Destroy caching when incorrect; Modified or file changed
9905 (not (and verilog-cache-enabled
9906 (or (equal (buffer-chars-modified-tick) (nth 1 fass))
9907 (and verilog-modi-cache-preserve-tick
9908 (<= verilog-modi-cache-preserve-tick (nth 1 fass))
9909 (equal verilog-modi-cache-preserve-buffer (current-buffer))))
9910 (equal (visited-file-modtime) (nth 2 fass)))))
9911 (setq verilog-modi-cache-list nil
9914 ;; Return data from cache hit
9918 ;; Clear then restore any highlighting to make emacs19 happy
9920 (verilog-save-font-mods
9921 (setq func-returns (funcall function)))
9922 ;; Cache for next time
9923 (setq verilog-modi-cache-list
9924 (cons (list (list modi function)
9925 (buffer-chars-modified-tick)
9926 (visited-file-modtime)
9928 verilog-modi-cache-list))
9931 (defun verilog-modi-cache-add (modi function element sig-list)
9932 "Add function return results to the module cache.
9933 Update MODI's cache for given FUNCTION so that the return ELEMENT of that
9934 function now contains the additional SIG-LIST parameters."
9937 (verilog-modi-goto modi)
9938 (if (setq fass (assoc (list modi function)
9939 verilog-modi-cache-list))
9940 (let ((func-returns (nth 3 fass)))
9941 (aset func-returns element
9942 (append sig-list (aref func-returns element))))))))
9944 (defmacro verilog-preserve-modi-cache (&rest body)
9945 "Execute the BODY forms, allowing cache preservation within BODY.
9946 This means that changes to the buffer will not result in the cache being
9947 flushed. If the changes affect the modsig state, they must call the
9948 modsig-cache-add-* function, else the results of later calls may be
9949 incorrect. Without this, changes are assumed to be adding/removing signals
9950 and invalidating the cache."
9951 `(let ((verilog-modi-cache-preserve-tick (buffer-chars-modified-tick))
9952 (verilog-modi-cache-preserve-buffer (current-buffer)))
9956 (defun verilog-modi-modport-lookup-one (modi name &optional ignore-error)
9957 "Given a MODI, return the declarations related to the given modport NAME."
9958 ;; Recursive routine - see below
9959 (let* ((realname (verilog-symbol-detick name t))
9960 (modport (assoc name (verilog-decls-get-modports (verilog-modi-get-decls modi)))))
9961 (or modport ignore-error
9962 (error (concat (verilog-point-text)
9963 ": Can't locate " name " modport definition"
9964 (if (not (equal name realname))
9965 (concat " (Expanded macro to " realname ")")
9967 (let* ((decls (verilog-modport-decls modport))
9968 (clks (verilog-modport-clockings modport)))
9969 ;; Now expand any clocking's
9971 (setq decls (verilog-decls-append
9973 (verilog-modi-modport-lookup-one modi (car clks) ignore-error)))
9974 (setq clks (cdr clks)))
9977 (defun verilog-modi-modport-lookup (modi name-re &optional ignore-error)
9978 "Given a MODI, return the declarations related to the given modport NAME-RE.
9979 If the modport points to any clocking blocks, expand the signals to include
9980 those clocking block's signals."
9981 ;; Recursive routine - see below
9982 (let* ((mod-decls (verilog-modi-get-decls modi))
9983 (clks (verilog-decls-get-modports mod-decls))
9984 (name-re (concat "^" name-re "$"))
9985 (decls (verilog-decls-new nil nil nil nil nil nil nil nil nil)))
9986 ;; Pull in all modports
9988 (when (string-match name-re (verilog-modport-name (car clks)))
9989 (setq decls (verilog-decls-append
9991 (verilog-modi-modport-lookup-one modi (verilog-modport-name (car clks)) ignore-error))))
9992 (setq clks (cdr clks)))
9995 (defun verilog-signals-matching-enum (in-list enum)
9996 "Return all signals in IN-LIST matching the given ENUM."
9999 (if (equal (verilog-sig-enum (car in-list)) enum)
10000 (setq out-list (cons (car in-list) out-list)))
10001 (setq in-list (cdr in-list)))
10003 ;; Namespace intentionally short for AUTOs and compatibility
10004 (let* ((enumvar (intern (concat "venum-" enum)))
10005 (enumlist (and (boundp enumvar) (eval enumvar))))
10007 (add-to-list 'out-list (list (car enumlist)))
10008 (setq enumlist (cdr enumlist))))
10009 (nreverse out-list)))
10011 (defun verilog-signals-matching-regexp (in-list regexp)
10012 "Return all signals in IN-LIST matching the given REGEXP, if non-nil."
10013 (if (or (not regexp) (equal regexp ""))
10015 (let ((case-fold-search verilog-case-fold)
10018 (if (string-match regexp (verilog-sig-name (car in-list)))
10019 (setq out-list (cons (car in-list) out-list)))
10020 (setq in-list (cdr in-list)))
10021 (nreverse out-list))))
10023 (defun verilog-signals-not-matching-regexp (in-list regexp)
10024 "Return all signals in IN-LIST not matching the given REGEXP, if non-nil."
10025 (if (or (not regexp) (equal regexp ""))
10027 (let ((case-fold-search verilog-case-fold)
10030 (if (not (string-match regexp (verilog-sig-name (car in-list))))
10031 (setq out-list (cons (car in-list) out-list)))
10032 (setq in-list (cdr in-list)))
10033 (nreverse out-list))))
10035 (defun verilog-signals-matching-dir-re (in-list decl-type regexp)
10036 "Return all signals in IN-LIST matching the given DECL-TYPE and REGEXP,
10038 (if (or (not regexp) (equal regexp ""))
10040 (let (out-list to-match)
10042 ;; Note verilog-insert-one-definition matches on this order
10043 (setq to-match (concat
10045 " " (verilog-sig-signed (car in-list))
10046 " " (verilog-sig-multidim (car in-list))
10047 (verilog-sig-bits (car in-list))))
10048 (if (string-match regexp to-match)
10049 (setq out-list (cons (car in-list) out-list)))
10050 (setq in-list (cdr in-list)))
10051 (nreverse out-list))))
10053 (defun verilog-signals-edit-wire-reg (in-list)
10054 "Return all signals in IN-LIST with wire/reg data types made blank."
10055 (mapcar (lambda (sig)
10056 (when (member (verilog-sig-type sig) '("wire" "reg"))
10057 (verilog-sig-type-set sig nil))
10061 (defun verilog-decls-get-signals (decls)
10062 "Return all declared signals in DECLS, excluding 'assign' statements."
10064 (verilog-decls-get-outputs decls)
10065 (verilog-decls-get-inouts decls)
10066 (verilog-decls-get-inputs decls)
10067 (verilog-decls-get-vars decls)
10068 (verilog-decls-get-consts decls)
10069 (verilog-decls-get-gparams decls)))
10071 (defun verilog-decls-get-ports (decls)
10073 (verilog-decls-get-outputs decls)
10074 (verilog-decls-get-inouts decls)
10075 (verilog-decls-get-inputs decls)))
10077 (defun verilog-decls-get-iovars (decls)
10079 (verilog-decls-get-vars decls)
10080 (verilog-decls-get-outputs decls)
10081 (verilog-decls-get-inouts decls)
10082 (verilog-decls-get-inputs decls)))
10084 (defsubst verilog-modi-cache-add-outputs (modi sig-list)
10085 (verilog-modi-cache-add modi 'verilog-read-decls 0 sig-list))
10086 (defsubst verilog-modi-cache-add-inouts (modi sig-list)
10087 (verilog-modi-cache-add modi 'verilog-read-decls 1 sig-list))
10088 (defsubst verilog-modi-cache-add-inputs (modi sig-list)
10089 (verilog-modi-cache-add modi 'verilog-read-decls 2 sig-list))
10090 (defsubst verilog-modi-cache-add-vars (modi sig-list)
10091 (verilog-modi-cache-add modi 'verilog-read-decls 3 sig-list))
10092 (defsubst verilog-modi-cache-add-gparams (modi sig-list)
10093 (verilog-modi-cache-add modi 'verilog-read-decls 7 sig-list))
10097 ;; Auto creation utilities
10100 (defun verilog-auto-re-search-do (search-for func)
10101 "Search for the given auto text regexp SEARCH-FOR, and perform FUNC where it occurs."
10102 (goto-char (point-min))
10103 (while (verilog-re-search-forward-quick search-for nil t)
10106 (defun verilog-insert-one-definition (sig type indent-pt)
10107 "Print out a definition for SIG of the given TYPE,
10108 with appropriate INDENT-PT indentation."
10109 (indent-to indent-pt)
10110 ;; Note verilog-signals-matching-dir-re matches on this order
10112 (when (verilog-sig-modport sig)
10113 (insert "." (verilog-sig-modport sig)))
10114 (when (verilog-sig-signed sig)
10115 (insert " " (verilog-sig-signed sig)))
10116 (when (verilog-sig-multidim sig)
10117 (insert " " (verilog-sig-multidim-string sig)))
10118 (when (verilog-sig-bits sig)
10119 (insert " " (verilog-sig-bits sig)))
10120 (indent-to (max 24 (+ indent-pt 16)))
10121 (unless (= (char-syntax (preceding-char)) ?\ )
10122 (insert " ")) ; Need space between "]name" if indent-to did nothing
10123 (insert (verilog-sig-name sig))
10124 (when (verilog-sig-memory sig)
10125 (insert " " (verilog-sig-memory sig))))
10127 (defun verilog-insert-definition (modi sigs direction indent-pt v2k &optional dont-sort)
10128 "Print out a definition for MODI's list of SIGS of the given DIRECTION,
10129 with appropriate INDENT-PT indentation. If V2K, use Verilog 2001 I/O
10130 format. Sort unless DONT-SORT. DIRECTION is normally wire/reg/output.
10131 When MODI is non-null, also add to modi-cache, for tracking."
10133 (cond ((equal direction "wire")
10134 (verilog-modi-cache-add-vars modi sigs))
10135 ((equal direction "reg")
10136 (verilog-modi-cache-add-vars modi sigs))
10137 ((equal direction "output")
10138 (verilog-modi-cache-add-outputs modi sigs)
10139 (when verilog-auto-declare-nettype
10140 (verilog-modi-cache-add-vars modi sigs)))
10141 ((equal direction "input")
10142 (verilog-modi-cache-add-inputs modi sigs)
10143 (when verilog-auto-declare-nettype
10144 (verilog-modi-cache-add-vars modi sigs)))
10145 ((equal direction "inout")
10146 (verilog-modi-cache-add-inouts modi sigs)
10147 (when verilog-auto-declare-nettype
10148 (verilog-modi-cache-add-vars modi sigs)))
10149 ((equal direction "interface"))
10150 ((equal direction "parameter")
10151 (verilog-modi-cache-add-gparams modi sigs))
10153 (error "Unsupported verilog-insert-definition direction: %s" direction))))
10155 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
10157 (let ((sig (car sigs)))
10158 (verilog-insert-one-definition
10160 ;; Want "type x" or "output type x", not "wire type x"
10161 (cond ((or (verilog-sig-type sig)
10162 verilog-auto-wire-type)
10164 (when (member direction '("input" "output" "inout"))
10165 (concat direction " "))
10166 (or (verilog-sig-type sig)
10167 verilog-auto-wire-type)))
10168 ((and verilog-auto-declare-nettype
10169 (member direction '("input" "output" "inout")))
10170 (concat direction " " verilog-auto-declare-nettype))
10174 (insert (if v2k "," ";"))
10175 (if (or (not (verilog-sig-comment sig))
10176 (equal "" (verilog-sig-comment sig)))
10178 (indent-to (max 48 (+ indent-pt 40)))
10179 (verilog-insert "// " (verilog-sig-comment sig) "\n"))
10180 (setq sigs (cdr sigs)))))
10183 (if (not (boundp 'indent-pt))
10184 (defvar indent-pt nil "Local used by insert-indent")))
10186 (defun verilog-insert-indent (&rest stuff)
10187 "Indent to position stored in local `indent-pt' variable, then insert STUFF.
10188 Presumes that any newlines end a list element."
10189 (let ((need-indent t))
10191 (if need-indent (indent-to indent-pt))
10192 (setq need-indent nil)
10193 (verilog-insert (car stuff))
10194 (setq need-indent (string-match "\n$" (car stuff))
10195 stuff (cdr stuff)))))
10196 ;;(let ((indent-pt 10)) (verilog-insert-indent "hello\n" "addon" "there\n"))
10198 (defun verilog-forward-or-insert-line ()
10199 "Move forward a line, unless at EOB, then insert a newline."
10200 (if (eobp) (insert "\n")
10203 (defun verilog-repair-open-comma ()
10204 "Insert comma if previous argument is other than an open parenthesis or endif."
10205 ;; We can't just search backward for ) as it might be inside another expression.
10206 ;; Also want "`ifdef X input foo `endif" to just leave things to the human to deal with
10208 (verilog-backward-syntactic-ws-quick)
10209 (when (and (not (save-excursion ;; Not beginning (, or existing ,
10211 (looking-at "[(,]")))
10212 (not (save-excursion ;; Not `endif, or user define
10214 (skip-chars-backward "[a-zA-Z0-9_`]")
10215 (looking-at "`"))))
10218 (defun verilog-repair-close-comma ()
10219 "If point is at a comma followed by a close parenthesis, fix it.
10220 This repairs those mis-inserted by an AUTOARG."
10221 ;; It would be much nicer if Verilog allowed extra commas like Perl does!
10223 (verilog-forward-close-paren)
10225 (verilog-backward-syntactic-ws-quick)
10227 (when (looking-at ",")
10230 (defun verilog-make-width-expression (range-exp)
10231 "Return an expression calculating the length of a range [x:y] in RANGE-EXP."
10232 ;; strip off the []
10233 (cond ((not range-exp)
10236 (if (string-match "^\\[\\(.*\\)\\]$" range-exp)
10237 (setq range-exp (match-string 1 range-exp)))
10238 (cond ((not range-exp)
10240 ;; [#:#] We can compute a numeric result
10241 ((string-match "^\\s *\\([0-9]+\\)\\s *:\\s *\\([0-9]+\\)\\s *$"
10244 (1+ (abs (- (string-to-number (match-string 1 range-exp))
10245 (string-to-number (match-string 2 range-exp)))))))
10246 ;; [PARAM-1:0] can just return PARAM
10247 ((string-match "^\\s *\\([a-zA-Z_][a-zA-Z0-9_]*\\)\\s *-\\s *1\\s *:\\s *0\\s *$" range-exp)
10248 (match-string 1 range-exp))
10249 ;; [arbitrary] need math
10250 ((string-match "^\\(.*\\)\\s *:\\s *\\(.*\\)\\s *$" range-exp)
10251 (concat "(1+(" (match-string 1 range-exp) ")"
10252 (if (equal "0" (match-string 2 range-exp))
10253 "" ;; Don't bother with -(0)
10254 (concat "-(" (match-string 2 range-exp) ")"))
10257 ;;(verilog-make-width-expression "`A:`B")
10259 (defun verilog-simplify-range-expression (expr)
10260 "Return a simplified range expression with constants eliminated from EXPR."
10261 ;; Note this is always called with brackets; ie [z] or [z:z]
10262 (if (not (string-match "[---+*()]" expr))
10263 expr ;; short-circuit
10266 (while (not (equal last-pass out))
10267 (setq last-pass out)
10268 ;; Prefix regexp needs beginning of match, or some symbol of
10269 ;; lesser or equal precedence. We assume the [:]'s exist in expr.
10271 (while (string-match
10272 (concat "\\([[({:*+-]\\)" ; - must be last
10273 "(\\<\\([0-9A-Za-z_]+\\))"
10276 (setq out (replace-match "\\1\\2\\3" nil nil out)))
10277 (while (string-match
10278 (concat "\\([[({:*+-]\\)" ; - must be last
10279 "\\$clog2\\s *(\\<\\([0-9]+\\))"
10282 (setq out (replace-match
10284 (match-string 1 out)
10285 (int-to-string (verilog-clog2 (string-to-number (match-string 2 out))))
10286 (match-string 3 out))
10288 ;; For precedence do * before +/-
10289 (while (string-match
10290 (concat "\\([[({:*+-]\\)"
10291 "\\([0-9]+\\)\\s *\\([*]\\)\\s *\\([0-9]+\\)"
10294 (setq out (replace-match
10295 (concat (match-string 1 out)
10296 (int-to-string (* (string-to-number (match-string 2 out))
10297 (string-to-number (match-string 4 out))))
10298 (match-string 5 out))
10300 (while (string-match
10301 (concat "\\([[({:+-]\\)" ; No * here as higher prec
10302 "\\([0-9]+\\)\\s *\\([---+]\\)\\s *\\([0-9]+\\)"
10305 (let ((pre (match-string 1 out))
10306 (lhs (string-to-number (match-string 2 out)))
10307 (rhs (string-to-number (match-string 4 out)))
10308 (post (match-string 5 out))
10310 (when (equal pre "-")
10311 (setq lhs (- lhs)))
10312 (setq val (if (equal (match-string 3 out) "-")
10316 (concat (if (and (equal pre "-")
10318 "" ;; Not "--20" but just "-20"
10320 (int-to-string val)
10325 ;;(verilog-simplify-range-expression "[1:3]") ;; 1
10326 ;;(verilog-simplify-range-expression "[(1):3]") ;; 1
10327 ;;(verilog-simplify-range-expression "[(((16)+1)+1+(1+1))]") ;;20
10328 ;;(verilog-simplify-range-expression "[(2*3+6*7)]") ;; 48
10329 ;;(verilog-simplify-range-expression "[(FOO*4-1*2)]") ;; FOO*4-2
10330 ;;(verilog-simplify-range-expression "[(FOO*4+1-1)]") ;; FOO*4+0
10331 ;;(verilog-simplify-range-expression "[(func(BAR))]") ;; func(BAR)
10332 ;;(verilog-simplify-range-expression "[FOO-1+1-1+1]") ;; FOO-0
10333 ;;(verilog-simplify-range-expression "[$clog2(2)]") ;; 1
10334 ;;(verilog-simplify-range-expression "[$clog2(7)]") ;; 3
10336 (defun verilog-clog2 (value)
10337 "Compute $clog2 - ceiling log2 of VALUE."
10340 (ceiling (/ (log value) (log 2)))))
10342 (defun verilog-typedef-name-p (variable-name)
10343 "Return true if the VARIABLE-NAME is a type definition."
10344 (when verilog-typedef-regexp
10345 (verilog-string-match-fold verilog-typedef-regexp variable-name)))
10351 (defun verilog-delete-autos-lined ()
10352 "Delete autos that occupy multiple lines, between begin and end comments."
10353 ;; The newline must not have a comment property, so we must
10354 ;; delete the end auto's newline, not the first newline
10356 (let ((pt (point)))
10358 (looking-at "\\s-*// Beginning")
10359 (search-forward "// End of automatic" nil t))
10363 (delete-region pt (point)))))
10365 (defun verilog-delete-empty-auto-pair ()
10366 "Delete begin/end auto pair at point, if empty."
10368 (when (looking-at (concat "\\s-*// Beginning of automatic.*\n"
10369 "\\s-*// End of automatics\n"))
10370 (delete-region (point) (save-excursion (forward-line 2) (point)))))
10372 (defun verilog-forward-close-paren ()
10373 "Find the close parenthesis that match the current point.
10374 Ignore other close parenthesis with matching open parens."
10376 (while (> parens 0)
10377 (unless (verilog-re-search-forward-quick "[()]" nil t)
10378 (error "%s: Mismatching ()" (verilog-point-text)))
10379 (cond ((= (preceding-char) ?\( )
10380 (setq parens (1+ parens)))
10381 ((= (preceding-char) ?\) )
10382 (setq parens (1- parens)))))))
10384 (defun verilog-backward-open-paren ()
10385 "Find the open parenthesis that match the current point.
10386 Ignore other open parenthesis with matching close parens."
10388 (while (> parens 0)
10389 (unless (verilog-re-search-backward-quick "[()]" nil t)
10390 (error "%s: Mismatching ()" (verilog-point-text)))
10391 (cond ((= (following-char) ?\) )
10392 (setq parens (1+ parens)))
10393 ((= (following-char) ?\( )
10394 (setq parens (1- parens)))))))
10396 (defun verilog-backward-open-bracket ()
10397 "Find the open bracket that match the current point.
10398 Ignore other open bracket with matching close bracket."
10400 (while (> parens 0)
10401 (unless (verilog-re-search-backward-quick "[][]" nil t)
10402 (error "%s: Mismatching []" (verilog-point-text)))
10403 (cond ((= (following-char) ?\] )
10404 (setq parens (1+ parens)))
10405 ((= (following-char) ?\[ )
10406 (setq parens (1- parens)))))))
10408 (defun verilog-delete-to-paren ()
10409 "Delete the automatic inst/sense/arg created by autos.
10410 Deletion stops at the matching end parenthesis, outside comments."
10411 (delete-region (point)
10413 (verilog-backward-open-paren)
10414 (verilog-forward-sexp-ign-cmt 1) ;; Moves to paren that closes argdecl's
10418 (defun verilog-auto-star-safe ()
10419 "Return if a .* AUTOINST is safe to delete or expand.
10420 It was created by the AUTOS themselves, or by the user."
10421 (and verilog-auto-star-expand
10423 (concat "[ \t\n\f,]*\\([)]\\|// " verilog-inst-comment-re "\\)"))))
10425 (defun verilog-delete-auto-star-all ()
10426 "Delete a .* AUTOINST, if it is safe."
10427 (when (verilog-auto-star-safe)
10428 (verilog-delete-to-paren)))
10430 (defun verilog-delete-auto-star-implicit ()
10431 "Delete all .* implicit connections created by `verilog-auto-star'.
10432 This function will be called automatically at save unless
10433 `verilog-auto-star-save' is set, any non-templated expanded pins will be
10436 (let (paren-pt indent have-close-paren)
10438 (goto-char (point-min))
10439 ;; We need to match these even outside of comments.
10440 ;; For reasonable performance, we don't check if inside comments, sorry.
10441 (while (re-search-forward "// Implicit \\.\\*" nil t)
10442 (setq paren-pt (point))
10443 (beginning-of-line)
10444 (setq have-close-paren
10446 (when (search-forward ");" paren-pt t)
10447 (setq indent (current-indentation))
10449 (delete-region (point) (+ 1 paren-pt)) ; Nuke line incl CR
10450 (when have-close-paren
10451 ;; Delete extra commentary
10455 (looking-at (concat "\\s *//\\s *" verilog-inst-comment-re "\n")))
10456 (delete-region (match-beginning 0) (match-end 0))))
10457 ;; If it is simple, we can put the ); on the same line as the last text
10458 (let ((rtn-pt (point)))
10460 (while (progn (backward-char 1)
10461 (looking-at "[ \t\n\f]")))
10462 (when (looking-at ",")
10463 (delete-region (+ 1 (point)) rtn-pt))))
10465 (indent-to indent))
10467 ;; Still need to kill final comma - always is one as we put one after the .*
10468 (re-search-backward ",")
10469 (delete-char 1))))))
10471 (defun verilog-delete-auto ()
10472 "Delete the automatic outputs, regs, and wires created by \\[verilog-auto].
10473 Use \\[verilog-auto] to re-insert the updated AUTOs.
10475 The hooks `verilog-before-delete-auto-hook' and `verilog-delete-auto-hook' are
10476 called before and after this function, respectively."
10479 (if (buffer-file-name)
10480 (find-file-noselect (buffer-file-name))) ;; To check we have latest version
10481 (verilog-save-no-change-functions
10482 (verilog-save-scan-cache
10483 ;; Allow user to customize
10484 (verilog-run-hooks 'verilog-before-delete-auto-hook)
10486 ;; Remove those that have multi-line insertions, possibly with parameters
10487 ;; We allow anything beginning with AUTO, so that users can add their own
10489 (verilog-auto-re-search-do
10490 (concat "/\\*AUTO[A-Za-z0-9_]+"
10491 ;; Optional parens or quoted parameter or .* for (((...)))
10492 "\\(\\|([^)]*)\\|(\"[^\"]*\")\\).*?"
10494 'verilog-delete-autos-lined)
10495 ;; Remove those that are in parenthesis
10496 (verilog-auto-re-search-do
10499 (verilog-regexp-words
10500 `("AS" "AUTOARG" "AUTOCONCATWIDTH" "AUTOINST" "AUTOINSTPARAM"
10503 'verilog-delete-to-paren)
10504 ;; Do .* instantiations, but avoid removing any user pins by looking for our magic comments
10505 (verilog-auto-re-search-do "\\.\\*"
10506 'verilog-delete-auto-star-all)
10507 ;; Remove template comments ... anywhere in case was pasted after AUTOINST removed
10508 (goto-char (point-min))
10509 (while (re-search-forward "\\s-*// \\(Templated\\|Implicit \\.\\*\\)\\([ \tLT0-9]*\\| LHS: .*\\)?$" nil t)
10510 (replace-match ""))
10513 (verilog-run-hooks 'verilog-delete-auto-hook)))))
10519 (defun verilog-inject-auto ()
10520 "Examine legacy non-AUTO code and insert AUTOs in appropriate places.
10522 Any always @ blocks with sensitivity lists that match computed lists will
10523 be replaced with /*AS*/ comments.
10525 Any cells will get /*AUTOINST*/ added to the end of the pin list.
10526 Pins with have identical names will be deleted.
10528 Argument lists will not be deleted, /*AUTOARG*/ will only be inserted to
10529 support adding new ports. You may wish to delete older ports yourself.
10533 module ExampInject (i, o);
10539 InstModule instName
10544 Typing \\[verilog-inject-auto] will make this into:
10546 module ExampInject (i, o/*AUTOARG*/
10551 always @ (/*AS*/i or j)
10553 InstModule instName
10562 (defun verilog-inject-arg ()
10563 "Inject AUTOARG into new code. See `verilog-inject-auto'."
10564 ;; Presume one module per file.
10566 (goto-char (point-min))
10567 (while (verilog-re-search-forward-quick "\\<module\\>" nil t)
10568 (let ((endmodp (save-excursion
10569 (verilog-re-search-forward-quick "\\<endmodule\\>" nil t)
10571 ;; See if there's already a comment .. inside a comment so not verilog-re-search
10572 (when (not (re-search-forward "/\\*AUTOARG\\*/" endmodp t))
10573 (verilog-re-search-forward-quick ";" nil t)
10575 (verilog-backward-syntactic-ws-quick)
10576 (backward-char 1) ; Moves to paren that closes argdecl's
10577 (when (looking-at ")")
10578 (verilog-insert "/*AUTOARG*/")))))))
10580 (defun verilog-inject-sense ()
10581 "Inject AUTOSENSE into new code. See `verilog-inject-auto'."
10583 (goto-char (point-min))
10584 (while (verilog-re-search-forward-quick "\\<always\\s *@\\s *(" nil t)
10585 (let* ((start-pt (point))
10586 (modi (verilog-modi-current))
10587 (moddecls (verilog-modi-get-decls modi))
10591 (verilog-forward-sexp-ign-cmt 1)
10592 (backward-char 1) ;; End )
10593 (when (not (verilog-re-search-backward-quick "/\\*\\(AUTOSENSE\\|AS\\)\\*/" start-pt t))
10594 (setq pre-sigs (verilog-signals-from-signame
10595 (verilog-read-signals start-pt (point)))
10596 got-sigs (verilog-auto-sense-sigs moddecls nil))
10597 (when (not (or (verilog-signals-not-in pre-sigs got-sigs) ; Both are equal?
10598 (verilog-signals-not-in got-sigs pre-sigs)))
10599 (delete-region start-pt (point))
10600 (verilog-insert "/*AS*/")))))))
10602 (defun verilog-inject-inst ()
10603 "Inject AUTOINST into new code. See `verilog-inject-auto'."
10605 (goto-char (point-min))
10606 ;; It's hard to distinguish modules; we'll instead search for pins.
10607 (while (verilog-re-search-forward-quick "\\.\\s *[a-zA-Z0-9`_\$]+\\s *(\\s *[a-zA-Z0-9`_\$]+\\s *)" nil t)
10608 (verilog-backward-open-paren) ;; Inst start
10610 ((= (preceding-char) ?\#) ;; #(...) parameter section, not pin. Skip.
10612 (verilog-forward-close-paren)) ;; Parameters done
10615 (let ((indent-pt (+ (current-column)))
10616 (end-pt (save-excursion (verilog-forward-close-paren) (point))))
10617 (cond ((verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-pt t)
10618 (goto-char end-pt)) ;; Already there, continue search with next instance
10620 ;; Delete identical interconnect
10621 (let ((case-fold-search nil)) ;; So we don't convert upper-to-lower, etc
10622 (while (verilog-re-search-forward-quick "\\.\\s *\\([a-zA-Z0-9`_\$]+\\)*\\s *(\\s *\\1\\s *)\\s *" end-pt t)
10623 (delete-region (match-beginning 0) (match-end 0))
10624 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))) ;; Keep it correct
10625 (while (or (looking-at "[ \t\n\f,]+")
10626 (looking-at "//[^\n]*"))
10627 (delete-region (match-beginning 0) (match-end 0))
10628 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))))))
10629 (verilog-forward-close-paren)
10631 ;; Not verilog-re-search, as we don't want to strip comments
10632 (while (re-search-backward "[ \t\n\f]+" (- (point) 1) t)
10633 (delete-region (match-beginning 0) (match-end 0)))
10634 (verilog-insert "\n")
10635 (verilog-insert-indent "/*AUTOINST*/")))))))))
10641 (defun verilog-diff-buffers-p (b1 b2 &optional whitespace)
10642 "Return nil if buffers B1 and B2 have same contents.
10643 Else, return point in B1 that first mismatches.
10644 If optional WHITESPACE true, ignore whitespace."
10646 (let* ((case-fold-search nil) ;; compare-buffer-substrings cares
10647 (p1 (with-current-buffer b1 (goto-char (point-min))))
10648 (p2 (with-current-buffer b2 (goto-char (point-min))))
10649 (maxp1 (with-current-buffer b1 (point-max)))
10650 (maxp2 (with-current-buffer b2 (point-max)))
10653 (while (not (and (eq p1 op1) (eq p2 op2)))
10654 ;; If both windows have whitespace optionally skip over it.
10656 ;; skip-syntax-* doesn't count \n
10657 (with-current-buffer b1
10659 (skip-chars-forward " \t\n\r\f\v")
10661 (with-current-buffer b2
10663 (skip-chars-forward " \t\n\r\f\v")
10664 (setq p2 (point))))
10665 (setq size (min (- maxp1 p1) (- maxp2 p2)))
10666 (setq progress (compare-buffer-substrings b2 p2 (+ size p2)
10667 b1 p1 (+ size p1)))
10668 (setq progress (if (zerop progress) size (1- (abs progress))))
10669 (setq op1 p1 op2 p2
10671 p2 (+ p2 progress)))
10673 (if (and (eq p1 maxp1) (eq p2 maxp2))
10676 (defun verilog-diff-file-with-buffer (f1 b2 &optional whitespace show)
10677 "View the differences between file F1 and buffer B2.
10678 This requires the external program `diff-command' to be in your `exec-path',
10679 and uses `diff-switches' in which you may want to have \"-u\" flag.
10680 Ignores WHITESPACE if t, and writes output to stdout if SHOW."
10681 ;; Similar to `diff-buffer-with-file' but works on XEmacs, and doesn't
10682 ;; call `diff' as `diff' has different calling semantics on different
10683 ;; versions of Emacs.
10684 (if (not (file-exists-p f1))
10685 (message "Buffer %s has no associated file on disc" (buffer-name b2))
10686 (with-temp-buffer "*Verilog-Diff*"
10687 (let ((outbuf (current-buffer))
10688 (f2 (make-temp-file "vm-diff-auto-")))
10691 (with-current-buffer b2
10694 (write-region (point-min) (point-max) f2 nil 'nomessage)))
10695 (call-process diff-command nil outbuf t
10696 diff-switches ;; User may want -u in diff-switches
10697 (if whitespace "-b" "")
10699 ;; Print out results. Alternatively we could have call-processed
10700 ;; ourself, but this way we can reuse diff switches
10702 (with-current-buffer outbuf (message "%s" (buffer-string))))))
10704 (when (file-exists-p f2)
10705 (delete-file f2))))))
10707 (defun verilog-diff-report (b1 b2 diffpt)
10708 "Report differences detected with `verilog-diff-auto'.
10709 Differences are between buffers B1 and B2, starting at point
10710 DIFFPT. This function is called via `verilog-diff-function'."
10711 (let ((name1 (with-current-buffer b1 (buffer-file-name))))
10712 (verilog-warn "%s:%d: Difference in AUTO expansion found"
10713 name1 (with-current-buffer b1
10714 (count-lines (point-min) diffpt)))
10715 (cond (noninteractive
10716 (verilog-diff-file-with-buffer name1 b2 t t))
10718 (ediff-buffers b1 b2)))))
10720 (defun verilog-diff-auto ()
10721 "Expand AUTOs in a temporary buffer and indicate any change.
10722 Whitespace is ignored when detecting differences, but once a
10723 difference is detected, whitespace differences may be shown.
10725 To call this from the command line, see \\[verilog-batch-diff-auto].
10727 The action on differences is selected with
10728 `verilog-diff-function'. The default is `verilog-diff-report'
10729 which will report an error and run `ediff' in interactive mode,
10730 or `diff' in batch mode."
10732 (let ((b1 (current-buffer)) b2 diffpt
10733 (name1 (buffer-file-name))
10734 (newname "*Verilog-Diff*"))
10736 (when (get-buffer newname)
10737 (kill-buffer newname))
10738 (setq b2 (let (buffer-file-name) ;; Else clone is upset
10739 (clone-buffer newname)))
10740 (with-current-buffer b2
10741 ;; auto requires the filename, but can't have same filename in two
10742 ;; buffers; so override both b1 and b2's names
10743 (let ((buffer-file-name name1))
10746 (with-current-buffer b1 (setq buffer-file-name nil))
10748 (when (not verilog-auto-star-save)
10749 (verilog-delete-auto-star-implicit)))
10750 ;; Restore name if unwind
10751 (with-current-buffer b1 (setq buffer-file-name name1)))))
10753 (setq diffpt (verilog-diff-buffers-p b1 b2 t))
10754 (cond ((not diffpt)
10755 (unless noninteractive (message "AUTO expansion identical"))
10756 (kill-buffer newname)) ;; Nice to cleanup after oneself
10758 (funcall verilog-diff-function b1 b2 diffpt)))
10759 ;; Return result of compare
10767 (defun verilog-auto-save-check ()
10768 "On saving see if we need auto update."
10769 (cond ((not verilog-auto-save-policy)) ; disabled
10770 ((not (save-excursion
10772 (let ((case-fold-search nil))
10773 (goto-char (point-min))
10774 (re-search-forward "AUTO" nil t))))))
10775 ((eq verilog-auto-save-policy 'force)
10777 ((not (buffer-modified-p)))
10778 ((eq verilog-auto-update-tick (buffer-chars-modified-tick))) ; up-to-date
10779 ((eq verilog-auto-save-policy 'detect)
10782 (when (yes-or-no-p "AUTO statements not recomputed, do it now? ")
10784 ;; Don't ask again if didn't update
10785 (set (make-local-variable 'verilog-auto-update-tick) (buffer-chars-modified-tick))))
10786 (when (not verilog-auto-star-save)
10787 (verilog-delete-auto-star-implicit))
10788 nil) ;; Always return nil -- we don't write the file ourselves
10790 (defun verilog-auto-read-locals ()
10791 "Return file local variable segment at bottom of file."
10793 (goto-char (point-max))
10794 (if (re-search-backward "Local Variables:" nil t)
10795 (buffer-substring-no-properties (point) (point-max))
10798 (defun verilog-auto-reeval-locals (&optional force)
10799 "Read file local variable segment at bottom of file if it has changed.
10800 If FORCE, always reread it."
10801 (let ((curlocal (verilog-auto-read-locals)))
10802 (when (or force (not (equal verilog-auto-last-file-locals curlocal)))
10803 (set (make-local-variable 'verilog-auto-last-file-locals) curlocal)
10804 ;; Note this may cause this function to be recursively invoked,
10805 ;; because hack-local-variables may call (verilog-mode)
10806 ;; The above when statement will prevent it from recursing forever.
10807 (hack-local-variables)
10814 (defun verilog-auto-arg-ports (sigs message indent-pt)
10815 "Print a list of ports for AUTOARG.
10816 Takes SIGS list, adds MESSAGE to front and inserts each at INDENT-PT."
10818 (when verilog-auto-arg-sort
10819 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
10821 (indent-to indent-pt)
10825 (indent-to indent-pt)
10827 (cond ((equal verilog-auto-arg-format 'single)
10829 (indent-to indent-pt)
10831 ;; verilog-auto-arg-format 'packed
10832 ((> (+ 2 (current-column) (length (verilog-sig-name (car sigs)))) fill-column)
10834 (indent-to indent-pt)
10839 (insert (verilog-sig-name (car sigs)) ",")
10840 (setq sigs (cdr sigs))))))
10842 (defun verilog-auto-arg ()
10843 "Expand AUTOARG statements.
10844 Replace the argument declarations at the beginning of the
10845 module with ones automatically derived from input and output
10846 statements. This can be dangerous if the module is instantiated
10847 using position-based connections, so use only name-based when
10848 instantiating the resulting module. Long lines are split based
10849 on the `fill-column', see \\[set-fill-column].
10852 Concatenation and outputting partial buses is not supported.
10854 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
10858 module ExampArg (/*AUTOARG*/);
10863 Typing \\[verilog-auto] will make this into:
10865 module ExampArg (/*AUTOARG*/
10875 The argument declarations may be printed in declaration order to
10876 best suit order based instantiations, or alphabetically, based on
10877 the `verilog-auto-arg-sort' variable.
10879 Formatting is controlled with `verilog-auto-arg-format' variable.
10881 Any ports declared between the ( and /*AUTOARG*/ are presumed to be
10882 predeclared and are not redeclared by AUTOARG. AUTOARG will make a
10883 conservative guess on adding a comma for the first signal, if you have
10884 any ifdefs or complicated expressions before the AUTOARG you will need
10885 to choose the comma yourself.
10887 Avoid declaring ports manually, as it makes code harder to maintain."
10889 (let* ((modi (verilog-modi-current))
10890 (moddecls (verilog-modi-get-decls modi))
10891 (skip-pins (aref (verilog-read-arg-pins) 0)))
10892 (verilog-repair-open-comma)
10893 (verilog-auto-arg-ports (verilog-signals-not-in
10894 (verilog-decls-get-outputs moddecls)
10897 verilog-indent-level-declaration)
10898 (verilog-auto-arg-ports (verilog-signals-not-in
10899 (verilog-decls-get-inouts moddecls)
10902 verilog-indent-level-declaration)
10903 (verilog-auto-arg-ports (verilog-signals-not-in
10904 (verilog-decls-get-inputs moddecls)
10907 verilog-indent-level-declaration)
10908 (verilog-repair-close-comma)
10909 (unless (eq (char-before) ?/ )
10911 (indent-to verilog-indent-level-declaration))))
10913 (defun verilog-auto-assign-modport ()
10914 "Expand AUTOASSIGNMODPORT statements, as part of \\[verilog-auto].
10915 Take input/output/inout statements from the specified interface
10916 and modport and use to build assignments into the modport, for
10917 making verification modules that connect to UVM interfaces.
10919 The first parameter is the name of an interface.
10921 The second parameter is a regexp of modports to read from in
10924 The third parameter is the instance name to use to dot reference into.
10926 The optional fourth parameter is a regular expression, and only
10927 signals matching the regular expression will be included.
10931 Interface names must be resolvable to filenames. See `verilog-auto-inst'.
10933 Inouts are not supported, as assignments must be unidirectional.
10935 If a signal is part of the interface header and in both a
10936 modport and the interface itself, it will not be listed. (As
10937 this would result in a syntax error when the connections are
10940 See the example in `verilog-auto-inout-modport'."
10942 (let* ((params (verilog-read-auto-params 3 4))
10943 (submod (nth 0 params))
10944 (modport-re (nth 1 params))
10945 (inst-name (nth 2 params))
10946 (regexp (nth 3 params))
10947 direction-re submodi) ;; direction argument not supported until requested
10948 ;; Lookup position, etc of co-module
10949 ;; Note this may raise an error
10950 (when (setq submodi (verilog-modi-lookup submod t))
10951 (let* ((indent-pt (current-indentation))
10952 (submoddecls (verilog-modi-get-decls submodi))
10953 (submodportdecls (verilog-modi-modport-lookup submodi modport-re))
10954 (sig-list-i (verilog-signals-in ;; Decls doesn't have data types, must resolve
10955 (verilog-decls-get-vars submoddecls)
10956 (verilog-signals-not-in
10957 (verilog-decls-get-inputs submodportdecls)
10958 (verilog-decls-get-ports submoddecls))))
10959 (sig-list-o (verilog-signals-in ;; Decls doesn't have data types, must resolve
10960 (verilog-decls-get-vars submoddecls)
10961 (verilog-signals-not-in
10962 (verilog-decls-get-outputs submodportdecls)
10963 (verilog-decls-get-ports submoddecls)))))
10965 (setq sig-list-i (verilog-signals-edit-wire-reg
10966 (verilog-signals-matching-dir-re
10967 (verilog-signals-matching-regexp sig-list-i regexp)
10968 "input" direction-re))
10969 sig-list-o (verilog-signals-edit-wire-reg
10970 (verilog-signals-matching-dir-re
10971 (verilog-signals-matching-regexp sig-list-o regexp)
10972 "output" direction-re)))
10973 (setq sig-list-i (sort (copy-alist sig-list-i) `verilog-signals-sort-compare))
10974 (setq sig-list-o (sort (copy-alist sig-list-o) `verilog-signals-sort-compare))
10975 (when (or sig-list-i sig-list-o)
10976 (verilog-insert-indent "// Beginning of automatic assignments from modport\n")
10977 ;; Don't sort them so an upper AUTOINST will match the main module
10978 (let ((sigs sig-list-o))
10980 (verilog-insert-indent "assign " (verilog-sig-name (car sigs))
10982 "." (verilog-sig-name (car sigs)) ";\n")
10983 (setq sigs (cdr sigs))))
10984 (let ((sigs sig-list-i))
10986 (verilog-insert-indent "assign " inst-name
10987 "." (verilog-sig-name (car sigs))
10988 " = " (verilog-sig-name (car sigs)) ";\n")
10989 (setq sigs (cdr sigs))))
10990 (verilog-insert-indent "// End of automatics\n")))))))
10992 (defun verilog-auto-inst-port-map (_port-st)
10995 (defvar vl-cell-type nil "See `verilog-auto-inst'.") ; Prevent compile warning
10996 (defvar vl-cell-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
10997 (defvar vl-modport nil "See `verilog-auto-inst'.") ; Prevent compile warning
10998 (defvar vl-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
10999 (defvar vl-width nil "See `verilog-auto-inst'.") ; Prevent compile warning
11000 (defvar vl-dir nil "See `verilog-auto-inst'.") ; Prevent compile warning
11001 (defvar vl-bits nil "See `verilog-auto-inst'.") ; Prevent compile warning
11002 (defvar vl-mbits nil "See `verilog-auto-inst'.") ; Prevent compile warning
11004 (defun verilog-auto-inst-port (port-st indent-pt moddecls tpl-list tpl-num for-star par-values)
11005 "Print out an instantiation connection for this PORT-ST.
11006 Insert to INDENT-PT, use template TPL-LIST.
11007 @ are instantiation numbers, replaced with TPL-NUM.
11008 @\"(expression @)\" are evaluated, with @ as a variable.
11009 If FOR-STAR add comment it is a .* expansion.
11010 If PAR-VALUES replace final strings with these parameter values."
11011 (let* ((port (verilog-sig-name port-st))
11012 (tpl-ass (or (assoc port (car tpl-list))
11013 (verilog-auto-inst-port-map port-st)))
11014 ;; vl-* are documented for user use
11015 (vl-name (verilog-sig-name port-st))
11016 (vl-width (verilog-sig-width port-st))
11017 (vl-modport (verilog-sig-modport port-st))
11018 (vl-mbits (if (verilog-sig-multidim port-st)
11019 (verilog-sig-multidim-string port-st) ""))
11020 (vl-bits (if (or verilog-auto-inst-vector
11021 (not (assoc port (verilog-decls-get-signals moddecls)))
11022 (not (equal (verilog-sig-bits port-st)
11024 (assoc port (verilog-decls-get-signals moddecls))))))
11025 (or (verilog-sig-bits port-st) "")
11027 (case-fold-search nil)
11028 (check-values par-values)
11030 ;; Replace parameters in bit-width
11031 (when (and check-values
11032 (not (equal vl-bits "")))
11033 (while check-values
11034 (setq vl-bits (verilog-string-replace-matches
11035 (concat "\\<" (nth 0 (car check-values)) "\\>")
11036 (concat "(" (nth 1 (car check-values)) ")")
11038 vl-mbits (verilog-string-replace-matches
11039 (concat "\\<" (nth 0 (car check-values)) "\\>")
11040 (concat "(" (nth 1 (car check-values)) ")")
11042 check-values (cdr check-values)))
11043 (setq vl-bits (verilog-simplify-range-expression vl-bits)
11044 vl-mbits (verilog-simplify-range-expression vl-mbits)
11045 vl-width (verilog-make-width-expression vl-bits))) ; Not in the loop for speed
11046 ;; Default net value if not found
11047 (setq dflt-bits (if (and (verilog-sig-bits port-st)
11048 (or (verilog-sig-multidim port-st)
11049 (verilog-sig-memory port-st)))
11050 (concat "/*" vl-mbits vl-bits "*/")
11052 tpl-net (concat port
11053 (if (and vl-modport
11054 ;; .modport cannot be added if attachment is
11055 ;; already declared as modport, VCS croaks
11056 (let ((sig (assoc port (verilog-decls-get-interfaces moddecls))))
11057 (not (and sig (verilog-sig-modport sig)))))
11058 (concat "." vl-modport) "")
11061 (cond (tpl-ass ; Template of exact port name
11062 (setq tpl-net (nth 1 tpl-ass)))
11063 ((nth 1 tpl-list) ; Wildcards in template, search them
11064 (let ((wildcards (nth 1 tpl-list)))
11066 (when (string-match (nth 0 (car wildcards)) port)
11067 (setq tpl-ass (car wildcards) ; so allow @ parsing
11068 tpl-net (replace-match (nth 1 (car wildcards))
11070 (setq wildcards (cdr wildcards))))))
11071 ;; Parse Templated variable
11073 ;; Evaluate @"(lispcode)"
11074 (when (string-match "@\".*[^\\]\"" tpl-net)
11075 (while (string-match "@\"\\(\\([^\\\"]*\\(\\\\.\\)*\\)*\\)\"" tpl-net)
11078 (substring tpl-net 0 (match-beginning 0))
11080 (let* ((expr (match-string 1 tpl-net))
11083 (setq expr (verilog-string-replace-matches "\\\\\"" "\"" nil nil expr))
11084 (setq expr (verilog-string-replace-matches "@" tpl-num nil nil expr))
11085 (prin1 (eval (car (read-from-string expr)))
11086 (lambda (_ch) ())))))
11087 (if (numberp value) (setq value (number-to-string value)))
11089 (substring tpl-net (match-end 0))))))
11090 ;; Replace @ and [] magic variables in final output
11091 (setq tpl-net (verilog-string-replace-matches "@" tpl-num nil nil tpl-net))
11092 (setq tpl-net (verilog-string-replace-matches "\\[\\]\\[\\]" dflt-bits nil nil tpl-net))
11093 (setq tpl-net (verilog-string-replace-matches "\\[\\]" vl-bits nil nil tpl-net)))
11095 (indent-to indent-pt)
11097 (unless (and verilog-auto-inst-dot-name
11098 (equal port tpl-net))
11099 (indent-to verilog-auto-inst-column)
11100 (insert "(" tpl-net ")"))
11103 (verilog-read-auto-template-hit tpl-ass)
11104 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
11105 verilog-auto-inst-column))
11106 ;; verilog-insert requires the complete comment in one call - including the newline
11107 (cond ((equal verilog-auto-inst-template-numbers `lhs)
11108 (verilog-insert " // Templated"
11109 " LHS: " (nth 0 tpl-ass)
11111 (verilog-auto-inst-template-numbers
11112 (verilog-insert " // Templated"
11113 " T" (int-to-string (nth 2 tpl-ass))
11114 " L" (int-to-string (nth 3 tpl-ass))
11117 (verilog-insert " // Templated\n"))))
11119 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
11120 verilog-auto-inst-column))
11121 (verilog-insert " // Implicit .\*\n")) ;For some reason the . or * must be escaped...
11124 ;;(verilog-auto-inst-port (list "foo" "[5:0]") 10 (list (list "foo" "a@\"(% (+ @ 1) 4)\"a")) "3")
11125 ;;(x "incom[@\"(+ (* 8 @) 7)\":@\"(* 8 @)\"]")
11126 ;;(x ".out (outgo[@\"(concat (+ (* 8 @) 7) \\\":\\\" ( * 8 @))\"]));")
11128 (defun verilog-auto-inst-port-list (sig-list indent-pt moddecls tpl-list tpl-num for-star par-values)
11129 "For `verilog-auto-inst' print a list of ports using `verilog-auto-inst-port'."
11130 (when verilog-auto-inst-sort
11131 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare)))
11132 (mapc (lambda (port)
11133 (verilog-auto-inst-port port indent-pt moddecls
11134 tpl-list tpl-num for-star par-values))
11137 (defun verilog-auto-inst-first ()
11138 "Insert , etc before first ever port in this instant, as part of \\[verilog-auto-inst]."
11139 ;; Do we need a trailing comma?
11140 ;; There maybe an ifdef or something similar before us. What a mess. Thus
11141 ;; to avoid trouble we only insert on preceding ) or *.
11142 ;; Insert first port on new line
11143 (insert "\n") ;; Must insert before search, so point will move forward if insert comma
11145 (verilog-re-search-backward-quick "[^ \t\n\f]" nil nil)
11146 (when (looking-at ")\\|\\*") ;; Generally don't insert, unless we are fairly sure
11150 (defun verilog-auto-star ()
11151 "Expand SystemVerilog .* pins, as part of \\[verilog-auto].
11153 If `verilog-auto-star-expand' is set, .* pins are treated if they were
11154 AUTOINST statements, otherwise they are ignored. For safety, Verilog mode
11155 will also ignore any .* that are not last in your pin list (this prevents
11156 it from deleting pins following the .* when it expands the AUTOINST.)
11158 On writing your file, unless `verilog-auto-star-save' is set, any
11159 non-templated expanded pins will be removed. You may do this at any time
11160 with \\[verilog-delete-auto-star-implicit].
11162 If you are converting a module to use .* for the first time, you may wish
11163 to use \\[verilog-inject-auto] and then replace the created AUTOINST with .*.
11165 See `verilog-auto-inst' for examples, templates, and more information."
11166 (when (verilog-auto-star-safe)
11167 (verilog-auto-inst)))
11169 (defun verilog-auto-inst ()
11170 "Expand AUTOINST statements, as part of \\[verilog-auto].
11171 Replace the pin connections to an instantiation or interface
11172 declaration with ones automatically derived from the module or
11173 interface header of the instantiated item.
11175 If `verilog-auto-star-expand' is set, also expand SystemVerilog .* ports,
11176 and delete them before saving unless `verilog-auto-star-save' is set.
11177 See `verilog-auto-star' for more information.
11179 The pins are printed in declaration order or alphabetically,
11180 based on the `verilog-auto-inst-sort' variable.
11183 Module names must be resolvable to filenames by adding a
11184 `verilog-library-extensions', and being found in the same directory, or
11185 by changing the variable `verilog-library-flags' or
11186 `verilog-library-directories'. Macros `modname are translated through the
11187 vh-{name} Emacs variable, if that is not found, it just ignores the \\=`.
11189 In templates you must have one signal per line, ending in a ), or ));,
11190 and have proper () nesting, including a final ); to end the template.
11192 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
11194 SystemVerilog multidimensional input/output has only experimental support.
11196 SystemVerilog .name syntax is used if `verilog-auto-inst-dot-name' is set.
11198 Parameters referenced by the instantiation will remain symbolic, unless
11199 `verilog-auto-inst-param-value' is set.
11201 Gate primitives (and/or) may have AUTOINST for the purpose of
11202 AUTOWIRE declarations, etc. Gates are the only case when
11203 position based connections are passed.
11205 The array part of arrayed instances are ignored; this may
11206 result in undesirable default AUTOINST connections; use a
11209 For example, first take the submodule InstModule.v:
11211 module InstModule (o,i);
11214 wire [31:0] o = {32{i}};
11217 This is then used in an upper level module:
11219 module ExampInst (o,i);
11222 InstModule instName
11226 Typing \\[verilog-auto] will make this into:
11228 module ExampInst (o,i);
11231 InstModule instName
11239 Where the list of inputs and outputs came from the inst module.
11243 Unless you are instantiating a module multiple times, or the module is
11244 something trivial like an adder, DO NOT CHANGE SIGNAL NAMES ACROSS HIERARCHY.
11245 It just makes for unmaintainable code. To sanitize signal names, try
11246 vrename from URL `http://www.veripool.org'.
11248 When you need to violate this suggestion there are two ways to list
11249 exceptions, placing them before the AUTOINST, or using templates.
11251 Any ports defined before the /*AUTOINST*/ are not included in the list of
11252 automatics. This is similar to making a template as described below, but
11253 is restricted to simple connections just like you normally make. Also note
11254 that any signals before the AUTOINST will only be picked up by AUTOWIRE if
11255 you have the appropriate // Input or // Output comment, and exactly the
11256 same line formatting as AUTOINST itself uses.
11258 InstModule instName
11260 .i (my_i_dont_mess_with_it),
11268 For multiple instantiations based upon a single template, create a
11269 commented out template:
11271 /* InstModule AUTO_TEMPLATE (
11276 Templates go ABOVE the instantiation(s). When an instantiation is
11277 expanded `verilog-mode' simply searches up for the closest template.
11278 Thus you can have multiple templates for the same module, just alternate
11279 between the template for an instantiation and the instantiation itself.
11280 (For backward compatibility if no template is found above, it
11281 will also look below, but do not use this behavior in new designs.)
11283 The module name must be the same as the name of the module in the
11284 instantiation name, and the code \"AUTO_TEMPLATE\" must be in these exact
11285 words and capitalized. Only signals that must be different for each
11286 instantiation need to be listed.
11288 Inside a template, a [] in a connection name (with nothing else
11289 inside the brackets) will be replaced by the same bus subscript
11290 as it is being connected to, or the [] will be removed if it is
11291 a single bit signal.
11293 Inside a template, a [][] in a connection name will behave
11294 similarly to a [] for scalar or single-dimensional connection;
11295 for a multidimensional connection it will print a comment
11296 similar to that printed when a template is not used. Generally
11297 it is a good idea to do this for all connections in a template,
11298 as then they will work for any width signal, and with AUTOWIRE.
11299 See PTL_BUS becoming PTL_BUSNEW below.
11301 Inside a template, a [] in a connection name (with nothing else inside
11302 the brackets) will be replaced by the same bus subscript as it is being
11303 connected to, or the [] will be removed if it is a single bit signal.
11304 Generally it is a good idea to do this for all connections in a template,
11305 as then they will work for any width signal, and with AUTOWIRE. See
11306 PTL_BUS becoming PTL_BUSNEW below.
11308 If you have a complicated template, set `verilog-auto-inst-template-numbers'
11309 to see which regexps are matching. Don't leave that mode set after
11310 debugging is completed though, it will result in lots of extra differences
11311 and merge conflicts.
11313 Setting `verilog-auto-template-warn-unused' will report errors
11314 if any template lines are unused.
11318 /* InstModule AUTO_TEMPLATE (
11319 .ptl_bus (ptl_busnew[]),
11322 InstModule ms2m (/*AUTOINST*/);
11324 Typing \\[verilog-auto] will make this into:
11326 InstModule ms2m (/*AUTOINST*/
11328 .NotInTemplate (NotInTemplate),
11329 .ptl_bus (ptl_busnew[3:0]), // Templated
11333 Multiple Module Templates:
11335 The same template lines can be applied to multiple modules with
11336 the syntax as follows:
11338 /* InstModuleA AUTO_TEMPLATE
11339 InstModuleB AUTO_TEMPLATE
11340 InstModuleC AUTO_TEMPLATE
11341 InstModuleD AUTO_TEMPLATE (
11342 .ptl_bus (ptl_busnew[]),
11346 Note there is only one AUTO_TEMPLATE opening parenthesis.
11350 It is common to instantiate a cell multiple times, so templates make it
11351 trivial to substitute part of the cell name into the connection name.
11353 /* InstName AUTO_TEMPLATE <optional \"REGEXP\"> (
11355 .sig2 (sigy[@\"(% (+ 1 @) 4)\"]),
11359 If no regular expression is provided immediately after the AUTO_TEMPLATE
11360 keyword, then the @ character in any connection names will be replaced
11361 with the instantiation number; the first digits found in the cell's
11362 instantiation name.
11364 If a regular expression is provided, the @ character will be replaced
11365 with the first \(\) grouping that matches against the cell name. Using a
11366 regexp of \"\\([0-9]+\\)\" provides identical values for @ as when no
11367 regexp is provided. If you use multiple layers of parenthesis,
11368 \"test\\([^0-9]+\\)_\\([0-9]+\\)\" would replace @ with non-number
11369 characters after test and before _, whereas
11370 \"\\(test\\([a-z]+\\)_\\([0-9]+\\)\\)\" would replace @ with the entire
11375 /* InstModule AUTO_TEMPLATE (
11376 .ptl_mapvalidx (ptl_mapvalid[@]),
11377 .ptl_mapvalidp1x (ptl_mapvalid[@\"(% (+ 1 @) 4)\"]),
11380 InstModule ms2m (/*AUTOINST*/);
11382 Typing \\[verilog-auto] will make this into:
11384 InstModule ms2m (/*AUTOINST*/
11386 .ptl_mapvalidx (ptl_mapvalid[2]),
11387 .ptl_mapvalidp1x (ptl_mapvalid[3]));
11389 Note the @ character was replaced with the 2 from \"ms2m\".
11391 Alternatively, using a regular expression for @:
11393 /* InstModule AUTO_TEMPLATE \"_\\([a-z]+\\)\" (
11394 .ptl_mapvalidx (@_ptl_mapvalid),
11395 .ptl_mapvalidp1x (ptl_mapvalid_@),
11398 InstModule ms2_FOO (/*AUTOINST*/);
11399 InstModule ms2_BAR (/*AUTOINST*/);
11401 Typing \\[verilog-auto] will make this into:
11403 InstModule ms2_FOO (/*AUTOINST*/
11405 .ptl_mapvalidx (FOO_ptl_mapvalid),
11406 .ptl_mapvalidp1x (ptl_mapvalid_FOO));
11407 InstModule ms2_BAR (/*AUTOINST*/
11409 .ptl_mapvalidx (BAR_ptl_mapvalid),
11410 .ptl_mapvalidp1x (ptl_mapvalid_BAR));
11415 A template entry of the form
11417 .pci_req\\([0-9]+\\)_l (pci_req_jtag_[\\1]),
11419 will apply an Emacs style regular expression search for any port beginning
11420 in pci_req followed by numbers and ending in _l and connecting that to
11421 the pci_req_jtag_[] net, with the bus subscript coming from what matches
11422 inside the first set of \\( \\). Thus pci_req2_l becomes pci_req_jtag_[2].
11424 Since \\([0-9]+\\) is so common and ugly to read, a @ in the port name
11425 does the same thing. (Note a @ in the connection/replacement text is
11426 completely different -- still use \\1 there!) Thus this is the same as
11427 the above template:
11429 .pci_req@_l (pci_req_jtag_[\\1]),
11431 Here's another example to remove the _l, useful when naming conventions
11432 specify _ alone to mean active low. Note the use of [] to keep the bus
11435 .\\(.*\\)_l (\\1_[]),
11439 First any regular expression template is expanded.
11441 If the syntax @\"( ... )\" is found in a connection, the expression in
11442 quotes will be evaluated as a Lisp expression, with @ replaced by the
11443 instantiation number. The MAPVALIDP1X example above would put @+1 modulo
11444 4 into the brackets. Quote all double-quotes inside the expression with
11445 a leading backslash (\\\"...\\\"); or if the Lisp template is also a
11446 regexp template backslash the backslash quote (\\\\\"...\\\\\").
11448 There are special variables defined that are useful in these
11451 vl-name Name portion of the input/output port.
11452 vl-bits Bus bits portion of the input/output port ('[2:0]').
11453 vl-mbits Multidimensional array bits for port ('[2:0][3:0]').
11454 vl-width Width of the input/output port ('3' for [2:0]).
11455 May be a (...) expression if bits isn't a constant.
11456 vl-dir Direction of the pin input/output/inout/interface.
11457 vl-modport The modport, if an interface with a modport.
11458 vl-cell-type Module name/type of the cell ('InstModule').
11459 vl-cell-name Instance name of the cell ('instName').
11461 Normal Lisp variables may be used in expressions. See
11462 `verilog-read-defines' which can set vh-{definename} variables for use
11463 here. Also, any comments of the form:
11465 /*AUTO_LISP(setq foo 1)*/
11467 will evaluate any Lisp expression inside the parenthesis between the
11468 beginning of the buffer and the point of the AUTOINST. This allows
11469 functions to be defined or variables to be changed between instantiations.
11470 (See also `verilog-auto-insert-lisp' if you want the output from your
11471 lisp function to be inserted.)
11473 Note that when using lisp expressions errors may occur when @ is not a
11474 number; you may need to use the standard Emacs Lisp functions
11475 `number-to-string' and `string-to-number'.
11477 After the evaluation is completed, @ substitution and [] substitution
11480 For more information see the \\[verilog-faq] and forums at URL
11481 `http://www.veripool.org'."
11484 (let* ((pt (point))
11485 (for-star (save-excursion (backward-char 2) (looking-at "\\.\\*")))
11486 (indent-pt (save-excursion (verilog-backward-open-paren)
11487 (1+ (current-column))))
11488 (verilog-auto-inst-column (max verilog-auto-inst-column
11489 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
11490 (modi (verilog-modi-current))
11491 (moddecls (verilog-modi-get-decls modi))
11492 submod submodi submoddecls
11493 inst skip-pins tpl-list tpl-num did-first par-values)
11495 ;; Find module name that is instantiated
11496 (setq submod (verilog-read-inst-module)
11497 inst (verilog-read-inst-name)
11498 vl-cell-type submod
11500 skip-pins (aref (verilog-read-inst-pins) 0))
11502 ;; Parse any AUTO_LISP() before here
11503 (verilog-read-auto-lisp (point-min) pt)
11505 ;; Read parameters (after AUTO_LISP)
11506 (setq par-values (and verilog-auto-inst-param-value
11507 (verilog-read-inst-param-value)))
11509 ;; Lookup position, etc of submodule
11510 ;; Note this may raise an error
11511 (when (and (not (member submod verilog-gate-keywords))
11512 (setq submodi (verilog-modi-lookup submod t)))
11513 (setq submoddecls (verilog-modi-get-decls submodi))
11514 ;; If there's a number in the instantiation, it may be an argument to the
11515 ;; automatic variable instantiation program.
11516 (let* ((tpl-info (verilog-read-auto-template submod))
11517 (tpl-regexp (aref tpl-info 0)))
11518 (setq tpl-num (if (verilog-string-match-fold tpl-regexp inst)
11519 (match-string 1 inst)
11521 tpl-list (aref tpl-info 1)))
11522 ;; Find submodule's signals and dump
11523 (let ((sig-list (and (equal (verilog-modi-get-type submodi) "interface")
11524 (verilog-signals-not-in
11525 (verilog-decls-get-vars submoddecls)
11527 (vl-dir "interfaced"))
11528 (when (and sig-list
11529 verilog-auto-inst-interfaced-ports)
11530 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11531 ;; Note these are searched for in verilog-read-sub-decls.
11532 (verilog-insert-indent "// Interfaced\n")
11533 (verilog-auto-inst-port-list sig-list indent-pt moddecls
11534 tpl-list tpl-num for-star par-values)))
11535 (let ((sig-list (verilog-signals-not-in
11536 (verilog-decls-get-interfaces submoddecls)
11538 (vl-dir "interface"))
11540 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11541 ;; Note these are searched for in verilog-read-sub-decls.
11542 (verilog-insert-indent "// Interfaces\n")
11543 (verilog-auto-inst-port-list sig-list indent-pt moddecls
11544 tpl-list tpl-num for-star par-values)))
11545 (let ((sig-list (verilog-signals-not-in
11546 (verilog-decls-get-outputs submoddecls)
11550 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11551 (verilog-insert-indent "// Outputs\n")
11552 (verilog-auto-inst-port-list sig-list indent-pt moddecls
11553 tpl-list tpl-num for-star par-values)))
11554 (let ((sig-list (verilog-signals-not-in
11555 (verilog-decls-get-inouts submoddecls)
11559 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11560 (verilog-insert-indent "// Inouts\n")
11561 (verilog-auto-inst-port-list sig-list indent-pt moddecls
11562 tpl-list tpl-num for-star par-values)))
11563 (let ((sig-list (verilog-signals-not-in
11564 (verilog-decls-get-inputs submoddecls)
11568 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11569 (verilog-insert-indent "// Inputs\n")
11570 (verilog-auto-inst-port-list sig-list indent-pt moddecls
11571 tpl-list tpl-num for-star par-values)))
11575 (re-search-backward "," pt t)
11578 (search-forward "\n") ;; Added by inst-port
11580 (if (search-forward ")" nil t) ;; From user, moved up a line
11582 (if (search-forward ";" nil t) ;; Don't error if user had syntax error and forgot it
11583 (delete-char -1)))))))))
11585 (defun verilog-auto-inst-param ()
11586 "Expand AUTOINSTPARAM statements, as part of \\[verilog-auto].
11587 Replace the parameter connections to an instantiation with ones
11588 automatically derived from the module header of the instantiated netlist.
11590 See \\[verilog-auto-inst] for limitations, and templates to customize the
11593 For example, first take the submodule InstModule.v:
11595 module InstModule (o,i);
11599 This is then used in an upper level module:
11601 module ExampInst (o,i);
11603 InstModule #(/*AUTOINSTPARAM*/)
11604 instName (/*AUTOINST*/);
11607 Typing \\[verilog-auto] will make this into:
11609 module ExampInst (o,i);
11612 InstModule #(/*AUTOINSTPARAM*/
11615 instName (/*AUTOINST*/);
11618 Where the list of parameter connections come from the inst module.
11622 You can customize the parameter connections using AUTO_TEMPLATEs,
11623 just as you would with \\[verilog-auto-inst]."
11626 (let* ((pt (point))
11627 (indent-pt (save-excursion (verilog-backward-open-paren)
11628 (1+ (current-column))))
11629 (verilog-auto-inst-column (max verilog-auto-inst-column
11630 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
11631 (modi (verilog-modi-current))
11632 (moddecls (verilog-modi-get-decls modi))
11633 submod submodi submoddecls
11634 inst skip-pins tpl-list tpl-num did-first)
11635 ;; Find module name that is instantiated
11636 (setq submod (save-excursion
11637 ;; Get to the point where AUTOINST normally is to read the module
11638 (verilog-re-search-forward-quick "[(;]" nil nil)
11639 (verilog-read-inst-module))
11640 inst (save-excursion
11641 ;; Get to the point where AUTOINST normally is to read the module
11642 (verilog-re-search-forward-quick "[(;]" nil nil)
11643 (verilog-read-inst-name))
11644 vl-cell-type submod
11646 skip-pins (aref (verilog-read-inst-pins) 0))
11648 ;; Parse any AUTO_LISP() before here
11649 (verilog-read-auto-lisp (point-min) pt)
11651 ;; Lookup position, etc of submodule
11652 ;; Note this may raise an error
11653 (when (setq submodi (verilog-modi-lookup submod t))
11654 (setq submoddecls (verilog-modi-get-decls submodi))
11655 ;; If there's a number in the instantiation, it may be an argument to the
11656 ;; automatic variable instantiation program.
11657 (let* ((tpl-info (verilog-read-auto-template submod))
11658 (tpl-regexp (aref tpl-info 0)))
11659 (setq tpl-num (if (verilog-string-match-fold tpl-regexp inst)
11660 (match-string 1 inst)
11662 tpl-list (aref tpl-info 1)))
11663 ;; Find submodule's signals and dump
11664 (let ((sig-list (verilog-signals-not-in
11665 (verilog-decls-get-gparams submoddecls)
11667 (vl-dir "parameter"))
11669 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11670 ;; Note these are searched for in verilog-read-sub-decls.
11671 (verilog-insert-indent "// Parameters\n")
11672 (verilog-auto-inst-port-list sig-list indent-pt moddecls
11673 tpl-list tpl-num nil nil)))
11677 (re-search-backward "," pt t)
11680 (search-forward "\n") ;; Added by inst-port
11682 (if (search-forward ")" nil t) ;; From user, moved up a line
11683 (delete-char -1)))))))))
11685 (defun verilog-auto-reg ()
11686 "Expand AUTOREG statements, as part of \\[verilog-auto].
11687 Make reg statements for any output that isn't already declared,
11688 and isn't a wire output from a block. `verilog-auto-wire-type'
11689 may be used to change the datatype of the declarations.
11692 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
11694 This does NOT work on memories, declare those yourself.
11698 module ExampReg (o,i);
11705 Typing \\[verilog-auto] will make this into:
11707 module ExampReg (o,i);
11711 // Beginning of automatic regs (for this module's undeclared outputs)
11713 // End of automatics
11717 ;; Point must be at insertion point.
11718 (let* ((indent-pt (current-indentation))
11719 (modi (verilog-modi-current))
11720 (moddecls (verilog-modi-get-decls modi))
11721 (modsubdecls (verilog-modi-get-sub-decls modi))
11722 (sig-list (verilog-signals-not-in
11723 (verilog-decls-get-outputs moddecls)
11724 (append (verilog-signals-with ;; ignore typed signals
11726 (verilog-decls-get-outputs moddecls))
11727 (verilog-decls-get-vars moddecls)
11728 (verilog-decls-get-assigns moddecls)
11729 (verilog-decls-get-consts moddecls)
11730 (verilog-decls-get-gparams moddecls)
11731 (verilog-subdecls-get-interfaced modsubdecls)
11732 (verilog-subdecls-get-outputs modsubdecls)
11733 (verilog-subdecls-get-inouts modsubdecls)))))
11735 (verilog-forward-or-insert-line)
11736 (verilog-insert-indent "// Beginning of automatic regs (for this module's undeclared outputs)\n")
11737 (verilog-insert-definition modi sig-list "reg" indent-pt nil)
11738 (verilog-insert-indent "// End of automatics\n")))))
11740 (defun verilog-auto-reg-input ()
11741 "Expand AUTOREGINPUT statements, as part of \\[verilog-auto].
11742 Make reg statements instantiation inputs that aren't already declared.
11743 This is useful for making a top level shell for testing the module that is
11744 to be instantiated.
11747 This ONLY detects inputs of AUTOINSTants (see `verilog-read-sub-decls').
11749 This does NOT work on memories, declare those yourself.
11751 An example (see `verilog-auto-inst' for what else is going on here):
11753 module ExampRegInput (o,i);
11757 InstModule instName
11761 Typing \\[verilog-auto] will make this into:
11763 module ExampRegInput (o,i);
11767 // Beginning of automatic reg inputs (for undeclared ...
11768 reg [31:0] iv; // From inst of inst.v
11769 // End of automatics
11770 InstModule instName
11778 ;; Point must be at insertion point.
11779 (let* ((indent-pt (current-indentation))
11780 (modi (verilog-modi-current))
11781 (moddecls (verilog-modi-get-decls modi))
11782 (modsubdecls (verilog-modi-get-sub-decls modi))
11783 (sig-list (verilog-signals-combine-bus
11784 (verilog-signals-not-in
11785 (append (verilog-subdecls-get-inputs modsubdecls)
11786 (verilog-subdecls-get-inouts modsubdecls))
11787 (append (verilog-decls-get-signals moddecls)
11788 (verilog-decls-get-assigns moddecls))))))
11790 (verilog-forward-or-insert-line)
11791 (verilog-insert-indent "// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)\n")
11792 (verilog-insert-definition modi sig-list "reg" indent-pt nil)
11793 (verilog-insert-indent "// End of automatics\n")))))
11795 (defun verilog-auto-logic-setup ()
11796 "Prepare variables due to AUTOLOGIC."
11797 (unless verilog-auto-wire-type
11798 (set (make-local-variable 'verilog-auto-wire-type)
11801 (defun verilog-auto-logic ()
11802 "Expand AUTOLOGIC statements, as part of \\[verilog-auto].
11803 Make wire statements using the SystemVerilog logic keyword.
11804 This is currently equivalent to:
11808 with the below at the bottom of the file
11810 // Local Variables:
11811 // verilog-auto-logic-type:\"logic\"
11814 In the future AUTOLOGIC may declare additional identifiers,
11815 while AUTOWIRE will not."
11817 (verilog-auto-logic-setup)
11818 (verilog-auto-wire)))
11820 (defun verilog-auto-wire ()
11821 "Expand AUTOWIRE statements, as part of \\[verilog-auto].
11822 Make wire statements for instantiations outputs that aren't
11823 already declared. `verilog-auto-wire-type' may be used to change
11824 the datatype of the declarations.
11827 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'),
11828 and all buses must have widths, such as those from AUTOINST, or using []
11831 This does NOT work on memories or SystemVerilog .name connections,
11832 declare those yourself.
11834 Verilog mode will add \"Couldn't Merge\" comments to signals it cannot
11835 determine how to bus together. This occurs when you have ports with
11836 non-numeric or non-sequential bus subscripts. If Verilog mode
11837 mis-guessed, you'll have to declare them yourself.
11839 An example (see `verilog-auto-inst' for what else is going on here):
11841 module ExampWire (o,i);
11845 InstModule instName
11849 Typing \\[verilog-auto] will make this into:
11851 module ExampWire (o,i);
11855 // Beginning of automatic wires
11856 wire [31:0] ov; // From inst of inst.v
11857 // End of automatics
11858 InstModule instName
11867 ;; Point must be at insertion point.
11868 (let* ((indent-pt (current-indentation))
11869 (modi (verilog-modi-current))
11870 (moddecls (verilog-modi-get-decls modi))
11871 (modsubdecls (verilog-modi-get-sub-decls modi))
11872 (sig-list (verilog-signals-combine-bus
11873 (verilog-signals-not-in
11874 (append (verilog-subdecls-get-outputs modsubdecls)
11875 (verilog-subdecls-get-inouts modsubdecls))
11876 (verilog-decls-get-signals moddecls)))))
11878 (verilog-forward-or-insert-line)
11879 (verilog-insert-indent "// Beginning of automatic wires (for undeclared instantiated-module outputs)\n")
11880 (verilog-insert-definition modi sig-list "wire" indent-pt nil)
11881 (verilog-insert-indent "// End of automatics\n")
11882 ;; We used to optionally call verilog-pretty-declarations and
11883 ;; verilog-pretty-expr here, but it's too slow on huge modules,
11884 ;; plus makes everyone's module change. Finally those call
11885 ;; syntax-ppss which is broken when change hooks are disabled.
11888 (defun verilog-auto-output ()
11889 "Expand AUTOOUTPUT statements, as part of \\[verilog-auto].
11890 Make output statements for any output signal from an /*AUTOINST*/ that
11891 isn't an input to another AUTOINST. This is useful for modules which
11892 only instantiate other modules.
11895 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
11897 If placed inside the parenthesis of a module declaration, it creates
11898 Verilog 2001 style, else uses Verilog 1995 style.
11900 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
11901 instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
11903 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
11905 Types are added to declarations if an AUTOLOGIC or
11906 `verilog-auto-wire-type' is set to logic.
11908 Signals matching `verilog-auto-output-ignore-regexp' are not included.
11910 An example (see `verilog-auto-inst' for what else is going on here):
11912 module ExampOutput (ov,i);
11915 InstModule instName
11919 Typing \\[verilog-auto] will make this into:
11921 module ExampOutput (ov,i);
11924 // Beginning of automatic outputs (from unused autoinst outputs)
11925 output [31:0] ov; // From inst of inst.v
11926 // End of automatics
11927 InstModule instName
11935 You may also provide an optional regular expression, in which case only
11936 signals matching the regular expression will be included. For example the
11937 same expansion will result from only extracting outputs starting with ov:
11939 /*AUTOOUTPUT(\"^ov\")*/"
11941 ;; Point must be at insertion point.
11942 (let* ((indent-pt (current-indentation))
11943 (params (verilog-read-auto-params 0 1))
11944 (regexp (nth 0 params))
11945 (v2k (verilog-in-paren-quick))
11946 (modi (verilog-modi-current))
11947 (moddecls (verilog-modi-get-decls modi))
11948 (modsubdecls (verilog-modi-get-sub-decls modi))
11949 (sig-list (verilog-signals-not-in
11950 (verilog-subdecls-get-outputs modsubdecls)
11951 (append (verilog-decls-get-outputs moddecls)
11952 (verilog-decls-get-inouts moddecls)
11953 (verilog-decls-get-inputs moddecls)
11954 (verilog-subdecls-get-inputs modsubdecls)
11955 (verilog-subdecls-get-inouts modsubdecls)))))
11957 (setq sig-list (verilog-signals-matching-regexp
11959 (setq sig-list (verilog-signals-not-matching-regexp
11960 sig-list verilog-auto-output-ignore-regexp))
11961 (verilog-forward-or-insert-line)
11962 (when v2k (verilog-repair-open-comma))
11964 (verilog-insert-indent "// Beginning of automatic outputs (from unused autoinst outputs)\n")
11965 (verilog-insert-definition modi sig-list "output" indent-pt v2k)
11966 (verilog-insert-indent "// End of automatics\n"))
11967 (when v2k (verilog-repair-close-comma)))))
11969 (defun verilog-auto-output-every ()
11970 "Expand AUTOOUTPUTEVERY statements, as part of \\[verilog-auto].
11971 Make output statements for any signals that aren't primary inputs or
11972 outputs already. This makes every signal in the design an output. This is
11973 useful to get Synopsys to preserve every signal in the design, since it
11974 won't optimize away the outputs.
11978 module ExampOutputEvery (o,i,tempa,tempb);
11981 /*AUTOOUTPUTEVERY*/
11983 wire tempb = tempa;
11987 Typing \\[verilog-auto] will make this into:
11989 module ExampOutputEvery (o,i,tempa,tempb);
11992 /*AUTOOUTPUTEVERY*/
11993 // Beginning of automatic outputs (every signal)
11996 // End of automatics
11998 wire tempb = tempa;
12002 You may also provide an optional regular expression, in which case only
12003 signals matching the regular expression will be included. For example the
12004 same expansion will result from only extracting outputs starting with ov:
12006 /*AUTOOUTPUTEVERY(\"^ov\")*/"
12008 ;;Point must be at insertion point
12009 (let* ((indent-pt (current-indentation))
12010 (params (verilog-read-auto-params 0 1))
12011 (regexp (nth 0 params))
12012 (v2k (verilog-in-paren-quick))
12013 (modi (verilog-modi-current))
12014 (moddecls (verilog-modi-get-decls modi))
12015 (sig-list (verilog-signals-combine-bus
12016 (verilog-signals-not-in
12017 (verilog-decls-get-signals moddecls)
12018 (verilog-decls-get-ports moddecls)))))
12020 (setq sig-list (verilog-signals-matching-regexp
12022 (setq sig-list (verilog-signals-not-matching-regexp
12023 sig-list verilog-auto-output-ignore-regexp))
12024 (verilog-forward-or-insert-line)
12025 (when v2k (verilog-repair-open-comma))
12027 (verilog-insert-indent "// Beginning of automatic outputs (every signal)\n")
12028 (verilog-insert-definition modi sig-list "output" indent-pt v2k)
12029 (verilog-insert-indent "// End of automatics\n"))
12030 (when v2k (verilog-repair-close-comma)))))
12032 (defun verilog-auto-input ()
12033 "Expand AUTOINPUT statements, as part of \\[verilog-auto].
12034 Make input statements for any input signal into an /*AUTOINST*/ that
12035 isn't declared elsewhere inside the module. This is useful for modules which
12036 only instantiate other modules.
12039 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
12041 If placed inside the parenthesis of a module declaration, it creates
12042 Verilog 2001 style, else uses Verilog 1995 style.
12044 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
12045 instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
12047 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
12049 Types are added to declarations if an AUTOLOGIC or
12050 `verilog-auto-wire-type' is set to logic.
12052 Signals matching `verilog-auto-input-ignore-regexp' are not included.
12054 An example (see `verilog-auto-inst' for what else is going on here):
12056 module ExampInput (ov,i);
12059 InstModule instName
12063 Typing \\[verilog-auto] will make this into:
12065 module ExampInput (ov,i);
12068 // Beginning of automatic inputs (from unused autoinst inputs)
12069 input i; // From inst of inst.v
12070 // End of automatics
12071 InstModule instName
12079 You may also provide an optional regular expression, in which case only
12080 signals matching the regular expression will be included. For example the
12081 same expansion will result from only extracting inputs starting with i:
12083 /*AUTOINPUT(\"^i\")*/"
12085 (let* ((indent-pt (current-indentation))
12086 (params (verilog-read-auto-params 0 1))
12087 (regexp (nth 0 params))
12088 (v2k (verilog-in-paren-quick))
12089 (modi (verilog-modi-current))
12090 (moddecls (verilog-modi-get-decls modi))
12091 (modsubdecls (verilog-modi-get-sub-decls modi))
12092 (sig-list (verilog-signals-not-in
12093 (verilog-subdecls-get-inputs modsubdecls)
12094 (append (verilog-decls-get-inputs moddecls)
12095 (verilog-decls-get-inouts moddecls)
12096 (verilog-decls-get-outputs moddecls)
12097 (verilog-decls-get-vars moddecls)
12098 (verilog-decls-get-consts moddecls)
12099 (verilog-decls-get-gparams moddecls)
12100 (verilog-subdecls-get-interfaced modsubdecls)
12101 (verilog-subdecls-get-outputs modsubdecls)
12102 (verilog-subdecls-get-inouts modsubdecls)))))
12104 (setq sig-list (verilog-signals-matching-regexp
12106 (setq sig-list (verilog-signals-not-matching-regexp
12107 sig-list verilog-auto-input-ignore-regexp))
12108 (verilog-forward-or-insert-line)
12109 (when v2k (verilog-repair-open-comma))
12111 (verilog-insert-indent "// Beginning of automatic inputs (from unused autoinst inputs)\n")
12112 (verilog-insert-definition modi sig-list "input" indent-pt v2k)
12113 (verilog-insert-indent "// End of automatics\n"))
12114 (when v2k (verilog-repair-close-comma)))))
12116 (defun verilog-auto-inout ()
12117 "Expand AUTOINOUT statements, as part of \\[verilog-auto].
12118 Make inout statements for any inout signal in an /*AUTOINST*/ that
12119 isn't declared elsewhere inside the module.
12122 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
12124 If placed inside the parenthesis of a module declaration, it creates
12125 Verilog 2001 style, else uses Verilog 1995 style.
12127 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
12128 instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
12130 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
12132 Types are added to declarations if an AUTOLOGIC or
12133 `verilog-auto-wire-type' is set to logic.
12135 Signals matching `verilog-auto-inout-ignore-regexp' are not included.
12137 An example (see `verilog-auto-inst' for what else is going on here):
12139 module ExampInout (ov,i);
12142 InstModule instName
12146 Typing \\[verilog-auto] will make this into:
12148 module ExampInout (ov,i);
12151 // Beginning of automatic inouts (from unused autoinst inouts)
12152 inout [31:0] ov; // From inst of inst.v
12153 // End of automatics
12154 InstModule instName
12162 You may also provide an optional regular expression, in which case only
12163 signals matching the regular expression will be included. For example the
12164 same expansion will result from only extracting inouts starting with i:
12166 /*AUTOINOUT(\"^i\")*/"
12168 ;; Point must be at insertion point.
12169 (let* ((indent-pt (current-indentation))
12170 (params (verilog-read-auto-params 0 1))
12171 (regexp (nth 0 params))
12172 (v2k (verilog-in-paren-quick))
12173 (modi (verilog-modi-current))
12174 (moddecls (verilog-modi-get-decls modi))
12175 (modsubdecls (verilog-modi-get-sub-decls modi))
12176 (sig-list (verilog-signals-not-in
12177 (verilog-subdecls-get-inouts modsubdecls)
12178 (append (verilog-decls-get-outputs moddecls)
12179 (verilog-decls-get-inouts moddecls)
12180 (verilog-decls-get-inputs moddecls)
12181 (verilog-subdecls-get-inputs modsubdecls)
12182 (verilog-subdecls-get-outputs modsubdecls)))))
12184 (setq sig-list (verilog-signals-matching-regexp
12186 (setq sig-list (verilog-signals-not-matching-regexp
12187 sig-list verilog-auto-inout-ignore-regexp))
12188 (verilog-forward-or-insert-line)
12189 (when v2k (verilog-repair-open-comma))
12191 (verilog-insert-indent "// Beginning of automatic inouts (from unused autoinst inouts)\n")
12192 (verilog-insert-definition modi sig-list "inout" indent-pt v2k)
12193 (verilog-insert-indent "// End of automatics\n"))
12194 (when v2k (verilog-repair-close-comma)))))
12196 (defun verilog-auto-inout-module (&optional complement all-in)
12197 "Expand AUTOINOUTMODULE statements, as part of \\[verilog-auto].
12198 Take input/output/inout statements from the specified module and insert
12199 into the current module. This is useful for making null templates and
12200 shell modules which need to have identical I/O with another module.
12201 Any I/O which are already defined in this module will not be redefined.
12202 For the complement of this function, see `verilog-auto-inout-comp',
12203 and to make monitors with all inputs, see `verilog-auto-inout-in'.
12206 If placed inside the parenthesis of a module declaration, it creates
12207 Verilog 2001 style, else uses Verilog 1995 style.
12209 Concatenation and outputting partial buses is not supported.
12211 Module names must be resolvable to filenames. See `verilog-auto-inst'.
12213 Signals are not inserted in the same order as in the original module,
12214 though they will appear to be in the same order to an AUTOINST
12215 instantiating either module.
12217 Signals declared as \"output reg\" or \"output wire\" etc will
12218 lose the wire/reg declaration so that shell modules may
12219 generate those outputs differently. However, \"output logic\"
12224 module ExampShell (/*AUTOARG*/);
12225 /*AUTOINOUTMODULE(\"ExampMain\")*/
12228 module ExampMain (i,o,io);
12234 Typing \\[verilog-auto] will make this into:
12236 module ExampShell (/*AUTOARG*/i,o,io);
12237 /*AUTOINOUTMODULE(\"ExampMain\")*/
12238 // Beginning of automatic in/out/inouts (from specific module)
12242 // End of automatics
12245 You may also provide an optional regular expression, in which case only
12246 signals matching the regular expression will be included. For example the
12247 same expansion will result from only extracting signals starting with i:
12249 /*AUTOINOUTMODULE(\"ExampMain\",\"^i\")*/
12251 You may also provide an optional third argument regular
12252 expression, in which case only signals which have that pin
12253 direction and data type matching that regular expression will be
12254 included. This matches against everything before the signal name
12255 in the declaration, for example against \"input\" (single
12256 bit), \"output logic\" (direction and type) or
12257 \"output [1:0]\" (direction and implicit type). You also
12258 probably want to skip spaces in your regexp.
12260 For example, the below will result in matching the output \"o\"
12261 against the previous example's module:
12263 /*AUTOINOUTMODULE(\"ExampMain\",\"\",\"^output.*\")*/
12265 You may also provide an optional fourth argument regular
12266 expression, which if not \"\" only signals which do NOT match
12267 that expression are included."
12268 ;; Beware spacing of quotes in above as can mess up Emacs indenter
12270 (let* ((params (verilog-read-auto-params 1 4))
12271 (submod (nth 0 params))
12272 (regexp (nth 1 params))
12273 (direction-re (nth 2 params))
12274 (not-re (nth 3 params))
12276 ;; Lookup position, etc of co-module
12277 ;; Note this may raise an error
12278 (when (setq submodi (verilog-modi-lookup submod t))
12279 (let* ((indent-pt (current-indentation))
12280 (v2k (verilog-in-paren-quick))
12281 (modi (verilog-modi-current))
12282 (moddecls (verilog-modi-get-decls modi))
12283 (submoddecls (verilog-modi-get-decls submodi))
12284 (sig-list-i (verilog-signals-not-in
12287 (verilog-decls-get-inputs submoddecls)
12288 (verilog-decls-get-inouts submoddecls)
12289 (verilog-decls-get-outputs submoddecls)))
12291 (verilog-decls-get-outputs submoddecls))
12292 (t (verilog-decls-get-inputs submoddecls)))
12293 (append (verilog-decls-get-inputs moddecls))))
12294 (sig-list-o (verilog-signals-not-in
12297 (verilog-decls-get-inputs submoddecls))
12298 (t (verilog-decls-get-outputs submoddecls)))
12299 (append (verilog-decls-get-outputs moddecls))))
12300 (sig-list-io (verilog-signals-not-in
12302 (t (verilog-decls-get-inouts submoddecls)))
12303 (append (verilog-decls-get-inouts moddecls))))
12304 (sig-list-if (verilog-signals-not-in
12305 (verilog-decls-get-interfaces submoddecls)
12306 (append (verilog-decls-get-interfaces moddecls)))))
12308 (setq sig-list-i (verilog-signals-edit-wire-reg
12309 (verilog-signals-not-matching-regexp
12310 (verilog-signals-matching-dir-re
12311 (verilog-signals-matching-regexp sig-list-i regexp)
12312 "input" direction-re) not-re))
12313 sig-list-o (verilog-signals-edit-wire-reg
12314 (verilog-signals-not-matching-regexp
12315 (verilog-signals-matching-dir-re
12316 (verilog-signals-matching-regexp sig-list-o regexp)
12317 "output" direction-re) not-re))
12318 sig-list-io (verilog-signals-edit-wire-reg
12319 (verilog-signals-not-matching-regexp
12320 (verilog-signals-matching-dir-re
12321 (verilog-signals-matching-regexp sig-list-io regexp)
12322 "inout" direction-re) not-re))
12323 sig-list-if (verilog-signals-not-matching-regexp
12324 (verilog-signals-matching-dir-re
12325 (verilog-signals-matching-regexp sig-list-if regexp)
12326 "interface" direction-re) not-re))
12327 (when v2k (verilog-repair-open-comma))
12328 (when (or sig-list-i sig-list-o sig-list-io sig-list-if)
12329 (verilog-insert-indent "// Beginning of automatic in/out/inouts (from specific module)\n")
12330 ;; Don't sort them so an upper AUTOINST will match the main module
12331 (verilog-insert-definition modi sig-list-o "output" indent-pt v2k t)
12332 (verilog-insert-definition modi sig-list-io "inout" indent-pt v2k t)
12333 (verilog-insert-definition modi sig-list-i "input" indent-pt v2k t)
12334 (verilog-insert-definition modi sig-list-if "interface" indent-pt v2k t)
12335 (verilog-insert-indent "// End of automatics\n"))
12336 (when v2k (verilog-repair-close-comma)))))))
12338 (defun verilog-auto-inout-comp ()
12339 "Expand AUTOINOUTCOMP statements, as part of \\[verilog-auto].
12340 Take input/output/inout statements from the specified module and
12341 insert the inverse into the current module (inputs become outputs
12342 and vice-versa.) This is useful for making test and stimulus
12343 modules which need to have complementing I/O with another module.
12344 Any I/O which are already defined in this module will not be
12345 redefined. For the complement of this function, see
12346 `verilog-auto-inout-module'.
12349 If placed inside the parenthesis of a module declaration, it creates
12350 Verilog 2001 style, else uses Verilog 1995 style.
12352 Concatenation and outputting partial buses is not supported.
12354 Module names must be resolvable to filenames. See `verilog-auto-inst'.
12356 Signals are not inserted in the same order as in the original module,
12357 though they will appear to be in the same order to an AUTOINST
12358 instantiating either module.
12362 module ExampShell (/*AUTOARG*/);
12363 /*AUTOINOUTCOMP(\"ExampMain\")*/
12366 module ExampMain (i,o,io);
12372 Typing \\[verilog-auto] will make this into:
12374 module ExampShell (/*AUTOARG*/i,o,io);
12375 /*AUTOINOUTCOMP(\"ExampMain\")*/
12376 // Beginning of automatic in/out/inouts (from specific module)
12380 // End of automatics
12383 You may also provide an optional regular expression, in which case only
12384 signals matching the regular expression will be included. For example the
12385 same expansion will result from only extracting signals starting with i:
12387 /*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/
12389 You may also provide an optional third argument regular
12390 expression, in which case only signals which have that pin
12391 direction and data type matching that regular expression will be
12392 included. This matches against everything before the signal name
12393 in the declaration, for example against \"input\" (single
12394 bit), \"output logic\" (direction and type)
12395 or \"output [1:0]\" (direction and implicit type). You also
12396 probably want to skip spaces in your regexp.
12398 For example, the below will result in matching the output \"o\"
12399 against the previous example's module:
12401 /*AUTOINOUTCOMP(\"ExampMain\",\"\",\"^output.*\")*/
12403 You may also provide an optional fourth argument regular
12404 expression, which if not \"\" only signals which do NOT match
12405 that expression are included."
12406 ;; Beware spacing of quotes in above as can mess up Emacs indenter
12407 (verilog-auto-inout-module t nil))
12409 (defun verilog-auto-inout-in ()
12410 "Expand AUTOINOUTIN statements, as part of \\[verilog-auto].
12411 Take input/output/inout statements from the specified module and
12412 insert them as all inputs into the current module. This is
12413 useful for making monitor modules which need to see all signals
12414 as inputs based on another module. Any I/O which are already
12415 defined in this module will not be redefined. See also
12416 `verilog-auto-inout-module'.
12419 If placed inside the parenthesis of a module declaration, it creates
12420 Verilog 2001 style, else uses Verilog 1995 style.
12422 Concatenation and outputting partial buses is not supported.
12424 Module names must be resolvable to filenames. See `verilog-auto-inst'.
12426 Signals are not inserted in the same order as in the original module,
12427 though they will appear to be in the same order to an AUTOINST
12428 instantiating either module.
12432 module ExampShell (/*AUTOARG*/);
12433 /*AUTOINOUTIN(\"ExampMain\")*/
12436 module ExampMain (i,o,io);
12442 Typing \\[verilog-auto] will make this into:
12444 module ExampShell (/*AUTOARG*/i,o,io);
12445 /*AUTOINOUTIN(\"ExampMain\")*/
12446 // Beginning of automatic in/out/inouts (from specific module)
12450 // End of automatics
12453 You may also provide an optional regular expression, in which case only
12454 signals matching the regular expression will be included. For example the
12455 same expansion will result from only extracting signals starting with i:
12457 /*AUTOINOUTIN(\"ExampMain\",\"^i\")*/"
12458 (verilog-auto-inout-module nil t))
12460 (defun verilog-auto-inout-param ()
12461 "Expand AUTOINOUTPARAM statements, as part of \\[verilog-auto].
12462 Take input/output/inout statements from the specified module and insert
12463 into the current module. This is useful for making null templates and
12464 shell modules which need to have identical I/O with another module.
12465 Any I/O which are already defined in this module will not be redefined.
12466 For the complement of this function, see `verilog-auto-inout-comp',
12467 and to make monitors with all inputs, see `verilog-auto-inout-in'.
12470 If placed inside the parenthesis of a module declaration, it creates
12471 Verilog 2001 style, else uses Verilog 1995 style.
12473 Module names must be resolvable to filenames. See `verilog-auto-inst'.
12475 Parameters are inserted in the same order as in the original module.
12477 Parameters do not have values, which is SystemVerilog 2009 syntax.
12481 module ExampShell ();
12482 /*AUTOINOUTPARAM(\"ExampMain\")*/
12485 module ExampMain ();
12486 parameter PARAM = 22;
12489 Typing \\[verilog-auto] will make this into:
12491 module ExampShell (/*AUTOARG*/i,o,io);
12492 /*AUTOINOUTPARAM(\"ExampMain\")*/
12493 // Beginning of automatic parameters (from specific module)
12495 // End of automatics
12498 You may also provide an optional regular expression, in which case only
12499 parameters matching the regular expression will be included. For example the
12500 same expansion will result from only extracting parameters starting with i:
12502 /*AUTOINOUTPARAM(\"ExampMain\",\"^i\")*/"
12504 (let* ((params (verilog-read-auto-params 1 2))
12505 (submod (nth 0 params))
12506 (regexp (nth 1 params))
12508 ;; Lookup position, etc of co-module
12509 ;; Note this may raise an error
12510 (when (setq submodi (verilog-modi-lookup submod t))
12511 (let* ((indent-pt (current-indentation))
12512 (v2k (verilog-in-paren-quick))
12513 (modi (verilog-modi-current))
12514 (moddecls (verilog-modi-get-decls modi))
12515 (submoddecls (verilog-modi-get-decls submodi))
12516 (sig-list-p (verilog-signals-not-in
12517 (verilog-decls-get-gparams submoddecls)
12518 (append (verilog-decls-get-gparams moddecls)))))
12520 (setq sig-list-p (verilog-signals-matching-regexp sig-list-p regexp))
12521 (when v2k (verilog-repair-open-comma))
12523 (verilog-insert-indent "// Beginning of automatic parameters (from specific module)\n")
12524 ;; Don't sort them so an upper AUTOINST will match the main module
12525 (verilog-insert-definition modi sig-list-p "parameter" indent-pt v2k t)
12526 (verilog-insert-indent "// End of automatics\n"))
12527 (when v2k (verilog-repair-close-comma)))))))
12529 (defun verilog-auto-inout-modport ()
12530 "Expand AUTOINOUTMODPORT statements, as part of \\[verilog-auto].
12531 Take input/output/inout statements from the specified interface
12532 and modport and insert into the current module. This is useful
12533 for making verification modules that connect to UVM interfaces.
12535 The first parameter is the name of an interface.
12537 The second parameter is a regexp of modports to read from in
12540 The optional third parameter is a regular expression, and only
12541 signals matching the regular expression will be included.
12544 If placed inside the parenthesis of a module declaration, it creates
12545 Verilog 2001 style, else uses Verilog 1995 style.
12547 Interface names must be resolvable to filenames. See `verilog-auto-inst'.
12549 As with other autos, any inputs/outputs declared in the module
12550 will suppress the AUTO from redeclaring an inputs/outputs by
12556 ( input logic clk );
12558 logic [7:0] req_dat;
12559 clocking mon_clkblk @(posedge clk);
12563 modport mp(clocking mon_clkblk);
12568 /*AUTOINOUTMODPORT(\"ExampIf\" \"mp\")*/
12569 // Beginning of automatic in/out/inouts (from modport)
12570 input [7:0] req_dat,
12572 // End of automatics
12574 /*AUTOASSIGNMODPORT(\"ExampIf\" \"mp\")*/
12577 Typing \\[verilog-auto] will make this into:
12582 /*AUTOINOUTMODPORT(\"ExampIf\" \"mp\")*/
12583 // Beginning of automatic in/out/inouts (from modport)
12586 // End of automatics
12589 If the modport is part of a UVM monitor/driver class, this
12590 creates a wrapper module that may be used to instantiate the
12591 driver/monitor using AUTOINST in the testbench."
12593 (let* ((params (verilog-read-auto-params 2 3))
12594 (submod (nth 0 params))
12595 (modport-re (nth 1 params))
12596 (regexp (nth 2 params))
12597 direction-re submodi) ;; direction argument not supported until requested
12598 ;; Lookup position, etc of co-module
12599 ;; Note this may raise an error
12600 (when (setq submodi (verilog-modi-lookup submod t))
12601 (let* ((indent-pt (current-indentation))
12602 (v2k (verilog-in-paren-quick))
12603 (modi (verilog-modi-current))
12604 (moddecls (verilog-modi-get-decls modi))
12605 (submoddecls (verilog-modi-get-decls submodi))
12606 (submodportdecls (verilog-modi-modport-lookup submodi modport-re))
12607 (sig-list-i (verilog-signals-in ;; Decls doesn't have data types, must resolve
12608 (verilog-decls-get-vars submoddecls)
12609 (verilog-signals-not-in
12610 (verilog-decls-get-inputs submodportdecls)
12611 (append (verilog-decls-get-ports submoddecls)
12612 (verilog-decls-get-ports moddecls)))))
12613 (sig-list-o (verilog-signals-in ;; Decls doesn't have data types, must resolve
12614 (verilog-decls-get-vars submoddecls)
12615 (verilog-signals-not-in
12616 (verilog-decls-get-outputs submodportdecls)
12617 (append (verilog-decls-get-ports submoddecls)
12618 (verilog-decls-get-ports moddecls)))))
12619 (sig-list-io (verilog-signals-in ;; Decls doesn't have data types, must resolve
12620 (verilog-decls-get-vars submoddecls)
12621 (verilog-signals-not-in
12622 (verilog-decls-get-inouts submodportdecls)
12623 (append (verilog-decls-get-ports submoddecls)
12624 (verilog-decls-get-ports moddecls))))))
12626 (setq sig-list-i (verilog-signals-edit-wire-reg
12627 (verilog-signals-matching-dir-re
12628 (verilog-signals-matching-regexp sig-list-i regexp)
12629 "input" direction-re))
12630 sig-list-o (verilog-signals-edit-wire-reg
12631 (verilog-signals-matching-dir-re
12632 (verilog-signals-matching-regexp sig-list-o regexp)
12633 "output" direction-re))
12634 sig-list-io (verilog-signals-edit-wire-reg
12635 (verilog-signals-matching-dir-re
12636 (verilog-signals-matching-regexp sig-list-io regexp)
12637 "inout" direction-re)))
12638 (when v2k (verilog-repair-open-comma))
12639 (when (or sig-list-i sig-list-o sig-list-io)
12640 (verilog-insert-indent "// Beginning of automatic in/out/inouts (from modport)\n")
12641 ;; Don't sort them so an upper AUTOINST will match the main module
12642 (verilog-insert-definition modi sig-list-o "output" indent-pt v2k t)
12643 (verilog-insert-definition modi sig-list-io "inout" indent-pt v2k t)
12644 (verilog-insert-definition modi sig-list-i "input" indent-pt v2k t)
12645 (verilog-insert-indent "// End of automatics\n"))
12646 (when v2k (verilog-repair-close-comma)))))))
12648 (defun verilog-auto-insert-lisp ()
12649 "Expand AUTOINSERTLISP statements, as part of \\[verilog-auto].
12650 The Lisp code provided is called before other AUTOS are expanded,
12651 and the Lisp code generally will call `insert' to insert text
12652 into the current file beginning on the line after the
12655 See also AUTOINSERTLAST and `verilog-auto-insert-last' which
12656 executes after (as opposed to before) other AUTOs.
12658 See also AUTO_LISP, which takes a Lisp expression and evaluates
12659 it during `verilog-auto-inst' but does not insert any text.
12663 module ExampInsertLisp;
12664 /*AUTOINSERTLISP(my-verilog-insert-hello \"world\")*/
12667 // For this example we declare the function in the
12668 // module's file itself. Often you'd define it instead
12669 // in a site-start.el or init file.
12673 (defun my-verilog-insert-hello (who)
12674 (insert (concat \"initial $write(\\\"hello \" who \"\\\");\\n\")))
12678 Typing \\[verilog-auto] will call my-verilog-insert-hello and
12679 expand the above into:
12681 // Beginning of automatic insert lisp
12682 initial $write(\"hello world\");
12683 // End of automatics
12685 You can also call an external program and insert the returned
12688 /*AUTOINSERTLISP(insert (shell-command-to-string \"echo //hello\"))*/
12689 // Beginning of automatic insert lisp
12691 // End of automatics"
12693 ;; Point is at end of /*AUTO...*/
12694 (let* ((indent-pt (current-indentation))
12695 (cmd-end-pt (save-excursion (search-backward ")")
12697 (point))) ;; Closing paren
12698 (cmd-beg-pt (save-excursion (goto-char cmd-end-pt)
12699 (backward-sexp 1) ;; Inside comment
12700 (point))) ;; Beginning paren
12701 (cmd (buffer-substring-no-properties cmd-beg-pt cmd-end-pt)))
12702 (verilog-forward-or-insert-line)
12703 ;; Some commands don't move point (like insert-file) so we always
12704 ;; add the begin/end comments, then delete it if not needed
12705 (verilog-insert-indent "// Beginning of automatic insert lisp\n")
12706 (verilog-insert-indent "// End of automatics\n")
12710 (setq verilog-scan-cache-tick nil) ;; Clear cache; inserted unknown text
12711 (verilog-delete-empty-auto-pair))))
12713 (defun verilog-auto-insert-last ()
12714 "Expand AUTOINSERTLAST statements, as part of \\[verilog-auto].
12715 The Lisp code provided is called after all other AUTOS have been
12716 expanded, and the Lisp code generally will call `insert' to
12717 insert text into the current file beginning on the line after the
12720 Other than when called (after AUTOs are expanded), the functionality
12721 is otherwise identical to AUTOINSERTLISP and `verilog-auto-insert-lisp' which
12722 executes before (as opposed to after) other AUTOs.
12724 See `verilog-auto-insert-lisp' for examples."
12725 (verilog-auto-insert-lisp))
12727 (defun verilog-auto-sense-sigs (moddecls presense-sigs)
12728 "Return list of signals for current AUTOSENSE block."
12729 (let* ((sigss (save-excursion
12730 (search-forward ")")
12731 (verilog-read-always-signals)))
12732 (sig-list (verilog-signals-not-params
12733 (verilog-signals-not-in (verilog-alw-get-inputs sigss)
12734 (append (and (not verilog-auto-sense-include-inputs)
12735 (verilog-alw-get-outputs-delayed sigss))
12736 (and (not verilog-auto-sense-include-inputs)
12737 (verilog-alw-get-outputs-immediate sigss))
12738 (verilog-alw-get-temps sigss)
12739 (verilog-decls-get-consts moddecls)
12740 (verilog-decls-get-gparams moddecls)
12744 (defun verilog-auto-sense ()
12745 "Expand AUTOSENSE statements, as part of \\[verilog-auto].
12746 Replace the always (/*AUTOSENSE*/) sensitivity list (/*AS*/ for short)
12747 with one automatically derived from all inputs declared in the always
12748 statement. Signals that are generated within the same always block are NOT
12749 placed into the sensitivity list (see `verilog-auto-sense-include-inputs').
12750 Long lines are split based on the `fill-column', see \\[set-fill-column].
12753 Verilog does not allow memories (multidimensional arrays) in sensitivity
12754 lists. AUTOSENSE will thus exclude them, and add a /*memory or*/ comment.
12757 AUTOSENSE cannot always determine if a \\=`define is a constant or a signal
12758 (it could be in an include file for example). If a \\=`define or other signal
12759 is put into the AUTOSENSE list and is not desired, use the AUTO_CONSTANT
12760 declaration anywhere in the module (parenthesis are required):
12762 /* AUTO_CONSTANT ( `this_is_really_constant_dont_autosense_it ) */
12764 Better yet, use a parameter, which will be understood to be constant
12768 If AUTOSENSE makes a mistake, please report it. (First try putting
12769 a begin/end after your always!) As a workaround, if a signal that
12770 shouldn't be in the sensitivity list was, use the AUTO_CONSTANT above.
12771 If a signal should be in the sensitivity list wasn't, placing it before
12772 the /*AUTOSENSE*/ comment will prevent it from being deleted when the
12773 autos are updated (or added if it occurs there already).
12777 always @ (/*AS*/) begin
12778 /* AUTO_CONSTANT (`constant) */
12779 outin = ina | inb | `constant;
12783 Typing \\[verilog-auto] will make this into:
12785 always @ (/*AS*/ina or inb) begin
12786 /* AUTO_CONSTANT (`constant) */
12787 outin = ina | inb | `constant;
12791 Note in Verilog 2001, you can often get the same result from the new @*
12792 operator. (This was added to the language in part due to AUTOSENSE!)
12795 outin = ina | inb | `constant;
12800 (let* ((start-pt (save-excursion
12801 (verilog-re-search-backward-quick "(" nil t)
12803 (indent-pt (save-excursion
12804 (or (and (goto-char start-pt) (1+ (current-column)))
12805 (current-indentation))))
12806 (modi (verilog-modi-current))
12807 (moddecls (verilog-modi-get-decls modi))
12808 (sig-memories (verilog-signals-memory
12809 (verilog-decls-get-vars moddecls)))
12810 sig-list not-first presense-sigs)
12811 ;; Read signals in always, eliminate outputs from sense list
12812 (setq presense-sigs (verilog-signals-from-signame
12814 (verilog-read-signals start-pt (point)))))
12815 (setq sig-list (verilog-auto-sense-sigs moddecls presense-sigs))
12817 (let ((tlen (length sig-list)))
12818 (setq sig-list (verilog-signals-not-in sig-list sig-memories))
12819 (if (not (eq tlen (length sig-list))) (verilog-insert " /*memory or*/ "))))
12820 (if (and presense-sigs ;; Add a "or" if not "(.... or /*AUTOSENSE*/"
12821 (save-excursion (goto-char (point))
12822 (verilog-re-search-backward-quick "[a-zA-Z0-9$_.%`]+" start-pt t)
12823 (verilog-re-search-backward-quick "\\s-" start-pt t)
12824 (while (looking-at "\\s-`endif")
12825 (verilog-re-search-backward-quick "[a-zA-Z0-9$_.%`]+" start-pt t)
12826 (verilog-re-search-backward-quick "\\s-" start-pt t))
12827 (not (looking-at "\\s-or\\b"))))
12828 (setq not-first t))
12829 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
12831 (cond ((> (+ 4 (current-column) (length (verilog-sig-name (car sig-list)))) fill-column) ;+4 for width of or
12833 (indent-to indent-pt)
12834 (if not-first (insert "or ")))
12835 (not-first (insert " or ")))
12836 (insert (verilog-sig-name (car sig-list)))
12837 (setq sig-list (cdr sig-list)
12840 (defun verilog-auto-reset ()
12841 "Expand AUTORESET statements, as part of \\[verilog-auto].
12842 Replace the /*AUTORESET*/ comment with code to initialize all
12843 registers set elsewhere in the always block.
12846 AUTORESET will not clear memories.
12848 AUTORESET uses <= if the signal has a <= assignment in the block,
12851 If <= is used, all = assigned variables are ignored if
12852 `verilog-auto-reset-blocking-in-non' is nil; they are presumed
12855 /*AUTORESET*/ presumes that any signals mentioned between the previous
12856 begin/case/if statement and the AUTORESET comment are being reset manually
12857 and should not be automatically reset. This includes omitting any signals
12858 used on the right hand side of assignments.
12860 By default, AUTORESET will include the width of the signal in the
12861 autos, SystemVerilog designs may want to change this. To control
12862 this behavior, see `verilog-auto-reset-widths'. In some cases
12863 AUTORESET must use a '0 assignment and it will print NOWIDTH; use
12864 `verilog-auto-reset-widths' unbased to prevent this.
12866 AUTORESET ties signals to deasserted, which is presumed to be zero.
12867 Signals that match `verilog-active-low-regexp' will be deasserted by tying
12870 AUTORESET may try to reset arrays or structures that cannot be
12871 reset by a simple assignment, resulting in compile errors. This
12872 is a feature to be taken as a hint that you need to reset these
12873 signals manually (or put them into a \"\\=`ifdef NEVER signal<=\\=`0;
12874 \\=`endif\" so Verilog-Mode ignores them.)
12878 always @(posedge clk or negedge reset_l) begin
12879 if (!reset_l) begin
12890 Typing \\[verilog-auto] will make this into:
12892 always @(posedge core_clk or negedge reset_l) begin
12893 if (!reset_l) begin
12896 // Beginning of autoreset for uninitialized flops
12898 b = 0; // if `verilog-auto-reset-blocking-in-non' true
12899 // End of automatics
12911 (let* ((indent-pt (current-indentation))
12912 (modi (verilog-modi-current))
12913 (moddecls (verilog-modi-get-decls modi))
12914 (all-list (verilog-decls-get-signals moddecls))
12915 sigss sig-list dly-list prereset-sigs)
12916 ;; Read signals in always, eliminate outputs from reset list
12917 (setq prereset-sigs (verilog-signals-from-signame
12919 (verilog-read-signals
12921 (verilog-re-search-backward-quick
12922 "\\(@\\|\\<\\(begin\\|if\\|case\\|always\\(_latch\\|_ff\\|_comb\\)?\\)\\>\\)" nil t)
12926 (verilog-re-search-backward-quick "\\(@\\|\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\)\\>\\)" nil t)
12927 (setq sigss (verilog-read-always-signals)))
12928 (setq dly-list (verilog-alw-get-outputs-delayed sigss))
12929 (setq sig-list (verilog-signals-not-in-struct
12931 (verilog-alw-get-outputs-delayed sigss)
12932 (when (or (not (verilog-alw-get-uses-delayed sigss))
12933 verilog-auto-reset-blocking-in-non)
12934 (verilog-alw-get-outputs-immediate sigss)))
12936 (verilog-alw-get-temps sigss)
12938 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
12941 (verilog-insert-indent "// Beginning of autoreset for uninitialized flops\n");
12943 (let ((sig (or (assoc (verilog-sig-name (car sig-list)) all-list) ;; As sig-list has no widths
12945 (indent-to indent-pt)
12946 (insert (verilog-sig-name sig)
12947 (if (assoc (verilog-sig-name sig) dly-list)
12948 (concat " <= " verilog-assignment-delay)
12950 (verilog-sig-tieoff sig)
12952 (setq sig-list (cdr sig-list))))
12953 (verilog-insert-indent "// End of automatics")))))
12955 (defun verilog-auto-tieoff ()
12956 "Expand AUTOTIEOFF statements, as part of \\[verilog-auto].
12957 Replace the /*AUTOTIEOFF*/ comment with code to wire-tie all unused output
12958 signals to deasserted.
12960 /*AUTOTIEOFF*/ is used to make stub modules; modules that have the same
12961 input/output list as another module, but no internals. Specifically, it
12962 finds all outputs in the module, and if that input is not otherwise declared
12963 as a register or wire, creates a tieoff.
12965 AUTORESET ties signals to deasserted, which is presumed to be zero.
12966 Signals that match `verilog-active-low-regexp' will be deasserted by tying
12969 You can add signals you do not want included in AUTOTIEOFF with
12970 `verilog-auto-tieoff-ignore-regexp'.
12972 `verilog-auto-wire-type' may be used to change the datatype of
12975 `verilog-auto-reset-widths' may be used to change how the tieoff
12976 value's width is generated.
12978 An example of making a stub for another module:
12980 module ExampStub (/*AUTOINST*/);
12981 /*AUTOINOUTPARAM(\"Foo\")*/
12982 /*AUTOINOUTMODULE(\"Foo\")*/
12984 // verilator lint_off UNUSED
12985 wire _unused_ok = &{1'b0,
12988 // verilator lint_on UNUSED
12991 Typing \\[verilog-auto] will make this into:
12993 module ExampStub (/*AUTOINST*/...);
12994 /*AUTOINOUTPARAM(\"Foo\")*/
12995 /*AUTOINOUTMODULE(\"Foo\")*/
12996 // Beginning of autotieoff
12998 // End of automatics
13001 // Beginning of autotieoff
13002 wire [2:0] foo = 3'b0;
13003 // End of automatics
13009 (let* ((indent-pt (current-indentation))
13010 (modi (verilog-modi-current))
13011 (moddecls (verilog-modi-get-decls modi))
13012 (modsubdecls (verilog-modi-get-sub-decls modi))
13013 (sig-list (verilog-signals-not-in
13014 (verilog-decls-get-outputs moddecls)
13015 (append (verilog-decls-get-vars moddecls)
13016 (verilog-decls-get-assigns moddecls)
13017 (verilog-decls-get-consts moddecls)
13018 (verilog-decls-get-gparams moddecls)
13019 (verilog-subdecls-get-interfaced modsubdecls)
13020 (verilog-subdecls-get-outputs modsubdecls)
13021 (verilog-subdecls-get-inouts modsubdecls)))))
13022 (setq sig-list (verilog-signals-not-matching-regexp
13023 sig-list verilog-auto-tieoff-ignore-regexp))
13025 (verilog-forward-or-insert-line)
13026 (verilog-insert-indent "// Beginning of automatic tieoffs (for this module's unterminated outputs)\n")
13027 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
13028 (verilog-modi-cache-add-vars modi sig-list) ; Before we trash list
13030 (let ((sig (car sig-list)))
13031 (cond ((equal verilog-auto-tieoff-declaration "assign")
13032 (indent-to indent-pt)
13033 (insert "assign " (verilog-sig-name sig)))
13035 (verilog-insert-one-definition sig verilog-auto-tieoff-declaration indent-pt)))
13036 (indent-to (max 48 (+ indent-pt 40)))
13037 (insert "= " (verilog-sig-tieoff sig)
13039 (setq sig-list (cdr sig-list))))
13040 (verilog-insert-indent "// End of automatics\n")))))
13042 (defun verilog-auto-undef ()
13043 "Expand AUTOUNDEF statements, as part of \\[verilog-auto].
13044 Take any \\=`defines since the last AUTOUNDEF in the current file
13045 and create \\=`undefs for them. This is used to insure that
13046 file-local defines do not pollute the global \\=`define name space.
13049 AUTOUNDEF presumes any identifier following \\=`define is the
13050 name of a define. Any \\=`ifdefs are ignored.
13052 AUTOUNDEF suppresses creating an \\=`undef for any define that was
13053 \\=`undefed before the AUTOUNDEF. This may be used to work around
13054 the ignoring of \\=`ifdefs as shown below.
13059 \\=`define M_BAR(x)
13063 \\=`undef M_BAZ // Emacs will see this and not \\=`undef M_BAZ
13068 Typing \\[verilog-auto] will make this into:
13072 // Beginning of automatic undefs
13075 // End of automatics
13077 You may also provide an optional regular expression, in which case only
13078 defines the regular expression will be undefed."
13080 (let* ((params (verilog-read-auto-params 0 1))
13081 (regexp (nth 0 params))
13082 (indent-pt (current-indentation))
13086 ;; Scan from start of file, or last AUTOUNDEF
13087 (or (verilog-re-search-backward-quick "/\\*AUTOUNDEF\\>" end-pt t)
13088 (goto-char (point-min)))
13089 (while (verilog-re-search-forward-quick
13090 "`\\(define\\|undef\\)\\s-*\\([a-zA-Z_][a-zA-Z_0-9]*\\)" end-pt t)
13091 (cond ((equal (match-string-no-properties 1) "define")
13092 (setq def (match-string-no-properties 2))
13093 (when (and (or (not regexp)
13094 (string-match regexp def))
13095 (not (member def defs))) ;; delete-dups not in 21.1
13096 (setq defs (cons def defs))))
13098 (setq defs (delete (match-string-no-properties 2) defs))))))
13100 (setq defs (sort defs 'string<))
13102 (verilog-forward-or-insert-line)
13103 (verilog-insert-indent "// Beginning of automatic undefs\n")
13105 (verilog-insert-indent "`undef " (car defs) "\n")
13106 (setq defs (cdr defs)))
13107 (verilog-insert-indent "// End of automatics\n")))))
13109 (defun verilog-auto-unused ()
13110 "Expand AUTOUNUSED statements, as part of \\[verilog-auto].
13111 Replace the /*AUTOUNUSED*/ comment with a comma separated list of all unused
13112 input and inout signals.
13114 /*AUTOUNUSED*/ is used to make stub modules; modules that have the same
13115 input/output list as another module, but no internals. Specifically, it
13116 finds all inputs and inouts in the module, and if that input is not otherwise
13117 used, adds it to a comma separated list.
13119 The comma separated list is intended to be used to create a _unused_ok
13120 signal. Using the exact name \"_unused_ok\" for name of the temporary
13121 signal is recommended as it will insure maximum forward compatibility, it
13122 also makes lint warnings easy to understand; ignore any unused warnings
13123 with \"unused\" in the signal name.
13125 To reduce simulation time, the _unused_ok signal should be forced to a
13126 constant to prevent wiggling. The easiest thing to do is use a
13127 reduction-and with 1'b0 as shown.
13129 This way all unused signals are in one place, making it convenient to add
13130 your tool's specific pragmas around the assignment to disable any unused
13133 You can add signals you do not want included in AUTOUNUSED with
13134 `verilog-auto-unused-ignore-regexp'.
13136 An example of making a stub for another module:
13138 module ExampStub (/*AUTOINST*/);
13139 /*AUTOINOUTPARAM(\"Examp\")*/
13140 /*AUTOINOUTMODULE(\"Examp\")*/
13142 // verilator lint_off UNUSED
13143 wire _unused_ok = &{1'b0,
13146 // verilator lint_on UNUSED
13149 Typing \\[verilog-auto] will make this into:
13152 // verilator lint_off UNUSED
13153 wire _unused_ok = &{1'b0,
13155 // Beginning of automatics
13159 // End of automatics
13161 // verilator lint_on UNUSED
13166 (let* ((indent-pt (progn (search-backward "/*") (current-column)))
13167 (modi (verilog-modi-current))
13168 (moddecls (verilog-modi-get-decls modi))
13169 (modsubdecls (verilog-modi-get-sub-decls modi))
13170 (sig-list (verilog-signals-not-in
13171 (append (verilog-decls-get-inputs moddecls)
13172 (verilog-decls-get-inouts moddecls))
13173 (append (verilog-subdecls-get-inputs modsubdecls)
13174 (verilog-subdecls-get-inouts modsubdecls)))))
13175 (setq sig-list (verilog-signals-not-matching-regexp
13176 sig-list verilog-auto-unused-ignore-regexp))
13178 (verilog-forward-or-insert-line)
13179 (verilog-insert-indent "// Beginning of automatic unused inputs\n")
13180 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
13182 (let ((sig (car sig-list)))
13183 (indent-to indent-pt)
13184 (insert (verilog-sig-name sig) ",\n")
13185 (setq sig-list (cdr sig-list))))
13186 (verilog-insert-indent "// End of automatics\n")))))
13188 (defun verilog-enum-ascii (signm elim-regexp)
13189 "Convert an enum name SIGNM to an ascii string for insertion.
13190 Remove user provided prefix ELIM-REGEXP."
13191 (or elim-regexp (setq elim-regexp "_ DONT MATCH IT_"))
13192 (let ((case-fold-search t))
13193 ;; All upper becomes all lower for readability
13194 (downcase (verilog-string-replace-matches elim-regexp "" nil nil signm))))
13196 (defun verilog-auto-ascii-enum ()
13197 "Expand AUTOASCIIENUM statements, as part of \\[verilog-auto].
13198 Create a register to contain the ASCII decode of an enumerated signal type.
13199 This will allow trace viewers to show the ASCII name of states.
13201 First, parameters are built into an enumeration using the synopsys enum
13202 comment. The comment must be between the keyword and the symbol.
13203 \(Annoying, but that's what Synopsys's dc_shell FSM reader requires.)
13205 Next, registers which that enum applies to are also tagged with the same
13208 Finally, an AUTOASCIIENUM command is used.
13210 The first parameter is the name of the signal to be decoded.
13212 The second parameter is the name to store the ASCII code into. For the
13213 signal foo, I suggest the name _foo__ascii, where the leading _ indicates
13214 a signal that is just for simulation, and the magic characters _ascii
13215 tell viewers like Dinotrace to display in ASCII format.
13217 The third optional parameter is a string which will be removed
13218 from the state names. It defaults to \"\" which removes nothing.
13220 The fourth optional parameter is \"onehot\" to force one-hot
13221 decoding. If unspecified, if and only if the first parameter
13222 width is 2^(number of states in enum) and does NOT match the
13223 width of the enum, the signal is assumed to be a one-hot
13224 decode. Otherwise, it's a normal encoded state vector.
13226 `verilog-auto-wire-type' may be used to change the datatype of
13229 \"auto enum\" may be used in place of \"synopsys enum\".
13233 //== State enumeration
13234 parameter [2:0] // synopsys enum state_info
13238 //== State variables
13239 reg [2:0] /* synopsys enum state_info */
13240 state_r; /* synopsys state_vector state_r */
13241 reg [2:0] /* synopsys enum state_info */
13244 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
13246 Typing \\[verilog-auto] will make this into:
13248 ... same front matter ...
13250 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
13251 // Beginning of automatic ASCII enum decoding
13252 reg [39:0] state_ascii_r; // Decode of state_r
13253 always @(state_r) begin
13255 SM_IDLE: state_ascii_r = \"idle \";
13256 SM_SEND: state_ascii_r = \"send \";
13257 SM_WAIT1: state_ascii_r = \"wait1\";
13258 default: state_ascii_r = \"%Erro\";
13261 // End of automatics"
13263 (let* ((params (verilog-read-auto-params 2 4))
13264 (undecode-name (nth 0 params))
13265 (ascii-name (nth 1 params))
13266 (elim-regexp (and (nth 2 params)
13267 (not (equal (nth 2 params) ""))
13269 (one-hot-flag (nth 3 params))
13271 (indent-pt (current-indentation))
13272 (modi (verilog-modi-current))
13273 (moddecls (verilog-modi-get-decls modi))
13275 (sig-list-consts (append (verilog-decls-get-consts moddecls)
13276 (verilog-decls-get-gparams moddecls)))
13277 (sig-list-all (verilog-decls-get-iovars moddecls))
13279 (undecode-sig (or (assoc undecode-name sig-list-all)
13280 (error "%s: Signal %s not found in design" (verilog-point-text) undecode-name)))
13281 (undecode-enum (or (verilog-sig-enum undecode-sig)
13282 (error "%s: Signal %s does not have an enum tag" (verilog-point-text) undecode-name)))
13284 (enum-sigs (verilog-signals-not-in
13285 (or (verilog-signals-matching-enum sig-list-consts undecode-enum)
13286 (error "%s: No state definitions for %s" (verilog-point-text) undecode-enum))
13290 (string-match "onehot" (or one-hot-flag ""))
13291 (and ;; width(enum) != width(sig)
13292 (or (not (verilog-sig-bits (car enum-sigs)))
13293 (not (equal (verilog-sig-width (car enum-sigs))
13294 (verilog-sig-width undecode-sig))))
13295 ;; count(enums) == width(sig)
13296 (equal (number-to-string (length enum-sigs))
13297 (verilog-sig-width undecode-sig)))))
13301 ;; Find number of ascii chars needed
13302 (let ((tmp-sigs enum-sigs))
13304 (setq enum-chars (max enum-chars (length (verilog-sig-name (car tmp-sigs))))
13305 ascii-chars (max ascii-chars (length (verilog-enum-ascii
13306 (verilog-sig-name (car tmp-sigs))
13308 tmp-sigs (cdr tmp-sigs))))
13310 (verilog-forward-or-insert-line)
13311 (verilog-insert-indent "// Beginning of automatic ASCII enum decoding\n")
13312 (let ((decode-sig-list (list (list ascii-name (format "[%d:0]" (- (* ascii-chars 8) 1))
13313 (concat "Decode of " undecode-name) nil nil))))
13314 (verilog-insert-definition modi decode-sig-list "reg" indent-pt nil))
13316 (verilog-insert-indent "always @(" undecode-name ") begin\n")
13317 (setq indent-pt (+ indent-pt verilog-indent-level))
13318 (verilog-insert-indent "case ({" undecode-name "})\n")
13319 (setq indent-pt (+ indent-pt verilog-case-indent))
13321 (let ((tmp-sigs enum-sigs)
13322 (chrfmt (format "%%-%ds %s = \"%%-%ds\";\n"
13323 (+ (if one-hot 9 1) (max 8 enum-chars))
13324 ascii-name ascii-chars))
13325 (errname (substring "%Error" 0 (min 6 ascii-chars))))
13327 (verilog-insert-indent
13330 (concat (if one-hot "(")
13331 ;; Use enum-sigs length as that's numeric
13332 ;; verilog-sig-width undecode-sig might not be.
13333 (if one-hot (number-to-string (length enum-sigs)))
13334 ;; We use a shift instead of var[index]
13335 ;; so that a non-one hot value will show as error.
13336 (if one-hot "'b1<<")
13337 (verilog-sig-name (car tmp-sigs))
13338 (if one-hot ")") ":")
13339 (verilog-enum-ascii (verilog-sig-name (car tmp-sigs))
13341 (setq tmp-sigs (cdr tmp-sigs)))
13342 (verilog-insert-indent (format chrfmt "default:" errname)))
13344 (setq indent-pt (- indent-pt verilog-case-indent))
13345 (verilog-insert-indent "endcase\n")
13346 (setq indent-pt (- indent-pt verilog-indent-level))
13347 (verilog-insert-indent "end\n"
13348 "// End of automatics\n"))))
13350 (defun verilog-auto-templated-rel ()
13351 "Replace Templated relative line numbers with absolute line numbers.
13352 Internal use only. This hacks around the line numbers in AUTOINST Templates
13353 being different from the final output's line numbering."
13354 (let ((templateno 0) (template-line (list 0)) (buf-line 1))
13355 ;; Find line number each template is on
13356 ;; Count lines as we go, as otherwise it's O(n^2) to use count-lines
13357 (goto-char (point-min))
13358 (while (not (eobp))
13359 (when (looking-at ".*AUTO_TEMPLATE")
13360 (setq templateno (1+ templateno))
13361 (setq template-line (cons buf-line template-line)))
13362 (setq buf-line (1+ buf-line))
13364 (setq template-line (nreverse template-line))
13365 ;; Replace T# L# with absolute line number
13366 (goto-char (point-min))
13367 (while (re-search-forward " Templated T\\([0-9]+\\) L\\([0-9]+\\)" nil t)
13369 (concat " Templated "
13370 (int-to-string (+ (nth (string-to-number (match-string 1))
13372 (string-to-number (match-string 2)))))
13375 (defun verilog-auto-template-lint ()
13376 "Check AUTO_TEMPLATEs for unused lines.
13377 Enable with `verilog-auto-template-warn-unused'."
13378 (let ((name1 (or (buffer-file-name) (buffer-name))))
13380 (goto-char (point-min))
13381 (while (re-search-forward
13382 "^\\s-*/?\\*?\\s-*[a-zA-Z0-9`_$]+\\s-+AUTO_TEMPLATE" nil t)
13383 (let* ((tpl-info (verilog-read-auto-template-middle))
13384 (tpl-list (aref tpl-info 1))
13385 (tlines (append (nth 0 tpl-list) (nth 1 tpl-list)))
13388 (setq tpl-ass (car tlines)
13389 tlines (cdr tlines))
13391 (unless (or (not (eval-when-compile (fboundp 'make-hash-table))) ;; Not supported, no warning
13392 (not verilog-auto-template-hits)
13393 (gethash (vector (nth 2 tpl-ass) (nth 3 tpl-ass))
13394 verilog-auto-template-hits))
13395 (verilog-warn-error "%s:%d: AUTO_TEMPLATE line unused: \".%s (%s)\""
13397 (+ (elt tpl-ass 3) ;; Template line number
13398 (count-lines (point-min) (point)))
13399 (elt tpl-ass 0) (elt tpl-ass 1))
13407 (defun verilog-auto (&optional inject) ; Use verilog-inject-auto instead of passing an arg
13408 "Expand AUTO statements.
13409 Look for any /*AUTO...*/ commands in the code, as used in
13410 instantiations or argument headers. Update the list of signals
13411 following the /*AUTO...*/ command.
13413 Use \\[verilog-delete-auto] to remove the AUTOs.
13415 Use \\[verilog-diff-auto] to see differences in AUTO expansion.
13417 Use \\[verilog-inject-auto] to insert AUTOs for the first time.
13419 Use \\[verilog-faq] for a pointer to frequently asked questions.
13421 For new users, we recommend setting `verilog-case-fold' to nil
13422 and `verilog-auto-arg-sort' to t.
13424 The hooks `verilog-before-auto-hook' and `verilog-auto-hook' are
13425 called before and after this function, respectively.
13428 module ModuleName (/*AUTOARG*/);
13433 InstMod instName #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);
13435 You can also update the AUTOs from the shell using:
13436 emacs --batch <filenames.v> -f verilog-batch-auto
13437 Or fix indentation with:
13438 emacs --batch <filenames.v> -f verilog-batch-indent
13439 Likewise, you can delete or inject AUTOs with:
13440 emacs --batch <filenames.v> -f verilog-batch-delete-auto
13441 emacs --batch <filenames.v> -f verilog-batch-inject-auto
13442 Or check if AUTOs have the same expansion
13443 emacs --batch <filenames.v> -f verilog-batch-diff-auto
13445 Using \\[describe-function], see also:
13446 `verilog-auto-arg' for AUTOARG module instantiations
13447 `verilog-auto-ascii-enum' for AUTOASCIIENUM enumeration decoding
13448 `verilog-auto-assign-modport' for AUTOASSIGNMODPORT assignment to/from modport
13449 `verilog-auto-inout' for AUTOINOUT making hierarchy inouts
13450 `verilog-auto-inout-comp' for AUTOINOUTCOMP copy complemented i/o
13451 `verilog-auto-inout-in' for AUTOINOUTIN inputs for all i/o
13452 `verilog-auto-inout-modport' for AUTOINOUTMODPORT i/o from an interface modport
13453 `verilog-auto-inout-module' for AUTOINOUTMODULE copying i/o from elsewhere
13454 `verilog-auto-inout-param' for AUTOINOUTPARAM copying params from elsewhere
13455 `verilog-auto-input' for AUTOINPUT making hierarchy inputs
13456 `verilog-auto-insert-lisp' for AUTOINSERTLISP insert code from lisp function
13457 `verilog-auto-insert-last' for AUTOINSERTLAST insert code from lisp function
13458 `verilog-auto-inst' for AUTOINST instantiation pins
13459 `verilog-auto-star' for AUTOINST .* SystemVerilog pins
13460 `verilog-auto-inst-param' for AUTOINSTPARAM instantiation params
13461 `verilog-auto-logic' for AUTOLOGIC declaring logic signals
13462 `verilog-auto-output' for AUTOOUTPUT making hierarchy outputs
13463 `verilog-auto-output-every' for AUTOOUTPUTEVERY making all outputs
13464 `verilog-auto-reg' for AUTOREG registers
13465 `verilog-auto-reg-input' for AUTOREGINPUT instantiation registers
13466 `verilog-auto-reset' for AUTORESET flop resets
13467 `verilog-auto-sense' for AUTOSENSE or AS always sensitivity lists
13468 `verilog-auto-tieoff' for AUTOTIEOFF output tieoffs
13469 `verilog-auto-undef' for AUTOUNDEF \\=`undef of local \\=`defines
13470 `verilog-auto-unused' for AUTOUNUSED unused inputs/inouts
13471 `verilog-auto-wire' for AUTOWIRE instantiation wires
13473 `verilog-read-defines' for reading \\=`define values
13474 `verilog-read-includes' for reading \\=`includes
13476 If you have bugs with these autos, please file an issue at
13477 URL `http://www.veripool.org/verilog-mode' or contact the AUTOAUTHOR
13478 Wilson Snyder (wsnyder@wsnyder.org)."
13480 (unless noninteractive (message "Updating AUTOs..."))
13481 (if (fboundp 'dinotrace-unannotate-all)
13482 (dinotrace-unannotate-all))
13483 (verilog-save-font-mods
13484 (let ((oldbuf (if (not (buffer-modified-p))
13486 (case-fold-search verilog-case-fold)
13487 ;; Cache directories; we don't write new files, so can't change
13488 (verilog-dir-cache-preserving t)
13489 ;; Cache current module
13490 (verilog-modi-cache-current-enable t)
13491 (verilog-modi-cache-current-max (point-min)) ; IE it's invalid
13492 verilog-modi-cache-current)
13494 ;; Disable change hooks for speed
13495 ;; This let can't be part of above let; must restore
13496 ;; after-change-functions before font-lock resumes
13497 (verilog-save-no-change-functions
13498 (verilog-save-scan-cache
13500 ;; Wipe cache; otherwise if we AUTOed a block above this one,
13501 ;; we'll misremember we have generated IOs, confusing AUTOOUTPUT
13502 (setq verilog-modi-cache-list nil)
13504 (setq verilog-auto-template-hits nil)
13505 ;; If we're not in verilog-mode, change syntax table so parsing works right
13506 (unless (eq major-mode `verilog-mode) (verilog-mode))
13507 ;; Allow user to customize
13508 (verilog-run-hooks 'verilog-before-auto-hook)
13509 ;; Try to save the user from needing to revert-file to reread file local-variables
13510 (verilog-auto-reeval-locals)
13511 (verilog-read-auto-lisp-present)
13512 (verilog-read-auto-lisp (point-min) (point-max))
13513 (verilog-getopt-flags)
13514 ;; From here on out, we can cache anything we read from disk
13515 (verilog-preserve-dir-cache
13516 ;; These two may seem obvious to do always, but on large includes it can be way too slow
13517 (when verilog-auto-read-includes
13518 (verilog-read-includes)
13519 (verilog-read-defines nil nil t))
13520 ;; Setup variables due to SystemVerilog expansion
13521 (verilog-auto-re-search-do "/\\*AUTOLOGIC\\*/" 'verilog-auto-logic-setup)
13522 ;; This particular ordering is important
13523 ;; INST: Lower modules correct, no internal dependencies, FIRST
13524 (verilog-preserve-modi-cache
13525 ;; Clear existing autos else we'll be screwed by existing ones
13526 (verilog-delete-auto)
13527 ;; Injection if appropriate
13529 (verilog-inject-inst)
13530 (verilog-inject-sense)
13531 (verilog-inject-arg))
13533 ;; Do user inserts first, so their code can insert AUTOs
13534 (verilog-auto-re-search-do "/\\*AUTOINSERTLISP(.*?)\\*/"
13535 'verilog-auto-insert-lisp)
13536 ;; Expand instances before need the signals the instances input/output
13537 (verilog-auto-re-search-do "/\\*AUTOINSTPARAM\\*/" 'verilog-auto-inst-param)
13538 (verilog-auto-re-search-do "/\\*AUTOINST\\*/" 'verilog-auto-inst)
13539 (verilog-auto-re-search-do "\\.\\*" 'verilog-auto-star)
13540 ;; Doesn't matter when done, but combine it with a common changer
13541 (verilog-auto-re-search-do "/\\*\\(AUTOSENSE\\|AS\\)\\*/" 'verilog-auto-sense)
13542 (verilog-auto-re-search-do "/\\*AUTORESET\\*/" 'verilog-auto-reset)
13543 ;; Must be done before autoin/out as creates a reg
13544 (verilog-auto-re-search-do "/\\*AUTOASCIIENUM(.*?)\\*/" 'verilog-auto-ascii-enum)
13546 ;; first in/outs from other files
13547 (verilog-auto-re-search-do "/\\*AUTOINOUTMODPORT(.*?)\\*/" 'verilog-auto-inout-modport)
13548 (verilog-auto-re-search-do "/\\*AUTOINOUTMODULE(.*?)\\*/" 'verilog-auto-inout-module)
13549 (verilog-auto-re-search-do "/\\*AUTOINOUTCOMP(.*?)\\*/" 'verilog-auto-inout-comp)
13550 (verilog-auto-re-search-do "/\\*AUTOINOUTIN(.*?)\\*/" 'verilog-auto-inout-in)
13551 (verilog-auto-re-search-do "/\\*AUTOINOUTPARAM(.*?)\\*/" 'verilog-auto-inout-param)
13552 ;; next in/outs which need previous sucked inputs first
13553 (verilog-auto-re-search-do "/\\*AUTOOUTPUT\\((.*?)\\)?\\*/" 'verilog-auto-output)
13554 (verilog-auto-re-search-do "/\\*AUTOINPUT\\((.*?)\\)?\\*/" 'verilog-auto-input)
13555 (verilog-auto-re-search-do "/\\*AUTOINOUT\\((.*?)\\)?\\*/" 'verilog-auto-inout)
13556 ;; Then tie off those in/outs
13557 (verilog-auto-re-search-do "/\\*AUTOTIEOFF\\*/" 'verilog-auto-tieoff)
13558 ;; These can be anywhere after AUTOINSERTLISP
13559 (verilog-auto-re-search-do "/\\*AUTOUNDEF\\((.*?)\\)?\\*/" 'verilog-auto-undef)
13560 ;; Wires/regs must be after inputs/outputs
13561 (verilog-auto-re-search-do "/\\*AUTOASSIGNMODPORT(.*?)\\*/" 'verilog-auto-assign-modport)
13562 (verilog-auto-re-search-do "/\\*AUTOLOGIC\\*/" 'verilog-auto-logic)
13563 (verilog-auto-re-search-do "/\\*AUTOWIRE\\*/" 'verilog-auto-wire)
13564 (verilog-auto-re-search-do "/\\*AUTOREG\\*/" 'verilog-auto-reg)
13565 (verilog-auto-re-search-do "/\\*AUTOREGINPUT\\*/" 'verilog-auto-reg-input)
13566 ;; outputevery needs AUTOOUTPUTs done first
13567 (verilog-auto-re-search-do "/\\*AUTOOUTPUTEVERY\\((.*?)\\)?\\*/" 'verilog-auto-output-every)
13568 ;; After we've created all new variables
13569 (verilog-auto-re-search-do "/\\*AUTOUNUSED\\*/" 'verilog-auto-unused)
13570 ;; Must be after all inputs outputs are generated
13571 (verilog-auto-re-search-do "/\\*AUTOARG\\*/" 'verilog-auto-arg)
13573 (verilog-auto-re-search-do "/\\*AUTOINSERTLAST(.*?)\\*/" 'verilog-auto-insert-last)
13574 ;; Fix line numbers (comments only)
13575 (when verilog-auto-inst-template-numbers
13576 (verilog-auto-templated-rel))
13577 (when verilog-auto-template-warn-unused
13578 (verilog-auto-template-lint))))
13580 (verilog-run-hooks 'verilog-auto-hook)
13582 (when verilog-auto-delete-trailing-whitespace
13583 (verilog-delete-trailing-whitespace))
13585 (set (make-local-variable 'verilog-auto-update-tick) (buffer-chars-modified-tick))
13587 ;; If end result is same as when started, clear modified flag
13588 (cond ((and oldbuf (equal oldbuf (buffer-string)))
13589 (set-buffer-modified-p nil)
13590 (unless noninteractive (message "Updating AUTOs...done (no changes)")))
13591 (t (unless noninteractive (message "Updating AUTOs...done"))))
13592 ;; End of after-change protection
13595 ;; Currently handled in verilog-save-font-mods
13600 ;; Skeleton based code insertion
13602 (defvar verilog-template-map
13603 (let ((map (make-sparse-keymap)))
13604 (define-key map "a" 'verilog-sk-always)
13605 (define-key map "b" 'verilog-sk-begin)
13606 (define-key map "c" 'verilog-sk-case)
13607 (define-key map "f" 'verilog-sk-for)
13608 (define-key map "g" 'verilog-sk-generate)
13609 (define-key map "h" 'verilog-sk-header)
13610 (define-key map "i" 'verilog-sk-initial)
13611 (define-key map "j" 'verilog-sk-fork)
13612 (define-key map "m" 'verilog-sk-module)
13613 (define-key map "o" 'verilog-sk-ovm-class)
13614 (define-key map "p" 'verilog-sk-primitive)
13615 (define-key map "r" 'verilog-sk-repeat)
13616 (define-key map "s" 'verilog-sk-specify)
13617 (define-key map "t" 'verilog-sk-task)
13618 (define-key map "u" 'verilog-sk-uvm-object)
13619 (define-key map "w" 'verilog-sk-while)
13620 (define-key map "x" 'verilog-sk-casex)
13621 (define-key map "z" 'verilog-sk-casez)
13622 (define-key map "?" 'verilog-sk-if)
13623 (define-key map ":" 'verilog-sk-else-if)
13624 (define-key map "/" 'verilog-sk-comment)
13625 (define-key map "A" 'verilog-sk-assign)
13626 (define-key map "F" 'verilog-sk-function)
13627 (define-key map "I" 'verilog-sk-input)
13628 (define-key map "O" 'verilog-sk-output)
13629 (define-key map "S" 'verilog-sk-state-machine)
13630 (define-key map "=" 'verilog-sk-inout)
13631 (define-key map "U" 'verilog-sk-uvm-component)
13632 (define-key map "W" 'verilog-sk-wire)
13633 (define-key map "R" 'verilog-sk-reg)
13634 (define-key map "D" 'verilog-sk-define-signal)
13636 "Keymap used in Verilog mode for smart template operations.")
13640 ;; Place the templates into Verilog Mode. They may be inserted under any key.
13641 ;; C-c C-t will be the default. If you use templates a lot, you
13642 ;; may want to consider moving the binding to another key in your init
13645 ;; Note \C-c and letter are reserved for users
13646 (define-key verilog-mode-map "\C-c\C-t" verilog-template-map)
13648 ;;; ---- statement skeletons ------------------------------------------
13650 (define-skeleton verilog-sk-prompt-condition
13651 "Prompt for the loop condition."
13652 "[condition]: " str )
13654 (define-skeleton verilog-sk-prompt-init
13655 "Prompt for the loop init statement."
13656 "[initial statement]: " str )
13658 (define-skeleton verilog-sk-prompt-inc
13659 "Prompt for the loop increment statement."
13660 "[increment statement]: " str )
13662 (define-skeleton verilog-sk-prompt-name
13663 "Prompt for the name of something."
13666 (define-skeleton verilog-sk-prompt-clock
13667 "Prompt for the name of something."
13668 "name and edge of clock(s): " str)
13670 (defvar verilog-sk-reset nil)
13671 (defun verilog-sk-prompt-reset ()
13672 "Prompt for the name of a state machine reset."
13673 (setq verilog-sk-reset (read-string "name of reset: " "rst")))
13676 (define-skeleton verilog-sk-prompt-state-selector
13677 "Prompt for the name of a state machine selector."
13678 "name of selector (eg {a,b,c,d}): " str )
13680 (define-skeleton verilog-sk-prompt-output
13681 "Prompt for the name of something."
13684 (define-skeleton verilog-sk-prompt-msb
13685 "Prompt for most significant bit specification."
13686 "msb:" str & ?: & '(verilog-sk-prompt-lsb) | -1 )
13688 (define-skeleton verilog-sk-prompt-lsb
13689 "Prompt for least significant bit specification."
13692 (defvar verilog-sk-p nil)
13693 (define-skeleton verilog-sk-prompt-width
13694 "Prompt for a width specification."
13697 (setq verilog-sk-p (point))
13698 (verilog-sk-prompt-msb)
13699 (if (> (point) verilog-sk-p) "] " " ")))
13701 (defun verilog-sk-header ()
13702 "Insert a descriptive header at the top of the file.
13703 See also `verilog-header' for an alternative format."
13706 (goto-char (point-min))
13707 (verilog-sk-header-tmpl)))
13709 (define-skeleton verilog-sk-header-tmpl
13710 "Insert a comment block containing the module title, author, etc."
13712 "// -*- Mode: Verilog -*-"
13713 "\n// Filename : " (buffer-name)
13714 "\n// Description : " str
13715 "\n// Author : " (user-full-name)
13716 "\n// Created On : " (current-time-string)
13717 "\n// Last Modified By: " (user-full-name)
13718 "\n// Last Modified On: " (current-time-string)
13719 "\n// Update Count : 0"
13720 "\n// Status : Unknown, Use with caution!"
13723 (define-skeleton verilog-sk-module
13724 "Insert a module definition."
13726 > "module " '(verilog-sk-prompt-name) " (/*AUTOARG*/ ) ;" \n
13728 > (- verilog-indent-level-behavioral) "endmodule" (progn (electric-verilog-terminate-line) nil))
13730 ;;; ------------------------------------------------------------------------
13731 ;;; Define a default OVM class, with macros and new()
13732 ;;; ------------------------------------------------------------------------
13734 (define-skeleton verilog-sk-ovm-class
13735 "Insert a class definition"
13737 > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n
13739 > "`ovm_object_utils_begin(" name ")" \n
13740 > (- verilog-indent-level) " `ovm_object_utils_end" \n
13742 > "function new(string name=\"" name "\");" \n
13743 > "super.new(name);" \n
13744 > (- verilog-indent-level) "endfunction" \n
13746 > "endclass" (progn (electric-verilog-terminate-line) nil))
13748 (define-skeleton verilog-sk-uvm-object
13749 "Insert a class definition"
13751 > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n
13753 > "`uvm_object_utils_begin(" name ")" \n
13754 > (- verilog-indent-level) "`uvm_object_utils_end" \n
13756 > "function new(string name=\"" name "\");" \n
13757 > "super.new(name);" \n
13758 > (- verilog-indent-level) "endfunction" \n
13760 > "endclass" (progn (electric-verilog-terminate-line) nil))
13762 (define-skeleton verilog-sk-uvm-component
13763 "Insert a class definition"
13765 > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n
13767 > "`uvm_component_utils_begin(" name ")" \n
13768 > (- verilog-indent-level) "`uvm_component_utils_end" \n
13770 > "function new(string name=\"\", uvm_component parent);" \n
13771 > "super.new(name, parent);" \n
13772 > (- verilog-indent-level) "endfunction" \n
13774 > "endclass" (progn (electric-verilog-terminate-line) nil))
13776 (define-skeleton verilog-sk-primitive
13777 "Insert a task definition."
13779 > "primitive " '(verilog-sk-prompt-name) " ( " '(verilog-sk-prompt-output) ("input:" ", " str ) " );"\n
13781 > (- verilog-indent-level-behavioral) "endprimitive" (progn (electric-verilog-terminate-line) nil))
13783 (define-skeleton verilog-sk-task
13784 "Insert a task definition."
13786 > "task " '(verilog-sk-prompt-name) & ?; \n
13790 > (- verilog-indent-level-behavioral) "end" \n
13791 > (- verilog-indent-level-behavioral) "endtask" (progn (electric-verilog-terminate-line) nil))
13793 (define-skeleton verilog-sk-function
13794 "Insert a function definition."
13796 > "function [" '(verilog-sk-prompt-width) | -1 '(verilog-sk-prompt-name) ?; \n
13800 > (- verilog-indent-level-behavioral) "end" \n
13801 > (- verilog-indent-level-behavioral) "endfunction" (progn (electric-verilog-terminate-line) nil))
13803 (define-skeleton verilog-sk-always
13804 "Insert always block. Uses the minibuffer to prompt
13805 for sensitivity list."
13807 > "always @ ( /*AUTOSENSE*/ ) begin\n"
13809 > (- verilog-indent-level-behavioral) "end" \n >
13812 (define-skeleton verilog-sk-initial
13813 "Insert an initial block."
13815 > "initial begin\n"
13817 > (- verilog-indent-level-behavioral) "end" \n > )
13819 (define-skeleton verilog-sk-specify
13820 "Insert specify block. "
13824 > (- verilog-indent-level-behavioral) "endspecify" \n > )
13826 (define-skeleton verilog-sk-generate
13827 "Insert generate block. "
13831 > (- verilog-indent-level-behavioral) "endgenerate" \n > )
13833 (define-skeleton verilog-sk-begin
13834 "Insert begin end block. Uses the minibuffer to prompt for name."
13836 > "begin" '(verilog-sk-prompt-name) \n
13838 > (- verilog-indent-level-behavioral) "end" )
13840 (define-skeleton verilog-sk-fork
13841 "Insert a fork join block."
13846 > (- verilog-indent-level-behavioral) "end" \n
13849 > (- verilog-indent-level-behavioral) "end" \n
13850 > (- verilog-indent-level-behavioral) "join" \n
13854 (define-skeleton verilog-sk-case
13855 "Build skeleton case statement, prompting for the selector expression,
13856 and the case items."
13857 "[selector expression]: "
13858 > "case (" str ") " \n
13859 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
13860 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
13862 (define-skeleton verilog-sk-casex
13863 "Build skeleton casex statement, prompting for the selector expression,
13864 and the case items."
13865 "[selector expression]: "
13866 > "casex (" str ") " \n
13867 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
13868 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
13870 (define-skeleton verilog-sk-casez
13871 "Build skeleton casez statement, prompting for the selector expression,
13872 and the case items."
13873 "[selector expression]: "
13874 > "casez (" str ") " \n
13875 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
13876 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
13878 (define-skeleton verilog-sk-if
13879 "Insert a skeleton if statement."
13880 > "if (" '(verilog-sk-prompt-condition) & ")" " begin" \n
13882 > (- verilog-indent-level-behavioral) "end " \n )
13884 (define-skeleton verilog-sk-else-if
13885 "Insert a skeleton else if statement."
13886 > (verilog-indent-line) "else if ("
13887 (progn (setq verilog-sk-p (point)) nil) '(verilog-sk-prompt-condition) (if (> (point) verilog-sk-p) ") " -1 ) & " begin" \n
13889 > "end" (progn (electric-verilog-terminate-line) nil))
13891 (define-skeleton verilog-sk-datadef
13892 "Common routine to get data definition."
13894 '(verilog-sk-prompt-width) | -1 ("name (RET to end):" str ", ") -2 ";" \n)
13896 (define-skeleton verilog-sk-input
13897 "Insert an input definition."
13899 > "input [" '(verilog-sk-datadef))
13901 (define-skeleton verilog-sk-output
13902 "Insert an output definition."
13904 > "output [" '(verilog-sk-datadef))
13906 (define-skeleton verilog-sk-inout
13907 "Insert an inout definition."
13909 > "inout [" '(verilog-sk-datadef))
13911 (defvar verilog-sk-signal nil)
13912 (define-skeleton verilog-sk-def-reg
13913 "Insert a reg definition."
13915 > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-signal ";" \n (verilog-pretty-declarations-auto) )
13917 (defun verilog-sk-define-signal ()
13918 "Insert a definition of signal under point at top of module."
13920 (let* ((sig-re "[a-zA-Z0-9_]*")
13921 (v1 (buffer-substring
13923 (skip-chars-backward sig-re)
13926 (skip-chars-forward sig-re)
13928 (if (not (member v1 verilog-keywords))
13930 (setq verilog-sk-signal v1)
13931 (verilog-beg-of-defun)
13932 (verilog-end-of-statement)
13933 (verilog-forward-syntactic-ws)
13934 (verilog-sk-def-reg)
13935 (message "signal at point is %s" v1))
13936 (message "object at point (%s) is a keyword" v1))))
13938 (define-skeleton verilog-sk-wire
13939 "Insert a wire definition."
13941 > "wire [" '(verilog-sk-datadef))
13943 (define-skeleton verilog-sk-reg
13944 "Insert a reg definition."
13946 > "reg [" '(verilog-sk-datadef))
13948 (define-skeleton verilog-sk-assign
13949 "Insert a skeleton assign statement."
13951 > "assign " '(verilog-sk-prompt-name) " = " _ ";" \n)
13953 (define-skeleton verilog-sk-while
13954 "Insert a skeleton while loop statement."
13956 > "while (" '(verilog-sk-prompt-condition) ") begin" \n
13958 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
13960 (define-skeleton verilog-sk-repeat
13961 "Insert a skeleton repeat loop statement."
13963 > "repeat (" '(verilog-sk-prompt-condition) ") begin" \n
13965 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
13967 (define-skeleton verilog-sk-for
13968 "Insert a skeleton while loop statement."
13971 '(verilog-sk-prompt-init) "; "
13972 '(verilog-sk-prompt-condition) "; "
13973 '(verilog-sk-prompt-inc)
13976 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
13978 (define-skeleton verilog-sk-comment
13979 "Inserts three comment lines, making a display comment."
13985 (define-skeleton verilog-sk-state-machine
13986 "Insert a state machine definition."
13987 "Name of state variable: "
13988 '(setq input "state")
13989 > "// State registers for " str | -23 \n
13990 '(setq verilog-sk-state str)
13991 > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-state ", next_" verilog-sk-state ?; \n
13994 > "// State FF for " verilog-sk-state \n
13995 > "always @ ( " (read-string "clock:" "posedge clk") " or " (verilog-sk-prompt-reset) " ) begin" \n
13996 > "if ( " verilog-sk-reset " ) " verilog-sk-state " = 0; else" \n
13997 > verilog-sk-state " = next_" verilog-sk-state ?; \n
13998 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil)
14000 > "// Next State Logic for " verilog-sk-state \n
14001 > "always @ ( /*AUTOSENSE*/ ) begin\n"
14002 > "case (" '(verilog-sk-prompt-state-selector) ") " \n
14003 > ("case selector: " str ": begin" \n > "next_" verilog-sk-state " = " _ ";" \n > (- verilog-indent-level-behavioral) "end" \n )
14004 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil)
14005 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil))
14009 ;; Include file loading with mouse/return event
14011 ;; idea & first impl.: M. Rouat (eldo-mode.el)
14012 ;; second (emacs/xemacs) impl.: G. Van der Plas (spice-mode.el)
14014 (if (featurep 'xemacs)
14015 (require 'overlay))
14017 (defconst verilog-include-file-regexp
14018 "^`include\\s-+\"\\([^\n\"]*\\)\""
14019 "Regexp that matches the include file.")
14021 (defvar verilog-mode-mouse-map
14022 (let ((map (make-sparse-keymap))) ; as described in info pages, make a map
14023 (set-keymap-parent map verilog-mode-map)
14024 ;; mouse button bindings
14025 (define-key map "\r" 'verilog-load-file-at-point)
14026 (if (featurep 'xemacs)
14027 (define-key map 'button2 'verilog-load-file-at-mouse);ffap-at-mouse ?
14028 (define-key map [mouse-2] 'verilog-load-file-at-mouse))
14029 (if (featurep 'xemacs)
14030 (define-key map 'Sh-button2 'mouse-yank) ; you wanna paste don't you ?
14031 (define-key map [S-mouse-2] 'mouse-yank-at-click))
14033 "Map containing mouse bindings for `verilog-mode'.")
14036 (defun verilog-highlight-region (beg end _old-len)
14037 "Colorize included files and modules in the (changed?) region.
14038 Clicking on the middle-mouse button loads them in a buffer (as in dired)."
14039 (when (or verilog-highlight-includes
14040 verilog-highlight-modules)
14042 (save-match-data ;; A query-replace may call this function - do not disturb
14043 (verilog-save-buffer-state
14044 (verilog-save-scan-cache
14047 (setq end-point (point-at-eol))
14049 (beginning-of-line) ; scan entire line
14050 ;; delete overlays existing on this line
14051 (let ((overlays (overlays-in (point) end-point)))
14054 (overlay-get (car overlays) 'detachable)
14055 (or (overlay-get (car overlays) 'verilog-include-file)
14056 (overlay-get (car overlays) 'verilog-inst-module)))
14057 (delete-overlay (car overlays)))
14058 (setq overlays (cdr overlays))))
14060 ;; make new include overlays
14061 (when verilog-highlight-includes
14062 (while (search-forward-regexp verilog-include-file-regexp end-point t)
14063 (goto-char (match-beginning 1))
14064 (let ((ov (make-overlay (match-beginning 1) (match-end 1))))
14065 (overlay-put ov 'start-closed 't)
14066 (overlay-put ov 'end-closed 't)
14067 (overlay-put ov 'evaporate 't)
14068 (overlay-put ov 'verilog-include-file 't)
14069 (overlay-put ov 'mouse-face 'highlight)
14070 (overlay-put ov 'local-map verilog-mode-mouse-map))))
14072 ;; make new module overlays
14074 ;; This scanner is syntax-fragile, so don't get bent
14075 (when verilog-highlight-modules
14076 (condition-case nil
14077 (while (verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-point t)
14079 (goto-char (match-beginning 0))
14080 (unless (verilog-inside-comment-or-string-p)
14081 (verilog-read-inst-module-matcher) ;; sets match 0
14082 (let* ((ov (make-overlay (match-beginning 0) (match-end 0))))
14083 (overlay-put ov 'start-closed 't)
14084 (overlay-put ov 'end-closed 't)
14085 (overlay-put ov 'evaporate 't)
14086 (overlay-put ov 'verilog-inst-module 't)
14087 (overlay-put ov 'mouse-face 'highlight)
14088 (overlay-put ov 'local-map verilog-mode-mouse-map)))))
14091 ;; Future highlights:
14092 ;; variables - make an Occur buffer of where referenced
14093 ;; pins - make an Occur buffer of the sig in the declaration module
14096 (defun verilog-highlight-buffer ()
14097 "Colorize included files and modules across the whole buffer."
14098 ;; Invoked via verilog-mode calling font-lock then `font-lock-mode-hook'
14100 ;; delete and remake overlays
14101 (verilog-highlight-region (point-min) (point-max) nil))
14103 ;; Deprecated, but was interactive, so we'll keep it around
14104 (defalias 'verilog-colorize-include-files-buffer 'verilog-highlight-buffer)
14106 ;; ffap-at-mouse isn't useful for Verilog mode. It uses library paths.
14107 ;; so define this function to do more or less the same as ffap-at-mouse
14108 ;; but first resolve filename...
14109 (defun verilog-load-file-at-mouse (event)
14110 "Load file under button 2 click's EVENT.
14111 Files are checked based on `verilog-library-flags'."
14113 (save-excursion ;; implement a Verilog specific ffap-at-mouse
14114 (mouse-set-point event)
14115 (verilog-load-file-at-point t)))
14117 ;; ffap isn't usable for Verilog mode. It uses library paths.
14118 ;; so define this function to do more or less the same as ffap
14119 ;; but first resolve filename...
14120 (defun verilog-load-file-at-point (&optional warn)
14121 "Load file under point.
14122 If WARN, throw warning if not found.
14123 Files are checked based on `verilog-library-flags'."
14125 (save-excursion ;; implement a Verilog specific ffap
14126 (let ((overlays (overlays-in (point) (point)))
14128 (while (and overlays (not hit))
14129 (when (overlay-get (car overlays) 'verilog-inst-module)
14130 (verilog-goto-defun-file (buffer-substring
14131 (overlay-start (car overlays))
14132 (overlay-end (car overlays))))
14134 (setq overlays (cdr overlays)))
14136 (beginning-of-line)
14137 (when (and (not hit)
14138 (looking-at verilog-include-file-regexp))
14139 (if (and (car (verilog-library-filenames
14140 (match-string 1) (buffer-file-name)))
14141 (file-readable-p (car (verilog-library-filenames
14142 (match-string 1) (buffer-file-name)))))
14143 (find-file (car (verilog-library-filenames
14144 (match-string 1) (buffer-file-name))))
14147 "File '%s' isn't readable, use shift-mouse2 to paste in this field"
14148 (match-string 1))))))))
14154 (defun verilog-faq ()
14155 "Tell the user their current version, and where to get the FAQ etc."
14157 (with-output-to-temp-buffer "*verilog-mode help*"
14158 (princ (format "You are using verilog-mode %s\n" verilog-mode-version))
14160 (princ "For new releases, see http://www.verilog.com\n")
14162 (princ "For frequently asked questions, see http://www.veripool.org/verilog-mode-faq.html\n")
14164 (princ "To submit a bug, use M-x verilog-submit-bug-report\n")
14167 (autoload 'reporter-submit-bug-report "reporter")
14168 (defvar reporter-prompt-for-summary-p)
14170 (defun verilog-submit-bug-report ()
14171 "Submit via mail a bug report on verilog-mode.el."
14173 (let ((reporter-prompt-for-summary-p t))
14174 (reporter-submit-bug-report
14175 "mac@verilog.com, wsnyder@wsnyder.org"
14176 (concat "verilog-mode v" verilog-mode-version)
14178 verilog-active-low-regexp
14179 verilog-after-save-font-hook
14180 verilog-align-ifelse
14181 verilog-assignment-delay
14182 verilog-auto-arg-sort
14183 verilog-auto-declare-nettype
14184 verilog-auto-delete-trailing-whitespace
14185 verilog-auto-endcomments
14187 verilog-auto-ignore-concat
14188 verilog-auto-indent-on-newline
14189 verilog-auto-inout-ignore-regexp
14190 verilog-auto-input-ignore-regexp
14191 verilog-auto-inst-column
14192 verilog-auto-inst-dot-name
14193 verilog-auto-inst-interfaced-ports
14194 verilog-auto-inst-param-value
14195 verilog-auto-inst-sort
14196 verilog-auto-inst-template-numbers
14197 verilog-auto-inst-vector
14198 verilog-auto-lineup
14199 verilog-auto-newline
14200 verilog-auto-output-ignore-regexp
14201 verilog-auto-read-includes
14202 verilog-auto-reset-blocking-in-non
14203 verilog-auto-reset-widths
14204 verilog-auto-save-policy
14205 verilog-auto-sense-defines-constant
14206 verilog-auto-sense-include-inputs
14207 verilog-auto-star-expand
14208 verilog-auto-star-save
14209 verilog-auto-template-warn-unused
14210 verilog-auto-tieoff-declaration
14211 verilog-auto-tieoff-ignore-regexp
14212 verilog-auto-unused-ignore-regexp
14213 verilog-auto-wire-type
14214 verilog-before-auto-hook
14215 verilog-before-delete-auto-hook
14216 verilog-before-getopt-flags-hook
14217 verilog-before-save-font-hook
14218 verilog-cache-enabled
14220 verilog-case-indent
14221 verilog-cexp-indent
14224 verilog-delete-auto-hook
14225 verilog-getopt-flags-hook
14226 verilog-highlight-grouping-keywords
14227 verilog-highlight-includes
14228 verilog-highlight-modules
14229 verilog-highlight-p1800-keywords
14230 verilog-highlight-translate-off
14231 verilog-indent-begin-after-if
14232 verilog-indent-declaration-macros
14233 verilog-indent-level
14234 verilog-indent-level-behavioral
14235 verilog-indent-level-declaration
14236 verilog-indent-level-directive
14237 verilog-indent-level-module
14238 verilog-indent-lists
14239 verilog-library-directories
14240 verilog-library-extensions
14241 verilog-library-files
14242 verilog-library-flags
14244 verilog-minimum-comment-distance
14246 verilog-mode-release-emacs
14247 verilog-mode-version
14248 verilog-preprocessor
14250 verilog-tab-always-indent
14251 verilog-tab-to-comment
14252 verilog-typedef-regexp
14258 I want to report a bug.
14260 Before I go further, I want to say that Verilog mode has changed my life.
14261 I save so much time, my files are colored nicely, my co workers respect
14262 my coding ability... until now. I'd really appreciate anything you
14263 could do to help me out with this minor deficiency in the product.
14265 I've taken a look at the Verilog-Mode FAQ at
14266 http://www.veripool.org/verilog-mode-faq.html.
14268 And, I've considered filing the bug on the issue tracker at
14269 http://www.veripool.org/verilog-mode-bugs
14270 since I realize that public bugs are easier for you to track,
14271 and for others to search, but would prefer to email.
14273 So, to reproduce the bug, start a fresh Emacs via " invocation-name "
14274 -no-init-file -no-site-file'. In a new buffer, in Verilog mode, type
14275 the code included below.
14277 Given those lines, I expected [[Fill in here]] to happen;
14278 but instead, [[Fill in here]] happens!.
14280 == The code: =="))))
14282 (provide 'verilog-mode)
14284 ;; Local Variables:
14285 ;; checkdoc-permit-comma-termination-flag:t
14286 ;; checkdoc-force-docstrings-flag:nil
14289 ;;; verilog-mode.el ends here