1 ;; verilog-mode.el --- major mode for editing verilog source in Emacs
3 ;; Copyright (C) 1996-2013 Free Software Foundation, Inc.
5 ;; Author: Michael McNamara (mac@verilog.com),
6 ;; Wilson Snyder (wsnyder@wsnyder.org)
7 ;; Please see our web sites:
8 ;; http://www.verilog.com
9 ;; http://www.veripool.org
11 ;; Keywords: languages
13 ;; Yoni Rabkin <yoni@rabkins.net> contacted the maintainer of this
14 ;; file on 19/3/2008, and the maintainer agreed that when a bug is
15 ;; filed in the Emacs bug reporting system against this file, a copy
16 ;; of the bug report be sent to the maintainer's email address.
18 ;; This code supports Emacs 21.1 and later
19 ;; And XEmacs 21.1 and later
20 ;; Please do not make changes that break Emacs 21. Thanks!
24 ;; This file is part of GNU Emacs.
26 ;; GNU Emacs is free software: you can redistribute it and/or modify
27 ;; it under the terms of the GNU General Public License as published by
28 ;; the Free Software Foundation, either version 3 of the License, or
29 ;; (at your option) any later version.
31 ;; GNU Emacs is distributed in the hope that it will be useful,
32 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
33 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34 ;; GNU General Public License for more details.
36 ;; You should have received a copy of the GNU General Public License
37 ;; along with GNU Emacs. If not, see <http://www.gnu.org/licenses/>.
41 ;; This mode borrows heavily from the Pascal-mode and the cc-mode of Emacs
46 ;; A major mode for editing Verilog HDL source code. When you have
47 ;; entered Verilog mode, you may get more info by pressing C-h m. You
48 ;; may also get online help describing various functions by: C-h f
49 ;; <Name of function you want described>
51 ;; KNOWN BUGS / BUG REPORTS
52 ;; =======================
54 ;; Verilog is a rapidly evolving language, and hence this mode is
55 ;; under continuous development. Hence this is beta code, and likely
56 ;; has bugs. Please report any issues to the issue tracker at
57 ;; http://www.veripool.org/verilog-mode
58 ;; Please use verilog-submit-bug-report to submit a report; type C-c
59 ;; C-b to invoke this and as a result I will have a much easier time
60 ;; of reproducing the bug you find, and hence fixing it.
62 ;; INSTALLING THE MODE
63 ;; ===================
65 ;; An older version of this mode may be already installed as a part of
66 ;; your environment, and one method of updating would be to update
67 ;; your Emacs environment. Sometimes this is difficult for local
68 ;; political/control reasons, and hence you can always install a
69 ;; private copy (or even a shared copy) which overrides the system
72 ;; You can get step by step help in installing this file by going to
73 ;; <http://www.verilog.com/emacs_install.html>
75 ;; The short list of installation instructions are: To set up
76 ;; automatic Verilog mode, put this file in your load path, and put
77 ;; the following in code (please un comment it first!) in your
78 ;; .emacs, or in your site's site-load.el
80 ; (autoload 'verilog-mode "verilog-mode" "Verilog mode" t )
81 ; (add-to-list 'auto-mode-alist '("\\.[ds]?vh?\\'" . verilog-mode))
83 ;; Be sure to examine at the help for verilog-auto, and the other
84 ;; verilog-auto-* functions for some major coding time savers.
86 ;; If you want to customize Verilog mode to fit your needs better,
87 ;; you may add the below lines (the values of the variables presented
88 ;; here are the defaults). Note also that if you use an Emacs that
89 ;; supports custom, it's probably better to use the custom menu to
90 ;; edit these. If working as a member of a large team these settings
91 ;; should be common across all users (in a site-start file), or set
92 ;; in Local Variables in every file. Otherwise, different people's
93 ;; AUTO expansion may result different whitespace changes.
95 ; ;; Enable syntax highlighting of **all** languages
96 ; (global-font-lock-mode t)
98 ; ;; User customization for Verilog mode
99 ; (setq verilog-indent-level 3
100 ; verilog-indent-level-module 3
101 ; verilog-indent-level-declaration 3
102 ; verilog-indent-level-behavioral 3
103 ; verilog-indent-level-directive 1
104 ; verilog-case-indent 2
105 ; verilog-auto-newline t
106 ; verilog-auto-indent-on-newline t
107 ; verilog-tab-always-indent t
108 ; verilog-auto-endcomments t
109 ; verilog-minimum-comment-distance 40
110 ; verilog-indent-begin-after-if t
111 ; verilog-auto-lineup 'declarations
112 ; verilog-highlight-p1800-keywords nil
113 ; verilog-linter "my_lint_shell_command"
120 ;; See commit history at http://www.veripool.org/verilog-mode.html
121 ;; (This section is required to appease checkdoc.)
125 ;; This variable will always hold the version number of the mode
126 (defconst verilog-mode-version (substring "$$Revision: 820 $$" 12 -3)
127 "Version of this Verilog mode.")
128 (defconst verilog-mode-release-date (substring "$$Date: 2012-09-17 20:43:10 -0400 (Mon, 17 Sep 2012) $$" 8 -3)
129 "Release date of this Verilog mode.")
130 (defconst verilog-mode-release-emacs t
131 "If non-nil, this version of Verilog mode was released with Emacs itself.")
133 (defun verilog-version ()
134 "Inform caller of the version of this file."
136 (message "Using verilog-mode version %s" verilog-mode-version))
138 ;; Insure we have certain packages, and deal with it if we don't
139 ;; Be sure to note which Emacs flavor and version added each feature.
141 ;; Provide stuff if we are XEmacs
142 (when (featurep 'xemacs)
147 (require 'regexp-opt)
149 ;; Bug in 19.28 through 19.30 skeleton.el, not provided.
156 (defmacro when (cond &rest body)
157 (list 'if cond (cons 'progn body))))
160 (if (fboundp 'unless)
162 (defmacro unless (cond &rest body)
163 (cons 'if (cons cond (cons nil body)))))
166 (if (fboundp 'store-match-data)
168 (defmacro store-match-data (&rest args) nil))
171 (if (fboundp 'char-before)
173 (defmacro char-before (&rest body)
174 (char-after (1- (point)))))
179 (defsubst point-at-bol (&optional N)
180 (save-excursion (beginning-of-line N) (point))))
185 (defsubst point-at-eol (&optional N)
186 (save-excursion (end-of-line N) (point))))
192 (if (fboundp 'match-string-no-properties)
194 (defsubst match-string-no-properties (num &optional string)
195 "Return string of text matched by last search, without text properties.
196 NUM specifies which parenthesized expression in the last regexp.
197 Value is nil if NUMth pair didn't match, or there were less than NUM pairs.
198 Zero means the entire text matched by the whole regexp or whole string.
199 STRING should be given if the last search was by `string-match' on STRING."
200 (if (match-beginning num)
204 (match-beginning num) (match-end num))))
205 (set-text-properties 0 (length result) nil result)
207 (buffer-substring-no-properties (match-beginning num)
212 (if (and (featurep 'custom) (fboundp 'custom-declare-variable))
213 nil ;; We've got what we needed
214 ;; We have the old custom-library, hack around it!
215 (defmacro defgroup (&rest args) nil)
216 (defmacro customize (&rest args)
218 "Sorry, Customize is not available with this version of Emacs"))
219 (defmacro defcustom (var value doc &rest args)
220 `(defvar ,var ,value ,doc))
222 (if (fboundp 'defface)
224 (defmacro defface (var values doc &rest args)
228 (if (and (featurep 'custom) (fboundp 'customize-group))
229 nil ;; We've got what we needed
230 ;; We have an intermediate custom-library, hack around it!
231 (defmacro customize-group (var &rest args)
235 (unless (boundp 'inhibit-point-motion-hooks)
236 (defvar inhibit-point-motion-hooks nil))
237 (unless (boundp 'deactivate-mark)
238 (defvar deactivate-mark nil))
241 ;; OK, do this stuff if we are NOT XEmacs:
242 (unless (featurep 'xemacs)
243 (unless (fboundp 'region-active-p)
244 (defmacro region-active-p ()
245 `(and transient-mark-mode mark-active))))
248 ;; Provide a regular expression optimization routine, using regexp-opt
249 ;; if provided by the user's elisp libraries
251 ;; The below were disabled when GNU Emacs 22 was released;
252 ;; perhaps some still need to be there to support Emacs 21.
253 (if (featurep 'xemacs)
254 (if (fboundp 'regexp-opt)
255 ;; regexp-opt is defined, does it take 3 or 2 arguments?
256 (if (fboundp 'function-max-args)
257 (let ((args (function-max-args `regexp-opt)))
259 ((eq args 3) ;; It takes 3
260 (condition-case nil ; Hide this defun from emacses
261 ;with just a two input regexp
262 (defun verilog-regexp-opt (a b)
263 "Deal with differing number of required arguments for `regexp-opt'.
264 Call 'regexp-opt' on A and B."
268 ((eq args 2) ;; It takes 2
269 (defun verilog-regexp-opt (a b)
270 "Call 'regexp-opt' on A and B."
274 ;; We can't tell; assume it takes 2
275 (defun verilog-regexp-opt (a b)
276 "Call 'regexp-opt' on A and B."
279 ;; There is no regexp-opt, provide our own
280 (defun verilog-regexp-opt (strings &optional paren shy)
281 (let ((open (if paren "\\(" "")) (close (if paren "\\)" "")))
282 (concat open (mapconcat 'regexp-quote strings "\\|") close)))
285 (defalias 'verilog-regexp-opt 'regexp-opt)))
288 ;; Both xemacs and emacs
290 (require 'diff) ;; diff-command and diff-switches
293 (require 'compile) ;; compilation-error-regexp-alist-alist
296 (unless (fboundp 'buffer-chars-modified-tick) ;; Emacs 22 added
297 (defmacro buffer-chars-modified-tick () (buffer-modified-tick)))
299 ;; Added in Emacs 24.1
301 (unless (fboundp 'prog-mode)
302 (define-derived-mode prog-mode fundamental-mode "Prog"))
306 (defun verilog-regexp-words (a)
307 "Call 'regexp-opt' with word delimiters for the words A."
308 (concat "\\<" (verilog-regexp-opt a t) "\\>")))
309 (defun verilog-regexp-words (a)
310 "Call 'regexp-opt' with word delimiters for the words A."
311 ;; The FAQ references this function, so user LISP sometimes calls it
312 (concat "\\<" (verilog-regexp-opt a t) "\\>"))
314 (defun verilog-easy-menu-filter (menu)
315 "Filter `easy-menu-define' MENU to support new features."
316 (cond ((not (featurep 'xemacs))
317 menu) ;; GNU Emacs - passthru
318 ;; XEmacs doesn't support :help. Strip it.
319 ;; Recursively filter the a submenu
321 (mapcar 'verilog-easy-menu-filter menu))
322 ;; Look for [:help "blah"] and remove
324 (let ((i 0) (out []))
325 (while (< i (length menu))
326 (if (equal `:help (aref menu i))
328 (setq out (vconcat out (vector (aref menu i)))
331 (t menu))) ;; Default - ok
332 ;;(verilog-easy-menu-filter
333 ;; `("Verilog" ("MA" ["SAA" nil :help "Help SAA"] ["SAB" nil :help "Help SAA"])
334 ;; "----" ["MB" nil :help "Help MB"]))
336 (defun verilog-define-abbrev (table name expansion &optional hook)
337 "Filter `define-abbrev' TABLE NAME EXPANSION and call HOOK.
338 Provides SYSTEM-FLAG in newer Emacs."
340 (define-abbrev table name expansion hook 0 t)
342 (define-abbrev table name expansion hook))))
344 (defun verilog-customize ()
345 "Customize variables and other settings used by Verilog-Mode."
347 (customize-group 'verilog-mode))
349 (defun verilog-font-customize ()
350 "Customize fonts used by Verilog-Mode."
352 (if (fboundp 'customize-apropos)
353 (customize-apropos "font-lock-*" 'faces)))
355 (defun verilog-booleanp (value)
356 "Return t if VALUE is boolean.
357 This implements GNU Emacs 22.1's `booleanp' function in earlier Emacs.
358 This function may be removed when Emacs 21 is no longer supported."
359 (or (equal value t) (equal value nil)))
361 (defun verilog-insert-last-command-event ()
362 "Insert the `last-command-event'."
363 (insert (if (featurep 'xemacs)
364 ;; XEmacs 21.5 doesn't like last-command-event
366 ;; And GNU Emacs 22 has obsoleted last-command-char
367 last-command-event)))
369 (defvar verilog-no-change-functions nil
370 "True if `after-change-functions' is disabled.
371 Use of `syntax-ppss' may break, as ppss's cache may get corrupted.")
373 (defvar verilog-in-hooks nil
374 "True when within a `verilog-run-hooks' block.")
376 (defmacro verilog-run-hooks (&rest hooks)
377 "Run each hook in HOOKS using `run-hooks'.
378 Set `verilog-in-hooks' during this time, to assist AUTO caches."
379 `(let ((verilog-in-hooks t))
380 (run-hooks ,@hooks)))
382 (defun verilog-syntax-ppss (&optional pos)
383 (when verilog-no-change-functions
385 (verilog-scan-cache-flush)
386 ;; else don't let the AUTO code itself get away with flushing the cache,
387 ;; as that'll make things very slow
389 (error "%s: Internal problem; use of syntax-ppss when cache may be corrupt"
390 (verilog-point-text))))
391 (if (fboundp 'syntax-ppss)
393 (parse-partial-sexp (point-min) (or pos (point)))))
395 (defgroup verilog-mode nil
396 "Major mode for Verilog source code."
400 ; (defgroup verilog-mode-fonts nil
401 ; "Facilitates easy customization fonts used in Verilog source text"
402 ; :link '(customize-apropos "font-lock-*" 'faces)
403 ; :group 'verilog-mode)
405 (defgroup verilog-mode-indent nil
406 "Customize indentation and highlighting of Verilog source text."
407 :group 'verilog-mode)
409 (defgroup verilog-mode-actions nil
410 "Customize actions on Verilog source text."
411 :group 'verilog-mode)
413 (defgroup verilog-mode-auto nil
414 "Customize AUTO actions when expanding Verilog source text."
415 :group 'verilog-mode)
417 (defvar verilog-debug nil
418 "Non-nil means enable debug messages for `verilog-mode' internals.")
420 (defvar verilog-warn-fatal nil
421 "Non-nil means `verilog-warn-error' warnings are fatal `error's.")
423 (defcustom verilog-linter
424 "echo 'No verilog-linter set, see \"M-x describe-variable verilog-linter\"'"
425 "Unix program and arguments to call to run a lint checker on Verilog source.
426 Depending on the `verilog-set-compile-command', this may be invoked when
427 you type \\[compile]. When the compile completes, \\[next-error] will take
428 you to the next lint error."
430 :group 'verilog-mode-actions)
431 ;; We don't mark it safe, as it's used as a shell command
433 (defcustom verilog-coverage
434 "echo 'No verilog-coverage set, see \"M-x describe-variable verilog-coverage\"'"
435 "Program and arguments to use to annotate for coverage Verilog source.
436 Depending on the `verilog-set-compile-command', this may be invoked when
437 you type \\[compile]. When the compile completes, \\[next-error] will take
438 you to the next lint error."
440 :group 'verilog-mode-actions)
441 ;; We don't mark it safe, as it's used as a shell command
443 (defcustom verilog-simulator
444 "echo 'No verilog-simulator set, see \"M-x describe-variable verilog-simulator\"'"
445 "Program and arguments to use to interpret Verilog source.
446 Depending on the `verilog-set-compile-command', this may be invoked when
447 you type \\[compile]. When the compile completes, \\[next-error] will take
448 you to the next lint error."
450 :group 'verilog-mode-actions)
451 ;; We don't mark it safe, as it's used as a shell command
453 (defcustom verilog-compiler
454 "echo 'No verilog-compiler set, see \"M-x describe-variable verilog-compiler\"'"
455 "Program and arguments to use to compile Verilog source.
456 Depending on the `verilog-set-compile-command', this may be invoked when
457 you type \\[compile]. When the compile completes, \\[next-error] will take
458 you to the next lint error."
460 :group 'verilog-mode-actions)
461 ;; We don't mark it safe, as it's used as a shell command
463 (defcustom verilog-preprocessor
464 ;; Very few tools give preprocessed output, so we'll default to Verilog-Perl
465 "vppreproc __FLAGS__ __FILE__"
466 "Program and arguments to use to preprocess Verilog source.
467 This is invoked with `verilog-preprocess', and depending on the
468 `verilog-set-compile-command', may also be invoked when you type
469 \\[compile]. When the compile completes, \\[next-error] will
470 take you to the next lint error."
472 :group 'verilog-mode-actions)
473 ;; We don't mark it safe, as it's used as a shell command
475 (defvar verilog-preprocess-history nil
476 "History for `verilog-preprocess'.")
478 (defvar verilog-tool 'verilog-linter
479 "Which tool to use for building compiler-command.
480 Either nil, `verilog-linter, `verilog-compiler,
481 `verilog-coverage, `verilog-preprocessor, or `verilog-simulator.
482 Alternatively use the \"Choose Compilation Action\" menu. See
483 `verilog-set-compile-command' for more information.")
485 (defcustom verilog-highlight-translate-off nil
486 "Non-nil means background-highlight code excluded from translation.
487 That is, all code between \"// synopsys translate_off\" and
488 \"// synopsys translate_on\" is highlighted using a different background color
489 \(face `verilog-font-lock-translate-off-face').
491 Note: This will slow down on-the-fly fontification (and thus editing).
493 Note: Activate the new setting in a Verilog buffer by re-fontifying it (menu
494 entry \"Fontify Buffer\"). XEmacs: turn off and on font locking."
496 :group 'verilog-mode-indent)
497 ;; Note we don't use :safe, as that would break on Emacsen before 22.0.
498 (put 'verilog-highlight-translate-off 'safe-local-variable 'verilog-booleanp)
500 (defcustom verilog-auto-lineup 'declarations
501 "Type of statements to lineup across multiple lines.
502 If 'all' is selected, then all line ups described below are done.
504 If 'declaration', then just declarations are lined up with any
505 preceding declarations, taking into account widths and the like,
506 so or example the code:
513 If 'assignment', then assignments are lined up with any preceding
514 assignments, so for example the code
515 a_long_variable <= b + c;
518 a_long_variable <= b + c;
521 In order to speed up editing, large blocks of statements are lined up
522 only when a \\[verilog-pretty-expr] is typed; and large blocks of declarations
523 are lineup only when \\[verilog-pretty-declarations] is typed."
525 :type '(radio (const :tag "Line up Assignments and Declarations" all)
526 (const :tag "Line up Assignment statements" assignments )
527 (const :tag "Line up Declarations" declarations)
528 (function :tag "Other"))
529 :group 'verilog-mode-indent )
530 (put 'verilog-auto-lineup 'safe-local-variable
531 '(lambda (x) (memq x '(nil all assignments declarations))))
533 (defcustom verilog-indent-level 3
534 "Indentation of Verilog statements with respect to containing block."
535 :group 'verilog-mode-indent
537 (put 'verilog-indent-level 'safe-local-variable 'integerp)
539 (defcustom verilog-indent-level-module 3
540 "Indentation of Module level Verilog statements (eg always, initial).
541 Set to 0 to get initial and always statements lined up on the left side of
543 :group 'verilog-mode-indent
545 (put 'verilog-indent-level-module 'safe-local-variable 'integerp)
547 (defcustom verilog-indent-level-declaration 3
548 "Indentation of declarations with respect to containing block.
549 Set to 0 to get them list right under containing block."
550 :group 'verilog-mode-indent
552 (put 'verilog-indent-level-declaration 'safe-local-variable 'integerp)
554 (defcustom verilog-indent-declaration-macros nil
555 "How to treat macro expansions in a declaration.
560 If non nil, treat as:
564 :group 'verilog-mode-indent
566 (put 'verilog-indent-declaration-macros 'safe-local-variable 'verilog-booleanp)
568 (defcustom verilog-indent-lists t
569 "How to treat indenting items in a list.
570 If t (the default), indent as:
571 always @( posedge a or
575 always @( posedge a or
577 :group 'verilog-mode-indent
579 (put 'verilog-indent-lists 'safe-local-variable 'verilog-booleanp)
581 (defcustom verilog-indent-level-behavioral 3
582 "Absolute indentation of first begin in a task or function block.
583 Set to 0 to get such code to start at the left side of the screen."
584 :group 'verilog-mode-indent
586 (put 'verilog-indent-level-behavioral 'safe-local-variable 'integerp)
588 (defcustom verilog-indent-level-directive 1
589 "Indentation to add to each level of `ifdef declarations.
590 Set to 0 to have all directives start at the left side of the screen."
591 :group 'verilog-mode-indent
593 (put 'verilog-indent-level-directive 'safe-local-variable 'integerp)
595 (defcustom verilog-cexp-indent 2
596 "Indentation of Verilog statements split across lines."
597 :group 'verilog-mode-indent
599 (put 'verilog-cexp-indent 'safe-local-variable 'integerp)
601 (defcustom verilog-case-indent 2
602 "Indentation for case statements."
603 :group 'verilog-mode-indent
605 (put 'verilog-case-indent 'safe-local-variable 'integerp)
607 (defcustom verilog-auto-newline t
608 "Non-nil means automatically newline after semicolons."
609 :group 'verilog-mode-indent
611 (put 'verilog-auto-newline 'safe-local-variable 'verilog-booleanp)
613 (defcustom verilog-auto-indent-on-newline t
614 "Non-nil means automatically indent line after newline."
615 :group 'verilog-mode-indent
617 (put 'verilog-auto-indent-on-newline 'safe-local-variable 'verilog-booleanp)
619 (defcustom verilog-tab-always-indent t
620 "Non-nil means TAB should always re-indent the current line.
621 A nil value means TAB will only reindent when at the beginning of the line."
622 :group 'verilog-mode-indent
624 (put 'verilog-tab-always-indent 'safe-local-variable 'verilog-booleanp)
626 (defcustom verilog-tab-to-comment nil
627 "Non-nil means TAB moves to the right hand column in preparation for a comment."
628 :group 'verilog-mode-actions
630 (put 'verilog-tab-to-comment 'safe-local-variable 'verilog-booleanp)
632 (defcustom verilog-indent-begin-after-if t
633 "Non-nil means indent begin statements following if, else, while, etc.
634 Otherwise, line them up."
635 :group 'verilog-mode-indent
637 (put 'verilog-indent-begin-after-if 'safe-local-variable 'verilog-booleanp)
639 (defcustom verilog-align-ifelse nil
640 "Non-nil means align `else' under matching `if'.
641 Otherwise else is lined up with first character on line holding matching if."
642 :group 'verilog-mode-indent
644 (put 'verilog-align-ifelse 'safe-local-variable 'verilog-booleanp)
646 (defcustom verilog-minimum-comment-distance 10
647 "Minimum distance (in lines) between begin and end required before a comment.
648 Setting this variable to zero results in every end acquiring a comment; the
649 default avoids too many redundant comments in tight quarters."
650 :group 'verilog-mode-indent
652 (put 'verilog-minimum-comment-distance 'safe-local-variable 'integerp)
654 (defcustom verilog-highlight-p1800-keywords nil
655 "Non-nil means highlight words newly reserved by IEEE-1800.
656 These will appear in `verilog-font-lock-p1800-face' in order to gently
657 suggest changing where these words are used as variables to something else.
658 A nil value means highlight these words as appropriate for the SystemVerilog
659 IEEE-1800 standard. Note that changing this will require restarting Emacs
660 to see the effect as font color choices are cached by Emacs."
661 :group 'verilog-mode-indent
663 (put 'verilog-highlight-p1800-keywords 'safe-local-variable 'verilog-booleanp)
665 (defcustom verilog-highlight-grouping-keywords nil
666 "Non-nil means highlight grouping keywords 'begin' and 'end' more dramatically.
667 If false, these words are in the `font-lock-type-face'; if True then they are in
668 `verilog-font-lock-ams-face'. Some find that special highlighting on these
669 grouping constructs allow the structure of the code to be understood at a glance."
670 :group 'verilog-mode-indent
672 (put 'verilog-highlight-grouping-keywords 'safe-local-variable 'verilog-booleanp)
674 (defcustom verilog-highlight-modules nil
675 "Non-nil means highlight module statements for `verilog-load-file-at-point'.
676 When true, mousing over module names will allow jumping to the
677 module definition. If false, this is not supported. Setting
678 this is experimental, and may lead to bad performance."
679 :group 'verilog-mode-indent
681 (put 'verilog-highlight-modules 'safe-local-variable 'verilog-booleanp)
683 (defcustom verilog-highlight-includes t
684 "Non-nil means highlight module statements for `verilog-load-file-at-point'.
685 When true, mousing over include file names will allow jumping to the
686 file referenced. If false, this is not supported."
687 :group 'verilog-mode-indent
689 (put 'verilog-highlight-includes 'safe-local-variable 'verilog-booleanp)
691 (defcustom verilog-auto-declare-nettype nil
692 "Non-nil specifies the data type to use with `verilog-auto-input' etc.
693 Set this to \"wire\" if the Verilog code uses \"`default_nettype
694 none\". Note using `default_nettype none isn't recommended practice; this
695 mode is experimental."
696 :version "24.1" ;; rev670
697 :group 'verilog-mode-actions
699 (put 'verilog-auto-declare-nettype 'safe-local-variable `stringp)
701 (defcustom verilog-auto-wire-type nil
702 "Non-nil specifies the data type to use with `verilog-auto-wire' etc.
703 Set this to \"logic\" for SystemVerilog code, or use `verilog-auto-logic'."
704 :version "24.1" ;; rev673
705 :group 'verilog-mode-actions
707 (put 'verilog-auto-wire-type 'safe-local-variable `stringp)
709 (defcustom verilog-auto-endcomments t
710 "Non-nil means insert a comment /* ... */ after 'end's.
711 The name of the function or case will be set between the braces."
712 :group 'verilog-mode-actions
714 (put 'verilog-auto-endcomments 'safe-local-variable 'verilog-booleanp)
716 (defcustom verilog-auto-delete-trailing-whitespace nil
717 "Non-nil means to `delete-trailing-whitespace' in `verilog-auto'."
718 :version "24.1" ;; rev703
719 :group 'verilog-mode-actions
721 (put 'verilog-auto-delete-trailing-whitespace 'safe-local-variable 'verilog-booleanp)
723 (defcustom verilog-auto-ignore-concat nil
724 "Non-nil means ignore signals in {...} concatenations for AUTOWIRE etc.
725 This will exclude signals referenced as pin connections in {...}
726 from AUTOWIRE, AUTOOUTPUT and friends. This flag should be set
727 for backward compatibility only and not set in new designs; it
728 may be removed in future versions."
729 :group 'verilog-mode-actions
731 (put 'verilog-auto-ignore-concat 'safe-local-variable 'verilog-booleanp)
733 (defcustom verilog-auto-read-includes nil
734 "Non-nil means to automatically read includes before AUTOs.
735 This will do a `verilog-read-defines' and `verilog-read-includes' before
736 each AUTO expansion. This makes it easier to embed defines and includes,
737 but can result in very slow reading times if there are many or large
739 :group 'verilog-mode-actions
741 (put 'verilog-auto-read-includes 'safe-local-variable 'verilog-booleanp)
743 (defcustom verilog-auto-save-policy nil
744 "Non-nil indicates action to take when saving a Verilog buffer with AUTOs.
745 A value of `force' will always do a \\[verilog-auto] automatically if
746 needed on every save. A value of `detect' will do \\[verilog-auto]
747 automatically when it thinks necessary. A value of `ask' will query the
748 user when it thinks updating is needed.
750 You should not rely on the 'ask or 'detect policies, they are safeguards
751 only. They do not detect when AUTOINSTs need to be updated because a
752 sub-module's port list has changed."
753 :group 'verilog-mode-actions
754 :type '(choice (const nil) (const ask) (const detect) (const force)))
756 (defcustom verilog-auto-star-expand t
757 "Non-nil means to expand SystemVerilog .* instance ports.
758 They will be expanded in the same way as if there was an AUTOINST in the
759 instantiation. See also `verilog-auto-star' and `verilog-auto-star-save'."
760 :group 'verilog-mode-actions
762 (put 'verilog-auto-star-expand 'safe-local-variable 'verilog-booleanp)
764 (defcustom verilog-auto-star-save nil
765 "Non-nil means save to disk SystemVerilog .* instance expansions.
766 A nil value indicates direct connections will be removed before saving.
767 Only meaningful to those created due to `verilog-auto-star-expand' being set.
769 Instead of setting this, you may want to use /*AUTOINST*/, which will
771 :group 'verilog-mode-actions
773 (put 'verilog-auto-star-save 'safe-local-variable 'verilog-booleanp)
775 (defvar verilog-auto-update-tick nil
776 "Modification tick at which autos were last performed.")
778 (defvar verilog-auto-last-file-locals nil
779 "Text from file-local-variables during last evaluation.")
781 (defvar verilog-diff-function 'verilog-diff-report
782 "Function to run when `verilog-diff-auto' detects differences.
783 Function takes three arguments, the original buffer, the
784 difference buffer, and the point in original buffer with the
789 (defvar verilog-error-regexp-added nil)
791 (defvar verilog-error-regexp-emacs-alist
794 "\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 3)
796 "([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 1 3)
798 ".*\\*[WE],[0-9A-Z]+\\(\[[0-9A-Z_,]+\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)" 2 3)
800 "[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 2)
802 "\\(WARNING\\|ERROR\\|INFO\\)[^:]*: \\([^,]+\\),\\s-+\\(line \\)?\\([0-9]+\\):" 2 4 )
805 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
806 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 2 5)
808 "\\(Error\\|Warning\\).*in file (\\([^ \t]+\\) at line *\\([0-9]+\\))" 2 3)
810 "\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 3)
812 "Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 2)
814 "\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 3)
816 "syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 2)
818 "%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4)
820 "^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 1 2)
822 "List of regexps for Verilog compilers.
823 See `compilation-error-regexp-alist' for the formatting. For Emacs 22+.")
825 (defvar verilog-error-regexp-xemacs-alist
826 ;; Emacs form is '((v-tool "re" 1 2) ...)
827 ;; XEmacs form is '(verilog ("re" 1 2) ...)
828 ;; So we can just map from Emacs to XEmacs
829 (cons 'verilog (mapcar 'cdr verilog-error-regexp-emacs-alist))
830 "List of regexps for Verilog compilers.
831 See `compilation-error-regexp-alist-alist' for the formatting. For XEmacs.")
833 (defvar verilog-error-font-lock-keywords
836 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t)
837 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t)
839 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 1 bold t)
840 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 3 bold t)
841 ;; verilog-IES (nc-verilog)
842 (".*\\*[WE],[0-9A-Z]+\\(\[[0-9A-Z_,]+\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)|" 2 bold t)
843 (".*\\*[WE],[0-9A-Z]+\\(\[[0-9A-Z_,]+\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)|" 3 bold t)
844 ;; verilog-surefire-1
845 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 bold t)
846 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 2 bold t)
847 ;; verilog-surefire-2
848 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 2 bold t)
849 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 3 bold t)
852 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
853 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t)
855 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
856 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t)
858 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 bold t)
859 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 3 bold t)
861 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t)
862 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t)
864 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t)
865 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 3 bold t)
867 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 bold t)
868 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t)
870 (".*%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 bold t)
871 (".*%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 4 bold t)
873 ("^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 1 bold t)
874 ("^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 2 bold t)
876 "Keywords to also highlight in Verilog *compilation* buffers.
877 Only used in XEmacs; GNU Emacs uses `verilog-error-regexp-emacs-alist'.")
879 (defcustom verilog-library-flags '("")
880 "List of standard Verilog arguments to use for /*AUTOINST*/.
881 These arguments are used to find files for `verilog-auto', and match
882 the flags accepted by a standard Verilog-XL simulator.
884 -f filename Reads more `verilog-library-flags' from the filename.
885 +incdir+dir Adds the directory to `verilog-library-directories'.
886 -Idir Adds the directory to `verilog-library-directories'.
887 -y dir Adds the directory to `verilog-library-directories'.
888 +libext+.v Adds the extensions to `verilog-library-extensions'.
889 -v filename Adds the filename to `verilog-library-files'.
891 filename Adds the filename to `verilog-library-files'.
892 This is not recommended, -v is a better choice.
894 You might want these defined in each file; put at the *END* of your file
898 // verilog-library-flags:(\"-y dir -y otherdir\")
901 Verilog-mode attempts to detect changes to this local variable, but they
902 are only insured to be correct when the file is first visited. Thus if you
903 have problems, use \\[find-alternate-file] RET to have these take effect.
905 See also the variables mentioned above."
906 :group 'verilog-mode-auto
907 :type '(repeat string))
908 (put 'verilog-library-flags 'safe-local-variable 'listp)
910 (defcustom verilog-library-directories '(".")
911 "List of directories when looking for files for /*AUTOINST*/.
912 The directory may be relative to the current file, or absolute.
913 Environment variables are also expanded in the directory names.
914 Having at least the current directory is a good idea.
916 You might want these defined in each file; put at the *END* of your file
920 // verilog-library-directories:(\".\" \"subdir\" \"subdir2\")
923 Verilog-mode attempts to detect changes to this local variable, but they
924 are only insured to be correct when the file is first visited. Thus if you
925 have problems, use \\[find-alternate-file] RET to have these take effect.
927 See also `verilog-library-flags', `verilog-library-files'
928 and `verilog-library-extensions'."
929 :group 'verilog-mode-auto
930 :type '(repeat file))
931 (put 'verilog-library-directories 'safe-local-variable 'listp)
933 (defcustom verilog-library-files '()
934 "List of files to search for modules.
935 AUTOINST will use this when it needs to resolve a module name.
936 This is a complete path, usually to a technology file with many standard
939 You might want these defined in each file; put at the *END* of your file
943 // verilog-library-files:(\"/some/path/technology.v\" \"/some/path/tech2.v\")
946 Verilog-mode attempts to detect changes to this local variable, but they
947 are only insured to be correct when the file is first visited. Thus if you
948 have problems, use \\[find-alternate-file] RET to have these take effect.
950 See also `verilog-library-flags', `verilog-library-directories'."
951 :group 'verilog-mode-auto
952 :type '(repeat directory))
953 (put 'verilog-library-files 'safe-local-variable 'listp)
955 (defcustom verilog-library-extensions '(".v" ".sv")
956 "List of extensions to use when looking for files for /*AUTOINST*/.
957 See also `verilog-library-flags', `verilog-library-directories'."
958 :type '(repeat string)
959 :group 'verilog-mode-auto)
960 (put 'verilog-library-extensions 'safe-local-variable 'listp)
962 (defcustom verilog-active-low-regexp nil
963 "If set, treat signals matching this regexp as active low.
964 This is used for AUTORESET and AUTOTIEOFF. For proper behavior,
965 you will probably also need `verilog-auto-reset-widths' set."
966 :group 'verilog-mode-auto
967 :type '(choice (const nil) regexp))
968 (put 'verilog-active-low-regexp 'safe-local-variable 'stringp)
970 (defcustom verilog-auto-sense-include-inputs nil
971 "Non-nil means AUTOSENSE should include all inputs.
972 If nil, only inputs that are NOT output signals in the same block are
974 :group 'verilog-mode-auto
976 (put 'verilog-auto-sense-include-inputs 'safe-local-variable 'verilog-booleanp)
978 (defcustom verilog-auto-sense-defines-constant nil
979 "Non-nil means AUTOSENSE should assume all defines represent constants.
980 When true, the defines will not be included in sensitivity lists. To
981 maintain compatibility with other sites, this should be set at the bottom
982 of each Verilog file that requires it, rather than being set globally."
983 :group 'verilog-mode-auto
985 (put 'verilog-auto-sense-defines-constant 'safe-local-variable 'verilog-booleanp)
987 (defcustom verilog-auto-reset-blocking-in-non t
988 "Non-nil means AUTORESET will reset blocking statements.
989 When true, AUTORESET will reset in blocking statements those
990 signals which were assigned with blocking assignments (=) even in
991 a block with non-blocking assignments (<=).
993 If nil, all blocking assigned signals are ignored when any
994 non-blocking assignment is in the AUTORESET block. This allows
995 blocking assignments to be used for temporary values and not have
996 those temporaries reset. See example in `verilog-auto-reset'."
997 :version "24.1" ;; rev718
999 :group 'verilog-mode-auto)
1000 (put 'verilog-auto-reset-blocking-in-non 'safe-local-variable 'verilog-booleanp)
1002 (defcustom verilog-auto-reset-widths t
1003 "True means AUTORESET should determine the width of signals.
1004 This is then used to set the width of the zero (32'h0 for example). This
1005 is required by some lint tools that aren't smart enough to ignore widths of
1006 the constant zero. This may result in ugly code when parameters determine
1007 the MSB or LSB of a signal inside an AUTORESET.
1009 If nil, AUTORESET uses \"0\" as the constant.
1011 If 'unbased', AUTORESET used the unbased unsized literal \"'0\"
1012 as the constant. This setting is strongly recommended for
1013 SystemVerilog designs."
1015 :group 'verilog-mode-auto)
1016 (put 'verilog-auto-reset-widths 'safe-local-variable
1017 '(lambda (x) (memq x '(nil t unbased))))
1019 (defcustom verilog-assignment-delay ""
1020 "Text used for delays in delayed assignments. Add a trailing space if set."
1021 :group 'verilog-mode-auto
1023 (put 'verilog-assignment-delay 'safe-local-variable 'stringp)
1025 (defcustom verilog-auto-arg-sort nil
1026 "Non-nil means AUTOARG signal names will be sorted, not in declaration order.
1027 Declaration order is advantageous with order based instantiations
1028 and is the default for backward compatibility. Sorted order
1029 reduces changes when declarations are moved around in a file, and
1030 it's bad practice to rely on order based instantiations anyhow.
1032 See also `verilog-auto-inst-sort'."
1033 :group 'verilog-mode-auto
1035 (put 'verilog-auto-arg-sort 'safe-local-variable 'verilog-booleanp)
1037 (defcustom verilog-auto-inst-dot-name nil
1038 "Non-nil means when creating ports with AUTOINST, use .name syntax.
1039 This will use \".port\" instead of \".port(port)\" when possible.
1040 This is only legal in SystemVerilog files, and will confuse older
1041 simulators. Setting `verilog-auto-inst-vector' to nil may also
1042 be desirable to increase how often .name will be used."
1043 :group 'verilog-mode-auto
1045 (put 'verilog-auto-inst-dot-name 'safe-local-variable 'verilog-booleanp)
1047 (defcustom verilog-auto-inst-param-value nil
1048 "Non-nil means AUTOINST will replace parameters with the parameter value.
1049 If nil, leave parameters as symbolic names.
1051 Parameters must be in Verilog 2001 format #(...), and if a parameter is not
1052 listed as such there (as when the default value is acceptable), it will not
1053 be replaced, and will remain symbolic.
1055 For example, imagine a submodule uses parameters to declare the size of its
1056 inputs. This is then used by an upper module:
1058 module InstModule (o,i);
1060 input [WIDTH-1:0] i;
1070 Note even though PARAM=10, the AUTOINST has left the parameter as a
1071 symbolic name. If `verilog-auto-inst-param-value' is set, this will
1080 :group 'verilog-mode-auto
1082 (put 'verilog-auto-inst-param-value 'safe-local-variable 'verilog-booleanp)
1084 (defcustom verilog-auto-inst-sort nil
1085 "Non-nil means AUTOINST signals will be sorted, not in declaration order.
1086 Also affects AUTOINSTPARAM. Declaration order is the default for
1087 backward compatibility, and as some teams prefer signals that are
1088 declared together to remain together. Sorted order reduces
1089 changes when declarations are moved around in a file.
1091 See also `verilog-auto-arg-sort'."
1092 :version "24.1" ;; rev688
1093 :group 'verilog-mode-auto
1095 (put 'verilog-auto-inst-sort 'safe-local-variable 'verilog-booleanp)
1097 (defcustom verilog-auto-inst-vector t
1098 "Non-nil means when creating default ports with AUTOINST, use bus subscripts.
1099 If nil, skip the subscript when it matches the entire bus as declared in
1100 the module (AUTOWIRE signals always are subscripted, you must manually
1101 declare the wire to have the subscripts removed.) Setting this to nil may
1102 speed up some simulators, but is less general and harder to read, so avoid."
1103 :group 'verilog-mode-auto
1105 (put 'verilog-auto-inst-vector 'safe-local-variable 'verilog-booleanp)
1107 (defcustom verilog-auto-inst-template-numbers nil
1108 "If true, when creating templated ports with AUTOINST, add a comment.
1110 If t, the comment will add the line number of the template that
1111 was used for that port declaration. This setting is suggested
1112 only for debugging use, as regular use may cause a large numbers
1115 If 'lhs', the comment will show the left hand side of the
1116 AUTO_TEMPLATE rule that is matched. This is less precise than
1117 numbering (t) when multiple rules have the same pin name, but
1118 won't merge conflict."
1119 :group 'verilog-mode-auto
1120 :type '(choice (const nil) (const t) (const lhs)))
1121 (put 'verilog-auto-inst-template-numbers 'safe-local-variable
1122 '(lambda (x) (memq x '(nil t lhs))))
1124 (defcustom verilog-auto-inst-column 40
1125 "Indent-to column number for net name part of AUTOINST created pin."
1126 :group 'verilog-mode-indent
1128 (put 'verilog-auto-inst-column 'safe-local-variable 'integerp)
1130 (defcustom verilog-auto-inst-interfaced-ports nil
1131 "Non-nil means include interfaced ports in AUTOINST expansions."
1132 :group 'verilog-mode-auto
1135 (put 'verilog-auto-inst-interfaced-ports 'safe-local-variable 'verilog-booleanp)
1137 (defcustom verilog-auto-input-ignore-regexp nil
1138 "If set, when creating AUTOINPUT list, ignore signals matching this regexp.
1139 See the \\[verilog-faq] for examples on using this."
1140 :group 'verilog-mode-auto
1141 :type '(choice (const nil) regexp))
1142 (put 'verilog-auto-input-ignore-regexp 'safe-local-variable 'stringp)
1144 (defcustom verilog-auto-inout-ignore-regexp nil
1145 "If set, when creating AUTOINOUT list, ignore signals matching this regexp.
1146 See the \\[verilog-faq] for examples on using this."
1147 :group 'verilog-mode-auto
1148 :type '(choice (const nil) regexp))
1149 (put 'verilog-auto-inout-ignore-regexp 'safe-local-variable 'stringp)
1151 (defcustom verilog-auto-output-ignore-regexp nil
1152 "If set, when creating AUTOOUTPUT list, ignore signals matching this regexp.
1153 See the \\[verilog-faq] for examples on using this."
1154 :group 'verilog-mode-auto
1155 :type '(choice (const nil) regexp))
1156 (put 'verilog-auto-output-ignore-regexp 'safe-local-variable 'stringp)
1158 (defcustom verilog-auto-template-warn-unused nil
1159 "Non-nil means report warning if an AUTO_TEMPLATE line is not used.
1160 This feature is not supported before Emacs 21.1 or XEmacs 21.4."
1161 :group 'verilog-mode-auto
1164 (put 'verilog-auto-template-warn-unused 'safe-local-variable 'verilog-booleanp)
1166 (defcustom verilog-auto-tieoff-declaration "wire"
1167 "Data type used for the declaration for AUTOTIEOFF.
1168 If \"wire\" then create a wire, if \"assign\" create an
1169 assignment, else the data type for variable creation."
1170 :version "24.1" ;; rev713
1171 :group 'verilog-mode-auto
1173 (put 'verilog-auto-tieoff-declaration 'safe-local-variable 'stringp)
1175 (defcustom verilog-auto-tieoff-ignore-regexp nil
1176 "If set, when creating AUTOTIEOFF list, ignore signals matching this regexp.
1177 See the \\[verilog-faq] for examples on using this."
1178 :group 'verilog-mode-auto
1179 :type '(choice (const nil) regexp))
1180 (put 'verilog-auto-tieoff-ignore-regexp 'safe-local-variable 'stringp)
1182 (defcustom verilog-auto-unused-ignore-regexp nil
1183 "If set, when creating AUTOUNUSED list, ignore signals matching this regexp.
1184 See the \\[verilog-faq] for examples on using this."
1185 :group 'verilog-mode-auto
1186 :type '(choice (const nil) regexp))
1187 (put 'verilog-auto-unused-ignore-regexp 'safe-local-variable 'stringp)
1189 (defcustom verilog-typedef-regexp nil
1190 "If non-nil, regular expression that matches Verilog-2001 typedef names.
1191 For example, \"_t$\" matches typedefs named with _t, as in the C language."
1192 :group 'verilog-mode-auto
1193 :type '(choice (const nil) regexp))
1194 (put 'verilog-typedef-regexp 'safe-local-variable 'stringp)
1196 (defcustom verilog-mode-hook 'verilog-set-compile-command
1197 "Hook run after Verilog mode is loaded."
1199 :group 'verilog-mode)
1201 (defcustom verilog-auto-hook nil
1202 "Hook run after `verilog-mode' updates AUTOs."
1203 :group 'verilog-mode-auto
1206 (defcustom verilog-before-auto-hook nil
1207 "Hook run before `verilog-mode' updates AUTOs."
1208 :group 'verilog-mode-auto
1211 (defcustom verilog-delete-auto-hook nil
1212 "Hook run after `verilog-mode' deletes AUTOs."
1213 :group 'verilog-mode-auto
1216 (defcustom verilog-before-delete-auto-hook nil
1217 "Hook run before `verilog-mode' deletes AUTOs."
1218 :group 'verilog-mode-auto
1221 (defcustom verilog-getopt-flags-hook nil
1222 "Hook run after `verilog-getopt-flags' determines the Verilog option lists."
1223 :group 'verilog-mode-auto
1226 (defcustom verilog-before-getopt-flags-hook nil
1227 "Hook run before `verilog-getopt-flags' determines the Verilog option lists."
1228 :group 'verilog-mode-auto
1231 (defcustom verilog-before-save-font-hook nil
1232 "Hook run before `verilog-save-font-mods' removes highlighting."
1233 :group 'verilog-mode-auto
1237 (defcustom verilog-after-save-font-hook nil
1238 "Hook run after `verilog-save-font-mods' restores highlighting."
1239 :group 'verilog-mode-auto
1243 (defvar verilog-imenu-generic-expression
1244 '((nil "^\\s-*\\(\\(m\\(odule\\|acromodule\\)\\)\\|primitive\\)\\s-+\\([a-zA-Z0-9_.:]+\\)" 4)
1245 ("*Vars*" "^\\s-*\\(reg\\|wire\\)\\s-+\\(\\|\\[[^]]+\\]\\s-+\\)\\([A-Za-z0-9_]+\\)" 3))
1246 "Imenu expression for Verilog mode. See `imenu-generic-expression'.")
1249 ;; provide a verilog-header function.
1250 ;; Customization variables:
1252 (defvar verilog-date-scientific-format nil
1253 "If non-nil, dates are written in scientific format (e.g. 1997/09/17).
1254 If nil, in European format (e.g. 17.09.1997). The brain-dead American
1255 format (e.g. 09/17/1997) is not supported.")
1257 (defvar verilog-company nil
1258 "Default name of Company for Verilog header.
1259 If set will become buffer local.")
1260 (make-variable-buffer-local 'verilog-company)
1262 (defvar verilog-project nil
1263 "Default name of Project for Verilog header.
1264 If set will become buffer local.")
1265 (make-variable-buffer-local 'verilog-project)
1267 (defvar verilog-mode-map
1268 (let ((map (make-sparse-keymap)))
1269 (define-key map ";" 'electric-verilog-semi)
1270 (define-key map [(control 59)] 'electric-verilog-semi-with-comment)
1271 (define-key map ":" 'electric-verilog-colon)
1272 ;;(define-key map "=" 'electric-verilog-equal)
1273 (define-key map "\`" 'electric-verilog-tick)
1274 (define-key map "\t" 'electric-verilog-tab)
1275 (define-key map "\r" 'electric-verilog-terminate-line)
1276 ;; backspace/delete key bindings
1277 (define-key map [backspace] 'backward-delete-char-untabify)
1278 (unless (boundp 'delete-key-deletes-forward) ; XEmacs variable
1279 (define-key map [delete] 'delete-char)
1280 (define-key map [(meta delete)] 'kill-word))
1281 (define-key map "\M-\C-b" 'electric-verilog-backward-sexp)
1282 (define-key map "\M-\C-f" 'electric-verilog-forward-sexp)
1283 (define-key map "\M-\r" `electric-verilog-terminate-and-indent)
1284 (define-key map "\M-\t" 'verilog-complete-word)
1285 (define-key map "\M-?" 'verilog-show-completions)
1286 ;; Note \C-c and letter are reserved for users
1287 (define-key map "\C-c\`" 'verilog-lint-off)
1288 (define-key map "\C-c\*" 'verilog-delete-auto-star-implicit)
1289 (define-key map "\C-c\?" 'verilog-diff-auto)
1290 (define-key map "\C-c\C-r" 'verilog-label-be)
1291 (define-key map "\C-c\C-i" 'verilog-pretty-declarations)
1292 (define-key map "\C-c=" 'verilog-pretty-expr)
1293 (define-key map "\C-c\C-b" 'verilog-submit-bug-report)
1294 (define-key map "\M-*" 'verilog-star-comment)
1295 (define-key map "\C-c\C-c" 'verilog-comment-region)
1296 (define-key map "\C-c\C-u" 'verilog-uncomment-region)
1297 (when (featurep 'xemacs)
1298 (define-key map [(meta control h)] 'verilog-mark-defun)
1299 (define-key map "\M-\C-a" 'verilog-beg-of-defun)
1300 (define-key map "\M-\C-e" 'verilog-end-of-defun))
1301 (define-key map "\C-c\C-d" 'verilog-goto-defun)
1302 (define-key map "\C-c\C-k" 'verilog-delete-auto)
1303 (define-key map "\C-c\C-a" 'verilog-auto)
1304 (define-key map "\C-c\C-s" 'verilog-auto-save-compile)
1305 (define-key map "\C-c\C-p" 'verilog-preprocess)
1306 (define-key map "\C-c\C-z" 'verilog-inject-auto)
1307 (define-key map "\C-c\C-e" 'verilog-expand-vector)
1308 (define-key map "\C-c\C-h" 'verilog-header)
1310 "Keymap used in Verilog mode.")
1314 verilog-menu verilog-mode-map "Menu for Verilog mode"
1315 (verilog-easy-menu-filter
1317 ("Choose Compilation Action"
1320 (setq verilog-tool nil)
1321 (verilog-set-compile-command))
1323 :selected (equal verilog-tool nil)
1324 :help "When invoking compilation, use compile-command"]
1327 (setq verilog-tool 'verilog-linter)
1328 (verilog-set-compile-command))
1330 :selected (equal verilog-tool `verilog-linter)
1331 :help "When invoking compilation, use lint checker"]
1334 (setq verilog-tool 'verilog-coverage)
1335 (verilog-set-compile-command))
1337 :selected (equal verilog-tool `verilog-coverage)
1338 :help "When invoking compilation, annotate for coverage"]
1341 (setq verilog-tool 'verilog-simulator)
1342 (verilog-set-compile-command))
1344 :selected (equal verilog-tool `verilog-simulator)
1345 :help "When invoking compilation, interpret Verilog source"]
1348 (setq verilog-tool 'verilog-compiler)
1349 (verilog-set-compile-command))
1351 :selected (equal verilog-tool `verilog-compiler)
1352 :help "When invoking compilation, compile Verilog source"]
1355 (setq verilog-tool 'verilog-preprocessor)
1356 (verilog-set-compile-command))
1358 :selected (equal verilog-tool `verilog-preprocessor)
1359 :help "When invoking compilation, preprocess Verilog source, see also `verilog-preprocess'"]
1362 ["Beginning of function" verilog-beg-of-defun
1364 :help "Move backward to the beginning of the current function or procedure"]
1365 ["End of function" verilog-end-of-defun
1367 :help "Move forward to the end of the current function or procedure"]
1368 ["Mark function" verilog-mark-defun
1370 :help "Mark the current Verilog function or procedure"]
1371 ["Goto function/module" verilog-goto-defun
1372 :help "Move to specified Verilog module/task/function"]
1373 ["Move to beginning of block" electric-verilog-backward-sexp
1374 :help "Move backward over one balanced expression"]
1375 ["Move to end of block" electric-verilog-forward-sexp
1376 :help "Move forward over one balanced expression"]
1379 ["Comment Region" verilog-comment-region
1380 :help "Put marked area into a comment"]
1381 ["UnComment Region" verilog-uncomment-region
1382 :help "Uncomment an area commented with Comment Region"]
1383 ["Multi-line comment insert" verilog-star-comment
1384 :help "Insert Verilog /* */ comment at point"]
1385 ["Lint error to comment" verilog-lint-off
1386 :help "Convert a Verilog linter warning line into a disable statement"]
1390 :help "Perform compilation-action (above) on the current buffer"]
1391 ["AUTO, Save, Compile" verilog-auto-save-compile
1392 :help "Recompute AUTOs, save buffer, and compile"]
1393 ["Next Compile Error" next-error
1394 :help "Visit next compilation error message and corresponding source code"]
1395 ["Ignore Lint Warning at point" verilog-lint-off
1396 :help "Convert a Verilog linter warning line into a disable statement"]
1398 ["Line up declarations around point" verilog-pretty-declarations
1399 :help "Line up declarations around point"]
1400 ["Line up equations around point" verilog-pretty-expr
1401 :help "Line up expressions around point"]
1402 ["Redo/insert comments on every end" verilog-label-be
1403 :help "Label matching begin ... end statements"]
1404 ["Expand [x:y] vector line" verilog-expand-vector
1405 :help "Take a signal vector on the current line and expand it to multiple lines"]
1406 ["Insert begin-end block" verilog-insert-block
1407 :help "Insert begin ... end"]
1408 ["Complete word" verilog-complete-word
1409 :help "Complete word at point"]
1411 ["Recompute AUTOs" verilog-auto
1412 :help "Expand AUTO meta-comment statements"]
1413 ["Kill AUTOs" verilog-delete-auto
1414 :help "Remove AUTO expansions"]
1415 ["Diff AUTOs" verilog-diff-auto
1416 :help "Show differences in AUTO expansions"]
1417 ["Inject AUTOs" verilog-inject-auto
1418 :help "Inject AUTOs into legacy non-AUTO buffer"]
1420 ["AUTO General" (describe-function 'verilog-auto)
1421 :help "Help introduction on AUTOs"]
1422 ["AUTO Library Flags" (describe-variable 'verilog-library-flags)
1423 :help "Help on verilog-library-flags"]
1424 ["AUTO Library Path" (describe-variable 'verilog-library-directories)
1425 :help "Help on verilog-library-directories"]
1426 ["AUTO Library Files" (describe-variable 'verilog-library-files)
1427 :help "Help on verilog-library-files"]
1428 ["AUTO Library Extensions" (describe-variable 'verilog-library-extensions)
1429 :help "Help on verilog-library-extensions"]
1430 ["AUTO `define Reading" (describe-function 'verilog-read-defines)
1431 :help "Help on reading `defines"]
1432 ["AUTO `include Reading" (describe-function 'verilog-read-includes)
1433 :help "Help on parsing `includes"]
1434 ["AUTOARG" (describe-function 'verilog-auto-arg)
1435 :help "Help on AUTOARG - declaring module port list"]
1436 ["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum)
1437 :help "Help on AUTOASCIIENUM - creating ASCII for enumerations"]
1438 ["AUTOASSIGNMODPORT" (describe-function 'verilog-auto-assign-modport)
1439 :help "Help on AUTOASSIGNMODPORT - creating assignments to/from modports"]
1440 ["AUTOINOUTCOMP" (describe-function 'verilog-auto-inout-comp)
1441 :help "Help on AUTOINOUTCOMP - copying complemented i/o from another file"]
1442 ["AUTOINOUTIN" (describe-function 'verilog-auto-inout-in)
1443 :help "Help on AUTOINOUTIN - copying i/o from another file as all inputs"]
1444 ["AUTOINOUTMODPORT" (describe-function 'verilog-auto-inout-modport)
1445 :help "Help on AUTOINOUTMODPORT - copying i/o from an interface modport"]
1446 ["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module)
1447 :help "Help on AUTOINOUTMODULE - copying i/o from another file"]
1448 ["AUTOINOUTPARAM" (describe-function 'verilog-auto-inout-param)
1449 :help "Help on AUTOINOUTPARAM - copying parameters from another file"]
1450 ["AUTOINSERTLISP" (describe-function 'verilog-auto-insert-lisp)
1451 :help "Help on AUTOINSERTLISP - insert text from a lisp function"]
1452 ["AUTOINOUT" (describe-function 'verilog-auto-inout)
1453 :help "Help on AUTOINOUT - adding inouts from cells"]
1454 ["AUTOINPUT" (describe-function 'verilog-auto-input)
1455 :help "Help on AUTOINPUT - adding inputs from cells"]
1456 ["AUTOINST" (describe-function 'verilog-auto-inst)
1457 :help "Help on AUTOINST - adding pins for cells"]
1458 ["AUTOINST (.*)" (describe-function 'verilog-auto-star)
1459 :help "Help on expanding Verilog-2001 .* pins"]
1460 ["AUTOINSTPARAM" (describe-function 'verilog-auto-inst-param)
1461 :help "Help on AUTOINSTPARAM - adding parameter pins to cells"]
1462 ["AUTOLOGIC" (describe-function 'verilog-auto-logic)
1463 :help "Help on AUTOLOGIC - declaring logic signals"]
1464 ["AUTOOUTPUT" (describe-function 'verilog-auto-output)
1465 :help "Help on AUTOOUTPUT - adding outputs from cells"]
1466 ["AUTOOUTPUTEVERY" (describe-function 'verilog-auto-output-every)
1467 :help "Help on AUTOOUTPUTEVERY - adding outputs of all signals"]
1468 ["AUTOREG" (describe-function 'verilog-auto-reg)
1469 :help "Help on AUTOREG - declaring registers for non-wires"]
1470 ["AUTOREGINPUT" (describe-function 'verilog-auto-reg-input)
1471 :help "Help on AUTOREGINPUT - declaring inputs for non-wires"]
1472 ["AUTORESET" (describe-function 'verilog-auto-reset)
1473 :help "Help on AUTORESET - resetting always blocks"]
1474 ["AUTOSENSE" (describe-function 'verilog-auto-sense)
1475 :help "Help on AUTOSENSE - sensitivity lists for always blocks"]
1476 ["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff)
1477 :help "Help on AUTOTIEOFF - tying off unused outputs"]
1478 ["AUTOUNDEF" (describe-function 'verilog-auto-undef)
1479 :help "Help on AUTOUNDEF - undefine all local defines"]
1480 ["AUTOUNUSED" (describe-function 'verilog-auto-unused)
1481 :help "Help on AUTOUNUSED - terminating unused inputs"]
1482 ["AUTOWIRE" (describe-function 'verilog-auto-wire)
1483 :help "Help on AUTOWIRE - declaring wires for cells"]
1486 ["Submit bug report" verilog-submit-bug-report
1487 :help "Submit via mail a bug report on verilog-mode.el"]
1488 ["Version and FAQ" verilog-faq
1489 :help "Show the current version, and where to get the FAQ etc"]
1490 ["Customize Verilog Mode..." verilog-customize
1491 :help "Customize variables and other settings used by Verilog-Mode"]
1492 ["Customize Verilog Fonts & Colors" verilog-font-customize
1493 :help "Customize fonts used by Verilog-Mode."])))
1496 verilog-stmt-menu verilog-mode-map "Menu for statement templates in Verilog."
1497 (verilog-easy-menu-filter
1499 ["Header" verilog-sk-header
1500 :help "Insert a header block at the top of file"]
1501 ["Comment" verilog-sk-comment
1502 :help "Insert a comment block"]
1504 ["Module" verilog-sk-module
1505 :help "Insert a module .. (/*AUTOARG*/);.. endmodule block"]
1506 ["OVM Class" verilog-sk-ovm-class
1507 :help "Insert an OVM class block"]
1508 ["UVM Class" verilog-sk-uvm-class
1509 :help "Insert an UVM class block"]
1510 ["Primitive" verilog-sk-primitive
1511 :help "Insert a primitive .. (.. );.. endprimitive block"]
1513 ["Input" verilog-sk-input
1514 :help "Insert an input declaration"]
1515 ["Output" verilog-sk-output
1516 :help "Insert an output declaration"]
1517 ["Inout" verilog-sk-inout
1518 :help "Insert an inout declaration"]
1519 ["Wire" verilog-sk-wire
1520 :help "Insert a wire declaration"]
1521 ["Reg" verilog-sk-reg
1522 :help "Insert a register declaration"]
1523 ["Define thing under point as a register" verilog-sk-define-signal
1524 :help "Define signal under point as a register at the top of the module"]
1526 ["Initial" verilog-sk-initial
1527 :help "Insert an initial begin .. end block"]
1528 ["Always" verilog-sk-always
1529 :help "Insert an always @(AS) begin .. end block"]
1530 ["Function" verilog-sk-function
1531 :help "Insert a function .. begin .. end endfunction block"]
1532 ["Task" verilog-sk-task
1533 :help "Insert a task .. begin .. end endtask block"]
1534 ["Specify" verilog-sk-specify
1535 :help "Insert a specify .. endspecify block"]
1536 ["Generate" verilog-sk-generate
1537 :help "Insert a generate .. endgenerate block"]
1539 ["Begin" verilog-sk-begin
1540 :help "Insert a begin .. end block"]
1542 :help "Insert an if (..) begin .. end block"]
1543 ["(if) else" verilog-sk-else-if
1544 :help "Insert an else if (..) begin .. end block"]
1545 ["For" verilog-sk-for
1546 :help "Insert a for (...) begin .. end block"]
1547 ["While" verilog-sk-while
1548 :help "Insert a while (...) begin .. end block"]
1549 ["Fork" verilog-sk-fork
1550 :help "Insert a fork begin .. end .. join block"]
1551 ["Repeat" verilog-sk-repeat
1552 :help "Insert a repeat (..) begin .. end block"]
1553 ["Case" verilog-sk-case
1554 :help "Insert a case block, prompting for details"]
1555 ["Casex" verilog-sk-casex
1556 :help "Insert a casex (...) item: begin.. end endcase block"]
1557 ["Casez" verilog-sk-casez
1558 :help "Insert a casez (...) item: begin.. end endcase block"])))
1560 (defvar verilog-mode-abbrev-table nil
1561 "Abbrev table in use in Verilog-mode buffers.")
1563 (define-abbrev-table 'verilog-mode-abbrev-table ())
1564 (verilog-define-abbrev verilog-mode-abbrev-table "class" "" 'verilog-sk-ovm-class)
1565 (verilog-define-abbrev verilog-mode-abbrev-table "always" "" 'verilog-sk-always)
1566 (verilog-define-abbrev verilog-mode-abbrev-table "begin" nil `verilog-sk-begin)
1567 (verilog-define-abbrev verilog-mode-abbrev-table "case" "" `verilog-sk-case)
1568 (verilog-define-abbrev verilog-mode-abbrev-table "for" "" `verilog-sk-for)
1569 (verilog-define-abbrev verilog-mode-abbrev-table "generate" "" `verilog-sk-generate)
1570 (verilog-define-abbrev verilog-mode-abbrev-table "initial" "" `verilog-sk-initial)
1571 (verilog-define-abbrev verilog-mode-abbrev-table "fork" "" `verilog-sk-fork)
1572 (verilog-define-abbrev verilog-mode-abbrev-table "module" "" `verilog-sk-module)
1573 (verilog-define-abbrev verilog-mode-abbrev-table "primitive" "" `verilog-sk-primitive)
1574 (verilog-define-abbrev verilog-mode-abbrev-table "repeat" "" `verilog-sk-repeat)
1575 (verilog-define-abbrev verilog-mode-abbrev-table "specify" "" `verilog-sk-specify)
1576 (verilog-define-abbrev verilog-mode-abbrev-table "task" "" `verilog-sk-task)
1577 (verilog-define-abbrev verilog-mode-abbrev-table "while" "" `verilog-sk-while)
1578 (verilog-define-abbrev verilog-mode-abbrev-table "casex" "" `verilog-sk-casex)
1579 (verilog-define-abbrev verilog-mode-abbrev-table "casez" "" `verilog-sk-casez)
1580 (verilog-define-abbrev verilog-mode-abbrev-table "if" "" `verilog-sk-if)
1581 (verilog-define-abbrev verilog-mode-abbrev-table "else if" "" `verilog-sk-else-if)
1582 (verilog-define-abbrev verilog-mode-abbrev-table "assign" "" `verilog-sk-assign)
1583 (verilog-define-abbrev verilog-mode-abbrev-table "function" "" `verilog-sk-function)
1584 (verilog-define-abbrev verilog-mode-abbrev-table "input" "" `verilog-sk-input)
1585 (verilog-define-abbrev verilog-mode-abbrev-table "output" "" `verilog-sk-output)
1586 (verilog-define-abbrev verilog-mode-abbrev-table "inout" "" `verilog-sk-inout)
1587 (verilog-define-abbrev verilog-mode-abbrev-table "wire" "" `verilog-sk-wire)
1588 (verilog-define-abbrev verilog-mode-abbrev-table "reg" "" `verilog-sk-reg)
1594 (defsubst verilog-within-string ()
1595 (nth 3 (parse-partial-sexp (point-at-bol) (point))))
1597 (defsubst verilog-string-replace-matches (from-string to-string fixedcase literal string)
1598 "Replace occurrences of FROM-STRING with TO-STRING.
1599 FIXEDCASE and LITERAL as in `replace-match`. STRING is what to replace.
1600 The case (verilog-string-replace-matches \"o\" \"oo\" nil nil \"foobar\")
1601 will break, as the o's continuously replace. xa -> x works ok though."
1602 ;; Hopefully soon to an Emacs built-in
1603 ;; Also note \ in the replacement prevent multiple replacements; IE
1604 ;; (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil "wire@_@")
1605 ;; Gives "wire\([0-9]+\)_@" not "wire\([0-9]+\)_\([0-9]+\)"
1607 (while (string-match from-string string start)
1608 (setq string (replace-match to-string fixedcase literal string)
1609 start (min (length string) (+ (match-beginning 0) (length to-string)))))
1612 (defsubst verilog-string-remove-spaces (string)
1613 "Remove spaces surrounding STRING."
1615 (setq string (verilog-string-replace-matches "^\\s-+" "" nil nil string))
1616 (setq string (verilog-string-replace-matches "\\s-+$" "" nil nil string))
1619 (defsubst verilog-re-search-forward (REGEXP BOUND NOERROR)
1620 ; checkdoc-params: (REGEXP BOUND NOERROR)
1621 "Like `re-search-forward', but skips over match in comments or strings."
1622 (let ((mdata '(nil nil))) ;; So match-end will return nil if no matches found
1624 (re-search-forward REGEXP BOUND NOERROR)
1625 (setq mdata (match-data))
1626 (and (verilog-skip-forward-comment-or-string)
1628 (setq mdata '(nil nil))
1632 (store-match-data mdata)
1635 (defsubst verilog-re-search-backward (REGEXP BOUND NOERROR)
1636 ; checkdoc-params: (REGEXP BOUND NOERROR)
1637 "Like `re-search-backward', but skips over match in comments or strings."
1638 (let ((mdata '(nil nil))) ;; So match-end will return nil if no matches found
1640 (re-search-backward REGEXP BOUND NOERROR)
1641 (setq mdata (match-data))
1642 (and (verilog-skip-backward-comment-or-string)
1644 (setq mdata '(nil nil))
1648 (store-match-data mdata)
1651 (defsubst verilog-re-search-forward-quick (regexp bound noerror)
1652 "Like `verilog-re-search-forward', including use of REGEXP BOUND and NOERROR,
1653 but trashes match data and is faster for REGEXP that doesn't match often.
1654 This uses `verilog-scan' and text properties to ignore comments,
1655 so there may be a large up front penalty for the first search."
1657 (while (and (not pt)
1658 (re-search-forward regexp bound noerror))
1659 (if (verilog-inside-comment-or-string-p)
1660 (re-search-forward "[/\"\n]" nil t) ;; Only way a comment or quote can end
1661 (setq pt (match-end 0))))
1664 (defsubst verilog-re-search-backward-quick (regexp bound noerror)
1665 ; checkdoc-params: (REGEXP BOUND NOERROR)
1666 "Like `verilog-re-search-backward', including use of REGEXP BOUND and NOERROR,
1667 but trashes match data and is faster for REGEXP that doesn't match often.
1668 This uses `verilog-scan' and text properties to ignore comments,
1669 so there may be a large up front penalty for the first search."
1671 (while (and (not pt)
1672 (re-search-backward regexp bound noerror))
1673 (if (verilog-inside-comment-or-string-p)
1674 (re-search-backward "[/\"]" nil t) ;; Only way a comment or quote can begin
1675 (setq pt (match-beginning 0))))
1678 (defsubst verilog-re-search-forward-substr (substr regexp bound noerror)
1679 "Like `re-search-forward', but first search for SUBSTR constant.
1680 Then searched for the normal REGEXP (which contains SUBSTR), with given
1681 BOUND and NOERROR. The REGEXP must fit within a single line.
1682 This speeds up complicated regexp matches."
1683 ;; Problem with overlap: search-forward BAR then FOOBARBAZ won't match.
1684 ;; thus require matches to be on one line, and use beginning-of-line.
1686 (while (and (not done)
1687 (search-forward substr bound noerror))
1690 (setq done (re-search-forward regexp (point-at-eol) noerror)))
1691 (unless (and (<= (match-beginning 0) (point))
1692 (>= (match-end 0) (point)))
1694 (when done (goto-char done))
1696 ;;(verilog-re-search-forward-substr "-end" "get-end-of" nil t) ;;-end (test bait)
1698 (defsubst verilog-re-search-backward-substr (substr regexp bound noerror)
1699 "Like `re-search-backward', but first search for SUBSTR constant.
1700 Then searched for the normal REGEXP (which contains SUBSTR), with given
1701 BOUND and NOERROR. The REGEXP must fit within a single line.
1702 This speeds up complicated regexp matches."
1703 ;; Problem with overlap: search-backward BAR then FOOBARBAZ won't match.
1704 ;; thus require matches to be on one line, and use beginning-of-line.
1706 (while (and (not done)
1707 (search-backward substr bound noerror))
1710 (setq done (re-search-backward regexp (point-at-bol) noerror)))
1711 (unless (and (<= (match-beginning 0) (point))
1712 (>= (match-end 0) (point)))
1714 (when done (goto-char done))
1716 ;;(verilog-re-search-backward-substr "-end" "get-end-of" nil t) ;;-end (test bait)
1718 (defun verilog-delete-trailing-whitespace ()
1719 "Delete trailing spaces or tabs, but not newlines nor linefeeds.
1720 Also add missing final newline.
1722 To call this from the command line, see \\[verilog-batch-diff-auto].
1724 To call on \\[verilog-auto], set `verilog-auto-delete-trailing-whitespace'."
1725 ;; Similar to `delete-trailing-whitespace' but that's not present in XEmacs
1727 (goto-char (point-min))
1728 (while (re-search-forward "[ \t]+$" nil t) ;; Not syntactic WS as no formfeed
1729 (replace-match "" nil nil))
1730 (goto-char (point-max))
1731 (unless (bolp) (insert "\n"))))
1733 (defvar compile-command)
1735 ;; compilation program
1736 (defun verilog-set-compile-command ()
1737 "Function to compute shell command to compile Verilog.
1739 This reads `verilog-tool' and sets `compile-command'. This specifies the
1740 program that executes when you type \\[compile] or
1741 \\[verilog-auto-save-compile].
1743 By default `verilog-tool' uses a Makefile if one exists in the
1744 current directory. If not, it is set to the `verilog-linter',
1745 `verilog-compiler', `verilog-coverage', `verilog-preprocessor',
1746 or `verilog-simulator' variables, as selected with the Verilog ->
1747 \"Choose Compilation Action\" menu.
1749 You should set `verilog-tool' or the other variables to the path and
1750 arguments for your Verilog simulator. For example:
1753 \"(cd /tmp; surecov %s)\".
1755 In the former case, the path to the current buffer is concat'ed to the
1756 value of `verilog-tool'; in the later, the path to the current buffer is
1757 substituted for the %s.
1759 Where __FLAGS__ appears in the string `verilog-current-flags'
1760 will be substituted.
1762 Where __FILE__ appears in the string, the variable
1763 `buffer-file-name' of the current buffer, without the directory
1764 portion, will be substituted."
1767 ((or (file-exists-p "makefile") ;If there is a makefile, use it
1768 (file-exists-p "Makefile"))
1769 (set (make-local-variable 'compile-command) "make "))
1771 (set (make-local-variable 'compile-command)
1773 (if (string-match "%s" (eval verilog-tool))
1774 (format (eval verilog-tool) (or buffer-file-name ""))
1775 (concat (eval verilog-tool) " " (or buffer-file-name "")))
1777 (verilog-modify-compile-command))
1779 (defun verilog-expand-command (command)
1780 "Replace meta-information in COMMAND and return it.
1781 Where __FLAGS__ appears in the string `verilog-current-flags'
1782 will be substituted. Where __FILE__ appears in the string, the
1783 current buffer's file-name, without the directory portion, will
1785 (setq command (verilog-string-replace-matches
1786 ;; Note \\b only works if under verilog syntax table
1787 "\\b__FLAGS__\\b" (verilog-current-flags)
1789 (setq command (verilog-string-replace-matches
1790 "\\b__FILE__\\b" (file-name-nondirectory
1791 (or (buffer-file-name) ""))
1795 (defun verilog-modify-compile-command ()
1796 "Update `compile-command' using `verilog-expand-command'."
1798 (stringp compile-command)
1799 (string-match "\\b\\(__FLAGS__\\|__FILE__\\)\\b" compile-command))
1800 (set (make-local-variable 'compile-command)
1801 (verilog-expand-command compile-command))))
1803 (if (featurep 'xemacs)
1804 ;; Following code only gets called from compilation-mode-hook on XEmacs to add error handling.
1805 (defun verilog-error-regexp-add-xemacs ()
1806 "Teach XEmacs about verilog errors.
1807 Called by `compilation-mode-hook'. This allows \\[next-error] to
1810 (if (boundp 'compilation-error-regexp-systems-alist)
1812 (not (equal compilation-error-regexp-systems-list 'all))
1813 (not (member compilation-error-regexp-systems-list 'verilog)))
1814 (push 'verilog compilation-error-regexp-systems-list)))
1815 (if (boundp 'compilation-error-regexp-alist-alist)
1816 (if (not (assoc 'verilog compilation-error-regexp-alist-alist))
1817 (setcdr compilation-error-regexp-alist-alist
1818 (cons verilog-error-regexp-xemacs-alist
1819 (cdr compilation-error-regexp-alist-alist)))))
1820 (if (boundp 'compilation-font-lock-keywords)
1822 (set (make-local-variable 'compilation-font-lock-keywords)
1823 verilog-error-font-lock-keywords)
1824 (font-lock-set-defaults)))
1825 ;; Need to re-run compilation-error-regexp builder
1826 (if (fboundp 'compilation-build-compilation-error-regexp-alist)
1827 (compilation-build-compilation-error-regexp-alist))
1830 ;; Following code only gets called from compilation-mode-hook on Emacs to add error handling.
1831 (defun verilog-error-regexp-add-emacs ()
1832 "Tell Emacs compile that we are Verilog.
1833 Called by `compilation-mode-hook'. This allows \\[next-error] to
1836 (if (boundp 'compilation-error-regexp-alist-alist)
1838 (if (not (assoc 'verilog-xl-1 compilation-error-regexp-alist-alist))
1841 (push (car item) compilation-error-regexp-alist)
1842 (push item compilation-error-regexp-alist-alist)
1844 verilog-error-regexp-emacs-alist)))))
1846 (if (featurep 'xemacs) (add-hook 'compilation-mode-hook 'verilog-error-regexp-add-xemacs))
1847 (if (featurep 'emacs) (add-hook 'compilation-mode-hook 'verilog-error-regexp-add-emacs))
1849 (defconst verilog-directive-re
1851 (verilog-regexp-words
1853 "`case" "`default" "`define" "`else" "`elsif" "`endfor" "`endif"
1854 "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
1855 "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
1856 "`time_scale" "`undef" "`while" ))))
1858 (defconst verilog-directive-re-1
1859 (concat "[ \t]*" verilog-directive-re))
1861 (defconst verilog-directive-begin
1862 "\\<`\\(for\\|i\\(f\\|fdef\\|fndef\\)\\|switch\\|while\\)\\>")
1864 (defconst verilog-directive-middle
1865 "\\<`\\(else\\|elsif\\|default\\|case\\)\\>")
1867 (defconst verilog-directive-end
1868 "`\\(endfor\\|endif\\|endswitch\\|endwhile\\)\\>")
1870 (defconst verilog-ovm-begin-re
1874 "`ovm_component_utils_begin"
1875 "`ovm_component_param_utils_begin"
1876 "`ovm_field_utils_begin"
1877 "`ovm_object_utils_begin"
1878 "`ovm_object_param_utils_begin"
1879 "`ovm_sequence_utils_begin"
1880 "`ovm_sequencer_utils_begin"
1883 (defconst verilog-ovm-end-re
1887 "`ovm_component_utils_end"
1888 "`ovm_field_utils_end"
1889 "`ovm_object_utils_end"
1890 "`ovm_sequence_utils_end"
1891 "`ovm_sequencer_utils_end"
1894 (defconst verilog-uvm-begin-re
1898 "`uvm_component_utils_begin"
1899 "`uvm_component_param_utils_begin"
1900 "`uvm_field_utils_begin"
1901 "`uvm_object_utils_begin"
1902 "`uvm_object_param_utils_begin"
1903 "`uvm_sequence_utils_begin"
1904 "`uvm_sequencer_utils_begin"
1907 (defconst verilog-uvm-end-re
1911 "`uvm_component_utils_end"
1912 "`uvm_field_utils_end"
1913 "`uvm_object_utils_end"
1914 "`uvm_sequence_utils_end"
1915 "`uvm_sequencer_utils_end"
1918 (defconst verilog-vmm-begin-re
1922 "`vmm_data_member_begin"
1923 "`vmm_env_member_begin"
1924 "`vmm_scenario_member_begin"
1925 "`vmm_subenv_member_begin"
1926 "`vmm_xactor_member_begin"
1929 (defconst verilog-vmm-end-re
1933 "`vmm_data_member_end"
1934 "`vmm_env_member_end"
1935 "`vmm_scenario_member_end"
1936 "`vmm_subenv_member_end"
1937 "`vmm_xactor_member_end"
1940 (defconst verilog-vmm-statement-re
1944 ;; "`vmm_xactor_member_enum_array"
1945 "`vmm_\\(data\\|env\\|scenario\\|subenv\\|xactor\\)_member_\\(scalar\\|string\\|enum\\|vmm_data\\|channel\\|xactor\\|subenv\\|user_defined\\)\\(_array\\)?"
1946 ;; "`vmm_xactor_member_scalar_array"
1947 ;; "`vmm_xactor_member_scalar"
1950 (defconst verilog-ovm-statement-re
1959 "`ovm_analysis_imp_decl"
1960 "`ovm_blocking_get_imp_decl"
1961 "`ovm_blocking_get_peek_imp_decl"
1962 "`ovm_blocking_master_imp_decl"
1963 "`ovm_blocking_peek_imp_decl"
1964 "`ovm_blocking_put_imp_decl"
1965 "`ovm_blocking_slave_imp_decl"
1966 "`ovm_blocking_transport_imp_decl"
1967 "`ovm_component_registry"
1968 "`ovm_component_registry_param"
1969 "`ovm_component_utils"
1972 "`ovm_declare_sequence_lib"
1979 "`ovm_field_aa_int_byte"
1980 "`ovm_field_aa_int_byte_unsigned"
1981 "`ovm_field_aa_int_int"
1982 "`ovm_field_aa_int_int_unsigned"
1983 "`ovm_field_aa_int_integer"
1984 "`ovm_field_aa_int_integer_unsigned"
1985 "`ovm_field_aa_int_key"
1986 "`ovm_field_aa_int_longint"
1987 "`ovm_field_aa_int_longint_unsigned"
1988 "`ovm_field_aa_int_shortint"
1989 "`ovm_field_aa_int_shortint_unsigned"
1990 "`ovm_field_aa_int_string"
1991 "`ovm_field_aa_object_int"
1992 "`ovm_field_aa_object_string"
1993 "`ovm_field_aa_string_int"
1994 "`ovm_field_aa_string_string"
1995 "`ovm_field_array_int"
1996 "`ovm_field_array_object"
1997 "`ovm_field_array_string"
2002 "`ovm_field_queue_int"
2003 "`ovm_field_queue_object"
2004 "`ovm_field_queue_string"
2005 "`ovm_field_sarray_int"
2010 "`ovm_get_peek_imp_decl"
2017 "`ovm_master_imp_decl"
2019 "`ovm_non_blocking_transport_imp_decl"
2020 "`ovm_nonblocking_get_imp_decl"
2021 "`ovm_nonblocking_get_peek_imp_decl"
2022 "`ovm_nonblocking_master_imp_decl"
2023 "`ovm_nonblocking_peek_imp_decl"
2024 "`ovm_nonblocking_put_imp_decl"
2025 "`ovm_nonblocking_slave_imp_decl"
2026 "`ovm_object_registry"
2027 "`ovm_object_registry_param"
2029 "`ovm_peek_imp_decl"
2030 "`ovm_phase_func_decl"
2031 "`ovm_phase_task_decl"
2032 "`ovm_print_aa_int_object"
2033 "`ovm_print_aa_string_int"
2034 "`ovm_print_aa_string_object"
2035 "`ovm_print_aa_string_string"
2036 "`ovm_print_array_int"
2037 "`ovm_print_array_object"
2038 "`ovm_print_array_string"
2039 "`ovm_print_object_queue"
2040 "`ovm_print_queue_int"
2041 "`ovm_print_string_queue"
2044 "`ovm_rand_send_with"
2046 "`ovm_sequence_utils"
2047 "`ovm_slave_imp_decl"
2048 "`ovm_transport_imp_decl"
2049 "`ovm_update_sequence_lib"
2050 "`ovm_update_sequence_lib_and_item"
2053 "`static_message") nil )))
2055 (defconst verilog-uvm-statement-re
2060 "`uvm_analysis_imp_decl"
2061 "`uvm_blocking_get_imp_decl"
2062 "`uvm_blocking_get_peek_imp_decl"
2063 "`uvm_blocking_master_imp_decl"
2064 "`uvm_blocking_peek_imp_decl"
2065 "`uvm_blocking_put_imp_decl"
2066 "`uvm_blocking_slave_imp_decl"
2067 "`uvm_blocking_transport_imp_decl"
2068 "`uvm_component_param_utils"
2069 "`uvm_component_registry"
2070 "`uvm_component_registry_param"
2071 "`uvm_component_utils"
2074 "`uvm_create_seq" ;; Undocumented in 1.1
2075 "`uvm_declare_p_sequencer"
2076 "`uvm_declare_sequence_lib" ;; Deprecated in 1.1
2079 "`uvm_do_callbacks_exit_on"
2080 "`uvm_do_obj_callbacks"
2081 "`uvm_do_obj_callbacks_exit_on"
2084 "`uvm_do_on_pri_with"
2088 "`uvm_do_seq" ;; Undocumented in 1.1
2089 "`uvm_do_seq_with" ;; Undocumented in 1.1
2092 "`uvm_error_context"
2094 "`uvm_fatal_context"
2095 "`uvm_field_aa_int_byte"
2096 "`uvm_field_aa_int_byte_unsigned"
2097 "`uvm_field_aa_int_enum"
2098 "`uvm_field_aa_int_int"
2099 "`uvm_field_aa_int_int_unsigned"
2100 "`uvm_field_aa_int_integer"
2101 "`uvm_field_aa_int_integer_unsigned"
2102 "`uvm_field_aa_int_key"
2103 "`uvm_field_aa_int_longint"
2104 "`uvm_field_aa_int_longint_unsigned"
2105 "`uvm_field_aa_int_shortint"
2106 "`uvm_field_aa_int_shortint_unsigned"
2107 "`uvm_field_aa_int_string"
2108 "`uvm_field_aa_object_int"
2109 "`uvm_field_aa_object_string"
2110 "`uvm_field_aa_string_int"
2111 "`uvm_field_aa_string_string"
2112 "`uvm_field_array_enum"
2113 "`uvm_field_array_int"
2114 "`uvm_field_array_object"
2115 "`uvm_field_array_string"
2120 "`uvm_field_queue_enum"
2121 "`uvm_field_queue_int"
2122 "`uvm_field_queue_object"
2123 "`uvm_field_queue_string"
2125 "`uvm_field_sarray_enum"
2126 "`uvm_field_sarray_int"
2127 "`uvm_field_sarray_object"
2128 "`uvm_field_sarray_string"
2131 "`uvm_file" ;; Undocumented in 1.1, use `__FILE__
2133 "`uvm_get_peek_imp_decl"
2136 "`uvm_line" ;; Undocumented in 1.1, use `__LINE__
2137 "`uvm_master_imp_decl"
2138 "`uvm_non_blocking_transport_imp_decl" ;; Deprecated in 1.1
2139 "`uvm_nonblocking_get_imp_decl"
2140 "`uvm_nonblocking_get_peek_imp_decl"
2141 "`uvm_nonblocking_master_imp_decl"
2142 "`uvm_nonblocking_peek_imp_decl"
2143 "`uvm_nonblocking_put_imp_decl"
2144 "`uvm_nonblocking_slave_imp_decl"
2145 "`uvm_nonblocking_transport_imp_decl"
2146 "`uvm_object_param_utils"
2147 "`uvm_object_registry"
2148 "`uvm_object_registry_param" ;; Undocumented in 1.1
2162 "`uvm_peek_imp_decl"
2165 "`uvm_rand_send_pri"
2166 "`uvm_rand_send_pri_with"
2167 "`uvm_rand_send_with"
2168 "`uvm_record_attribute"
2173 "`uvm_sequence_utils" ;; Deprecated in 1.1
2174 "`uvm_set_super_type"
2175 "`uvm_slave_imp_decl"
2176 "`uvm_transport_imp_decl"
2178 "`uvm_unpack_arrayN"
2184 "`uvm_unpack_queueN"
2186 "`uvm_unpack_sarray"
2187 "`uvm_unpack_sarrayN"
2188 "`uvm_unpack_string"
2189 "`uvm_update_sequence_lib" ;; Deprecated in 1.1
2190 "`uvm_update_sequence_lib_and_item" ;; Deprecated in 1.1
2192 "`uvm_warning_context") nil )))
2196 ;; Regular expressions used to calculate indent, etc.
2198 (defconst verilog-symbol-re "\\<[a-zA-Z_][a-zA-Z_0-9.]*\\>")
2205 (defconst verilog-assignment-operator-re
2209 ;; blocking assignment_operator
2210 "=" "+=" "-=" "*=" "/=" "%=" "&=" "|=" "^=" "<<=" ">>=" "<<<=" ">>>="
2211 ;; non blocking assignment operator
2214 "==" "!=" "===" "!===" "<=" ">=" "==\?" "!=\?"
2219 ;; Is this a legal verilog operator?
2223 (defconst verilog-assignment-operation-re
2225 ; "\\(^\\s-*[A-Za-z0-9_]+\\(\\[\\([A-Za-z0-9_]+\\)\\]\\)*\\s-*\\)"
2226 ; "\\(^\\s-*[^=<>+-*/%&|^:\\s-]+[^=<>+-*/%&|^\n]*?\\)"
2227 "\\(^.*?\\)" "\\B" verilog-assignment-operator-re "\\B" ))
2229 (defconst verilog-label-re (concat verilog-symbol-re "\\s-*:\\s-*"))
2230 (defconst verilog-property-re
2231 (concat "\\(" verilog-label-re "\\)?"
2232 "\\(\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(assert\\)"))
2233 ;; "\\(assert\\|assume\\|cover\\)\\s-+property\\>"
2235 (defconst verilog-no-indent-begin-re
2236 "\\<\\(if\\|else\\|while\\|for\\|repeat\\|always\\|always_comb\\|always_ff\\|always_latch\\)\\>")
2238 (defconst verilog-ends-re
2239 ;; Parenthesis indicate type of keyword found
2241 "\\(\\<else\\>\\)\\|" ; 1
2242 "\\(\\<if\\>\\)\\|" ; 2
2243 "\\(\\<assert\\>\\)\\|" ; 3
2244 "\\(\\<end\\>\\)\\|" ; 3.1
2245 "\\(\\<endcase\\>\\)\\|" ; 4
2246 "\\(\\<endfunction\\>\\)\\|" ; 5
2247 "\\(\\<endtask\\>\\)\\|" ; 6
2248 "\\(\\<endspecify\\>\\)\\|" ; 7
2249 "\\(\\<endtable\\>\\)\\|" ; 8
2250 "\\(\\<endgenerate\\>\\)\\|" ; 9
2251 "\\(\\<join\\(_any\\|_none\\)?\\>\\)\\|" ; 10
2252 "\\(\\<endclass\\>\\)\\|" ; 11
2253 "\\(\\<endgroup\\>\\)\\|" ; 12
2255 "\\(\\<`vmm_data_member_end\\>\\)\\|"
2256 "\\(\\<`vmm_env_member_end\\>\\)\\|"
2257 "\\(\\<`vmm_scenario_member_end\\>\\)\\|"
2258 "\\(\\<`vmm_subenv_member_end\\>\\)\\|"
2259 "\\(\\<`vmm_xactor_member_end\\>\\)\\|"
2261 "\\(\\<`ovm_component_utils_end\\>\\)\\|"
2262 "\\(\\<`ovm_field_utils_end\\>\\)\\|"
2263 "\\(\\<`ovm_object_utils_end\\>\\)\\|"
2264 "\\(\\<`ovm_sequence_utils_end\\>\\)\\|"
2265 "\\(\\<`ovm_sequencer_utils_end\\>\\)"
2267 "\\(\\<`uvm_component_utils_end\\>\\)\\|"
2268 "\\(\\<`uvm_field_utils_end\\>\\)\\|"
2269 "\\(\\<`uvm_object_utils_end\\>\\)\\|"
2270 "\\(\\<`uvm_sequence_utils_end\\>\\)\\|"
2271 "\\(\\<`uvm_sequencer_utils_end\\>\\)"
2274 (defconst verilog-auto-end-comment-lines-re
2275 ;; Matches to names in this list cause auto-end-commenting
2277 verilog-directive-re "\\)\\|\\("
2279 (verilog-regexp-words
2307 ;;; NOTE: verilog-leap-to-head expects that verilog-end-block-re and
2308 ;;; verilog-end-block-ordered-re matches exactly the same strings.
2309 (defconst verilog-end-block-ordered-re
2310 ;; Parenthesis indicate type of keyword found
2311 (concat "\\(\\<endcase\\>\\)\\|" ; 1
2312 "\\(\\<end\\>\\)\\|" ; 2
2313 "\\(\\<end" ; 3, but not used
2314 "\\(" ; 4, but not used
2315 "\\(function\\)\\|" ; 5
2317 "\\(module\\)\\|" ; 7
2318 "\\(primitive\\)\\|" ; 8
2319 "\\(interface\\)\\|" ; 9
2320 "\\(package\\)\\|" ; 10
2321 "\\(class\\)\\|" ; 11
2322 "\\(group\\)\\|" ; 12
2323 "\\(program\\)\\|" ; 13
2324 "\\(sequence\\)\\|" ; 14
2325 "\\(clocking\\)\\|" ; 15
2327 (defconst verilog-end-block-re
2329 (verilog-regexp-words
2331 `("end" ;; closes begin
2332 "endcase" ;; closes any of case, casex casez or randcase
2333 "join" "join_any" "join_none" ;; closes fork
2348 "`ovm_component_utils_end"
2349 "`ovm_field_utils_end"
2350 "`ovm_object_utils_end"
2351 "`ovm_sequence_utils_end"
2352 "`ovm_sequencer_utils_end"
2354 "`uvm_component_utils_end"
2355 "`uvm_field_utils_end"
2356 "`uvm_object_utils_end"
2357 "`uvm_sequence_utils_end"
2358 "`uvm_sequencer_utils_end"
2360 "`vmm_data_member_end"
2361 "`vmm_env_member_end"
2362 "`vmm_scenario_member_end"
2363 "`vmm_subenv_member_end"
2364 "`vmm_xactor_member_end"
2368 (defconst verilog-endcomment-reason-re
2369 ;; Parenthesis indicate type of keyword found
2371 "\\(\\<begin\\>\\)\\|" ; 1
2372 "\\(\\<else\\>\\)\\|" ; 2
2373 "\\(\\<end\\>\\s-+\\<else\\>\\)\\|" ; 3
2374 "\\(\\<always_comb\\>\\(\[ \t\]*@\\)?\\)\\|" ; 4
2375 "\\(\\<always_ff\\>\\(\[ \t\]*@\\)?\\)\\|" ; 5
2376 "\\(\\<always_latch\\>\\(\[ \t\]*@\\)?\\)\\|" ; 6
2377 "\\(\\<fork\\>\\)\\|" ; 7
2378 "\\(\\<always\\>\\(\[ \t\]*@\\)?\\)\\|"
2380 verilog-property-re "\\|"
2381 "\\(\\(" verilog-label-re "\\)?\\<assert\\>\\)\\|"
2382 "\\(\\<clocking\\>\\)\\|"
2383 "\\(\\<task\\>\\)\\|"
2384 "\\(\\<function\\>\\)\\|"
2385 "\\(\\<initial\\>\\)\\|"
2386 "\\(\\<interface\\>\\)\\|"
2387 "\\(\\<package\\>\\)\\|"
2388 "\\(\\<final\\>\\)\\|"
2390 "\\(\\<while\\>\\)\\|"
2391 "\\(\\<for\\(ever\\|each\\)?\\>\\)\\|"
2392 "\\(\\<repeat\\>\\)\\|\\(\\<wait\\>\\)\\|"
2395 (defconst verilog-named-block-re "begin[ \t]*:")
2397 ;; These words begin a block which can occur inside a module which should be indented,
2398 ;; and closed with the respective word from the end-block list
2400 (defconst verilog-beg-block-re
2402 (verilog-regexp-words
2404 "case" "casex" "casez" "randcase"
2414 "`ovm_component_utils_begin"
2415 "`ovm_component_param_utils_begin"
2416 "`ovm_field_utils_begin"
2417 "`ovm_object_utils_begin"
2418 "`ovm_object_param_utils_begin"
2419 "`ovm_sequence_utils_begin"
2420 "`ovm_sequencer_utils_begin"
2422 "`uvm_component_utils_begin"
2423 "`uvm_component_param_utils_begin"
2424 "`uvm_field_utils_begin"
2425 "`uvm_object_utils_begin"
2426 "`uvm_object_param_utils_begin"
2427 "`uvm_sequence_utils_begin"
2428 "`uvm_sequencer_utils_begin"
2430 "`vmm_data_member_begin"
2431 "`vmm_env_member_begin"
2432 "`vmm_scenario_member_begin"
2433 "`vmm_subenv_member_begin"
2434 "`vmm_xactor_member_begin"
2436 ;; These are the same words, in a specific order in the regular
2437 ;; expression so that matching will work nicely for
2438 ;; verilog-forward-sexp and verilog-calc-indent
2439 (defconst verilog-beg-block-re-ordered
2440 ( concat "\\(\\<begin\\>\\)" ;1
2441 "\\|\\(\\<randcase\\>\\|\\(\\<unique\\s-+\\|priority\\s-+\\)?case[xz]?\\>\\)" ; 2,3
2442 "\\|\\(\\(\\<disable\\>\\s-+\\|\\<wait\\>\\s-+\\)?fork\\>\\)" ;4,5
2443 "\\|\\(\\<class\\>\\)" ;6
2444 "\\|\\(\\<table\\>\\)" ;7
2445 "\\|\\(\\<specify\\>\\)" ;8
2446 "\\|\\(\\<function\\>\\)" ;9
2447 "\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)*\\<function\\>\\)" ;10
2448 "\\|\\(\\<task\\>\\)" ;14
2449 "\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)*\\<task\\>\\)" ;15
2450 "\\|\\(\\<generate\\>\\)" ;18
2451 "\\|\\(\\<covergroup\\>\\)" ;16 20
2452 "\\|\\(\\(\\(\\<cover\\>\\s-+\\)\\|\\(\\<assert\\>\\s-+\\)\\)*\\<property\\>\\)" ;17 21
2453 "\\|\\(\\<\\(rand\\)?sequence\\>\\)" ;21 25
2454 "\\|\\(\\<clocking\\>\\)" ;22 27
2455 "\\|\\(\\<`[ou]vm_[a-z_]+_begin\\>\\)" ;28
2456 "\\|\\(\\<`vmm_[a-z_]+_member_begin\\>\\)"
2460 (defconst verilog-end-block-ordered-rry
2461 [ "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
2462 "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)"
2463 "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
2464 "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)"
2465 "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)"
2466 "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)"
2467 "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)"
2468 "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)"
2469 "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)"
2470 "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)"
2471 "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)"
2472 "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)"
2473 "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)"
2476 (defconst verilog-nameable-item-re
2478 (verilog-regexp-words
2481 "join" "join_any" "join_none"
2498 (defconst verilog-declaration-opener
2500 (verilog-regexp-words
2501 `("module" "begin" "task" "function"))))
2503 (defconst verilog-declaration-prefix-re
2505 (verilog-regexp-words
2508 "inout" "input" "output" "ref"
2510 "const" "static" "protected" "local"
2512 "localparam" "parameter" "var"
2516 (defconst verilog-declaration-core-re
2518 (verilog-regexp-words
2520 ;; port direction (by themselves)
2521 "inout" "input" "output"
2522 ;; integer_atom_type
2523 "byte" "shortint" "int" "longint" "integer" "time"
2524 ;; integer_vector_type
2527 "shortreal" "real" "realtime"
2529 "supply0" "supply1" "tri" "triand" "trior" "trireg" "tri0" "tri1" "uwire" "wire" "wand" "wor"
2531 "string" "event" "chandle" "virtual" "enum" "genvar"
2534 "mailbox" "semaphore"
2536 (defconst verilog-declaration-re
2537 (concat "\\(" verilog-declaration-prefix-re "\\s-*\\)?" verilog-declaration-core-re))
2538 (defconst verilog-range-re "\\(\\[[^]]*\\]\\s-*\\)+")
2539 (defconst verilog-optional-signed-re "\\s-*\\(signed\\)?")
2540 (defconst verilog-optional-signed-range-re
2542 "\\s-*\\(\\<\\(reg\\|wire\\)\\>\\s-*\\)?\\(\\<signed\\>\\s-*\\)?\\(" verilog-range-re "\\)?"))
2543 (defconst verilog-macroexp-re "`\\sw+")
2545 (defconst verilog-delay-re "#\\s-*\\(\\([0-9_]+\\('s?[hdxbo][0-9a-fA-F_xz]+\\)?\\)\\|\\(([^()]*)\\)\\|\\(\\sw+\\)\\)")
2546 (defconst verilog-declaration-re-2-no-macro
2547 (concat "\\s-*" verilog-declaration-re
2548 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
2550 (defconst verilog-declaration-re-2-macro
2551 (concat "\\s-*" verilog-declaration-re
2552 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
2553 "\\|\\(" verilog-macroexp-re "\\)"
2555 (defconst verilog-declaration-re-1-macro
2556 (concat "^" verilog-declaration-re-2-macro))
2558 (defconst verilog-declaration-re-1-no-macro (concat "^" verilog-declaration-re-2-no-macro))
2560 (defconst verilog-defun-re
2561 (eval-when-compile (verilog-regexp-words `("macromodule" "module" "class" "program" "interface" "package" "primitive" "config"))))
2562 (defconst verilog-end-defun-re
2563 (eval-when-compile (verilog-regexp-words `("endmodule" "endclass" "endprogram" "endinterface" "endpackage" "endprimitive" "endconfig"))))
2564 (defconst verilog-zero-indent-re
2565 (concat verilog-defun-re "\\|" verilog-end-defun-re))
2566 (defconst verilog-inst-comment-re
2567 (eval-when-compile (verilog-regexp-words `("Outputs" "Inouts" "Inputs" "Interfaces" "Interfaced"))))
2569 (defconst verilog-behavioral-block-beg-re
2570 (eval-when-compile (verilog-regexp-words `("initial" "final" "always" "always_comb" "always_latch" "always_ff"
2571 "function" "task"))))
2572 (defconst verilog-coverpoint-re "\\w+\\s*:\\s*\\(coverpoint\\|cross\\constraint\\)" )
2573 (defconst verilog-indent-re
2575 (verilog-regexp-words
2578 "always" "always_latch" "always_ff" "always_comb"
2580 ; "unique" "priority"
2581 "case" "casex" "casez" "randcase" "endcase"
2583 "clocking" "endclocking"
2584 "config" "endconfig"
2585 "covergroup" "endgroup"
2586 "fork" "join" "join_any" "join_none"
2587 "function" "endfunction"
2589 "generate" "endgenerate"
2591 "interface" "endinterface"
2592 "module" "macromodule" "endmodule"
2593 "package" "endpackage"
2594 "primitive" "endprimitive"
2595 "program" "endprogram"
2596 "property" "endproperty"
2597 "sequence" "randsequence" "endsequence"
2598 "specify" "endspecify"
2605 "`if" "`ifdef" "`ifndef" "`else" "`elsif" "`endif"
2606 "`while" "`endwhile"
2611 "`protect" "`endprotect"
2612 "`switch" "`endswitch"
2616 "`ovm_component_utils_begin"
2617 "`ovm_component_param_utils_begin"
2618 "`ovm_field_utils_begin"
2619 "`ovm_object_utils_begin"
2620 "`ovm_object_param_utils_begin"
2621 "`ovm_sequence_utils_begin"
2622 "`ovm_sequencer_utils_begin"
2624 "`ovm_component_utils_end"
2625 "`ovm_field_utils_end"
2626 "`ovm_object_utils_end"
2627 "`ovm_sequence_utils_end"
2628 "`ovm_sequencer_utils_end"
2630 "`uvm_component_utils_begin"
2631 "`uvm_component_param_utils_begin"
2632 "`uvm_field_utils_begin"
2633 "`uvm_object_utils_begin"
2634 "`uvm_object_param_utils_begin"
2635 "`uvm_sequence_utils_begin"
2636 "`uvm_sequencer_utils_begin"
2638 "`uvm_component_utils_end" ;; Typo in spec, it's not uvm_component_end
2639 "`uvm_field_utils_end"
2640 "`uvm_object_utils_end"
2641 "`uvm_sequence_utils_end"
2642 "`uvm_sequencer_utils_end"
2644 "`vmm_data_member_begin"
2645 "`vmm_env_member_begin"
2646 "`vmm_scenario_member_begin"
2647 "`vmm_subenv_member_begin"
2648 "`vmm_xactor_member_begin"
2650 "`vmm_data_member_end"
2651 "`vmm_env_member_end"
2652 "`vmm_scenario_member_end"
2653 "`vmm_subenv_member_end"
2654 "`vmm_xactor_member_end"
2657 (defconst verilog-defun-level-not-generate-re
2659 (verilog-regexp-words
2660 `( "module" "macromodule" "primitive" "class" "program"
2661 "interface" "package" "config"))))
2663 (defconst verilog-defun-level-re
2665 (verilog-regexp-words
2667 `( "module" "macromodule" "primitive" "class" "program"
2668 "interface" "package" "config")
2669 `( "initial" "final" "always" "always_comb" "always_ff"
2670 "always_latch" "endtask" "endfunction" )))))
2672 (defconst verilog-defun-level-generate-only-re
2674 (verilog-regexp-words
2675 `( "initial" "final" "always" "always_comb" "always_ff"
2676 "always_latch" "endtask" "endfunction" ))))
2678 (defconst verilog-cpp-level-re
2680 (verilog-regexp-words
2682 "endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass"
2684 (defconst verilog-disable-fork-re "\\(disable\\|wait\\)\\s-+fork\\>")
2685 (defconst verilog-extended-case-re "\\(\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
2686 (defconst verilog-extended-complete-re
2687 (concat "\\(\\(\\<extern\\s-+\\|\\<\\(\\<pure\\>\\s-+\\)?virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)\\)"
2688 "\\|\\(\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)\\)"
2689 "\\|\\(\\(\\<import\\>\\s-+\\)?\\(\"DPI-C\"\\s-+\\)?\\(\\<pure\\>\\s-+\\)?\\(function\\>\\|task\\>\\)\\)"
2690 "\\|" verilog-extended-case-re ))
2691 (defconst verilog-basic-complete-re
2693 (verilog-regexp-words
2695 "always" "assign" "always_latch" "always_ff" "always_comb" "constraint"
2696 "import" "initial" "final" "module" "macromodule" "repeat" "randcase" "while"
2697 "if" "for" "forever" "foreach" "else" "parameter" "do" "localparam" "assert"
2699 (defconst verilog-complete-reg
2701 verilog-extended-complete-re "\\|\\(" verilog-basic-complete-re "\\)"))
2703 (defconst verilog-end-statement-re
2704 (concat "\\(" verilog-beg-block-re "\\)\\|\\("
2705 verilog-end-block-re "\\)"))
2707 (defconst verilog-endcase-re
2708 (concat verilog-extended-case-re "\\|"
2713 (defconst verilog-exclude-str-start "/* -----\\/----- EXCLUDED -----\\/-----"
2714 "String used to mark beginning of excluded text.")
2715 (defconst verilog-exclude-str-end " -----/\\----- EXCLUDED -----/\\----- */"
2716 "String used to mark end of excluded text.")
2717 (defconst verilog-preprocessor-re
2719 (verilog-regexp-words
2721 "`define" "`include" "`ifdef" "`ifndef" "`if" "`endif" "`else"
2724 (defconst verilog-keywords
2725 '( "`case" "`default" "`define" "`else" "`endfor" "`endif"
2726 "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
2727 "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
2728 "`time_scale" "`undef" "`while"
2730 "after" "alias" "always" "always_comb" "always_ff" "always_latch" "and"
2731 "assert" "assign" "assume" "automatic" "before" "begin" "bind"
2732 "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte"
2733 "case" "casex" "casez" "cell" "chandle" "class" "clocking" "cmos"
2734 "config" "const" "constraint" "context" "continue" "cover"
2735 "covergroup" "coverpoint" "cross" "deassign" "default" "defparam"
2736 "design" "disable" "dist" "do" "edge" "else" "end" "endcase"
2737 "endclass" "endclocking" "endconfig" "endfunction" "endgenerate"
2738 "endgroup" "endinterface" "endmodule" "endpackage" "endprimitive"
2739 "endprogram" "endproperty" "endspecify" "endsequence" "endtable"
2740 "endtask" "enum" "event" "expect" "export" "extends" "extern"
2741 "final" "first_match" "for" "force" "foreach" "forever" "fork"
2742 "forkjoin" "function" "generate" "genvar" "highz0" "highz1" "if"
2743 "iff" "ifnone" "ignore_bins" "illegal_bins" "import" "incdir"
2744 "include" "initial" "inout" "input" "inside" "instance" "int"
2745 "integer" "interface" "intersect" "join" "join_any" "join_none"
2746 "large" "liblist" "library" "local" "localparam" "logic"
2747 "longint" "macromodule" "mailbox" "matches" "medium" "modport" "module"
2748 "nand" "negedge" "new" "nmos" "nor" "noshowcancelled" "not"
2749 "notif0" "notif1" "null" "or" "output" "package" "packed"
2750 "parameter" "pmos" "posedge" "primitive" "priority" "program"
2751 "property" "protected" "pull0" "pull1" "pulldown" "pullup"
2752 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
2753 "randcase" "randsequence" "rcmos" "real" "realtime" "ref" "reg"
2754 "release" "repeat" "return" "rnmos" "rpmos" "rtran" "rtranif0"
2755 "rtranif1" "scalared" "semaphore" "sequence" "shortint" "shortreal"
2756 "showcancelled" "signed" "small" "solve" "specify" "specparam"
2757 "static" "string" "strong0" "strong1" "struct" "super" "supply0"
2758 "supply1" "table" "tagged" "task" "this" "throughout" "time"
2759 "timeprecision" "timeunit" "tran" "tranif0" "tranif1" "tri"
2760 "tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union"
2761 "unique" "unsigned" "use" "uwire" "var" "vectored" "virtual" "void"
2762 "wait" "wait_order" "wand" "weak0" "weak1" "while" "wildcard"
2763 "wire" "with" "within" "wor" "xnor" "xor"
2765 "accept_on" "checker" "endchecker" "eventually" "global" "implies"
2766 "let" "nexttime" "reject_on" "restrict" "s_always" "s_eventually"
2767 "s_nexttime" "s_until" "s_until_with" "strong" "sync_accept_on"
2768 "sync_reject_on" "unique0" "until" "until_with" "untyped" "weak"
2770 "List of Verilog keywords.")
2772 (defconst verilog-comment-start-regexp "//\\|/\\*"
2773 "Dual comment value for `comment-start-regexp'.")
2775 (defvar verilog-mode-syntax-table
2776 (let ((table (make-syntax-table)))
2777 ;; Populate the syntax TABLE.
2778 (modify-syntax-entry ?\\ "\\" table)
2779 (modify-syntax-entry ?+ "." table)
2780 (modify-syntax-entry ?- "." table)
2781 (modify-syntax-entry ?= "." table)
2782 (modify-syntax-entry ?% "." table)
2783 (modify-syntax-entry ?< "." table)
2784 (modify-syntax-entry ?> "." table)
2785 (modify-syntax-entry ?& "." table)
2786 (modify-syntax-entry ?| "." table)
2787 ;; FIXME: This goes against Emacs conventions. Use "_" syntax instead and
2788 ;; then use regexps with things like "\\_<...\\_>".
2789 (modify-syntax-entry ?` "w" table)
2790 (modify-syntax-entry ?_ "w" table)
2791 (modify-syntax-entry ?\' "." table)
2793 ;; Set up TABLE to handle block and line style comments.
2794 (if (featurep 'xemacs)
2796 ;; XEmacs (formerly Lucid) has the best implementation
2797 (modify-syntax-entry ?/ ". 1456" table)
2798 (modify-syntax-entry ?* ". 23" table)
2799 (modify-syntax-entry ?\n "> b" table))
2800 ;; Emacs does things differently, but we can work with it
2801 (modify-syntax-entry ?/ ". 124b" table)
2802 (modify-syntax-entry ?* ". 23" table)
2803 (modify-syntax-entry ?\n "> b" table))
2805 "Syntax table used in Verilog mode buffers.")
2807 (defvar verilog-font-lock-keywords nil
2808 "Default highlighting for Verilog mode.")
2810 (defvar verilog-font-lock-keywords-1 nil
2811 "Subdued level highlighting for Verilog mode.")
2813 (defvar verilog-font-lock-keywords-2 nil
2814 "Medium level highlighting for Verilog mode.
2815 See also `verilog-font-lock-extra-types'.")
2817 (defvar verilog-font-lock-keywords-3 nil
2818 "Gaudy level highlighting for Verilog mode.
2819 See also `verilog-font-lock-extra-types'.")
2821 (defvar verilog-font-lock-translate-off-face
2822 'verilog-font-lock-translate-off-face
2823 "Font to use for translated off regions.")
2824 (defface verilog-font-lock-translate-off-face
2827 (:background "gray90" :italic t ))
2830 (:background "gray10" :italic t ))
2831 (((class grayscale) (background light))
2832 (:foreground "DimGray" :italic t))
2833 (((class grayscale) (background dark))
2834 (:foreground "LightGray" :italic t))
2836 "Font lock mode face used to background highlight translate-off regions."
2837 :group 'font-lock-highlighting-faces)
2839 (defvar verilog-font-lock-p1800-face
2840 'verilog-font-lock-p1800-face
2841 "Font to use for p1800 keywords.")
2842 (defface verilog-font-lock-p1800-face
2845 (:foreground "DarkOrange3" :bold t ))
2848 (:foreground "orange1" :bold t ))
2850 "Font lock mode face used to highlight P1800 keywords."
2851 :group 'font-lock-highlighting-faces)
2853 (defvar verilog-font-lock-ams-face
2854 'verilog-font-lock-ams-face
2855 "Font to use for Analog/Mixed Signal keywords.")
2856 (defface verilog-font-lock-ams-face
2859 (:foreground "Purple" :bold t ))
2862 (:foreground "orange1" :bold t ))
2864 "Font lock mode face used to highlight AMS keywords."
2865 :group 'font-lock-highlighting-faces)
2867 (defvar verilog-font-grouping-keywords-face
2868 'verilog-font-lock-grouping-keywords-face
2869 "Font to use for Verilog Grouping Keywords (such as begin..end).")
2870 (defface verilog-font-lock-grouping-keywords-face
2873 (:foreground "red4" :bold t ))
2876 (:foreground "red4" :bold t ))
2878 "Font lock mode face used to highlight verilog grouping keywords."
2879 :group 'font-lock-highlighting-faces)
2881 (let* ((verilog-type-font-keywords
2885 "and" "bit" "buf" "bufif0" "bufif1" "cmos" "defparam"
2886 "event" "genvar" "inout" "input" "integer" "localparam"
2887 "logic" "mailbox" "nand" "nmos" "not" "notif0" "notif1" "or"
2888 "output" "parameter" "pmos" "pull0" "pull1" "pulldown" "pullup"
2889 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran"
2890 "rtranif0" "rtranif1" "semaphore" "signed" "struct" "supply"
2891 "supply0" "supply1" "time" "tran" "tranif0" "tranif1"
2892 "tri" "tri0" "tri1" "triand" "trior" "trireg" "typedef"
2893 "uwire" "vectored" "wand" "wire" "wor" "xnor" "xor"
2896 (verilog-pragma-keywords
2899 '("surefire" "auto" "synopsys" "rtl_synthesis" "verilint" "leda" "0in"
2902 (verilog-1800-2005-keywords
2905 '("alias" "assert" "assume" "automatic" "before" "bind"
2906 "bins" "binsof" "break" "byte" "cell" "chandle" "class"
2907 "clocking" "config" "const" "constraint" "context" "continue"
2908 "cover" "covergroup" "coverpoint" "cross" "deassign" "design"
2909 "dist" "do" "edge" "endclass" "endclocking" "endconfig"
2910 "endgroup" "endprogram" "endproperty" "endsequence" "enum"
2911 "expect" "export" "extends" "extern" "first_match" "foreach"
2912 "forkjoin" "genvar" "highz0" "highz1" "ifnone" "ignore_bins"
2913 "illegal_bins" "import" "incdir" "include" "inside" "instance"
2914 "int" "intersect" "large" "liblist" "library" "local" "longint"
2915 "matches" "medium" "modport" "new" "noshowcancelled" "null"
2916 "packed" "program" "property" "protected" "pull0" "pull1"
2917 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
2918 "randcase" "randsequence" "ref" "release" "return" "scalared"
2919 "sequence" "shortint" "shortreal" "showcancelled" "small" "solve"
2920 "specparam" "static" "string" "strong0" "strong1" "struct"
2921 "super" "tagged" "this" "throughout" "timeprecision" "timeunit"
2922 "type" "union" "unsigned" "use" "var" "virtual" "void"
2923 "wait_order" "weak0" "weak1" "wildcard" "with" "within"
2926 (verilog-1800-2009-keywords
2929 '("accept_on" "checker" "endchecker" "eventually" "global"
2930 "implies" "let" "nexttime" "reject_on" "restrict" "s_always"
2931 "s_eventually" "s_nexttime" "s_until" "s_until_with" "strong"
2932 "sync_accept_on" "sync_reject_on" "unique0" "until"
2933 "until_with" "untyped" "weak" ) nil )))
2935 (verilog-ams-keywords
2938 '("above" "abs" "absdelay" "acos" "acosh" "ac_stim"
2939 "aliasparam" "analog" "analysis" "asin" "asinh" "atan" "atan2" "atanh"
2940 "branch" "ceil" "connectmodule" "connectrules" "cos" "cosh" "ddt"
2941 "ddx" "discipline" "driver_update" "enddiscipline" "endconnectrules"
2942 "endnature" "endparamset" "exclude" "exp" "final_step" "flicker_noise"
2943 "floor" "flow" "from" "ground" "hypot" "idt" "idtmod" "inf"
2944 "initial_step" "laplace_nd" "laplace_np" "laplace_zd" "laplace_zp"
2945 "last_crossing" "limexp" "ln" "log" "max" "min" "nature"
2946 "net_resolution" "noise_table" "paramset" "potential" "pow" "sin"
2947 "sinh" "slew" "sqrt" "tan" "tanh" "timer" "transition" "white_noise"
2948 "wreal" "zi_nd" "zi_np" "zi_zd" ) nil )))
2950 (verilog-font-keywords
2954 "assign" "case" "casex" "casez" "randcase" "deassign"
2955 "default" "disable" "else" "endcase" "endfunction"
2956 "endgenerate" "endinterface" "endmodule" "endprimitive"
2957 "endspecify" "endtable" "endtask" "final" "for" "force" "return" "break"
2958 "continue" "forever" "fork" "function" "generate" "if" "iff" "initial"
2959 "interface" "join" "join_any" "join_none" "macromodule" "module" "negedge"
2960 "package" "endpackage" "always" "always_comb" "always_ff"
2961 "always_latch" "posedge" "primitive" "priority" "release"
2962 "repeat" "specify" "table" "task" "unique" "wait" "while"
2963 "class" "program" "endclass" "endprogram"
2966 (verilog-font-grouping-keywords
2969 '( "begin" "end" ) nil ))))
2971 (setq verilog-font-lock-keywords
2973 ;; Fontify all builtin keywords
2974 (concat "\\<\\(" verilog-font-keywords "\\|"
2975 ;; And user/system tasks and functions
2976 "\\$[a-zA-Z][a-zA-Z0-9_\\$]*"
2978 ;; Fontify all types
2979 (if verilog-highlight-grouping-keywords
2980 (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
2981 'verilog-font-lock-ams-face)
2982 (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
2983 'font-lock-type-face))
2984 (cons (concat "\\<\\(" verilog-type-font-keywords "\\)\\>")
2985 'font-lock-type-face)
2986 ;; Fontify IEEE-1800-2005 keywords appropriately
2987 (if verilog-highlight-p1800-keywords
2988 (cons (concat "\\<\\(" verilog-1800-2005-keywords "\\)\\>")
2989 'verilog-font-lock-p1800-face)
2990 (cons (concat "\\<\\(" verilog-1800-2005-keywords "\\)\\>")
2991 'font-lock-type-face))
2992 ;; Fontify IEEE-1800-2009 keywords appropriately
2993 (if verilog-highlight-p1800-keywords
2994 (cons (concat "\\<\\(" verilog-1800-2009-keywords "\\)\\>")
2995 'verilog-font-lock-p1800-face)
2996 (cons (concat "\\<\\(" verilog-1800-2009-keywords "\\)\\>")
2997 'font-lock-type-face))
2998 ;; Fontify Verilog-AMS keywords
2999 (cons (concat "\\<\\(" verilog-ams-keywords "\\)\\>")
3000 'verilog-font-lock-ams-face)))
3002 (setq verilog-font-lock-keywords-1
3003 (append verilog-font-lock-keywords
3005 ;; Fontify module definitions
3007 "\\<\\(\\(macro\\)?module\\|primitive\\|class\\|program\\|interface\\|package\\|task\\)\\>\\s-*\\(\\sw+\\)"
3008 '(1 font-lock-keyword-face)
3009 '(3 font-lock-function-name-face 'prepend))
3010 ;; Fontify function definitions
3012 (concat "\\<function\\>\\s-+\\(integer\\|real\\(time\\)?\\|time\\)\\s-+\\(\\sw+\\)" )
3013 '(1 font-lock-keyword-face)
3014 '(3 font-lock-constant-face prepend))
3015 '("\\<function\\>\\s-+\\(\\[[^]]+\\]\\)\\s-+\\(\\sw+\\)"
3016 (1 font-lock-keyword-face)
3017 (2 font-lock-constant-face append))
3018 '("\\<function\\>\\s-+\\(\\sw+\\)"
3019 1 'font-lock-constant-face append))))
3021 (setq verilog-font-lock-keywords-2
3022 (append verilog-font-lock-keywords-1
3025 (concat "\\(//\\s-*\\(" verilog-pragma-keywords "\\)\\s-.*\\)")
3026 ;; Fontify escaped names
3027 '("\\(\\\\\\S-*\\s-\\)" 0 font-lock-function-name-face)
3028 ;; Fontify macro definitions/ uses
3029 '("`\\s-*[A-Za-z][A-Za-z0-9_]*" 0 (if (boundp 'font-lock-preprocessor-face)
3030 'font-lock-preprocessor-face
3031 'font-lock-type-face))
3032 ;; Fontify delays/numbers
3033 '("\\(@\\)\\|\\(#\\s-*\\(\\(\[0-9_.\]+\\('s?[hdxbo][0-9a-fA-F_xz]*\\)?\\)\\|\\(([^()]+)\\|\\sw+\\)\\)\\)"
3034 0 font-lock-type-face append)
3035 ;; Fontify instantiation names
3036 '("\\([A-Za-z][A-Za-z0-9_]*\\)\\s-*(" 1 font-lock-function-name-face)
3039 (setq verilog-font-lock-keywords-3
3040 (append verilog-font-lock-keywords-2
3041 (when verilog-highlight-translate-off
3043 ;; Fontify things in translate off regions
3044 '(verilog-match-translate-off
3045 (0 'verilog-font-lock-translate-off-face prepend))
3049 ;; Buffer state preservation
3051 (defmacro verilog-save-buffer-state (&rest body)
3052 "Execute BODY forms, saving state around insignificant change.
3053 Changes in text properties like `face' or `syntax-table' are
3054 considered insignificant. This macro allows text properties to
3055 be changed, even in a read-only buffer.
3057 A change is considered significant if it affects the buffer text
3058 in any way that isn't completely restored again. Any
3059 user-visible changes to the buffer must not be within a
3060 `verilog-save-buffer-state'."
3061 ;; From c-save-buffer-state
3062 `(let* ((modified (buffer-modified-p))
3063 (buffer-undo-list t)
3064 (inhibit-read-only t)
3065 (inhibit-point-motion-hooks t)
3066 (verilog-no-change-functions t)
3067 before-change-functions
3068 after-change-functions
3070 buffer-file-name ; Prevent primitives checking
3071 buffer-file-truename) ; for file modification
3076 (set-buffer-modified-p nil)))))
3078 (defmacro verilog-save-no-change-functions (&rest body)
3079 "Execute BODY forms, disabling all change hooks in BODY.
3080 For insignificant changes, see instead `verilog-save-buffer-state'."
3081 `(let* ((inhibit-point-motion-hooks t)
3082 (verilog-no-change-functions t)
3083 before-change-functions
3084 after-change-functions)
3087 (defvar verilog-save-font-mod-hooked nil
3088 "Local variable when inside a `verilog-save-font-mods' block.")
3089 (make-variable-buffer-local 'verilog-save-font-mod-hooked)
3091 (defmacro verilog-save-font-mods (&rest body)
3092 "Execute BODY forms, disabling text modifications to allow performing BODY.
3093 Includes temporary disabling of `font-lock' to restore the buffer
3094 to full text form for parsing. Additional actions may be specified with
3095 `verilog-before-save-font-hook' and `verilog-after-save-font-hook'."
3096 ;; Before version 20, match-string with font-lock returns a
3097 ;; vector that is not equal to the string. IE if on "input"
3098 ;; nil==(equal "input" (progn (looking-at "input") (match-string 0)))
3099 `(let* ((hooked (unless verilog-save-font-mod-hooked
3100 (verilog-run-hooks 'verilog-before-save-font-hook)
3102 (verilog-save-font-mod-hooked t)
3103 (fontlocked (when (and (boundp 'font-lock-mode) font-lock-mode)
3109 (when fontlocked (font-lock-mode t))
3110 (when hooked (verilog-run-hooks 'verilog-after-save-font-hook)))))
3113 ;; Comment detection and caching
3115 (defvar verilog-scan-cache-preserving nil
3116 "If set, the specified buffer's comment properties are static.
3117 Buffer changes will be ignored. See `verilog-inside-comment-or-string-p'
3118 and `verilog-scan'.")
3120 (defvar verilog-scan-cache-tick nil
3121 "Modification tick at which `verilog-scan' was last completed.")
3122 (make-variable-buffer-local 'verilog-scan-cache-tick)
3124 (defun verilog-scan-cache-flush ()
3125 "Flush the `verilog-scan' cache."
3126 (setq verilog-scan-cache-tick nil))
3128 (defun verilog-scan-cache-ok-p ()
3129 "Return t iff the scan cache is up to date."
3130 (or (and verilog-scan-cache-preserving
3131 (eq verilog-scan-cache-preserving (current-buffer))
3132 verilog-scan-cache-tick)
3133 (equal verilog-scan-cache-tick (buffer-chars-modified-tick))))
3135 (defmacro verilog-save-scan-cache (&rest body)
3136 "Execute the BODY forms, allowing scan cache preservation within BODY.
3137 This requires that insertions must use `verilog-insert'."
3138 ;; If the buffer is out of date, trash it, as we'll not check later the tick
3139 ;; Note this must work properly if there's multiple layers of calls
3140 ;; to verilog-save-scan-cache even with differing ticks.
3142 (unless (verilog-scan-cache-ok-p) ;; Must be before let
3143 (setq verilog-scan-cache-tick nil))
3144 (let* ((verilog-scan-cache-preserving (current-buffer)))
3147 (defun verilog-scan-region (beg end)
3148 "Parse between BEG and END for `verilog-inside-comment-or-string-p'.
3149 This creates v-cmts properties where comments are in force."
3150 ;; Why properties and not overlays? Overlays have much slower non O(1)
3152 ;; This function is warm - called on every verilog-insert
3155 (verilog-save-buffer-state
3158 (while (< (point) end)
3159 (cond ((looking-at "//")
3161 (or (search-forward "\n" end t)
3163 ;; "1+": The leading // or /* itself isn't considered as
3164 ;; being "inside" the comment, so that a (search-backward)
3165 ;; that lands at the start of the // won't mis-indicate
3166 ;; it's inside a comment. Also otherwise it would be
3167 ;; hard to find a commented out /*AS*/ vs one that isn't
3168 (put-text-property (1+ pt) (point) 'v-cmts t))
3169 ((looking-at "/\\*")
3171 (or (search-forward "*/" end t)
3172 ;; No error - let later code indicate it so we can
3173 ;; use inside functions on-the-fly
3174 ;;(error "%s: Unmatched /* */, at char %d"
3175 ;; (verilog-point-text) (point))
3177 (put-text-property (1+ pt) (point) 'v-cmts t))
3180 (or (re-search-forward "[^\\]\"" end t) ;; don't forward-char first, since we look for a non backslash first
3181 ;; No error - let later code indicate it so we can
3183 (put-text-property (1+ pt) (point) 'v-cmts t))
3186 (if (re-search-forward "[/\"]" end t)
3188 (goto-char end))))))))))
3190 (defun verilog-scan ()
3191 "Parse the buffer, marking all comments with properties.
3192 Also assumes any text inserted since `verilog-scan-cache-tick'
3193 either is ok to parse as a non-comment, or `verilog-insert' was used."
3194 ;; See also `verilog-scan-debug' and `verilog-scan-and-debug'
3195 (unless (verilog-scan-cache-ok-p)
3197 (verilog-save-buffer-state
3199 (message "Scanning %s cache=%s cachetick=%S tick=%S" (current-buffer)
3200 verilog-scan-cache-preserving verilog-scan-cache-tick
3201 (buffer-chars-modified-tick)))
3202 (remove-text-properties (point-min) (point-max) '(v-cmts nil))
3203 (verilog-scan-region (point-min) (point-max))
3204 (setq verilog-scan-cache-tick (buffer-chars-modified-tick))
3205 (when verilog-debug (message "Scanning... done"))))))
3207 (defun verilog-scan-debug ()
3208 "For debugging, show with display face results of `verilog-scan'."
3210 ;;(if dbg (setq dbg (concat dbg (format "verilog-scan-debug\n"))))
3212 (goto-char (point-min))
3213 (remove-text-properties (point-min) (point-max) '(face nil))
3215 (cond ((get-text-property (point) 'v-cmts)
3216 (put-text-property (point) (1+ (point)) `face 'underline)
3217 ;;(if dbg (setq dbg (concat dbg (format " v-cmts at %S\n" (point)))))
3220 (goto-char (or (next-property-change (point)) (point-max))))))))
3222 (defun verilog-scan-and-debug ()
3223 "For debugging, run `verilog-scan' and `verilog-scan-debug'."
3224 (let (verilog-scan-cache-preserving
3225 verilog-scan-cache-tick)
3226 (goto-char (point-min))
3228 (verilog-scan-debug)))
3230 (defun verilog-inside-comment-or-string-p (&optional pos)
3231 "Check if optional point POS is inside a comment.
3232 This may require a slow pre-parse of the buffer with `verilog-scan'
3233 to establish comment properties on all text."
3234 ;; This function is very hot
3237 (and (>= pos (point-min))
3238 (get-text-property pos 'v-cmts))
3239 (get-text-property (point) 'v-cmts)))
3241 (defun verilog-insert (&rest stuff)
3242 "Insert STUFF arguments, tracking for `verilog-inside-comment-or-string-p'.
3243 Any insert that includes a comment must have the entire comment
3244 inserted using a single call to `verilog-insert'."
3247 (insert (car stuff))
3248 (setq stuff (cdr stuff)))
3249 (verilog-scan-region pt (point))))
3253 (defun verilog-declaration-end ()
3254 (search-forward ";"))
3256 (defun verilog-point-text (&optional pointnum)
3257 "Return text describing where POINTNUM or current point is (for errors).
3258 Use filename, if current buffer being edited shorten to just buffer name."
3259 (concat (or (and (equal (window-buffer (selected-window)) (current-buffer))
3263 ":" (int-to-string (1+ (count-lines (point-min) (or pointnum (point)))))))
3265 (defun electric-verilog-backward-sexp ()
3266 "Move backward over one balanced expression."
3268 ;; before that see if we are in a comment
3269 (verilog-backward-sexp))
3271 (defun electric-verilog-forward-sexp ()
3272 "Move forward over one balanced expression."
3274 ;; before that see if we are in a comment
3275 (verilog-forward-sexp))
3277 ;;;used by hs-minor-mode
3278 (defun verilog-forward-sexp-function (arg)
3280 (verilog-backward-sexp)
3281 (verilog-forward-sexp)))
3284 (defun verilog-backward-sexp ()
3289 (if (not (looking-at "\\<"))
3292 ((verilog-skip-backward-comment-or-string))
3293 ((looking-at "\\<else\\>")
3295 verilog-end-block-re
3296 "\\|\\(\\<else\\>\\)"
3297 "\\|\\(\\<if\\>\\)"))
3298 (while (and (not found)
3299 (verilog-re-search-backward reg nil 'move))
3301 ((match-end 1) ; matched verilog-end-block-re
3302 ; try to leap back to matching outward block by striding across
3303 ; indent level changing tokens then immediately
3304 ; previous line governs indentation.
3305 (verilog-leap-to-head))
3306 ((match-end 2) ; else, we're in deep
3307 (setq elsec (1+ elsec)))
3308 ((match-end 3) ; found it
3309 (setq elsec (1- elsec))
3311 ;; Now previous line describes syntax
3312 (setq found 't))))))
3313 ((looking-at verilog-end-block-re)
3314 (verilog-leap-to-head))
3315 ((looking-at "\\(endmodule\\>\\)\\|\\(\\<endprimitive\\>\\)\\|\\(\\<endclass\\>\\)\\|\\(\\<endprogram\\>\\)\\|\\(\\<endinterface\\>\\)\\|\\(\\<endpackage\\>\\)")
3318 (verilog-re-search-backward "\\<\\(macro\\)?module\\>" nil 'move))
3320 (verilog-re-search-backward "\\<primitive\\>" nil 'move))
3322 (verilog-re-search-backward "\\<class\\>" nil 'move))
3324 (verilog-re-search-backward "\\<program\\>" nil 'move))
3326 (verilog-re-search-backward "\\<interface\\>" nil 'move))
3328 (verilog-re-search-backward "\\<package\\>" nil 'move))
3331 (backward-sexp 1))))
3336 (defun verilog-forward-sexp ()
3341 (if (not (looking-at "\\<"))
3344 ((verilog-skip-forward-comment-or-string)
3345 (verilog-forward-syntactic-ws))
3346 ((looking-at verilog-beg-block-re-ordered)
3349 ;; Search forward for matching end
3350 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
3352 ;; Search forward for matching endcase
3353 (setq reg "\\(\\<randcase\\>\\|\\(\\<unique\\>\\s-+\\|\\<priority\\>\\s-+\\)?\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )
3354 (setq md 3) ;; ender is third item in regexp
3357 ;; might be "disable fork" or "wait fork"
3361 (looking-at verilog-disable-fork-re)
3362 (and (looking-at "fork")
3364 (setq here (point)) ;; sometimes a fork is just a fork
3366 (looking-at verilog-disable-fork-re))))
3367 (progn ;; it is a disable fork; ignore it
3368 (goto-char (match-end 0))
3371 (progn ;; it is a nice simple fork
3372 (goto-char here) ;; return from looking for "disable fork"
3373 ;; Search forward for matching join
3374 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))))
3376 ;; Search forward for matching endclass
3377 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
3380 ;; Search forward for matching endtable
3381 (setq reg "\\<endtable\\>" )
3384 ;; Search forward for matching endspecify
3385 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
3387 ;; Search forward for matching endfunction
3388 (setq reg "\\<endfunction\\>" )
3391 ;; Search forward for matching endfunction
3392 (setq reg "\\<endfunction\\>" )
3395 ;; Search forward for matching endtask
3396 (setq reg "\\<endtask\\>" )
3399 ;; Search forward for matching endtask
3400 (setq reg "\\<endtask\\>" )
3403 ;; Search forward for matching endgenerate
3404 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
3406 ;; Search forward for matching endgroup
3407 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
3409 ;; Search forward for matching endproperty
3410 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
3412 ;; Search forward for matching endsequence
3413 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" )
3414 (setq md 3)) ; 3 to get to endsequence in the reg above
3416 ;; Search forward for matching endclocking
3417 (setq reg "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)" )))
3424 (while (verilog-re-search-forward reg nil 'move)
3426 ((match-end md) ; a closer in regular expression, so we are climbing out
3427 (setq depth (1- depth))
3428 (if (= 0 depth) ; we are out!
3430 ((match-end 1) ; an opener in the r-e, so we are in deeper now
3431 (setq here (point)) ; remember where we started
3432 (goto-char (match-beginning 1))
3435 (looking-at verilog-disable-fork-re)
3436 (and (looking-at "fork")
3439 (looking-at verilog-disable-fork-re))))
3440 (progn ;; it is a disable fork; another false alarm
3441 (goto-char (match-end 0)))
3442 (progn ;; it is a simple fork (or has nothing to do with fork)
3444 (setq depth (1+ depth))))))))))
3445 (if (verilog-re-search-forward reg nil 'move)
3446 (throw 'skip 1))))))
3448 ((looking-at (concat
3449 "\\(\\<\\(macro\\)?module\\>\\)\\|"
3450 "\\(\\<primitive\\>\\)\\|"
3451 "\\(\\<class\\>\\)\\|"
3452 "\\(\\<program\\>\\)\\|"
3453 "\\(\\<interface\\>\\)\\|"
3454 "\\(\\<package\\>\\)"))
3457 (verilog-re-search-forward "\\<endmodule\\>" nil 'move))
3459 (verilog-re-search-forward "\\<endprimitive\\>" nil 'move))
3461 (verilog-re-search-forward "\\<endclass\\>" nil 'move))
3463 (verilog-re-search-forward "\\<endprogram\\>" nil 'move))
3465 (verilog-re-search-forward "\\<endinterface\\>" nil 'move))
3467 (verilog-re-search-forward "\\<endpackage\\>" nil 'move))
3470 (if (= (following-char) ?\) )
3472 (forward-sexp 1)))))
3475 (if (= (following-char) ?\) )
3477 (forward-sexp 1))))))
3479 (defun verilog-declaration-beg ()
3480 (verilog-re-search-backward verilog-declaration-re (bobp) t))
3486 (defvar verilog-which-tool 1)
3488 (define-derived-mode verilog-mode prog-mode "Verilog"
3489 "Major mode for editing Verilog code.
3490 \\<verilog-mode-map>
3491 See \\[describe-function] verilog-auto (\\[verilog-auto]) for details on how
3492 AUTOs can improve coding efficiency.
3494 Use \\[verilog-faq] for a pointer to frequently asked questions.
3496 NEWLINE, TAB indents for Verilog code.
3497 Delete converts tabs to spaces as it moves back.
3499 Supports highlighting.
3501 Turning on Verilog mode calls the value of the variable `verilog-mode-hook'
3502 with no args, if that value is non-nil.
3504 Variables controlling indentation/edit style:
3506 variable `verilog-indent-level' (default 3)
3507 Indentation of Verilog statements with respect to containing block.
3508 `verilog-indent-level-module' (default 3)
3509 Absolute indentation of Module level Verilog statements.
3510 Set to 0 to get initial and always statements lined up
3511 on the left side of your screen.
3512 `verilog-indent-level-declaration' (default 3)
3513 Indentation of declarations with respect to containing block.
3514 Set to 0 to get them list right under containing block.
3515 `verilog-indent-level-behavioral' (default 3)
3516 Indentation of first begin in a task or function block
3517 Set to 0 to get such code to lined up underneath the task or
3519 `verilog-indent-level-directive' (default 1)
3520 Indentation of `ifdef/`endif blocks.
3521 `verilog-cexp-indent' (default 1)
3522 Indentation of Verilog statements broken across lines i.e.:
3525 `verilog-case-indent' (default 2)
3526 Indentation for case statements.
3527 `verilog-auto-newline' (default nil)
3528 Non-nil means automatically newline after semicolons and the punctuation
3530 `verilog-auto-indent-on-newline' (default t)
3531 Non-nil means automatically indent line after newline.
3532 `verilog-tab-always-indent' (default t)
3533 Non-nil means TAB in Verilog mode should always reindent the current line,
3534 regardless of where in the line point is when the TAB command is used.
3535 `verilog-indent-begin-after-if' (default t)
3536 Non-nil means to indent begin statements following a preceding
3537 if, else, while, for and repeat statements, if any. Otherwise,
3538 the begin is lined up with the preceding token. If t, you get:
3540 begin // amount of indent based on `verilog-cexp-indent'
3544 `verilog-auto-endcomments' (default t)
3545 Non-nil means a comment /* ... */ is set after the ends which ends
3546 cases, tasks, functions and modules.
3547 The type and name of the object will be set between the braces.
3548 `verilog-minimum-comment-distance' (default 10)
3549 Minimum distance (in lines) between begin and end required before a comment
3550 will be inserted. Setting this variable to zero results in every
3551 end acquiring a comment; the default avoids too many redundant
3552 comments in tight quarters.
3553 `verilog-auto-lineup' (default 'declarations)
3554 List of contexts where auto lineup of code should be done.
3556 Variables controlling other actions:
3558 `verilog-linter' (default surelint)
3559 Unix program to call to run the lint checker. This is the default
3560 command for \\[compile-command] and \\[verilog-auto-save-compile].
3562 See \\[customize] for the complete list of variables.
3564 AUTO expansion functions are, in part:
3566 \\[verilog-auto] Expand AUTO statements.
3567 \\[verilog-delete-auto] Remove the AUTOs.
3568 \\[verilog-inject-auto] Insert AUTOs for the first time.
3570 Some other functions are:
3572 \\[verilog-complete-word] Complete word with appropriate possibilities.
3573 \\[verilog-mark-defun] Mark function.
3574 \\[verilog-beg-of-defun] Move to beginning of current function.
3575 \\[verilog-end-of-defun] Move to end of current function.
3576 \\[verilog-label-be] Label matching begin ... end, fork ... join, etc statements.
3578 \\[verilog-comment-region] Put marked area in a comment.
3579 \\[verilog-uncomment-region] Uncomment an area commented with \\[verilog-comment-region].
3580 \\[verilog-insert-block] Insert begin ... end.
3581 \\[verilog-star-comment] Insert /* ... */.
3583 \\[verilog-sk-always] Insert an always @(AS) begin .. end block.
3584 \\[verilog-sk-begin] Insert a begin .. end block.
3585 \\[verilog-sk-case] Insert a case block, prompting for details.
3586 \\[verilog-sk-for] Insert a for (...) begin .. end block, prompting for details.
3587 \\[verilog-sk-generate] Insert a generate .. endgenerate block.
3588 \\[verilog-sk-header] Insert a header block at the top of file.
3589 \\[verilog-sk-initial] Insert an initial begin .. end block.
3590 \\[verilog-sk-fork] Insert a fork begin .. end .. join block.
3591 \\[verilog-sk-module] Insert a module .. (/*AUTOARG*/);.. endmodule block.
3592 \\[verilog-sk-ovm-class] Insert an OVM Class block.
3593 \\[verilog-sk-uvm-class] Insert an UVM Class block.
3594 \\[verilog-sk-primitive] Insert a primitive .. (.. );.. endprimitive block.
3595 \\[verilog-sk-repeat] Insert a repeat (..) begin .. end block.
3596 \\[verilog-sk-specify] Insert a specify .. endspecify block.
3597 \\[verilog-sk-task] Insert a task .. begin .. end endtask block.
3598 \\[verilog-sk-while] Insert a while (...) begin .. end block, prompting for details.
3599 \\[verilog-sk-casex] Insert a casex (...) item: begin.. end endcase block, prompting for details.
3600 \\[verilog-sk-casez] Insert a casez (...) item: begin.. end endcase block, prompting for details.
3601 \\[verilog-sk-if] Insert an if (..) begin .. end block.
3602 \\[verilog-sk-else-if] Insert an else if (..) begin .. end block.
3603 \\[verilog-sk-comment] Insert a comment block.
3604 \\[verilog-sk-assign] Insert an assign .. = ..; statement.
3605 \\[verilog-sk-function] Insert a function .. begin .. end endfunction block.
3606 \\[verilog-sk-input] Insert an input declaration, prompting for details.
3607 \\[verilog-sk-output] Insert an output declaration, prompting for details.
3608 \\[verilog-sk-state-machine] Insert a state machine definition, prompting for details.
3609 \\[verilog-sk-inout] Insert an inout declaration, prompting for details.
3610 \\[verilog-sk-wire] Insert a wire declaration, prompting for details.
3611 \\[verilog-sk-reg] Insert a register declaration, prompting for details.
3612 \\[verilog-sk-define-signal] Define signal under point as a register at the top of the module.
3614 All key bindings can be seen in a Verilog-buffer with \\[describe-bindings].
3615 Key bindings specific to `verilog-mode-map' are:
3617 \\{verilog-mode-map}"
3618 :abbrev-table verilog-mode-abbrev-table
3619 (set (make-local-variable 'beginning-of-defun-function)
3620 'verilog-beg-of-defun)
3621 (set (make-local-variable 'end-of-defun-function)
3622 'verilog-end-of-defun)
3623 (set-syntax-table verilog-mode-syntax-table)
3624 (set (make-local-variable 'indent-line-function)
3625 #'verilog-indent-line-relative)
3626 (setq comment-indent-function 'verilog-comment-indent)
3627 (set (make-local-variable 'parse-sexp-ignore-comments) nil)
3628 (set (make-local-variable 'comment-start) "// ")
3629 (set (make-local-variable 'comment-end) "")
3630 (set (make-local-variable 'comment-start-skip) "/\\*+ *\\|// *")
3631 (set (make-local-variable 'comment-multi-line) nil)
3632 ;; Set up for compilation
3633 (setq verilog-which-tool 1)
3634 (setq verilog-tool 'verilog-linter)
3635 (verilog-set-compile-command)
3636 (when (boundp 'hack-local-variables-hook) ;; Also modify any file-local-variables
3637 (add-hook 'hack-local-variables-hook 'verilog-modify-compile-command t))
3640 (when (featurep 'xemacs)
3641 (easy-menu-add verilog-stmt-menu)
3642 (easy-menu-add verilog-menu)
3643 (setq mode-popup-menu (cons "Verilog Mode" verilog-stmt-menu)))
3645 ;; Stuff for GNU Emacs
3646 (set (make-local-variable 'font-lock-defaults)
3647 `((verilog-font-lock-keywords
3648 verilog-font-lock-keywords-1
3649 verilog-font-lock-keywords-2
3650 verilog-font-lock-keywords-3)
3652 ,(if (functionp 'syntax-ppss)
3653 ;; verilog-beg-of-defun uses syntax-ppss, and syntax-ppss uses
3654 ;; font-lock-beginning-of-syntax-function, so
3655 ;; font-lock-beginning-of-syntax-function, can't use
3656 ;; verilog-beg-of-defun.
3658 'verilog-beg-of-defun)))
3659 ;;------------------------------------------------------------
3660 ;; now hook in 'verilog-highlight-include-files (eldo-mode.el&spice-mode.el)
3661 ;; all buffer local:
3662 (unless noninteractive ;; Else can't see the result, and change hooks are slow
3663 (when (featurep 'xemacs)
3664 (make-local-hook 'font-lock-mode-hook)
3665 (make-local-hook 'font-lock-after-fontify-buffer-hook); doesn't exist in Emacs
3666 (make-local-hook 'after-change-functions))
3667 (add-hook 'font-lock-mode-hook 'verilog-highlight-buffer t t)
3668 (add-hook 'font-lock-after-fontify-buffer-hook 'verilog-highlight-buffer t t) ; not in Emacs
3669 (add-hook 'after-change-functions 'verilog-highlight-region t t))
3671 ;; Tell imenu how to handle Verilog.
3672 (set (make-local-variable 'imenu-generic-expression)
3673 verilog-imenu-generic-expression)
3674 ;; Tell which-func-modes that imenu knows about verilog
3675 (when (and (boundp 'which-func-modes) (listp which-func-modes))
3676 (add-to-list 'which-func-modes 'verilog-mode))
3678 (when (boundp 'hs-special-modes-alist)
3679 (unless (assq 'verilog-mode hs-special-modes-alist)
3680 (setq hs-special-modes-alist
3681 (cons '(verilog-mode-mode "\\<begin\\>" "\\<end\\>" nil
3682 verilog-forward-sexp-function)
3683 hs-special-modes-alist))))
3686 (add-hook 'write-contents-hooks 'verilog-auto-save-check nil 'local)
3687 ;; verilog-mode-hook call added by define-derived-mode
3692 ;; Electric functions
3694 (defun electric-verilog-terminate-line (&optional arg)
3695 "Terminate line and indent next line.
3696 With optional ARG, remove existing end of line comments."
3698 ;; before that see if we are in a comment
3699 (let ((state (save-excursion (verilog-syntax-ppss))))
3701 ((nth 7 state) ; Inside // comment
3704 (delete-horizontal-space)
3709 (beginning-of-line)))
3710 (verilog-indent-line))
3711 ((nth 4 state) ; Inside any comment (hence /**/)
3713 (verilog-more-comment))
3715 ;; First, check if current line should be indented
3717 (delete-horizontal-space)
3719 (skip-chars-forward " \t")
3720 (if (looking-at verilog-auto-end-comment-lines-re)
3721 (let ((indent-str (verilog-indent-line)))
3722 ;; Maybe we should set some endcomments
3723 (if verilog-auto-endcomments
3724 (verilog-set-auto-endcomments indent-str arg))
3726 (delete-horizontal-space)
3733 (delete-horizontal-space)
3735 ;; see if we should line up assignments
3737 (if (or (eq 'all verilog-auto-lineup)
3738 (eq 'assignments verilog-auto-lineup))
3739 (verilog-pretty-expr t "\\(<\\|:\\)?=" ))
3743 (if verilog-auto-indent-on-newline
3744 (verilog-indent-line)))
3748 (defun electric-verilog-terminate-and-indent ()
3749 "Insert a newline and indent for the next statement."
3751 (electric-verilog-terminate-line 1))
3753 (defun electric-verilog-semi ()
3754 "Insert `;' character and reindent the line."
3756 (verilog-insert-last-command-event)
3758 (if (or (verilog-in-comment-or-string-p)
3759 (verilog-in-escaped-name-p))
3763 (verilog-forward-ws&directives)
3764 (verilog-indent-line))
3765 (if (and verilog-auto-newline
3766 (not (verilog-parenthesis-depth)))
3767 (electric-verilog-terminate-line))))
3769 (defun electric-verilog-semi-with-comment ()
3770 "Insert `;' character, reindent the line and indent for comment."
3775 (verilog-indent-line))
3776 (indent-for-comment))
3778 (defun electric-verilog-colon ()
3779 "Insert `:' and do all indentations except line indent on this line."
3781 (verilog-insert-last-command-event)
3782 ;; Do nothing if within string.
3784 (verilog-within-string)
3785 (not (verilog-in-case-region-p)))
3789 (lim (progn (verilog-beg-of-statement) (point))))
3791 (verilog-backward-case-item lim)
3792 (verilog-indent-line)))
3793 ;; (let ((verilog-tab-always-indent nil))
3794 ;; (verilog-indent-line))
3797 ;;(defun electric-verilog-equal ()
3798 ;; "Insert `=', and do indentation if within block."
3800 ;; (verilog-insert-last-command-event)
3801 ;; Could auto line up expressions, but not yet
3802 ;; (if (eq (car (verilog-calculate-indent)) 'block)
3803 ;; (let ((verilog-tab-always-indent nil))
3804 ;; (verilog-indent-command)))
3807 (defun electric-verilog-tick ()
3808 "Insert back-tick, and indent to column 0 if this is a CPP directive."
3810 (verilog-insert-last-command-event)
3812 (if (verilog-in-directive-p)
3813 (verilog-indent-line))))
3815 (defun electric-verilog-tab ()
3816 "Function called when TAB is pressed in Verilog mode."
3818 ;; If verilog-tab-always-indent, indent the beginning of the line.
3820 ;; The region is active, indent it.
3821 ((and (region-active-p)
3822 (not (eq (region-beginning) (region-end))))
3823 (indent-region (region-beginning) (region-end) nil))
3824 ((or verilog-tab-always-indent
3826 (skip-chars-backward " \t")
3828 (let* ((oldpnt (point))
3832 (skip-chars-forward " \t")
3833 (verilog-indent-line)
3834 (back-to-indentation)
3836 (if (< (point) boi-point)
3837 (back-to-indentation)
3838 (cond ((not verilog-tab-to-comment))
3842 (indent-for-comment)
3843 (when (and (eolp) (= oldpnt (point)))
3844 ; kill existing comment
3846 (re-search-forward comment-start-skip oldpnt 'move)
3847 (goto-char (match-beginning 0))
3848 (skip-chars-backward " \t")
3849 (kill-region (point) oldpnt)))))))
3850 (t (progn (insert "\t")))))
3855 ;; Interactive functions
3858 (defun verilog-indent-buffer ()
3859 "Indent-region the entire buffer as Verilog code.
3860 To call this from the command line, see \\[verilog-batch-indent]."
3863 (indent-region (point-min) (point-max) nil))
3865 (defun verilog-insert-block ()
3866 "Insert Verilog begin ... end; block in the code with right indentation."
3868 (verilog-indent-line)
3870 (electric-verilog-terminate-line)
3872 (electric-verilog-terminate-line)
3875 (verilog-indent-line)))
3877 (defun verilog-star-comment ()
3878 "Insert Verilog star comment at point."
3880 (verilog-indent-line)
3888 (defun verilog-insert-1 (fmt max)
3889 "Use format string FMT to insert integers 0 to MAX - 1.
3890 Inserts one integer per line, at the current column. Stops early
3891 if it reaches the end of the buffer."
3892 (let ((col (current-column))
3896 (insert (format fmt n))
3898 ;; Note that this function does not bother to check for lines
3899 ;; shorter than col.
3903 (move-to-column col))))))
3905 (defun verilog-insert-indices (max)
3906 "Insert a set of indices into a rectangle.
3907 The upper left corner is defined by point. Indices begin with 0
3908 and extend to the MAX - 1. If no prefix arg is given, the user
3909 is prompted for a value. The indices are surrounded by square
3910 brackets \[]. For example, the following code with the point
3911 located after the first 'a' gives:
3917 a = b ==> insert-indices ==> a[ 4] = b
3923 (interactive "NMAX: ")
3924 (verilog-insert-1 "[%3d]" max))
3926 (defun verilog-generate-numbers (max)
3927 "Insert a set of generated numbers into a rectangle.
3928 The upper left corner is defined by point. The numbers are padded to three
3929 digits, starting with 000 and extending to (MAX - 1). If no prefix argument
3930 is supplied, then the user is prompted for the MAX number. Consider the
3931 following code fragment:
3937 buf buf ==> generate-numbers ==> buf buf004
3943 (interactive "NMAX: ")
3944 (verilog-insert-1 "%3.3d" max))
3946 (defun verilog-mark-defun ()
3947 "Mark the current Verilog function (or procedure).
3948 This puts the mark at the end, and point at the beginning."
3950 (if (featurep 'xemacs)
3953 (verilog-end-of-defun)
3955 (verilog-beg-of-defun)
3956 (if (fboundp 'zmacs-activate-region)
3957 (zmacs-activate-region)))
3960 (defun verilog-comment-region (start end)
3961 ; checkdoc-params: (start end)
3962 "Put the region into a Verilog comment.
3963 The comments that are in this area are \"deformed\":
3964 `*)' becomes `!(*' and `}' becomes `!{'.
3965 These deformed comments are returned to normal if you use
3966 \\[verilog-uncomment-region] to undo the commenting.
3968 The commented area starts with `verilog-exclude-str-start', and ends with
3969 `verilog-exclude-str-end'. But if you change these variables,
3970 \\[verilog-uncomment-region] won't recognize the comments."
3973 ;; Insert start and endcomments
3975 (if (and (save-excursion (skip-chars-forward " \t") (eolp))
3976 (not (save-excursion (skip-chars-backward " \t") (bolp))))
3978 (beginning-of-line))
3979 (insert verilog-exclude-str-end)
3984 (insert verilog-exclude-str-start)
3986 ;; Replace end-comments within commented area
3989 (while (re-search-backward "\\*/" start t)
3990 (replace-match "*-/" t t)))
3992 (let ((s+1 (1+ start)))
3993 (while (re-search-backward "/\\*" s+1 t)
3994 (replace-match "/-*" t t))))))
3996 (defun verilog-uncomment-region ()
3997 "Uncomment a commented area; change deformed comments back to normal.
3998 This command does nothing if the pointer is not in a commented
3999 area. See also `verilog-comment-region'."
4002 (let ((start (point))
4004 ;; Find the boundaries of the comment
4006 (setq start (progn (search-backward verilog-exclude-str-start nil t)
4008 (setq end (progn (search-forward verilog-exclude-str-end nil t)
4010 ;; Check if we're really inside a comment
4011 (if (or (equal start (point)) (<= end (point)))
4012 (message "Not standing within commented area.")
4014 ;; Remove endcomment
4017 (let ((pos (point)))
4019 (delete-region pos (1+ (point))))
4020 ;; Change comments back to normal
4022 (while (re-search-backward "\\*-/" start t)
4023 (replace-match "*/" t t)))
4025 (while (re-search-backward "/-\\*" start t)
4026 (replace-match "/*" t t)))
4027 ;; Remove start comment
4030 (let ((pos (point)))
4032 (delete-region pos (1+ (point)))))))))
4034 (defun verilog-beg-of-defun ()
4035 "Move backward to the beginning of the current function or procedure."
4037 (verilog-re-search-backward verilog-defun-re nil 'move))
4039 (defun verilog-beg-of-defun-quick ()
4040 "Move backward to the beginning of the current function or procedure.
4041 Uses `verilog-scan' cache."
4043 (verilog-re-search-backward-quick verilog-defun-re nil 'move))
4045 (defun verilog-end-of-defun ()
4046 "Move forward to the end of the current function or procedure."
4048 (verilog-re-search-forward verilog-end-defun-re nil 'move))
4050 (defun verilog-get-beg-of-defun (&optional warn)
4052 (cond ((verilog-re-search-forward-quick verilog-defun-re nil t)
4055 (error "%s: Can't find module beginning" (verilog-point-text))
4057 (defun verilog-get-end-of-defun (&optional warn)
4059 (cond ((verilog-re-search-forward-quick verilog-end-defun-re nil t)
4062 (error "%s: Can't find endmodule" (verilog-point-text))
4065 (defun verilog-label-be (&optional arg)
4066 "Label matching begin ... end, fork ... join and case ... endcase statements.
4067 With ARG, first kill any existing labels."
4072 (verilog-beg-of-defun)
4075 (verilog-end-of-defun)
4077 (goto-char (marker-position b))
4079 (message "Relabeling module..."))
4081 (> (marker-position e) (point))
4082 (verilog-re-search-forward
4084 "\\<end\\(\\(function\\)\\|\\(task\\)\\|\\(module\\)\\|\\(primitive\\)\\|\\(interface\\)\\|\\(package\\)\\|\\(case\\)\\)?\\>"
4085 "\\|\\(`endif\\)\\|\\(`else\\)")
4087 (goto-char (match-beginning 0))
4088 (let ((indent-str (verilog-indent-line)))
4089 (verilog-set-auto-endcomments indent-str 't)
4091 (delete-horizontal-space))
4093 (if (= 9 (% cnt 10))
4094 (message "%d..." cnt)))
4099 (message "%d lines auto commented" cnt))))
4101 (defun verilog-beg-of-statement ()
4102 "Move backward to beginning of statement."
4104 ;; Move back token by token until we see the end
4105 ;; of some earlier line.
4108 ;; If the current point does not begin a new
4109 ;; statement, as in the character ahead of us is a ';', or SOF
4110 ;; or the string after us unambiguously starts a statement,
4111 ;; or the token before us unambiguously ends a statement,
4112 ;; then move back a token and test again.
4114 ;; stop if beginning of buffer
4116 ;; stop if we find a ;
4117 (= (preceding-char) ?\;)
4118 ;; stop if we see a named coverpoint
4119 (looking-at "\\w+\\W*:\\W*\\(coverpoint\\|cross\\|constraint\\)")
4120 ;; keep going if we are in the middle of a word
4121 (not (or (looking-at "\\<") (forward-word -1)))
4122 ;; stop if we see an assertion (perhaps labeled)
4124 (looking-at "\\(\\<\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(\\<assert\\>\\)")
4128 (verilog-backward-token)
4129 (if (looking-at verilog-label-re)
4132 ;; stop if we see an extended complete reg, perhaps a complete one
4134 (looking-at verilog-complete-reg)
4136 (while (and (looking-at verilog-extended-complete-re)
4137 (progn (setq p (point))
4138 (verilog-backward-token)
4141 ;; stop if we see a complete reg (previous found extended ones)
4142 (looking-at verilog-basic-complete-re)
4143 ;; stop if previous token is an ender
4145 (verilog-backward-token)
4147 (looking-at verilog-end-block-re)
4148 (looking-at verilog-preprocessor-re))))) ;; end of test
4149 (verilog-backward-syntactic-ws)
4150 (verilog-backward-token))
4151 ;; Now point is where the previous line ended.
4152 (verilog-forward-syntactic-ws)))
4154 (defun verilog-beg-of-statement-1 ()
4155 "Move backward to beginning of statement."
4157 (if (verilog-in-comment-p)
4158 (verilog-backward-syntactic-ws))
4161 (while (not (looking-at verilog-complete-reg))
4163 (verilog-backward-syntactic-ws)
4165 (= (preceding-char) ?\;)
4167 (verilog-backward-token)
4168 (looking-at verilog-ends-re)))
4172 (verilog-backward-token))))
4173 (verilog-forward-syntactic-ws)))
4176 ; (not (looking-at verilog-complete-reg))
4178 ; (not (= (preceding-char) ?\;)))
4179 ; (verilog-backward-token)
4180 ; (verilog-backward-syntactic-ws)
4181 ; (setq pt (point)))
4183 ; ;(verilog-forward-syntactic-ws)
4185 (defun verilog-end-of-statement ()
4186 "Move forward to end of current statement."
4190 ((verilog-in-directive-p)
4194 ((looking-at verilog-beg-block-re)
4195 (verilog-forward-sexp))
4197 ((equal (char-after) ?\})
4200 ;; Skip to end of statement
4201 ((condition-case nil
4206 (verilog-skip-forward-comment-or-string)
4209 (cond ((looking-at "[ \t]*;")
4210 (skip-chars-forward "^;")
4212 (throw 'found (point)))
4215 (looking-at verilog-beg-block-re))
4216 (goto-char (match-beginning 0))
4218 ((looking-at "[ \t]*)")
4219 (throw 'found (point)))
4221 (throw 'found (point)))
4227 ;; Skip a whole block
4230 (verilog-re-search-forward verilog-end-statement-re nil 'move)
4231 (setq nest (if (match-end 1)
4235 (throw 'found (point)))
4237 (throw 'found (verilog-end-of-statement))))))
4240 (defun verilog-in-case-region-p ()
4241 "Return true if in a case region.
4242 More specifically, point @ in the line foo : @ begin"
4246 (progn (verilog-forward-syntactic-ws)
4247 (looking-at "\\<begin\\>"))
4248 (progn (verilog-backward-syntactic-ws)
4249 (= (preceding-char) ?\:)))
4253 (verilog-re-search-backward
4254 (concat "\\(\\<module\\>\\)\\|\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|"
4255 "\\(\\<endcase\\>\\)\\>")
4259 (setq nest (1+ nest)))
4263 (setq nest (1- nest)))
4265 (throw 'found (= nest 0)))))))
4268 (defun verilog-backward-up-list (arg)
4269 "Call `backward-up-list' ARG, ignoring comments."
4270 (let ((parse-sexp-ignore-comments t))
4271 (backward-up-list arg)))
4273 (defun verilog-forward-sexp-cmt (arg)
4274 "Call `forward-sexp' ARG, inside comments."
4275 (let ((parse-sexp-ignore-comments nil))
4276 (forward-sexp arg)))
4278 (defun verilog-forward-sexp-ign-cmt (arg)
4279 "Call `forward-sexp' ARG, ignoring comments."
4280 (let ((parse-sexp-ignore-comments t))
4281 (forward-sexp arg)))
4283 (defun verilog-in-generate-region-p ()
4284 "Return true if in a generate region.
4285 More specifically, after a generate and before an endgenerate."
4292 (verilog-re-search-backward
4293 "\\<\\(module\\)\\|\\(generate\\)\\|\\(endgenerate\\)\\>" nil 'move)
4295 ((match-end 1) ; module - we have crawled out
4297 ((match-end 2) ; generate
4298 (setq nest (1- nest)))
4299 ((match-end 3) ; endgenerate
4300 (setq nest (1+ nest))))))))
4301 (= nest 0) )) ; return nest
4303 (defun verilog-in-fork-region-p ()
4304 "Return true if between a fork and join."
4306 (let ((lim (save-excursion (verilog-beg-of-defun) (point)))
4311 (verilog-re-search-backward "\\<\\(fork\\)\\|\\(join\\(_any\\|_none\\)?\\)\\>" lim 'move)
4313 ((match-end 1) ; fork
4314 (setq nest (1- nest)))
4315 ((match-end 2) ; join
4316 (setq nest (1+ nest)))))))
4317 (= nest 0) )) ; return nest
4319 (defun verilog-backward-case-item (lim)
4320 "Skip backward to nearest enclosing case item.
4321 Limit search to point LIM."
4327 (verilog-re-search-backward verilog-endcomment-reason-re
4330 ;; Try to find the real :
4331 (if (save-excursion (search-backward ":" lim1 t))
4337 (verilog-re-search-backward "\\(\\[\\)\\|\\(\\]\\)\\|\\(:\\)"
4341 (setq colon (1+ colon))
4343 (error "%s: unbalanced [" (verilog-point-text))))
4345 (setq colon (1- colon)))
4348 (setq colon (1+ colon)))))
4349 ;; Skip back to beginning of case item
4350 (skip-chars-backward "\t ")
4351 (verilog-skip-backward-comment-or-string)
4356 (verilog-re-search-backward
4357 "\\<\\(case[zx]?\\)\\>\\|;\\|\\<end\\>" nil 'move)
4361 (goto-char (match-end 1))
4362 (verilog-forward-ws&directives)
4363 (if (looking-at "(")
4366 (verilog-forward-ws&directives)))
4369 (goto-char (match-end 0))
4370 (verilog-forward-ws&directives)
4372 (error "Malformed case item"))))
4373 (setq str (buffer-substring b e))
4377 "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
4378 (setq str (concat (substring str 0 e) "...")))
4387 (defun verilog-kill-existing-comment ()
4388 "Kill auto comment on this line."
4396 (search-forward "//" e t))))
4398 (delete-region (- b 2) e)))))
4400 (defconst verilog-directive-nest-re
4401 (concat "\\(`else\\>\\)\\|"
4402 "\\(`endif\\>\\)\\|"
4404 "\\(`ifdef\\>\\)\\|"
4405 "\\(`ifndef\\>\\)\\|"
4407 (defun verilog-set-auto-endcomments (indent-str kill-existing-comment)
4408 "Add ending comment with given INDENT-STR.
4409 With KILL-EXISTING-COMMENT, remove what was there before.
4410 Insert `// case: 7 ' or `// NAME ' on this line if appropriate.
4411 Insert `// case expr ' if this line ends a case block.
4412 Insert `// ifdef FOO ' if this line ends code conditional on FOO.
4413 Insert `// NAME ' if this line ends a function, task, module,
4414 primitive or interface named NAME."
4417 (; Comment close preprocessor directives
4419 (looking-at "\\(`endif\\)\\|\\(`else\\)")
4420 (or kill-existing-comment
4421 (not (save-excursion
4423 (search-backward "//" (point-at-bol) t)))))
4426 (else (if (match-end 2) "!" " ")))
4428 (if kill-existing-comment
4429 (verilog-kill-existing-comment))
4430 (delete-horizontal-space)
4433 (while (and (/= nest 0)
4434 (verilog-re-search-backward verilog-directive-nest-re nil 'move))
4436 ((match-end 1) ; `else
4439 ((match-end 2) ; `endif
4440 (setq nest (1+ nest)))
4441 ((match-end 3) ; `if
4442 (setq nest (1- nest)))
4443 ((match-end 4) ; `ifdef
4444 (setq nest (1- nest)))
4445 ((match-end 5) ; `ifndef
4446 (setq nest (1- nest)))
4447 ((match-end 6) ; `elsif
4458 (skip-chars-forward "^ \t")
4459 (verilog-forward-syntactic-ws)
4462 (skip-chars-forward "a-zA-Z0-9_")
4465 (if (> (count-lines (point) b) verilog-minimum-comment-distance)
4466 (insert (concat " // " else m " " (buffer-substring b e))))
4468 (insert " // unmatched `else, `elsif or `endif")
4471 (; Comment close case/class/function/task/module and named block
4472 (and (looking-at "\\<end")
4473 (or kill-existing-comment
4474 (not (save-excursion
4476 (search-backward "//" (point-at-bol) t)))))
4477 (let ((type (car indent-str)))
4478 (unless (eq type 'declaration)
4479 (unless (looking-at (concat "\\(" verilog-end-block-ordered-re "\\)[ \t]*:")) ;; ignore named ends
4480 (if (looking-at verilog-end-block-ordered-re)
4482 (;- This is a case block; search back for the start of this case
4483 (match-end 1) ;; of verilog-end-block-ordered-re
4486 (str "UNMATCHED!!"))
4488 (verilog-leap-to-head)
4490 ((looking-at "\\<randcase\\>")
4491 (setq str "randcase")
4493 ((looking-at "\\(\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
4494 (goto-char (match-end 0))
4495 (setq str (concat (match-string 0) " " (verilog-get-expr)))
4499 (if kill-existing-comment
4500 (verilog-kill-existing-comment))
4501 (delete-horizontal-space)
4502 (insert (concat " // " str ))
4503 (if err (ding 't))))
4505 (;- This is a begin..end block
4506 (match-end 2) ;; of verilog-end-block-ordered-re
4507 (let ((str " // UNMATCHED !!")
4513 (verilog-leap-to-head)
4514 (setq there (point))
4515 (if (not (match-end 0))
4519 (if kill-existing-comment
4520 (verilog-kill-existing-comment))
4521 (delete-horizontal-space)
4525 (save-excursion (verilog-beg-of-defun) (point)))
4528 (;-- handle named block differently
4529 (looking-at verilog-named-block-re)
4530 (search-forward ":")
4531 (setq there (point))
4532 (setq str (verilog-get-expr))
4534 (setq str (concat " // block: " str )))
4536 ((verilog-in-case-region-p) ;-- handle case item differently
4538 (setq str (verilog-backward-case-item lim))
4539 (setq there (point))
4541 (setq str (concat " // case: " str )))
4543 (;- try to find "reason" for this begin
4547 ;; (verilog-backward-token)
4548 (verilog-beg-of-statement)
4552 ((looking-at verilog-endcomment-reason-re)
4553 (setq there (match-end 0))
4554 (setq cntx (concat (match-string 0) " "))
4560 (if (and (verilog-continued-line)
4561 (looking-at "\\<repeat\\>\\|\\<wait\\>\\|\\<always\\>"))
4563 (goto-char (match-end 0))
4564 (setq there (point))
4566 (concat " // " (match-string 0) " " (verilog-get-expr))))
4572 ( reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)\\|\\(assert\\)"))
4574 (while (verilog-re-search-backward reg nil 'move)
4576 ((match-end 1) ; begin
4577 (setq nest (1- nest)))
4578 ((match-end 2) ; end
4579 (setq nest (1+ nest)))
4583 (goto-char (match-end 0))
4584 (setq there (point))
4586 (setq str (verilog-get-expr))
4587 (setq str (concat " // else: !if" str ))
4592 (goto-char (match-end 0))
4593 (setq there (point))
4595 (setq str (verilog-get-expr))
4596 (setq str (concat " // else: !assert " str ))
4597 (throw 'skip 1)))))))))
4602 (reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)\\|\\(assert\\)"))
4604 (while (verilog-re-search-backward reg nil 'move)
4606 ((match-end 1) ; begin
4607 (setq nest (1- nest)))
4608 ((match-end 2) ; end
4609 (setq nest (1+ nest)))
4613 (goto-char (match-end 0))
4614 (setq there (point))
4616 (setq str (verilog-get-expr))
4617 (setq str (concat " // else: !if" str ))
4622 (goto-char (match-end 0))
4623 (setq there (point))
4625 (setq str (verilog-get-expr))
4626 (setq str (concat " // else: !assert " str ))
4627 (throw 'skip 1)))))))))
4629 (; always_comb, always_ff, always_latch
4630 (or (match-end 4) (match-end 5) (match-end 6))
4631 (goto-char (match-end 0))
4632 (setq there (point))
4634 (setq str (concat " // " cntx )))
4636 (;- task/function/initial et cetera
4639 (goto-char (match-end 0))
4640 (setq there (point))
4642 (setq str (concat " // " cntx (verilog-get-expr))))
4645 (setq str " // auto-endcomment confused "))))
4648 (verilog-in-case-region-p) ;-- handle case item differently
4650 (setq there (point))
4652 (setq str (verilog-backward-case-item lim))))
4654 (setq str (concat " // case: " str )))
4656 ((verilog-in-fork-region-p)
4658 (setq str " // fork branch" ))
4660 ((looking-at "\\<end\\>")
4663 (verilog-forward-syntactic-ws)
4665 (setq str (verilog-get-expr))
4666 (setq str (concat " // " cntx str )))
4671 (if kill-existing-comment
4672 (verilog-kill-existing-comment))
4673 (delete-horizontal-space)
4675 (> (count-lines here there) verilog-minimum-comment-distance))
4679 (;- this is endclass, which can be nested
4680 (match-end 11) ;; of verilog-end-block-ordered-re
4683 (reg "\\<\\(class\\)\\|\\(endclass\\)\\|\\(package\\|primitive\\|\\(macro\\)?module\\)\\>")
4687 (while (verilog-re-search-backward reg nil 'move)
4689 ((match-end 3) ; endclass
4691 (setq string "unmatched endclass")
4694 ((match-end 2) ; endclass
4695 (setq nest (1+ nest)))
4697 ((match-end 1) ; class
4698 (setq nest (1- nest))
4701 (goto-char (match-end 0))
4704 (skip-chars-forward "^ \t")
4705 (verilog-forward-ws&directives)
4708 (skip-chars-forward "a-zA-Z0-9_")
4710 (setq string (buffer-substring b e)))
4714 (insert (concat " // " string ))))
4716 (;- this is end{function,generate,task,module,primitive,table,generate}
4717 ;- which can not be nested.
4719 (let (string reg (name-re nil))
4721 (if kill-existing-comment
4723 (verilog-kill-existing-comment)))
4724 (delete-horizontal-space)
4727 ((match-end 5) ;; of verilog-end-block-ordered-re
4728 (setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
4729 (setq name-re "\\w+\\s-*("))
4730 ((match-end 6) ;; of verilog-end-block-ordered-re
4731 (setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
4732 (setq name-re "\\w+\\s-*("))
4733 ((match-end 7) ;; of verilog-end-block-ordered-re
4734 (setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\<endmodule\\>"))
4735 ((match-end 8) ;; of verilog-end-block-ordered-re
4736 (setq reg "\\(\\<primitive\\>\\)\\|\\(\\<\\(endprimitive\\|package\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4737 ((match-end 9) ;; of verilog-end-block-ordered-re
4738 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<\\(endinterface\\|package\\|primitive\\|\\(macro\\)?module\\)\\>\\)"))
4739 ((match-end 10) ;; of verilog-end-block-ordered-re
4740 (setq reg "\\(\\<package\\>\\)\\|\\(\\<\\(endpackage\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4741 ((match-end 11) ;; of verilog-end-block-ordered-re
4742 (setq reg "\\(\\<class\\>\\)\\|\\(\\<\\(endclass\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4743 ((match-end 12) ;; of verilog-end-block-ordered-re
4744 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<\\(endcovergroup\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4745 ((match-end 13) ;; of verilog-end-block-ordered-re
4746 (setq reg "\\(\\<program\\>\\)\\|\\(\\<\\(endprogram\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4747 ((match-end 14) ;; of verilog-end-block-ordered-re
4748 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<\\(endsequence\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4749 ((match-end 15) ;; of verilog-end-block-ordered-re
4750 (setq reg "\\(\\<clocking\\>\\)\\|\\<endclocking\\>"))
4752 (t (error "Problem in verilog-set-auto-endcomments")))
4755 (verilog-re-search-backward reg nil 'move)
4759 (skip-chars-forward "^ \t")
4760 (verilog-forward-ws&directives)
4761 (if (looking-at "static\\|automatic")
4763 (goto-char (match-end 0))
4764 (verilog-forward-ws&directives)))
4765 (if (and name-re (verilog-re-search-forward name-re nil 'move))
4767 (goto-char (match-beginning 0))
4768 (verilog-forward-ws&directives)))
4771 (skip-chars-forward "a-zA-Z0-9_")
4773 (setq string (buffer-substring b e)))
4776 (setq string "unmatched end(function|task|module|primitive|interface|package|class|clocking)")))))
4778 (insert (concat " // " string )))
4781 (defun verilog-get-expr()
4782 "Grab expression at point, e.g., case ( a | b & (c ^d))."
4784 (verilog-forward-syntactic-ws)
4785 (skip-chars-forward " \t")
4791 (verilog-forward-syntactic-ws)
4792 (if (looking-at "(")
4795 (while (and (/= par 0)
4796 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
4799 (setq par (1+ par)))
4801 (setq par (1- par)))))))
4805 (while (and (/= par 0)
4806 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
4809 (setq par (1+ par)))
4811 (setq par (1- par)))))
4815 (while (and (/= par 0)
4816 (verilog-re-search-forward "\\(\\[\\)\\|\\(\\]\\)" nil 'move))
4819 (setq par (1+ par)))
4821 (setq par (1- par)))))
4822 (verilog-forward-syntactic-ws)
4823 (skip-chars-forward "^ \t\n\f")
4825 ((looking-at "/[/\\*]")
4828 (skip-chars-forward "^: \t\n\f")
4830 (str (buffer-substring b e)))
4831 (if (setq e (string-match "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
4832 (setq str (concat (substring str 0 e) "...")))
4835 (defun verilog-expand-vector ()
4836 "Take a signal vector on the current line and expand it to multiple lines.
4837 Useful for creating tri's and other expanded fields."
4839 (verilog-expand-vector-internal "[" "]"))
4841 (defun verilog-expand-vector-internal (bra ket)
4842 "Given BRA, the start brace and KET, the end brace, expand one line into many lines."
4845 (let ((signal-string (buffer-substring (point)
4847 (end-of-line) (point)))))
4851 "\\([0-9]*\\)\\(:[0-9]*\\|\\)\\(::[0-9---]*\\|\\)"
4853 "\\(.*\\)$") signal-string)
4854 (let* ((sig-head (match-string 1 signal-string))
4855 (vec-start (string-to-number (match-string 2 signal-string)))
4856 (vec-end (if (= (match-beginning 3) (match-end 3))
4859 (substring signal-string (1+ (match-beginning 3))
4862 (if (= (match-beginning 4) (match-end 4))
4865 (substring signal-string (+ 2 (match-beginning 4))
4867 (sig-tail (match-string 5 signal-string))
4872 (let ((tmp vec-start))
4873 (setq vec-start vec-end
4875 vec-range (- vec-range))))
4876 (if (< vec-end vec-start)
4877 (while (<= vec-end vec-start)
4878 (setq vec (append vec (list vec-start)))
4879 (setq vec-start (- vec-start vec-range)))
4880 (while (<= vec-start vec-end)
4881 (setq vec (append vec (list vec-start)))
4882 (setq vec-start (+ vec-start vec-range))))
4884 ;; Delete current line
4885 (delete-region (point) (progn (forward-line 0) (point)))
4889 (insert (concat sig-head bra
4890 (int-to-string (car vec)) ket sig-tail "\n"))
4891 (setq vec (cdr vec)))
4896 (defun verilog-strip-comments ()
4897 "Strip all comments from the Verilog code."
4899 (goto-char (point-min))
4900 (while (re-search-forward "//" nil t)
4901 (if (verilog-within-string)
4902 (re-search-forward "\"" nil t)
4903 (if (verilog-in-star-comment-p)
4904 (re-search-forward "\*/" nil t)
4905 (let ((bpt (- (point) 2)))
4907 (delete-region bpt (point))))))
4909 (goto-char (point-min))
4910 (while (re-search-forward "/\\*" nil t)
4911 (if (verilog-within-string)
4912 (re-search-forward "\"" nil t)
4913 (let ((bpt (- (point) 2)))
4914 (re-search-forward "\\*/")
4915 (delete-region bpt (point))))))
4917 (defun verilog-one-line ()
4918 "Convert structural Verilog instances to occupy one line."
4920 (goto-char (point-min))
4921 (while (re-search-forward "\\([^;]\\)[ \t]*\n[ \t]*" nil t)
4922 (replace-match "\\1 " nil nil)))
4924 (defun verilog-linter-name ()
4925 "Return name of linter, either surelint or verilint."
4926 (let ((compile-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
4928 (lint-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
4930 (cond ((equal compile-word1 "surelint") `surelint)
4931 ((equal compile-word1 "verilint") `verilint)
4932 ((equal lint-word1 "surelint") `surelint)
4933 ((equal lint-word1 "verilint") `verilint)
4934 (t `surelint)))) ;; back compatibility
4936 (defun verilog-lint-off ()
4937 "Convert a Verilog linter warning line into a disable statement.
4939 pci_bfm_null.v, line 46: Unused input: pci_rst_
4940 becomes a comment for the appropriate tool.
4942 The first word of the `compile-command' or `verilog-linter'
4943 variables is used to determine which product is being used.
4945 See \\[verilog-surelint-off] and \\[verilog-verilint-off]."
4947 (let ((linter (verilog-linter-name)))
4948 (cond ((equal linter `surelint)
4949 (verilog-surelint-off))
4950 ((equal linter `verilint)
4951 (verilog-verilint-off))
4952 (t (error "Linter name not set")))))
4954 (defvar compilation-last-buffer)
4955 (defvar next-error-last-buffer)
4957 (defun verilog-surelint-off ()
4958 "Convert a SureLint warning line into a disable statement.
4959 Run from Verilog source window; assumes there is a *compile* buffer
4960 with point set appropriately.
4963 WARNING [STD-UDDONX]: xx.v, line 8: output out is never assigned.
4965 // surefire lint_line_off UDDONX"
4967 (let ((buff (if (boundp 'next-error-last-buffer)
4968 next-error-last-buffer
4969 compilation-last-buffer)))
4970 (when (buffer-live-p buff)
4972 (switch-to-buffer buff)
4975 (looking-at "\\(INFO\\|WARNING\\|ERROR\\) \\[[^-]+-\\([^]]+\\)\\]: \\([^,]+\\), line \\([0-9]+\\): \\(.*\\)$")
4976 (let* ((code (match-string 2))
4977 (file (match-string 3))
4978 (line (match-string 4))
4979 (buffer (get-file-buffer file))
4984 (and (file-exists-p file)
4985 (find-file-noselect file)))
4987 (let* ((pop-up-windows t))
4988 (let ((name (expand-file-name
4990 (format "Find this error in: (default %s) "
4993 (if (file-directory-p name)
4994 (setq name (expand-file-name filename name)))
4996 (and (file-exists-p name)
4997 (find-file-noselect name))))))))
4998 (switch-to-buffer buffer)
4999 (goto-char (point-min))
5000 (forward-line (- (string-to-number line)))
5004 ((verilog-in-slash-comment-p)
5005 (re-search-backward "//")
5007 ((looking-at "// surefire lint_off_line ")
5008 (goto-char (match-end 0))
5009 (let ((lim (point-at-eol)))
5010 (if (re-search-forward code lim 'move)
5012 (insert (concat " " code)))))
5015 ((verilog-in-star-comment-p)
5016 (re-search-backward "/\*")
5017 (insert (format " // surefire lint_off_line %6s" code )))
5019 (insert (format " // surefire lint_off_line %6s" code ))
5022 (defun verilog-verilint-off ()
5023 "Convert a Verilint warning line into a disable statement.
5026 (W240) pci_bfm_null.v, line 46: Unused input: pci_rst_
5028 //Verilint 240 off // WARNING: Unused input"
5032 (when (looking-at "\\(.*\\)([WE]\\([0-9A-Z]+\\)).*,\\s +line\\s +[0-9]+:\\s +\\([^:\n]+\\):?.*$")
5033 (replace-match (format
5034 ;; %3s makes numbers 1-999 line up nicely
5035 "\\1//Verilint %3s off // WARNING: \\3"
5038 (verilog-indent-line))))
5040 (defun verilog-auto-save-compile ()
5041 "Update automatics with \\[verilog-auto], save the buffer, and compile."
5043 (verilog-auto) ; Always do it for safety
5045 (compile compile-command))
5047 (defun verilog-preprocess (&optional command filename)
5048 "Preprocess the buffer, similar to `compile', but put output in Verilog-Mode.
5049 Takes optional COMMAND or defaults to `verilog-preprocessor', and
5050 FILENAME to find directory to run in, or defaults to `buffer-file-name`."
5053 (let ((default (verilog-expand-command verilog-preprocessor)))
5054 (set (make-local-variable `verilog-preprocessor)
5055 (read-from-minibuffer "Run Preprocessor (like this): "
5057 'verilog-preprocess-history default)))))
5058 (unless command (setq command (verilog-expand-command verilog-preprocessor)))
5059 (let* ((fontlocked (and (boundp 'font-lock-mode) font-lock-mode))
5060 (dir (file-name-directory (or filename buffer-file-name)))
5061 (cmd (concat "cd " dir "; " command)))
5062 (with-output-to-temp-buffer "*Verilog-Preprocessed*"
5063 (with-current-buffer (get-buffer "*Verilog-Preprocessed*")
5064 (insert (concat "// " cmd "\n"))
5065 (call-process shell-file-name nil t nil shell-command-switch cmd)
5067 ;; Without this force, it takes a few idle seconds
5068 ;; to get the color, which is very jarring
5069 (when fontlocked (font-lock-fontify-buffer))))))
5076 (defun verilog-warn (string &rest args)
5077 "Print a warning with `format' using STRING and optional ARGS."
5078 (apply 'message (concat "%%Warning: " string) args))
5080 (defun verilog-warn-error (string &rest args)
5081 "Call `error' using STRING and optional ARGS.
5082 If `verilog-warn-fatal' is non-nil, call `verilog-warn' instead."
5083 (if verilog-warn-fatal
5084 (apply 'error string args)
5085 (apply 'verilog-warn string args)))
5087 (defmacro verilog-batch-error-wrapper (&rest body)
5088 "Execute BODY and add error prefix to any errors found.
5089 This lets programs calling batch mode to easily extract error messages."
5090 `(let ((verilog-warn-fatal nil))
5094 (error "%%Error: %s%s" (error-message-string err)
5095 (if (featurep 'xemacs) "\n" "")))))) ;; XEmacs forgets to add a newline
5097 (defun verilog-batch-execute-func (funref &optional no-save)
5098 "Internal processing of a batch command.
5099 Runs FUNREF on all command arguments.
5100 Save the result unless optional NO-SAVE is t."
5101 (verilog-batch-error-wrapper
5102 ;; Setting global variables like that is *VERY NASTY* !!! --Stef
5103 ;; However, this function is called only when Emacs is being used as
5104 ;; a standalone language instead of as an editor, so we'll live.
5106 ;; General globals needed
5107 (setq make-backup-files nil)
5108 (setq-default make-backup-files nil)
5109 (setq enable-local-variables t)
5110 (setq enable-local-eval t)
5111 ;; Make sure any sub-files we read get proper mode
5112 (setq-default major-mode 'verilog-mode)
5113 ;; Ditto files already read in
5115 (when (buffer-file-name buf)
5116 (with-current-buffer buf
5119 ;; Process the files
5120 (mapcar (lambda (buf)
5121 (when (buffer-file-name buf)
5123 (if (not (file-exists-p (buffer-file-name buf)))
5125 (concat "File not found: " (buffer-file-name buf))))
5126 (message (concat "Processing " (buffer-file-name buf)))
5129 (unless no-save (save-buffer)))))
5132 (defun verilog-batch-auto ()
5133 "For use with --batch, perform automatic expansions as a stand-alone tool.
5134 This sets up the appropriate Verilog mode environment, updates automatics
5135 with \\[verilog-auto] on all command-line files, and saves the buffers.
5136 For proper results, multiple filenames need to be passed on the command
5137 line in bottom-up order."
5138 (unless noninteractive
5139 (error "Use verilog-batch-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
5140 (verilog-batch-execute-func `verilog-auto))
5142 (defun verilog-batch-delete-auto ()
5143 "For use with --batch, perform automatic deletion as a stand-alone tool.
5144 This sets up the appropriate Verilog mode environment, deletes automatics
5145 with \\[verilog-delete-auto] on all command-line files, and saves the buffers."
5146 (unless noninteractive
5147 (error "Use verilog-batch-delete-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
5148 (verilog-batch-execute-func `verilog-delete-auto))
5150 (defun verilog-batch-delete-trailing-whitespace ()
5151 "For use with --batch, perform whitespace deletion as a stand-alone tool.
5152 This sets up the appropriate Verilog mode environment, removes
5153 whitespace with \\[verilog-delete-trailing-whitespace] on all
5154 command-line files, and saves the buffers."
5155 (unless noninteractive
5156 (error "Use verilog-batch-delete-trailing-whitespace only with --batch")) ;; Otherwise we'd mess up buffer modes
5157 (verilog-batch-execute-func `verilog-delete-trailing-whitespace))
5159 (defun verilog-batch-diff-auto ()
5160 "For use with --batch, perform automatic differences as a stand-alone tool.
5161 This sets up the appropriate Verilog mode environment, expand automatics
5162 with \\[verilog-diff-auto] on all command-line files, and reports an error
5163 if any differences are observed. This is appropriate for adding to regressions
5164 to insure automatics are always properly maintained."
5165 (unless noninteractive
5166 (error "Use verilog-batch-diff-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
5167 (verilog-batch-execute-func `verilog-diff-auto t))
5169 (defun verilog-batch-inject-auto ()
5170 "For use with --batch, perform automatic injection as a stand-alone tool.
5171 This sets up the appropriate Verilog mode environment, injects new automatics
5172 with \\[verilog-inject-auto] on all command-line files, and saves the buffers.
5173 For proper results, multiple filenames need to be passed on the command
5174 line in bottom-up order."
5175 (unless noninteractive
5176 (error "Use verilog-batch-inject-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
5177 (verilog-batch-execute-func `verilog-inject-auto))
5179 (defun verilog-batch-indent ()
5180 "For use with --batch, reindent an entire file as a stand-alone tool.
5181 This sets up the appropriate Verilog mode environment, calls
5182 \\[verilog-indent-buffer] on all command-line files, and saves the buffers."
5183 (unless noninteractive
5184 (error "Use verilog-batch-indent only with --batch")) ;; Otherwise we'd mess up buffer modes
5185 (verilog-batch-execute-func `verilog-indent-buffer))
5191 (defconst verilog-indent-alist
5192 '((block . (+ ind verilog-indent-level))
5193 (case . (+ ind verilog-case-indent))
5194 (cparenexp . (+ ind verilog-indent-level))
5195 (cexp . (+ ind verilog-cexp-indent))
5196 (defun . verilog-indent-level-module)
5197 (declaration . verilog-indent-level-declaration)
5198 (directive . (verilog-calculate-indent-directive))
5199 (tf . verilog-indent-level)
5200 (behavioral . (+ verilog-indent-level-behavioral verilog-indent-level-module))
5203 (comment . (verilog-comment-indent))
5207 (defun verilog-continued-line-1 (lim)
5208 "Return true if this is a continued line.
5209 Set point to where line starts. Limit search to point LIM."
5210 (let ((continued 't))
5211 (if (eq 0 (forward-line -1))
5214 (verilog-backward-ws&directives lim)
5216 (setq continued nil)
5217 (setq continued (verilog-backward-token))))
5218 (setq continued nil))
5221 (defun verilog-calculate-indent ()
5222 "Calculate the indent of the current Verilog line.
5223 Examine previous lines. Once a line is found that is definitive as to the
5224 type of the current line, return that lines' indent level and its type.
5225 Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
5227 (let* ((starting_position (point))
5229 (begin (looking-at "[ \t]*begin\\>"))
5230 (lim (save-excursion (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)" nil t)))
5231 (type (catch 'nesting
5232 ;; Keep working backwards until we can figure out
5233 ;; what type of statement this is.
5234 ;; Basically we need to figure out
5235 ;; 1) if this is a continuation of the previous line;
5236 ;; 2) are we in a block scope (begin..end)
5238 ;; if we are in a comment, done.
5239 (if (verilog-in-star-comment-p)
5240 (throw 'nesting 'comment))
5242 ;; if we have a directive, done.
5243 (if (save-excursion (beginning-of-line)
5244 (and (looking-at verilog-directive-re-1)
5245 (not (or (looking-at "[ \t]*`[ou]vm_")
5246 (looking-at "[ \t]*`vmm_")))))
5247 (throw 'nesting 'directive))
5248 ;; indent structs as if there were module level
5249 (if (verilog-in-struct-p)
5250 (throw 'nesting 'block))
5252 ;; if we are in a parenthesized list, and the user likes to indent these, return.
5253 ;; unless we are in the newfangled coverpoint or constraint blocks
5255 verilog-indent-lists
5257 (not (verilog-in-coverage-p))
5260 (throw 'nesting 'block)))
5262 ;; See if we are continuing a previous line
5264 ;; trap out if we crawl off the top of the buffer
5265 (if (bobp) (throw 'nesting 'cpp))
5267 (if (verilog-continued-line-1 lim)
5270 (not (looking-at verilog-complete-reg))
5271 (verilog-continued-line-1 lim))
5272 (progn (goto-char sp)
5273 (throw 'nesting 'cexp))
5278 (not verilog-indent-begin-after-if)
5279 (looking-at verilog-no-indent-begin-re))
5282 (skip-chars-forward " \t")
5283 (throw 'nesting 'statement))
5285 (throw 'nesting 'cexp))))
5286 ;; not a continued line
5287 (goto-char starting_position))
5289 (if (looking-at "\\<else\\>")
5290 ;; search back for governing if, striding across begin..end pairs
5293 (while (verilog-re-search-backward verilog-ends-re nil 'move)
5295 ((match-end 1) ; else, we're in deep
5296 (setq elsec (1+ elsec)))
5298 (setq elsec (1- elsec))
5300 (if verilog-align-ifelse
5301 (throw 'nesting 'statement)
5302 (progn ;; back up to first word on this line
5304 (verilog-forward-syntactic-ws)
5305 (throw 'nesting 'statement)))))
5306 ((match-end 3) ; assert block
5307 (setq elsec (1- elsec))
5308 (verilog-beg-of-statement) ;; doesn't get to beginning
5309 (if (looking-at verilog-property-re)
5310 (throw 'nesting 'statement) ; We don't need an endproperty for these
5311 (throw 'nesting 'block) ;We still need an endproperty
5314 ; try to leap back to matching outward block by striding across
5315 ; indent level changing tokens then immediately
5316 ; previous line governs indentation.
5317 (let (( reg) (nest 1))
5318 ;; verilog-ends => else|if|end|join(_any|_none|)|endcase|endclass|endtable|endspecify|endfunction|endtask|endgenerate|endgroup
5320 ((match-end 4) ; end
5321 ;; Search back for matching begin
5322 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
5323 ((match-end 5) ; endcase
5324 ;; Search back for matching case
5325 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
5326 ((match-end 6) ; endfunction
5327 ;; Search back for matching function
5328 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
5329 ((match-end 7) ; endtask
5330 ;; Search back for matching task
5331 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
5332 ((match-end 8) ; endspecify
5333 ;; Search back for matching specify
5334 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
5335 ((match-end 9) ; endtable
5336 ;; Search back for matching table
5337 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
5338 ((match-end 10) ; endgenerate
5339 ;; Search back for matching generate
5340 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
5341 ((match-end 11) ; joins
5342 ;; Search back for matching fork
5343 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|none\\)?\\>\\)" ))
5344 ((match-end 12) ; class
5345 ;; Search back for matching class
5346 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
5347 ((match-end 13) ; covergroup
5348 ;; Search back for matching covergroup
5349 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" )))
5351 (while (verilog-re-search-backward reg nil 'move)
5353 ((match-end 1) ; begin
5354 (setq nest (1- nest))
5357 ((match-end 2) ; end
5358 (setq nest (1+ nest)))))
5360 (throw 'nesting (verilog-calc-1)))
5364 ;; Return type of block and indent level.
5367 (if (> par 0) ; Unclosed Parenthesis
5368 (list 'cparenexp par)
5371 (list type (verilog-case-indent-level)))
5372 ((eq type 'statement)
5373 (list type (current-column)))
5377 (list type (verilog-current-indent-level))))))))
5379 (defun verilog-wai ()
5380 "Show matching nesting block for debugging."
5383 (let* ((type (verilog-calc-1))
5385 ;; Return type of block and indent level.
5389 verilog-indent-lists
5390 (not(or (verilog-in-coverage-p)
5391 (verilog-in-struct-p)))
5396 (setq depth (verilog-case-indent-level)))
5397 ((eq type 'statement)
5398 (setq depth (current-column)))
5402 (setq depth (verilog-current-indent-level)))))
5403 (message "You are at nesting %s depth %d" type depth))))
5404 (defun verilog-calc-1 ()
5406 (let ((re (concat "\\({\\|}\\|" verilog-indent-re "\\)")))
5407 (while (verilog-re-search-backward re nil 'move)
5410 ((equal (char-after) ?\{)
5411 (if (verilog-at-constraint-p)
5412 (throw 'nesting 'block)))
5414 ((equal (char-after) ?\})
5415 (let ((there (verilog-at-close-constraint-p)))
5416 (if there ;; we are at the } that closes a constraint. Find the { that opens it
5420 (verilog-beg-of-statement)))))
5422 ((looking-at verilog-beg-block-re-ordered)
5424 ((match-end 2) ; *sigh* could be "unique case" or "priority casex"
5425 (let ((here (point)))
5426 (verilog-beg-of-statement)
5427 (if (looking-at verilog-extended-case-re)
5428 (throw 'nesting 'case)
5430 (throw 'nesting 'case))
5432 ((match-end 4) ; *sigh* could be "disable fork"
5433 (let ((here (point)))
5434 (verilog-beg-of-statement)
5435 (if (looking-at verilog-disable-fork-re)
5436 t ; this is a normal statement
5437 (progn ; or is fork, starts a new block
5439 (throw 'nesting 'block)))))
5441 ((match-end 27) ; *sigh* might be a clocking declaration
5442 (let ((here (point)))
5443 (if (verilog-in-paren)
5444 t ; this is a normal statement
5445 (progn ; or is fork, starts a new block
5447 (throw 'nesting 'block)))))
5449 ;; need to consider typedef struct here...
5450 ((looking-at "\\<class\\|struct\\|function\\|task\\>")
5451 ; *sigh* These words have an optional prefix:
5452 ; extern {virtual|protected}? function a();
5453 ; typedef class foo;
5454 ; and we don't want to confuse this with
5459 (verilog-beg-of-statement)
5460 (if (looking-at verilog-beg-block-re-ordered)
5461 (throw 'nesting 'block)
5462 (throw 'nesting 'defun)))
5465 ((looking-at "\\<property\\>")
5467 ; {assert|assume|cover} property (); are complete
5468 ; and could also be labeled: - foo: assert property
5470 ; property ID () ... needs end_property
5471 (verilog-beg-of-statement)
5472 (if (looking-at verilog-property-re)
5473 (throw 'continue 'statement) ; We don't need an endproperty for these
5474 (throw 'nesting 'block) ;We still need an endproperty
5477 (t (throw 'nesting 'block))))
5479 ((looking-at verilog-end-block-re)
5480 (verilog-leap-to-head)
5481 (if (verilog-in-case-region-p)
5483 (verilog-leap-to-case-head)
5484 (if (looking-at verilog-extended-case-re)
5485 (throw 'nesting 'case)))))
5487 ((looking-at verilog-defun-level-re)
5488 (if (looking-at verilog-defun-level-generate-only-re)
5489 (if (verilog-in-generate-region-p)
5490 (throw 'continue 'foo) ; always block in a generate - keep looking
5491 (throw 'nesting 'defun))
5492 (throw 'nesting 'defun)))
5494 ((looking-at verilog-cpp-level-re)
5495 (throw 'nesting 'cpp))
5498 (throw 'nesting 'cpp)))))
5500 (throw 'nesting 'cpp))))
5502 (defun verilog-calculate-indent-directive ()
5503 "Return indentation level for directive.
5504 For speed, the searcher looks at the last directive, not the indent
5505 of the appropriate enclosing block."
5506 (let ((base -1) ;; Indent of the line that determines our indentation
5507 (ind 0)) ;; Relative offset caused by other directives (like `endif on same line as `else)
5508 ;; Start at current location, scan back for another directive
5512 (while (and (< base 0)
5513 (verilog-re-search-backward verilog-directive-re nil t))
5514 (cond ((save-excursion (skip-chars-backward " \t") (bolp))
5515 (setq base (current-indentation))))
5516 (cond ((and (looking-at verilog-directive-end) (< base 0)) ;; Only matters when not at BOL
5517 (setq ind (- ind verilog-indent-level-directive)))
5518 ((and (looking-at verilog-directive-middle) (>= base 0)) ;; Only matters when at BOL
5519 (setq ind (+ ind verilog-indent-level-directive)))
5520 ((looking-at verilog-directive-begin)
5521 (setq ind (+ ind verilog-indent-level-directive)))))
5522 ;; Adjust indent to starting indent of critical line
5523 (setq ind (max 0 (+ ind base))))
5527 (skip-chars-forward " \t")
5528 (cond ((or (looking-at verilog-directive-middle)
5529 (looking-at verilog-directive-end))
5530 (setq ind (max 0 (- ind verilog-indent-level-directive))))))
5533 (defun verilog-leap-to-case-head ()
5536 (verilog-re-search-backward
5538 "\\(\\<randcase\\>\\|\\(\\<unique\\s-+\\|priority\\s-+\\)?\\<case[xz]?\\>\\)"
5539 "\\|\\(\\<endcase\\>\\)" )
5543 (let ((here (point)))
5544 (verilog-beg-of-statement)
5545 (unless (looking-at verilog-extended-case-re)
5547 (setq nest (1- nest)))
5549 (setq nest (1+ nest)))
5554 (defun verilog-leap-to-head ()
5555 "Move point to the head of this block.
5556 Jump from end to matching begin, from endcase to matching case, and so on."
5562 ((looking-at "\\<end\\>")
5563 ;; 1: Search back for matching begin
5564 (setq reg (concat "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|"
5565 "\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))
5566 ((looking-at "\\<endtask\\>")
5567 ;; 2: Search back for matching task
5568 (setq reg "\\(\\<task\\>\\)\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)+\\<task\\>\\)")
5570 ((looking-at "\\<endcase\\>")
5572 (verilog-leap-to-case-head) )
5573 (setq reg nil) ; to force skip
5576 ((looking-at "\\<join\\(_any\\|_none\\)?\\>")
5577 ;; 4: Search back for matching fork
5578 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
5579 ((looking-at "\\<endclass\\>")
5580 ;; 5: Search back for matching class
5581 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
5582 ((looking-at "\\<endtable\\>")
5583 ;; 6: Search back for matching table
5584 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
5585 ((looking-at "\\<endspecify\\>")
5586 ;; 7: Search back for matching specify
5587 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
5588 ((looking-at "\\<endfunction\\>")
5589 ;; 8: Search back for matching function
5590 (setq reg "\\(\\<function\\>\\)\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)+\\<function\\>\\)")
5592 ;;(setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
5593 ((looking-at "\\<endgenerate\\>")
5594 ;; 8: Search back for matching generate
5595 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
5596 ((looking-at "\\<endgroup\\>")
5597 ;; 10: Search back for matching covergroup
5598 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
5599 ((looking-at "\\<endproperty\\>")
5600 ;; 11: Search back for matching property
5601 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
5602 ((looking-at verilog-uvm-end-re)
5603 ;; 12: Search back for matching sequence
5604 (setq reg (concat "\\(" verilog-uvm-begin-re "\\|" verilog-uvm-end-re "\\)")))
5605 ((looking-at verilog-ovm-end-re)
5606 ;; 12: Search back for matching sequence
5607 (setq reg (concat "\\(" verilog-ovm-begin-re "\\|" verilog-ovm-end-re "\\)")))
5608 ((looking-at verilog-vmm-end-re)
5609 ;; 12: Search back for matching sequence
5610 (setq reg (concat "\\(" verilog-vmm-begin-re "\\|" verilog-vmm-end-re "\\)")))
5611 ((looking-at "\\<endinterface\\>")
5612 ;; 12: Search back for matching interface
5613 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<endinterface\\>\\)" ))
5614 ((looking-at "\\<endsequence\\>")
5615 ;; 12: Search back for matching sequence
5616 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" ))
5617 ((looking-at "\\<endclocking\\>")
5618 ;; 12: Search back for matching clocking
5619 (setq reg "\\(\\<clocking\\)\\|\\(\\<endclocking\\>\\)" )))
5622 (if (eq nesting 'yes)
5624 (while (verilog-re-search-backward reg nil 'move)
5626 ((match-end 1) ; begin
5627 (if (looking-at "fork")
5628 (let ((here (point)))
5629 (verilog-beg-of-statement)
5630 (unless (looking-at verilog-disable-fork-re)
5632 (setq nest (1- nest))))
5633 (setq nest (1- nest)))
5635 ;; Now previous line describes syntax
5640 ((match-end 2) ; end
5641 (setq nest (1+ nest)))
5643 ;; endcase, jump to case
5645 (setq nest (1+ nest))
5647 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
5649 ;; join, jump to fork
5651 (setq nest (1+ nest))
5653 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
5657 (verilog-re-search-backward reg nil 'move)
5658 (match-end 1)) ; task -> could be virtual and/or protected
5660 (verilog-beg-of-statement)
5662 (throw 'skip 1)))))))
5664 (defun verilog-continued-line ()
5665 "Return true if this is a continued line.
5666 Set point to where line starts."
5667 (let ((continued 't))
5668 (if (eq 0 (forward-line -1))
5671 (verilog-backward-ws&directives)
5673 (setq continued nil)
5674 (while (and continued
5676 (skip-chars-backward " \t")
5678 (setq continued (verilog-backward-token)))))
5679 (setq continued nil))
5682 (defun verilog-backward-token ()
5683 "Step backward token, returning true if this is a continued line."
5685 (verilog-backward-syntactic-ws)
5689 (;-- Anything ending in a ; is complete
5690 (= (preceding-char) ?\;)
5692 (; If a "}" is prefixed by a ";", then this is a complete statement
5693 ; i.e.: constraint foo { a = b; }
5694 (= (preceding-char) ?\})
5697 (not(verilog-at-close-constraint-p))))
5698 (;-- constraint foo { a = b }
5699 ; is a complete statement. *sigh*
5700 (= (preceding-char) ?\{)
5703 (not (verilog-at-constraint-p))))
5705 (= (preceding-char) ?\")
5707 (verilog-skip-backward-comment-or-string)
5711 (= (preceding-char) ?\])
5713 (verilog-backward-open-bracket)
5716 (;-- Could be 'case (foo)' or 'always @(bar)' which is complete
5717 ; also could be simply '@(foo)'
5719 ; (b, ... which ISN'T complete
5720 ;;;; Do we need this???
5721 (= (preceding-char) ?\))
5724 (verilog-backward-up-list 1)
5725 (verilog-backward-syntactic-ws)
5726 (let ((back (point)))
5730 ((looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|case\\(\\|[xz]\\)\\|for\\(\\|each\\|ever\\)\\|i\\(f\\|nitial\\)\\|repeat\\|while\\)\\>")
5731 (not (looking-at "\\<randcase\\>\\|\\<case[xz]?\\>[^:]")))
5732 ((looking-at verilog-uvm-statement-re)
5734 ((looking-at verilog-uvm-begin-re)
5736 ((looking-at verilog-uvm-end-re)
5738 ((looking-at verilog-ovm-statement-re)
5740 ((looking-at verilog-ovm-begin-re)
5742 ((looking-at verilog-ovm-end-re)
5744 ;; JBA find VMM macros
5745 ((looking-at verilog-vmm-statement-re)
5747 ((looking-at verilog-vmm-begin-re)
5749 ((looking-at verilog-vmm-end-re)
5751 ;; JBA trying to catch macro lines with no ; at end
5752 ((looking-at "\\<`")
5757 ((= (preceding-char) ?\@)
5760 (verilog-backward-token)
5761 (not (looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|initial\\|while\\)\\>"))))
5762 ((= (preceding-char) ?\#)
5766 (;-- any of begin|initial|while are complete statements; 'begin : foo' is also complete
5769 (while (= (preceding-char) ?\_)
5772 ((looking-at "\\<else\\>")
5774 ((looking-at verilog-behavioral-block-beg-re)
5776 ((looking-at verilog-indent-re)
5781 (verilog-backward-syntactic-ws)
5783 ((= (preceding-char) ?\:)
5785 (verilog-backward-syntactic-ws)
5787 (if (looking-at verilog-nameable-item-re )
5790 ((= (preceding-char) ?\#)
5793 ((= (preceding-char) ?\`)
5801 (defun verilog-backward-syntactic-ws ()
5802 "Move backwards putting point after first non-whitespace non-comment."
5803 (verilog-skip-backward-comments)
5804 (forward-comment (- (buffer-size))))
5806 (defun verilog-backward-syntactic-ws-quick ()
5807 "As with `verilog-backward-syntactic-ws' but use `verilog-scan' cache."
5808 (while (cond ((bobp)
5810 ((> (skip-syntax-backward " ") 0)
5812 ((eq (preceding-char) ?\n) ;; \n's terminate // so aren't space syntax
5815 ((or (verilog-inside-comment-or-string-p (1- (point)))
5816 (verilog-inside-comment-or-string-p (point)))
5817 (re-search-backward "[/\"]" nil t) ;; Only way a comment or quote can begin
5820 (defun verilog-forward-syntactic-ws ()
5821 (verilog-skip-forward-comment-p)
5822 (forward-comment (buffer-size)))
5824 (defun verilog-backward-ws&directives (&optional bound)
5825 "Backward skip over syntactic whitespace and compiler directives for Emacs 19.
5826 Optional BOUND limits search."
5828 (let* ((bound (or bound (point-min)))
5831 (if (< bound (point))
5833 (let ((state (save-excursion (verilog-syntax-ppss))))
5835 ((nth 7 state) ;; in // comment
5836 (verilog-re-search-backward "//" nil 'move)
5837 (skip-chars-backward "/"))
5838 ((nth 4 state) ;; in /* */ comment
5839 (verilog-re-search-backward "/\*" nil 'move))))
5840 (narrow-to-region bound (point))
5841 (while (/= here (point))
5843 (verilog-skip-backward-comments)
5848 ((and verilog-highlight-translate-off
5849 (verilog-within-translate-off))
5850 (verilog-back-to-start-translate-off (point-min)))
5851 ((looking-at verilog-directive-re-1)
5855 (if p (goto-char p))))))))
5857 (defun verilog-forward-ws&directives (&optional bound)
5858 "Forward skip over syntactic whitespace and compiler directives for Emacs 19.
5859 Optional BOUND limits search."
5861 (let* ((bound (or bound (point-max)))
5864 (if (> bound (point))
5866 (let ((state (save-excursion (verilog-syntax-ppss))))
5868 ((nth 7 state) ;; in // comment
5871 (skip-chars-forward " \t\n\f")
5873 ((nth 4 state) ;; in /* */ comment
5874 (verilog-re-search-forward "\*\/\\s-*" nil 'move))))
5875 (narrow-to-region (point) bound)
5876 (while (/= here (point))
5879 (forward-comment (buffer-size))
5880 (and (looking-at "\\s-*(\\*.*\\*)\\s-*") ;; Attribute
5881 (goto-char (match-end 0)))
5884 (if (looking-at verilog-directive-re-1)
5887 (beginning-of-line 2))))))))
5889 (defun verilog-in-comment-p ()
5890 "Return true if in a star or // comment."
5891 (let ((state (save-excursion (verilog-syntax-ppss))))
5892 (or (nth 4 state) (nth 7 state))))
5894 (defun verilog-in-star-comment-p ()
5895 "Return true if in a star comment."
5896 (let ((state (save-excursion (verilog-syntax-ppss))))
5898 (nth 4 state) ; t if in a comment of style a // or b /**/
5900 (nth 7 state) ; t if in a comment of style b /**/
5903 (defun verilog-in-slash-comment-p ()
5904 "Return true if in a slash comment."
5905 (let ((state (save-excursion (verilog-syntax-ppss))))
5908 (defun verilog-in-comment-or-string-p ()
5909 "Return true if in a string or comment."
5910 (let ((state (save-excursion (verilog-syntax-ppss))))
5911 (or (nth 3 state) (nth 4 state) (nth 7 state)))) ; Inside string or comment)
5913 (defun verilog-in-attribute-p ()
5914 "Return true if point is in an attribute (* [] attribute *)."
5917 (verilog-re-search-backward "\\((\\*\\)\\|\\(\\*)\\)" nil 'move)
5918 (numberp (match-beginning 1)))))
5920 (defun verilog-in-parameter-p ()
5921 "Return true if point is in a parameter assignment #( p1=1, p2=5)."
5924 (verilog-re-search-backward "\\(#(\\)\\|\\()\\)" nil 'move)
5925 (numberp (match-beginning 1)))))
5927 (defun verilog-in-escaped-name-p ()
5928 "Return true if in an escaped name."
5931 (skip-chars-backward "^ \t\n\f")
5932 (if (equal (char-after (point) ) ?\\ )
5935 (defun verilog-in-directive-p ()
5936 "Return true if in a directive."
5939 (looking-at verilog-directive-re-1)))
5941 (defun verilog-in-parenthesis-p ()
5942 "Return true if in a ( ) expression (but not { } or [ ])."
5945 (verilog-re-search-backward "\\((\\)\\|\\()\\)" nil 'move)
5946 (numberp (match-beginning 1)))))
5948 (defun verilog-in-paren ()
5949 "Return true if in a parenthetical expression.
5950 May cache result using `verilog-syntax-ppss'."
5951 (let ((state (save-excursion (verilog-syntax-ppss))))
5952 (> (nth 0 state) 0 )))
5954 (defun verilog-in-paren-quick ()
5955 "Return true if in a parenthetical expression.
5956 Always starts from `point-min', to allow inserts with hooks disabled."
5957 ;; The -quick refers to its use alongside the other -quick functions,
5958 ;; not that it's likely to be faster than verilog-in-paren.
5959 (let ((state (save-excursion (parse-partial-sexp (point-min) (point)))))
5960 (> (nth 0 state) 0 )))
5962 (defun verilog-in-struct-p ()
5963 "Return true if in a struct declaration."
5966 (if (verilog-in-paren)
5968 (verilog-backward-up-list 1)
5969 (verilog-at-struct-p)
5973 (defun verilog-in-coverage-p ()
5974 "Return true if in a constraint or coverpoint expression."
5977 (if (verilog-in-paren)
5979 (verilog-backward-up-list 1)
5980 (verilog-at-constraint-p)
5983 (defun verilog-at-close-constraint-p ()
5984 "If at the } that closes a constraint or covergroup, return true."
5986 (equal (char-after) ?\})
5990 (verilog-backward-ws&directives)
5991 (if (equal (char-before) ?\;)
5995 (defun verilog-at-constraint-p ()
5996 "If at the { of a constraint or coverpoint definition, return true, moving point to constraint."
5999 (equal (char-after) ?\{)
6001 (progn (backward-char 1)
6002 (verilog-backward-ws&directives)
6003 (equal (char-before) ?\;))))
6005 (verilog-re-search-backward "\\<constraint\\|coverpoint\\|cross\\>" nil 'move)
6009 (defun verilog-at-struct-p ()
6010 "If at the { of a struct, return true, moving point to struct."
6012 (if (and (equal (char-after) ?\{)
6013 (verilog-backward-token))
6014 (looking-at "\\<struct\\|union\\|packed\\|\\(un\\)?signed\\>")
6017 (defun verilog-parenthesis-depth ()
6018 "Return non zero if in parenthetical-expression."
6019 (save-excursion (nth 1 (verilog-syntax-ppss))))
6022 (defun verilog-skip-forward-comment-or-string ()
6023 "Return true if in a string or comment."
6024 (let ((state (save-excursion (verilog-syntax-ppss))))
6026 ((nth 3 state) ;Inside string
6027 (search-forward "\"")
6029 ((nth 7 state) ;Inside // comment
6032 ((nth 4 state) ;Inside any comment (hence /**/)
6033 (search-forward "*/"))
6037 (defun verilog-skip-backward-comment-or-string ()
6038 "Return true if in a string or comment."
6039 (let ((state (save-excursion (verilog-syntax-ppss))))
6041 ((nth 3 state) ;Inside string
6042 (search-backward "\"")
6044 ((nth 7 state) ;Inside // comment
6045 (search-backward "//")
6046 (skip-chars-backward "/")
6048 ((nth 4 state) ;Inside /* */ comment
6049 (search-backward "/*")
6054 (defun verilog-skip-backward-comments ()
6055 "Return true if a comment was skipped."
6059 (let ((state (save-excursion (verilog-syntax-ppss))))
6061 ((nth 7 state) ;Inside // comment
6062 (search-backward "//")
6063 (skip-chars-backward "/")
6064 (skip-chars-backward " \t\n\f")
6066 ((nth 4 state) ;Inside /* */ comment
6067 (search-backward "/*")
6068 (skip-chars-backward " \t\n\f")
6071 (= (char-before) ?\/)
6072 (= (char-before (1- (point))) ?\*))
6073 (goto-char (- (point) 2))
6074 t) ;; Let nth 4 state handle the rest
6076 (= (char-before) ?\))
6077 (= (char-before (1- (point))) ?\*))
6078 (goto-char (- (point) 2))
6079 (if (search-backward "(*" nil t)
6081 (skip-chars-backward " \t\n\f")
6084 (goto-char (+ (point) 2))
6087 (/= (skip-chars-backward " \t\n\f") 0))))))))
6089 (defun verilog-skip-forward-comment-p ()
6090 "If in comment, move to end and return true."
6092 (state (save-excursion (verilog-syntax-ppss)))
6094 ((nth 3 state) ;Inside string
6096 ((nth 7 state) ;Inside // comment
6100 ((nth 4 state) ;Inside /* comment
6101 (search-forward "*/")
6103 ((verilog-in-attribute-p) ;Inside (* attribute
6104 (search-forward "*)" nil t)
6107 (skip-chars-forward " \t\n\f")
6110 ((looking-at "\\/\\*")
6113 (goto-char (match-end 0))
6114 (if (search-forward "*/" nil t)
6116 (skip-chars-forward " \t\n\f")
6121 ((looking-at "(\\*")
6124 (goto-char (match-end 0))
6125 (if (search-forward "*)" nil t)
6127 (skip-chars-forward " \t\n\f")
6135 (defun verilog-indent-line-relative ()
6136 "Cheap version of indent line.
6137 Only look at a few lines to determine indent level."
6141 (if (looking-at "^[ \t]*$")
6142 (cond ;- A blank line; No need to be too smart.
6144 (setq indent-str (list 'cpp 0)))
6145 ((verilog-continued-line)
6146 (let ((sp1 (point)))
6147 (if (verilog-continued-line)
6151 (list 'statement (verilog-current-indent-level))))
6153 (setq indent-str (list 'block (verilog-current-indent-level)))))
6156 (setq indent-str (verilog-calculate-indent))))
6157 (progn (skip-chars-forward " \t")
6158 (setq indent-str (verilog-calculate-indent))))
6159 (verilog-do-indent indent-str)))
6161 (defun verilog-indent-line ()
6162 "Indent for special part of code."
6163 (verilog-do-indent (verilog-calculate-indent)))
6165 (defun verilog-do-indent (indent-str)
6166 (let ((type (car indent-str))
6167 (ind (car (cdr indent-str))))
6169 (; handle continued exp
6171 (let ((here (point)))
6172 (verilog-backward-syntactic-ws)
6175 (= (preceding-char) ?\,)
6176 (= (preceding-char) ?\])
6178 (verilog-beg-of-statement-1)
6179 (looking-at verilog-declaration-re)))
6184 (verilog-beg-of-statement-1)
6186 (if (looking-at verilog-declaration-re)
6187 (progn ;; we have multiple words
6188 (goto-char (match-end 0))
6189 (skip-chars-forward " \t")
6191 ((and verilog-indent-declaration-macros
6192 (= (following-char) ?\`))
6196 (skip-chars-forward " \t")))
6197 ((= (following-char) ?\[)
6200 (verilog-backward-up-list -1)
6201 (skip-chars-forward " \t"))))
6205 (+ (current-column) verilog-cexp-indent))))))
6207 (indent-line-to val)
6208 (if (and (not verilog-indent-lists)
6210 (verilog-pretty-declarations-auto))
6212 ((= (preceding-char) ?\) )
6214 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
6215 (indent-line-to val)))
6219 (verilog-beg-of-statement-1)
6220 (if (and (< (point) here)
6221 (verilog-re-search-forward "=[ \\t]*" here 'move))
6222 (setq val (current-column))
6223 (setq val (eval (cdr (assoc type verilog-indent-alist)))))
6225 (indent-line-to val))))))
6227 (; handle inside parenthetical expressions
6228 (eq type 'cparenexp)
6230 (val (save-excursion
6231 (verilog-backward-up-list 1)
6233 (if verilog-indent-lists
6234 (skip-chars-forward " \t")
6235 (verilog-forward-syntactic-ws))
6239 (decl (save-excursion
6241 (verilog-forward-syntactic-ws)
6243 (looking-at verilog-declaration-re))))
6244 (indent-line-to val)
6246 (verilog-pretty-declarations-auto))))
6248 (;-- Handle the ends
6250 (looking-at verilog-end-block-re )
6251 (verilog-at-close-constraint-p))
6252 (let ((val (if (eq type 'statement)
6253 (- ind verilog-indent-level)
6255 (indent-line-to val)))
6257 (;-- Case -- maybe line 'em up
6258 (and (eq type 'case) (not (looking-at "^[ \t]*$")))
6261 ((looking-at "\\<endcase\\>")
6262 (indent-line-to ind))
6264 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
6265 (indent-line-to val))))))
6268 (and (eq type 'defun)
6269 (looking-at verilog-zero-indent-re))
6276 (looking-at verilog-declaration-re))
6277 (verilog-indent-declaration ind))
6279 (;-- Everything else
6281 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
6282 (indent-line-to val))))
6284 (if (looking-at "[ \t]+$")
6285 (skip-chars-forward " \t"))
6286 indent-str ; Return indent data
6289 (defun verilog-current-indent-level ()
6290 "Return the indent-level of the current statement."
6294 (setq par-pos (verilog-parenthesis-depth))
6298 (setq par-pos (verilog-parenthesis-depth)))
6299 (skip-chars-forward " \t")
6302 (defun verilog-case-indent-level ()
6303 "Return the indent-level of the current statement.
6304 Do not count named blocks or case-statements."
6306 (skip-chars-forward " \t")
6308 ((looking-at verilog-named-block-re)
6310 ((and (not (looking-at verilog-extended-case-re))
6311 (looking-at "^[^:;]+[ \t]*:"))
6312 (verilog-re-search-forward ":" nil t)
6313 (skip-chars-forward " \t")
6316 (current-column)))))
6318 (defun verilog-indent-comment ()
6319 "Indent current line as comment."
6322 ((verilog-in-star-comment-p)
6324 (re-search-backward "/\\*" nil t)
6325 (1+(current-column))))
6330 (re-search-backward "//" nil t)
6331 (current-column))))))
6332 (indent-line-to stcol)
6335 (defun verilog-more-comment ()
6336 "Make more comment lines like the previous."
6340 ((verilog-in-star-comment-p)
6343 (re-search-backward "/\\*" nil t)
6344 (1+(current-column))))
6349 (re-search-backward "//" nil t)
6350 (current-column))))))
6356 (skip-chars-forward " \t")
6360 (defun verilog-comment-indent (&optional arg)
6361 "Return the column number the line should be indented to.
6362 ARG is ignored, for `comment-indent-function' compatibility."
6364 ((verilog-in-star-comment-p)
6366 (re-search-backward "/\\*" nil t)
6367 (1+(current-column))))
6372 (re-search-backward "//" nil t)
6373 (current-column)))))
6377 (defun verilog-pretty-declarations-auto (&optional quiet)
6378 "Call `verilog-pretty-declarations' QUIET based on `verilog-auto-lineup'."
6379 (when (or (eq 'all verilog-auto-lineup)
6380 (eq 'declarations verilog-auto-lineup))
6381 (verilog-pretty-declarations quiet)))
6383 (defun verilog-pretty-declarations (&optional quiet)
6384 "Line up declarations around point.
6385 Be verbose about progress unless optional QUIET set."
6387 (let* ((m1 (make-marker))
6401 ; (verilog-beg-of-statement-1)
6403 (verilog-forward-syntactic-ws)
6404 (and (not (verilog-in-directive-p)) ;; could have `define input foo
6405 (looking-at verilog-declaration-re)))
6407 (if (verilog-parenthesis-depth)
6408 ;; in an argument list or parameter block
6409 (setq el (verilog-backward-up-list -1)
6412 (verilog-backward-up-list 1)
6413 (forward-line) ;; ignore ( input foo,
6414 (verilog-re-search-forward verilog-declaration-re el 'move)
6415 (goto-char (match-beginning 0))
6416 (skip-chars-backward " \t")
6418 startpos (set-marker (make-marker) start)
6421 (verilog-backward-up-list -1)
6423 (verilog-backward-syntactic-ws)
6425 endpos (set-marker (make-marker) end)
6429 (skip-chars-forward " \t")
6432 ;; in a declaration block (not in argument list)
6435 (verilog-beg-of-statement-1)
6436 (while (and (looking-at verilog-declaration-re)
6438 (skip-chars-backward " \t")
6441 (verilog-backward-syntactic-ws)
6443 (verilog-beg-of-statement-1))
6445 startpos (set-marker (make-marker) start)
6448 (verilog-end-of-statement)
6449 (setq e (point)) ;Might be on last line
6450 (verilog-forward-syntactic-ws)
6451 (while (looking-at verilog-declaration-re)
6452 (verilog-end-of-statement)
6454 (verilog-forward-syntactic-ws))
6456 endpos (set-marker (make-marker) end)
6459 (verilog-do-indent (verilog-calculate-indent))
6460 (verilog-forward-ws&directives)
6462 ;; OK, start and end are set
6463 (goto-char (marker-position startpos))
6464 (if (and (not quiet)
6465 (> (- end start) 100))
6466 (message "Lining up declarations..(please stand by)"))
6467 ;; Get the beginning of line indent first
6468 (while (progn (setq e (marker-position endpos))
6471 ((save-excursion (skip-chars-backward " \t")
6473 (verilog-forward-ws&directives)
6474 (indent-line-to base-ind)
6475 (verilog-forward-ws&directives)
6477 (verilog-re-search-forward "[ \t\n\f]" e 'move)))
6480 (verilog-re-search-forward "[ \t\n\f]" e 'move)))
6483 ;; Now find biggest prefix
6484 (setq ind (verilog-get-lineup-indent (marker-position startpos) endpos))
6485 ;; Now indent each line.
6486 (goto-char (marker-position startpos))
6487 (while (progn (setq e (marker-position endpos))
6488 (setq r (- e (point)))
6491 (unless quiet (message "%d" r))
6492 ;;(verilog-do-indent (verilog-calculate-indent)))
6493 (verilog-forward-ws&directives)
6495 ((or (and verilog-indent-declaration-macros
6496 (looking-at verilog-declaration-re-2-macro))
6497 (looking-at verilog-declaration-re-2-no-macro))
6498 (let ((p (match-end 0)))
6500 (if (verilog-re-search-forward "[[#`]" p 'move)
6504 (goto-char (marker-position m1))
6510 ((verilog-continued-line-1 (marker-position startpos))
6512 (indent-line-to ind))
6513 ((verilog-in-struct-p)
6514 ;; could have a declaration of a user defined item
6516 (verilog-end-of-statement))
6517 (t ; Must be comment or white space
6519 (verilog-forward-ws&directives)
6522 (unless quiet (message "")))))))
6524 (defun verilog-pretty-expr (&optional quiet myre)
6525 "Line up expressions around point, optionally QUIET with regexp MYRE ignored."
6527 (if (not (verilog-in-comment-or-string-p))
6529 (let ( (rexp (concat "^\\s-*" verilog-complete-reg))
6530 (rexp1 (concat "^\\s-*" verilog-basic-complete-re)))
6532 (if (and (not (looking-at rexp ))
6533 (looking-at verilog-assignment-operation-re)
6535 (goto-char (match-end 2))
6536 (and (not (verilog-in-attribute-p))
6537 (not (verilog-in-parameter-p))
6538 (not (verilog-in-comment-or-string-p)))))
6539 (let* ((here (point))
6545 (verilog-backward-syntactic-ws)
6547 (while (and (not (looking-at rexp1))
6548 (looking-at verilog-assignment-operation-re)
6552 (verilog-backward-syntactic-ws)
6554 ) ;Ack, need to grok `define
6560 (setq e (point)) ;Might be on last line
6561 (verilog-forward-syntactic-ws)
6564 (not (looking-at rexp1 ))
6565 (looking-at verilog-assignment-operation-re)
6568 (not (eq e (point)))))
6570 (verilog-forward-syntactic-ws)
6574 (endpos (set-marker (make-marker) end))
6578 (verilog-do-indent (verilog-calculate-indent))
6579 (if (and (not quiet)
6580 (> (- end start) 100))
6581 (message "Lining up expressions..(please stand by)"))
6583 ;; Set indent to minimum throughout region
6584 (while (< (point) (marker-position endpos))
6586 (verilog-just-one-space verilog-assignment-operation-re)
6588 (verilog-do-indent (verilog-calculate-indent))
6590 (verilog-forward-syntactic-ws)
6593 ;; Now find biggest prefix
6594 (setq ind (verilog-get-lineup-indent-2 verilog-assignment-operation-re start endpos))
6596 ;; Now indent each line.
6598 (while (progn (setq e (marker-position endpos))
6599 (setq r (- e (point)))
6602 (if (not quiet) (message "%d" r))
6604 ((looking-at verilog-assignment-operation-re)
6605 (goto-char (match-beginning 2))
6606 (if (not (or (verilog-in-parenthesis-p) ;; leave attributes and comparisons alone
6607 (verilog-in-coverage-p)))
6608 (if (eq (char-after) ?=)
6609 (indent-to (1+ ind)) ; line up the = of the <= with surrounding =
6613 ((verilog-continued-line-1 start)
6615 (indent-line-to ind))
6616 (t ; Must be comment or white space
6618 (verilog-forward-ws&directives)
6622 (unless quiet (message ""))
6625 (defun verilog-just-one-space (myre)
6626 "Remove extra spaces around regular expression MYRE."
6628 (if (and (not(looking-at verilog-complete-reg))
6630 (let ((p1 (match-end 1))
6636 (just-one-space)))))
6638 (defun verilog-indent-declaration (baseind)
6639 "Indent current lines as declaration.
6640 Line up the variable names based on previous declaration's indentation.
6641 BASEIND is the base indent to offset everything."
6643 (let ((pos (point-marker))
6644 (lim (save-excursion
6645 ;; (verilog-re-search-backward verilog-declaration-opener nil 'move)
6646 (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)\\|\\(\\<task\\>\\)" nil 'move)
6652 (+ baseind (eval (cdr (assoc 'declaration verilog-indent-alist)))))
6653 (indent-line-to val)
6655 ;; Use previous declaration (in this module) as template.
6656 (if (or (eq 'all verilog-auto-lineup)
6657 (eq 'declarations verilog-auto-lineup))
6658 (if (verilog-re-search-backward
6659 (or (and verilog-indent-declaration-macros
6660 verilog-declaration-re-1-macro)
6661 verilog-declaration-re-1-no-macro) lim t)
6663 (goto-char (match-end 0))
6664 (skip-chars-forward " \t")
6665 (setq ind (current-column))
6669 (eval (cdr (assoc 'declaration verilog-indent-alist)))))
6670 (indent-line-to val)
6671 (if (and verilog-indent-declaration-macros
6672 (looking-at verilog-declaration-re-2-macro))
6673 (let ((p (match-end 0)))
6675 (if (verilog-re-search-forward "[[#`]" p 'move)
6679 (goto-char (marker-position m1))
6682 (if (/= (current-column) ind)
6686 (if (looking-at verilog-declaration-re-2-no-macro)
6687 (let ((p (match-end 0)))
6689 (if (verilog-re-search-forward "[[`#]" p 'move)
6693 (goto-char (marker-position m1))
6696 (if (/= (current-column) ind)
6699 (indent-to ind))))))))))
6702 (defun verilog-get-lineup-indent (b edpos)
6703 "Return the indent level that will line up several lines within the region.
6704 Region is defined by B and EDPOS."
6708 ;; Get rightmost position
6709 (while (progn (setq e (marker-position edpos))
6711 (if (verilog-re-search-forward
6712 (or (and verilog-indent-declaration-macros
6713 verilog-declaration-re-1-macro)
6714 verilog-declaration-re-1-no-macro) e 'move)
6716 (goto-char (match-end 0))
6717 (verilog-backward-syntactic-ws)
6718 (if (> (current-column) ind)
6719 (setq ind (current-column)))
6720 (goto-char (match-end 0)))))
6723 ;; No lineup-string found
6726 (verilog-backward-syntactic-ws)
6727 ;;(skip-chars-backward " \t")
6728 (1+ (current-column))))))
6730 (defun verilog-get-lineup-indent-2 (myre b edpos)
6731 "Return the indent level that will line up several lines within the region."
6735 ;; Get rightmost position
6736 (while (progn (setq e (marker-position edpos))
6738 (if (and (verilog-re-search-forward myre e 'move)
6739 (not (verilog-in-attribute-p))) ;; skip attribute exprs
6741 (goto-char (match-beginning 2))
6742 (verilog-backward-syntactic-ws)
6743 (if (> (current-column) ind)
6744 (setq ind (current-column)))
6745 (goto-char (match-end 0)))
6749 ;; No lineup-string found
6752 (skip-chars-backward " \t")
6753 (1+ (current-column))))))
6755 (defun verilog-comment-depth (type val)
6756 "A useful mode debugging aide. TYPE and VAL are comments for insertion."
6764 (if (re-search-backward " /\\* \[#-\]# \[a-zA-Z\]+ \[0-9\]+ ## \\*/" b t)
6766 (replace-match " /* -# ## */")
6770 (insert " /* ## ## */"))))
6773 (format "%s %d" type val))))
6779 (defvar verilog-str nil)
6780 (defvar verilog-all nil)
6781 (defvar verilog-pred nil)
6782 (defvar verilog-buffer-to-use nil)
6783 (defvar verilog-flag nil)
6784 (defvar verilog-toggle-completions nil
6785 "True means \\<verilog-mode-map>\\[verilog-complete-word] should try all possible completions one by one.
6786 Repeated use of \\[verilog-complete-word] will show you all of them.
6787 Normally, when there is more than one possible completion,
6788 it displays a list of all possible completions.")
6791 (defvar verilog-type-keywords
6793 "and" "buf" "bufif0" "bufif1" "cmos" "defparam" "inout" "input"
6794 "integer" "localparam" "logic" "mailbox" "nand" "nmos" "nor" "not" "notif0"
6795 "notif1" "or" "output" "parameter" "pmos" "pull0" "pull1" "pulldown" "pullup"
6796 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran" "rtranif0"
6797 "rtranif1" "semaphore" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1"
6798 "triand" "trior" "trireg" "wand" "wire" "wor" "xnor" "xor"
6800 "Keywords for types used when completing a word in a declaration or parmlist.
6801 \(integer, real, reg...)")
6803 (defvar verilog-cpp-keywords
6804 '("module" "macromodule" "primitive" "timescale" "define" "ifdef" "ifndef" "else"
6806 "Keywords to complete when at first word of a line in declarative scope.
6807 \(initial, always, begin, assign...)
6808 The procedures and variables defined within the Verilog program
6809 will be completed at runtime and should not be added to this list.")
6811 (defvar verilog-defun-keywords
6814 "always" "always_comb" "always_ff" "always_latch" "assign"
6815 "begin" "end" "generate" "endgenerate" "module" "endmodule"
6816 "specify" "endspecify" "function" "endfunction" "initial" "final"
6817 "task" "endtask" "primitive" "endprimitive"
6819 verilog-type-keywords)
6820 "Keywords to complete when at first word of a line in declarative scope.
6821 \(initial, always, begin, assign...)
6822 The procedures and variables defined within the Verilog program
6823 will be completed at runtime and should not be added to this list.")
6825 (defvar verilog-block-keywords
6827 "begin" "break" "case" "continue" "else" "end" "endfunction"
6828 "endgenerate" "endinterface" "endpackage" "endspecify" "endtask"
6829 "for" "fork" "if" "join" "join_any" "join_none" "repeat" "return"
6831 "Keywords to complete when at first word of a line in behavioral scope.
6832 \(begin, if, then, else, for, fork...)
6833 The procedures and variables defined within the Verilog program
6834 will be completed at runtime and should not be added to this list.")
6836 (defvar verilog-tf-keywords
6837 '("begin" "break" "fork" "join" "join_any" "join_none" "case" "end" "endtask" "endfunction" "if" "else" "for" "while" "repeat")
6838 "Keywords to complete when at first word of a line in a task or function.
6839 \(begin, if, then, else, for, fork.)
6840 The procedures and variables defined within the Verilog program
6841 will be completed at runtime and should not be added to this list.")
6843 (defvar verilog-case-keywords
6844 '("begin" "fork" "join" "join_any" "join_none" "case" "end" "endcase" "if" "else" "for" "repeat")
6845 "Keywords to complete when at first word of a line in case scope.
6846 \(begin, if, then, else, for, fork...)
6847 The procedures and variables defined within the Verilog program
6848 will be completed at runtime and should not be added to this list.")
6850 (defvar verilog-separator-keywords
6851 '("else" "then" "begin")
6852 "Keywords to complete when NOT standing at the first word of a statement.
6853 \(else, then, begin...)
6854 Variables and function names defined within the Verilog program
6855 will be completed at runtime and should not be added to this list.")
6857 (defvar verilog-gate-ios
6858 ;; All these have an implied {"input"...} at the end
6872 ("pulldown" "output")
6877 ("rtran" "inout" "inout")
6878 ("rtranif0" "inout" "inout")
6879 ("rtranif1" "inout" "inout")
6880 ("tran" "inout" "inout")
6881 ("tranif0" "inout" "inout")
6882 ("tranif1" "inout" "inout")
6885 "Map of direction for each positional argument to each gate primitive.")
6887 (defvar verilog-gate-keywords (mapcar `car verilog-gate-ios)
6888 "Keywords for gate primitives.")
6890 (defun verilog-string-diff (str1 str2)
6891 "Return index of first letter where STR1 and STR2 differs."
6895 (if (or (> (1+ diff) (length str1))
6896 (> (1+ diff) (length str2)))
6898 (or (equal (aref str1 diff) (aref str2 diff))
6900 (setq diff (1+ diff))))))
6902 ;; Calculate all possible completions for functions if argument is `function',
6903 ;; completions for procedures if argument is `procedure' or both functions and
6904 ;; procedures otherwise.
6906 (defun verilog-func-completion (type)
6907 "Build regular expression for module/task/function names.
6908 TYPE is 'module, 'tf for task or function, or t if unknown."
6909 (if (string= verilog-str "")
6910 (setq verilog-str "[a-zA-Z_]"))
6911 (let ((verilog-str (concat (cond
6912 ((eq type 'module) "\\<\\(module\\)\\s +")
6913 ((eq type 'tf) "\\<\\(task\\|function\\)\\s +")
6914 (t "\\<\\(task\\|function\\|module\\)\\s +"))
6915 "\\<\\(" verilog-str "[a-zA-Z0-9_.]*\\)\\>"))
6918 (if (not (looking-at verilog-defun-re))
6919 (verilog-re-search-backward verilog-defun-re nil t))
6922 ;; Search through all reachable functions
6923 (goto-char (point-min))
6924 (while (verilog-re-search-forward verilog-str (point-max) t)
6925 (progn (setq match (buffer-substring (match-beginning 2)
6927 (if (or (null verilog-pred)
6928 (funcall verilog-pred match))
6929 (setq verilog-all (cons match verilog-all)))))
6930 (if (match-beginning 0)
6931 (goto-char (match-beginning 0)))))
6933 (defun verilog-get-completion-decl (end)
6934 "Macro for searching through current declaration (var, type or const)
6935 for matches of `str' and adding the occurrence tp `all' through point END."
6936 (let ((re (or (and verilog-indent-declaration-macros
6937 verilog-declaration-re-2-macro)
6938 verilog-declaration-re-2-no-macro))
6941 (while (and (< (point) end)
6942 (verilog-re-search-forward re end t))
6943 ;; Traverse current line
6944 (setq decl-end (save-excursion (verilog-declaration-end)))
6945 (while (and (verilog-re-search-forward verilog-symbol-re decl-end t)
6946 (not (match-end 1)))
6947 (setq match (buffer-substring (match-beginning 0) (match-end 0)))
6948 (if (string-match (concat "\\<" verilog-str) match)
6949 (if (or (null verilog-pred)
6950 (funcall verilog-pred match))
6951 (setq verilog-all (cons match verilog-all)))))
6955 (defun verilog-type-completion ()
6956 "Calculate all possible completions for types."
6957 (let ((start (point))
6959 ;; Search for all reachable type declarations
6960 (while (or (verilog-beg-of-defun)
6961 (setq goon (not goon)))
6963 (if (and (< start (prog1 (save-excursion (verilog-end-of-defun)
6966 (verilog-re-search-forward
6967 "\\<type\\>\\|\\<\\(begin\\|function\\|procedure\\)\\>"
6969 (not (match-end 1)))
6970 ;; Check current type declaration
6971 (verilog-get-completion-decl start))))))
6973 (defun verilog-var-completion ()
6974 "Calculate all possible completions for variables (or constants)."
6975 (let ((start (point)))
6976 ;; Search for all reachable var declarations
6977 (verilog-beg-of-defun)
6979 ;; Check var declarations
6980 (verilog-get-completion-decl start))))
6982 (defun verilog-keyword-completion (keyword-list)
6983 "Give list of all possible completions of keywords in KEYWORD-LIST."
6985 (if (string-match (concat "\\<" verilog-str) s)
6986 (if (or (null verilog-pred)
6987 (funcall verilog-pred s))
6988 (setq verilog-all (cons s verilog-all)))))
6992 (defun verilog-completion (verilog-str verilog-pred verilog-flag)
6993 "Function passed to `completing-read', `try-completion' or `all-completions'.
6994 Called to get completion on VERILOG-STR. If VERILOG-PRED is non-nil, it
6995 must be a function to be called for every match to check if this should
6996 really be a match. If VERILOG-FLAG is t, the function returns a list of
6997 all possible completions. If VERILOG-FLAG is nil it returns a string,
6998 the longest possible completion, or t if VERILOG-STR is an exact match.
6999 If VERILOG-FLAG is 'lambda, the function returns t if VERILOG-STR is an
7000 exact match, nil otherwise."
7002 (let ((verilog-all nil))
7003 ;; Set buffer to use for searching labels. This should be set
7004 ;; within functions which use verilog-completions
7005 (set-buffer verilog-buffer-to-use)
7007 ;; Determine what should be completed
7008 (let ((state (car (verilog-calculate-indent))))
7009 (cond ((eq state 'defun)
7010 (save-excursion (verilog-var-completion))
7011 (verilog-func-completion 'module)
7012 (verilog-keyword-completion verilog-defun-keywords))
7014 ((eq state 'behavioral)
7015 (save-excursion (verilog-var-completion))
7016 (verilog-func-completion 'module)
7017 (verilog-keyword-completion verilog-defun-keywords))
7020 (save-excursion (verilog-var-completion))
7021 (verilog-func-completion 'tf)
7022 (verilog-keyword-completion verilog-block-keywords))
7025 (save-excursion (verilog-var-completion))
7026 (verilog-func-completion 'tf)
7027 (verilog-keyword-completion verilog-case-keywords))
7030 (save-excursion (verilog-var-completion))
7031 (verilog-func-completion 'tf)
7032 (verilog-keyword-completion verilog-tf-keywords))
7035 (save-excursion (verilog-var-completion))
7036 (verilog-keyword-completion verilog-cpp-keywords))
7038 ((eq state 'cparenexp)
7039 (save-excursion (verilog-var-completion)))
7042 (save-excursion (verilog-var-completion))
7043 (verilog-func-completion 'both)
7044 (verilog-keyword-completion verilog-separator-keywords))))
7046 ;; Now we have built a list of all matches. Give response to caller
7047 (verilog-completion-response))))
7049 (defun verilog-completion-response ()
7050 (cond ((or (equal verilog-flag 'lambda) (null verilog-flag))
7051 ;; This was not called by all-completions
7052 (if (null verilog-all)
7053 ;; Return nil if there was no matching label
7055 ;; Get longest string common in the labels
7056 (let* ((elm (cdr verilog-all))
7057 (match (car verilog-all))
7058 (min (length match))
7060 (if (string= match verilog-str)
7061 ;; Return t if first match was an exact match
7063 (while (not (null elm))
7064 ;; Find longest common string
7065 (if (< (setq tmp (verilog-string-diff match (car elm))) min)
7068 (setq match (substring match 0 min))))
7069 ;; Terminate with match=t if this is an exact match
7070 (if (string= (car elm) verilog-str)
7074 (setq elm (cdr elm)))))
7075 ;; If this is a test just for exact match, return nil ot t
7076 (if (and (equal verilog-flag 'lambda) (not (equal match 't)))
7079 ;; If flag is t, this was called by all-completions. Return
7080 ;; list of all possible completions
7084 (defvar verilog-last-word-numb 0)
7085 (defvar verilog-last-word-shown nil)
7086 (defvar verilog-last-completions nil)
7088 (defun verilog-complete-word ()
7089 "Complete word at current point.
7090 \(See also `verilog-toggle-completions', `verilog-type-keywords',
7091 and `verilog-separator-keywords'.)"
7093 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
7094 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
7095 (verilog-str (buffer-substring b e))
7096 ;; The following variable is used in verilog-completion
7097 (verilog-buffer-to-use (current-buffer))
7098 (allcomp (if (and verilog-toggle-completions
7099 (string= verilog-last-word-shown verilog-str))
7100 verilog-last-completions
7101 (all-completions verilog-str 'verilog-completion)))
7102 (match (if verilog-toggle-completions
7104 verilog-str (mapcar (lambda (elm)
7105 (cons elm 0)) allcomp)))))
7106 ;; Delete old string
7109 ;; Toggle-completions inserts whole labels
7110 (if verilog-toggle-completions
7112 ;; Update entry number in list
7113 (setq verilog-last-completions allcomp
7114 verilog-last-word-numb
7115 (if (>= verilog-last-word-numb (1- (length allcomp)))
7117 (1+ verilog-last-word-numb)))
7118 (setq verilog-last-word-shown (elt allcomp verilog-last-word-numb))
7119 ;; Display next match or same string if no match was found
7120 (if (not (null allcomp))
7121 (insert "" verilog-last-word-shown)
7122 (insert "" verilog-str)
7123 (message "(No match)")))
7124 ;; The other form of completion does not necessarily do that.
7126 ;; Insert match if found, or the original string if no match
7127 (if (or (null match) (equal match 't))
7128 (progn (insert "" verilog-str)
7129 (message "(No match)"))
7131 ;; Give message about current status of completion
7132 (cond ((equal match 't)
7133 (if (not (null (cdr allcomp)))
7134 (message "(Complete but not unique)")
7135 (message "(Sole completion)")))
7136 ;; Display buffer if the current completion didn't help
7137 ;; on completing the label.
7138 ((and (not (null (cdr allcomp))) (= (length verilog-str)
7140 (with-output-to-temp-buffer "*Completions*"
7141 (display-completion-list allcomp))
7142 ;; Wait for a key press. Then delete *Completion* window
7143 (momentary-string-display "" (point))
7144 (delete-window (get-buffer-window (get-buffer "*Completions*")))
7147 (defun verilog-show-completions ()
7148 "Show all possible completions at current point."
7150 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
7151 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
7152 (verilog-str (buffer-substring b e))
7153 ;; The following variable is used in verilog-completion
7154 (verilog-buffer-to-use (current-buffer))
7155 (allcomp (if (and verilog-toggle-completions
7156 (string= verilog-last-word-shown verilog-str))
7157 verilog-last-completions
7158 (all-completions verilog-str 'verilog-completion))))
7159 ;; Show possible completions in a temporary buffer.
7160 (with-output-to-temp-buffer "*Completions*"
7161 (display-completion-list allcomp))
7162 ;; Wait for a key press. Then delete *Completion* window
7163 (momentary-string-display "" (point))
7164 (delete-window (get-buffer-window (get-buffer "*Completions*")))))
7167 (defun verilog-get-default-symbol ()
7168 "Return symbol around current point as a string."
7170 (buffer-substring (progn
7171 (skip-chars-backward " \t")
7172 (skip-chars-backward "a-zA-Z0-9_")
7175 (skip-chars-forward "a-zA-Z0-9_")
7178 (defun verilog-build-defun-re (str &optional arg)
7179 "Return function/task/module starting with STR as regular expression.
7180 With optional second ARG non-nil, STR is the complete name of the instruction."
7182 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "\\)\\>")
7183 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "[a-zA-Z0-9_]*\\)\\>")))
7185 (defun verilog-comp-defun (verilog-str verilog-pred verilog-flag)
7186 "Function passed to `completing-read', `try-completion' or `all-completions'.
7187 Returns a completion on any function name based on VERILOG-STR prefix. If
7188 VERILOG-PRED is non-nil, it must be a function to be called for every match
7189 to check if this should really be a match. If VERILOG-FLAG is t, the
7190 function returns a list of all possible completions. If it is nil it
7191 returns a string, the longest possible completion, or t if VERILOG-STR is
7192 an exact match. If VERILOG-FLAG is 'lambda, the function returns t if
7193 VERILOG-STR is an exact match, nil otherwise."
7195 (let ((verilog-all nil)
7198 ;; Set buffer to use for searching labels. This should be set
7199 ;; within functions which use verilog-completions
7200 (set-buffer verilog-buffer-to-use)
7202 (let ((verilog-str verilog-str))
7203 ;; Build regular expression for functions
7204 (if (string= verilog-str "")
7205 (setq verilog-str (verilog-build-defun-re "[a-zA-Z_]"))
7206 (setq verilog-str (verilog-build-defun-re verilog-str)))
7207 (goto-char (point-min))
7209 ;; Build a list of all possible completions
7210 (while (verilog-re-search-forward verilog-str nil t)
7211 (setq match (buffer-substring (match-beginning 2) (match-end 2)))
7212 (if (or (null verilog-pred)
7213 (funcall verilog-pred match))
7214 (setq verilog-all (cons match verilog-all)))))
7216 ;; Now we have built a list of all matches. Give response to caller
7217 (verilog-completion-response))))
7219 (defun verilog-goto-defun ()
7220 "Move to specified Verilog module/interface/task/function.
7221 The default is a name found in the buffer around point.
7222 If search fails, other files are checked based on
7223 `verilog-library-flags'."
7225 (let* ((default (verilog-get-default-symbol))
7226 ;; The following variable is used in verilog-comp-function
7227 (verilog-buffer-to-use (current-buffer))
7228 (label (if (not (string= default ""))
7229 ;; Do completion with default
7230 (completing-read (concat "Goto-Label: (default "
7232 'verilog-comp-defun nil nil "")
7233 ;; There is no default value. Complete without it
7234 (completing-read "Goto-Label: "
7235 'verilog-comp-defun nil nil "")))
7237 ;; Make sure library paths are correct, in case need to resolve module
7238 (verilog-auto-reeval-locals)
7239 (verilog-getopt-flags)
7240 ;; If there was no response on prompt, use default value
7241 (if (string= label "")
7242 (setq label default))
7243 ;; Goto right place in buffer if label is not an empty string
7244 (or (string= label "")
7247 (goto-char (point-min))
7249 (re-search-forward (verilog-build-defun-re label t) nil t)))
7252 (beginning-of-line))
7254 (verilog-goto-defun-file label))))
7256 ;; Eliminate compile warning
7257 (defvar occur-pos-list)
7259 (defun verilog-showscopes ()
7260 "List all scopes in this module."
7262 (let ((buffer (current-buffer))
7266 (prevpos (point-min))
7267 (final-context-start (make-marker))
7268 (regexp "\\(module\\s-+\\w+\\s-*(\\)\\|\\(\\w+\\s-+\\w+\\s-*(\\)"))
7269 (with-output-to-temp-buffer "*Occur*"
7271 (message (format "Searching for %s ..." regexp))
7272 ;; Find next match, but give up if prev match was at end of buffer.
7273 (while (and (not (= prevpos (point-max)))
7274 (verilog-re-search-forward regexp nil t))
7275 (goto-char (match-beginning 0))
7278 (setq linenum (+ linenum (count-lines prevpos (point)))))
7279 (setq prevpos (point))
7280 (goto-char (match-end 0))
7281 (let* ((start (save-excursion
7282 (goto-char (match-beginning 0))
7283 (forward-line (if (< nlines 0) nlines (- nlines)))
7285 (end (save-excursion
7286 (goto-char (match-end 0))
7288 (forward-line (1+ nlines))
7291 (tag (format "%3d" linenum))
7292 (empty (make-string (length tag) ?\ ))
7295 (setq tem (make-marker))
7296 (set-marker tem (point))
7297 (set-buffer standard-output)
7298 (setq occur-pos-list (cons tem occur-pos-list))
7299 (or first (zerop nlines)
7300 (insert "--------\n"))
7302 (insert-buffer-substring buffer start end)
7303 (backward-char (- end start))
7304 (setq tem (if (< nlines 0) (- nlines) nlines))
7308 (setq tem (1- tem)))
7309 (let ((this-linenum linenum))
7310 (set-marker final-context-start
7311 (+ (point) (- (match-end 0) (match-beginning 0))))
7312 (while (< (point) final-context-start)
7314 (setq tag (format "%3d" this-linenum)))
7315 (insert tag ?:)))))))
7316 (set-buffer-modified-p nil))))
7319 ;; Highlight helper functions
7320 (defconst verilog-directive-regexp "\\(translate\\|coverage\\|lint\\)_")
7321 (defun verilog-within-translate-off ()
7322 "Return point if within translate-off region, else nil."
7323 (and (save-excursion
7325 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "\\(on\\|off\\)\\>")
7327 (equal "off" (match-string 2))
7330 (defun verilog-start-translate-off (limit)
7331 "Return point before translate-off directive if before LIMIT, else nil."
7332 (when (re-search-forward
7333 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
7335 (match-beginning 0)))
7337 (defun verilog-back-to-start-translate-off (limit)
7338 "Return point before translate-off directive if before LIMIT, else nil."
7339 (when (re-search-backward
7340 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
7342 (match-beginning 0)))
7344 (defun verilog-end-translate-off (limit)
7345 "Return point after translate-on directive if before LIMIT, else nil."
7347 (re-search-forward (concat
7348 "//\\s-*.*\\s-*" verilog-directive-regexp "on\\>") limit t))
7350 (defun verilog-match-translate-off (limit)
7351 "Match a translate-off block, setting `match-data' and returning t, else nil.
7352 Bound search by LIMIT."
7353 (when (< (point) limit)
7354 (let ((start (or (verilog-within-translate-off)
7355 (verilog-start-translate-off limit)))
7356 (case-fold-search t))
7358 (let ((end (or (verilog-end-translate-off limit) limit)))
7359 (set-match-data (list start end))
7360 (goto-char end))))))
7362 (defun verilog-font-lock-match-item (limit)
7363 "Match, and move over, any declaration item after point.
7364 Bound search by LIMIT. Adapted from
7365 `font-lock-match-c-style-declaration-item-and-skip-to-next'."
7368 (narrow-to-region (point-min) limit)
7370 (when (looking-at "\\s-*\\([a-zA-Z]\\w*\\)")
7372 (goto-char (match-end 1))
7373 ;; move to next item
7374 (if (looking-at "\\(\\s-*,\\)")
7375 (goto-char (match-end 1))
7380 ;; Added by Subbu Meiyappan for Header
7382 (defun verilog-header ()
7383 "Insert a standard Verilog file header.
7384 See also `verilog-sk-header' for an alternative format."
7386 (let ((start (point)))
7388 //-----------------------------------------------------------------------------
7390 // Project : <project>
7391 //-----------------------------------------------------------------------------
7392 // File : <filename>
7393 // Author : <author>
7394 // Created : <credate>
7395 // Last modified : <moddate>
7396 //-----------------------------------------------------------------------------
7399 //-----------------------------------------------------------------------------
7400 // Copyright (c) <copydate> by <company> This model is the confidential and
7401 // proprietary property of <company> and the possession or use of this
7402 // file requires a written license from <company>.
7403 //------------------------------------------------------------------------------
7404 // Modification history :
7406 //-----------------------------------------------------------------------------
7410 (search-forward "<filename>")
7411 (replace-match (buffer-name) t t)
7412 (search-forward "<author>") (replace-match "" t t)
7413 (insert (user-full-name))
7414 (insert " <" (user-login-name) "@" (system-name) ">")
7415 (search-forward "<credate>") (replace-match "" t t)
7416 (verilog-insert-date)
7417 (search-forward "<moddate>") (replace-match "" t t)
7418 (verilog-insert-date)
7419 (search-forward "<copydate>") (replace-match "" t t)
7420 (verilog-insert-year)
7421 (search-forward "<modhist>") (replace-match "" t t)
7422 (verilog-insert-date)
7423 (insert " : created")
7426 (setq string (read-string "title: "))
7427 (search-forward "<title>")
7428 (replace-match string t t)
7429 (setq string (read-string "project: " verilog-project))
7430 (setq verilog-project string)
7431 (search-forward "<project>")
7432 (replace-match string t t)
7433 (setq string (read-string "Company: " verilog-company))
7434 (setq verilog-company string)
7435 (search-forward "<company>")
7436 (replace-match string t t)
7437 (search-forward "<company>")
7438 (replace-match string t t)
7439 (search-forward "<company>")
7440 (replace-match string t t)
7441 (search-backward "<description>")
7442 (replace-match "" t t))))
7444 ;; verilog-header Uses the verilog-insert-date function
7446 (defun verilog-insert-date ()
7447 "Insert date from the system."
7449 (if verilog-date-scientific-format
7450 (insert (format-time-string "%Y/%m/%d"))
7451 (insert (format-time-string "%d.%m.%Y"))))
7453 (defun verilog-insert-year ()
7454 "Insert year from the system."
7456 (insert (format-time-string "%Y")))
7460 ;; Signal list parsing
7463 ;; Elements of a signal list
7464 ;; Unfortunately we use 'assoc' on this, so can't be a vector
7465 (defsubst verilog-sig-new (name bits comment mem enum signed type multidim modport)
7466 (list name bits comment mem enum signed type multidim modport))
7467 (defsubst verilog-sig-name (sig)
7469 (defsubst verilog-sig-bits (sig)
7471 (defsubst verilog-sig-comment (sig)
7473 (defsubst verilog-sig-memory (sig)
7475 (defsubst verilog-sig-enum (sig)
7477 (defsubst verilog-sig-signed (sig)
7479 (defsubst verilog-sig-type (sig)
7481 (defsubst verilog-sig-type-set (sig type)
7482 (setcar (nthcdr 6 sig) type))
7483 (defsubst verilog-sig-multidim (sig)
7485 (defsubst verilog-sig-multidim-string (sig)
7486 (if (verilog-sig-multidim sig)
7487 (let ((str "") (args (verilog-sig-multidim sig)))
7489 (setq str (concat str (car args)))
7490 (setq args (cdr args)))
7492 (defsubst verilog-sig-modport (sig)
7494 (defsubst verilog-sig-width (sig)
7495 (verilog-make-width-expression (verilog-sig-bits sig)))
7497 (defsubst verilog-alw-new (outputs-del outputs-imm temps inputs)
7498 (vector outputs-del outputs-imm temps inputs))
7499 (defsubst verilog-alw-get-outputs-delayed (sigs)
7501 (defsubst verilog-alw-get-outputs-immediate (sigs)
7503 (defsubst verilog-alw-get-temps (sigs)
7505 (defsubst verilog-alw-get-inputs (sigs)
7507 (defsubst verilog-alw-get-uses-delayed (sigs)
7510 (defsubst verilog-modport-new (name clockings decls)
7511 (list name clockings decls))
7512 (defsubst verilog-modport-name (sig)
7514 (defsubst verilog-modport-clockings (sig)
7515 (nth 1 sig)) ;; Returns list of names
7516 (defsubst verilog-modport-clockings-add (sig val)
7517 (setcar (nthcdr 1 sig) (cons val (nth 1 sig))))
7518 (defsubst verilog-modport-decls (sig)
7519 (nth 2 sig)) ;; Returns verilog-decls-* structure
7520 (defsubst verilog-modport-decls-set (sig val)
7521 (setcar (nthcdr 2 sig) val))
7523 (defsubst verilog-modi-new (name fob pt type)
7524 (vector name fob pt type))
7525 (defsubst verilog-modi-name (modi)
7527 (defsubst verilog-modi-file-or-buffer (modi)
7529 (defsubst verilog-modi-get-point (modi)
7531 (defsubst verilog-modi-get-type (modi) ;; "module" or "interface"
7533 (defsubst verilog-modi-get-decls (modi)
7534 (verilog-modi-cache-results modi 'verilog-read-decls))
7535 (defsubst verilog-modi-get-sub-decls (modi)
7536 (verilog-modi-cache-results modi 'verilog-read-sub-decls))
7538 ;; Signal reading for given module
7539 ;; Note these all take modi's - as returned from verilog-modi-current
7540 (defsubst verilog-decls-new (out inout in vars modports assigns consts gparams interfaces)
7541 (vector out inout in vars modports assigns consts gparams interfaces))
7542 (defsubst verilog-decls-append (a b)
7543 (cond ((not a) b) ((not b) a)
7544 (t (vector (append (aref a 0) (aref b 0)) (append (aref a 1) (aref b 1))
7545 (append (aref a 2) (aref b 2)) (append (aref a 3) (aref b 3))
7546 (append (aref a 4) (aref b 4)) (append (aref a 5) (aref b 5))
7547 (append (aref a 6) (aref b 6)) (append (aref a 7) (aref b 7))
7548 (append (aref a 8) (aref b 8))))))
7549 (defsubst verilog-decls-get-outputs (decls)
7551 (defsubst verilog-decls-get-inouts (decls)
7553 (defsubst verilog-decls-get-inputs (decls)
7555 (defsubst verilog-decls-get-vars (decls)
7557 (defsubst verilog-decls-get-modports (decls) ;; Also for clocking blocks; contains another verilog-decls struct
7558 (aref decls 4)) ;; Returns verilog-modport* structure
7559 (defsubst verilog-decls-get-assigns (decls)
7561 (defsubst verilog-decls-get-consts (decls)
7563 (defsubst verilog-decls-get-gparams (decls)
7565 (defsubst verilog-decls-get-interfaces (decls)
7569 (defsubst verilog-subdecls-new (out inout in intf intfd)
7570 (vector out inout in intf intfd))
7571 (defsubst verilog-subdecls-get-outputs (subdecls)
7573 (defsubst verilog-subdecls-get-inouts (subdecls)
7575 (defsubst verilog-subdecls-get-inputs (subdecls)
7577 (defsubst verilog-subdecls-get-interfaces (subdecls)
7579 (defsubst verilog-subdecls-get-interfaced (subdecls)
7582 (defun verilog-signals-from-signame (signame-list)
7583 "Return signals in standard form from SIGNAME-LIST, a simple list of names."
7584 (mapcar (lambda (name) (verilog-sig-new name nil nil nil nil nil nil nil nil))
7587 (defun verilog-signals-in (in-list not-list)
7588 "Return list of signals in IN-LIST that are also in NOT-LIST.
7589 Also remove any duplicates in IN-LIST.
7590 Signals must be in standard (base vector) form."
7591 ;; This function is hot, so implemented as O(1)
7592 (cond ((eval-when-compile (fboundp 'make-hash-table))
7593 (let ((ht (make-hash-table :test 'equal :rehash-size 4.0))
7594 (ht-not (make-hash-table :test 'equal :rehash-size 4.0))
7597 (puthash (car (car not-list)) t ht-not)
7598 (setq not-list (cdr not-list)))
7600 (when (and (gethash (verilog-sig-name (car in-list)) ht-not)
7601 (not (gethash (verilog-sig-name (car in-list)) ht)))
7602 (setq out-list (cons (car in-list) out-list))
7603 (puthash (verilog-sig-name (car in-list)) t ht))
7604 (setq in-list (cdr in-list)))
7605 (nreverse out-list)))
7606 ;; Slower Fallback if no hash tables (pre Emacs 21.1/XEmacs 21.4)
7610 (if (and (assoc (verilog-sig-name (car in-list)) not-list)
7611 (not (assoc (verilog-sig-name (car in-list)) out-list)))
7612 (setq out-list (cons (car in-list) out-list)))
7613 (setq in-list (cdr in-list)))
7614 (nreverse out-list)))))
7615 ;;(verilog-signals-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("C" "")))
7617 (defun verilog-signals-not-in (in-list not-list)
7618 "Return list of signals in IN-LIST that aren't also in NOT-LIST.
7619 Also remove any duplicates in IN-LIST.
7620 Signals must be in standard (base vector) form."
7621 ;; This function is hot, so implemented as O(1)
7622 (cond ((eval-when-compile (fboundp 'make-hash-table))
7623 (let ((ht (make-hash-table :test 'equal :rehash-size 4.0))
7626 (puthash (car (car not-list)) t ht)
7627 (setq not-list (cdr not-list)))
7629 (when (not (gethash (verilog-sig-name (car in-list)) ht))
7630 (setq out-list (cons (car in-list) out-list))
7631 (puthash (verilog-sig-name (car in-list)) t ht))
7632 (setq in-list (cdr in-list)))
7633 (nreverse out-list)))
7634 ;; Slower Fallback if no hash tables (pre Emacs 21.1/XEmacs 21.4)
7638 (if (and (not (assoc (verilog-sig-name (car in-list)) not-list))
7639 (not (assoc (verilog-sig-name (car in-list)) out-list)))
7640 (setq out-list (cons (car in-list) out-list)))
7641 (setq in-list (cdr in-list)))
7642 (nreverse out-list)))))
7643 ;;(verilog-signals-not-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" "")))
7645 (defun verilog-signals-memory (in-list)
7646 "Return list of signals in IN-LIST that are memorized (multidimensional)."
7649 (if (nth 3 (car in-list))
7650 (setq out-list (cons (car in-list) out-list)))
7651 (setq in-list (cdr in-list)))
7653 ;;(verilog-signals-memory '(("A" nil nil "[3:0]")) '(("B" nil nil nil)))
7655 (defun verilog-signals-sort-compare (a b)
7656 "Compare signal A and B for sorting."
7657 (string< (verilog-sig-name a) (verilog-sig-name b)))
7659 (defun verilog-signals-not-params (in-list)
7660 "Return list of signals in IN-LIST that aren't parameters or numeric constants."
7663 (unless (boundp (intern (concat "vh-" (verilog-sig-name (car in-list)))))
7664 (setq out-list (cons (car in-list) out-list)))
7665 (setq in-list (cdr in-list)))
7666 (nreverse out-list)))
7668 (defun verilog-signals-with (func in-list)
7669 "Return IN-LIST with only signals where FUNC passed each signal is true."
7672 (when (funcall func (car in-list))
7673 (setq out-list (cons (car in-list) out-list)))
7674 (setq in-list (cdr in-list)))
7675 (nreverse out-list)))
7677 (defun verilog-signals-combine-bus (in-list)
7678 "Return a list of signals in IN-LIST, with buses combined.
7679 Duplicate signals are also removed. For example A[2] and A[1] become A[2:1]."
7682 sig highbit lowbit ; Temp information about current signal
7683 sv-name sv-highbit sv-lowbit ; Details about signal we are forming
7684 sv-comment sv-memory sv-enum sv-signed sv-type sv-multidim sv-busstring
7687 ;; Shove signals so duplicated signals will be adjacent
7688 (setq in-list (sort in-list `verilog-signals-sort-compare))
7690 (setq sig (car in-list))
7691 ;; No current signal; form from existing details
7693 (setq sv-name (verilog-sig-name sig)
7696 sv-comment (verilog-sig-comment sig)
7697 sv-memory (verilog-sig-memory sig)
7698 sv-enum (verilog-sig-enum sig)
7699 sv-signed (verilog-sig-signed sig)
7700 sv-type (verilog-sig-type sig)
7701 sv-multidim (verilog-sig-multidim sig)
7702 sv-modport (verilog-sig-modport sig)
7705 ;; Extract bus details
7706 (setq bus (verilog-sig-bits sig))
7707 (setq bus (and bus (verilog-simplify-range-expression bus)))
7709 (or (and (string-match "\\[\\([0-9]+\\):\\([0-9]+\\)\\]" bus)
7710 (setq highbit (string-to-number (match-string 1 bus))
7711 lowbit (string-to-number
7712 (match-string 2 bus))))
7713 (and (string-match "\\[\\([0-9]+\\)\\]" bus)
7714 (setq highbit (string-to-number (match-string 1 bus))
7716 ;; Combine bits in bus
7718 (setq sv-highbit (max highbit sv-highbit)
7719 sv-lowbit (min lowbit sv-lowbit))
7720 (setq sv-highbit highbit
7723 ;; String, probably something like `preproc:0
7724 (setq sv-busstring bus)))
7725 ;; Peek ahead to next signal
7726 (setq in-list (cdr in-list))
7727 (setq sig (car in-list))
7728 (cond ((and sig (equal sv-name (verilog-sig-name sig)))
7729 ;; Combine with this signal
7730 (when (and sv-busstring
7731 (not (equal sv-busstring (verilog-sig-bits sig))))
7732 (when nil ;; Debugging
7733 (message (concat "Warning, can't merge into single bus "
7735 ", the AUTOs may be wrong")))
7736 (setq buswarn ", Couldn't Merge"))
7737 (if (verilog-sig-comment sig) (setq combo ", ..."))
7738 (setq sv-memory (or sv-memory (verilog-sig-memory sig))
7739 sv-enum (or sv-enum (verilog-sig-enum sig))
7740 sv-signed (or sv-signed (verilog-sig-signed sig))
7741 sv-type (or sv-type (verilog-sig-type sig))
7742 sv-multidim (or sv-multidim (verilog-sig-multidim sig))
7743 sv-modport (or sv-modport (verilog-sig-modport sig))))
7744 ;; Doesn't match next signal, add to queue, zero in prep for next
7745 ;; Note sig may also be nil for the last signal in the list
7748 (cons (verilog-sig-new
7752 (concat "[" (int-to-string sv-highbit) ":"
7753 (int-to-string sv-lowbit) "]")))
7754 (concat sv-comment combo buswarn)
7755 sv-memory sv-enum sv-signed sv-type sv-multidim sv-modport)
7761 (defun verilog-sig-tieoff (sig)
7762 "Return tieoff expression for given SIG, with appropriate width.
7763 Tieoff value uses `verilog-active-low-regexp' and
7764 `verilog-auto-reset-widths'."
7766 (if (and verilog-active-low-regexp
7767 (string-match verilog-active-low-regexp (verilog-sig-name sig)))
7769 (cond ((not verilog-auto-reset-widths)
7771 ((equal verilog-auto-reset-widths 'unbased)
7773 ;; Else presume verilog-auto-reset-widths is true
7775 (let* ((width (verilog-sig-width sig)))
7776 (if (string-match "^[0-9]+$" width)
7777 (concat width (if (verilog-sig-signed sig) "'sh0" "'h0"))
7778 (concat "{" width "{1'b0}}")))))))
7784 (defun verilog-decls-princ (decls &optional header prefix)
7785 "For debug, dump the `verilog-read-decls' structure DECLS."
7787 (if header (princ header))
7788 (setq prefix (or prefix ""))
7789 (verilog-signals-princ (verilog-decls-get-outputs decls)
7790 (concat prefix "Outputs:\n") (concat prefix " "))
7791 (verilog-signals-princ (verilog-decls-get-inouts decls)
7792 (concat prefix "Inout:\n") (concat prefix " "))
7793 (verilog-signals-princ (verilog-decls-get-inputs decls)
7794 (concat prefix "Inputs:\n") (concat prefix " "))
7795 (verilog-signals-princ (verilog-decls-get-vars decls)
7796 (concat prefix "Vars:\n") (concat prefix " "))
7797 (verilog-signals-princ (verilog-decls-get-assigns decls)
7798 (concat prefix "Assigns:\n") (concat prefix " "))
7799 (verilog-signals-princ (verilog-decls-get-consts decls)
7800 (concat prefix "Consts:\n") (concat prefix " "))
7801 (verilog-signals-princ (verilog-decls-get-gparams decls)
7802 (concat prefix "Gparams:\n") (concat prefix " "))
7803 (verilog-signals-princ (verilog-decls-get-interfaces decls)
7804 (concat prefix "Interfaces:\n") (concat prefix " "))
7805 (verilog-modport-princ (verilog-decls-get-modports decls)
7806 (concat prefix "Modports:\n") (concat prefix " "))
7809 (defun verilog-signals-princ (signals &optional header prefix)
7810 "For debug, dump internal SIGNALS structures, with HEADER and PREFIX."
7812 (if header (princ header))
7814 (let ((sig (car signals)))
7815 (setq signals (cdr signals))
7817 (princ "\"") (princ (verilog-sig-name sig)) (princ "\"")
7818 (princ " bits=") (princ (verilog-sig-bits sig))
7819 (princ " cmt=") (princ (verilog-sig-comment sig))
7820 (princ " mem=") (princ (verilog-sig-memory sig))
7821 (princ " enum=") (princ (verilog-sig-enum sig))
7822 (princ " sign=") (princ (verilog-sig-signed sig))
7823 (princ " type=") (princ (verilog-sig-type sig))
7824 (princ " dim=") (princ (verilog-sig-multidim sig))
7825 (princ " modp=") (princ (verilog-sig-modport sig))
7828 (defun verilog-modport-princ (modports &optional header prefix)
7829 "For debug, dump internal MODPORT structures, with HEADER and PREFIX."
7831 (if header (princ header))
7833 (let ((sig (car modports)))
7834 (setq modports (cdr modports))
7836 (princ "\"") (princ (verilog-modport-name sig)) (princ "\"")
7837 (princ " clockings=") (princ (verilog-modport-clockings sig))
7839 (verilog-decls-princ (verilog-modport-decls sig)
7840 (concat prefix " syms:\n")
7841 (concat prefix " "))))))
7844 ;; Port/Wire/Etc Reading
7847 (defun verilog-read-inst-backward-name ()
7848 "Internal. Move point back to beginning of inst-name."
7849 (verilog-backward-open-paren)
7852 (verilog-re-search-backward-quick "\\()\\|\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil) ; ] isn't word boundary
7853 (cond ((looking-at ")")
7854 (verilog-backward-open-paren))
7855 (t (setq done t)))))
7856 (while (looking-at "\\]")
7857 (verilog-backward-open-bracket)
7858 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil))
7859 (skip-chars-backward "a-zA-Z0-9`_$"))
7861 (defun verilog-read-inst-module-matcher ()
7862 "Set match data 0 with module_name when point is inside instantiation."
7863 (verilog-read-inst-backward-name)
7864 ;; Skip over instantiation name
7865 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary
7866 ;; Check for parameterized instantiations
7867 (when (looking-at ")")
7868 (verilog-backward-open-paren)
7869 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil))
7870 (skip-chars-backward "a-zA-Z0-9'_$")
7871 (looking-at "[a-zA-Z0-9`_\$]+")
7872 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
7873 (buffer-substring-no-properties (match-beginning 0) (match-end 0))
7874 ;; Caller assumes match-beginning/match-end is still set
7877 (defun verilog-read-inst-module ()
7878 "Return module_name when point is inside instantiation."
7880 (verilog-read-inst-module-matcher)))
7882 (defun verilog-read-inst-name ()
7883 "Return instance_name when point is inside instantiation."
7885 (verilog-read-inst-backward-name)
7886 (looking-at "[a-zA-Z0-9`_\$]+")
7887 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
7888 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
7890 (defun verilog-read-module-name ()
7891 "Return module name when after its ( or ;."
7893 (re-search-backward "[(;]")
7894 ;; Due to "module x import y (" we must search for declaration begin
7895 (verilog-re-search-backward-quick verilog-defun-re nil nil)
7896 (goto-char (match-end 0))
7897 (verilog-re-search-forward-quick "\\b[a-zA-Z0-9`_\$]+" nil nil)
7898 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
7899 (verilog-symbol-detick
7900 (buffer-substring-no-properties (match-beginning 0) (match-end 0)) t)))
7902 (defun verilog-read-inst-param-value ()
7903 "Return list of parameters and values when point is inside instantiation."
7905 (verilog-read-inst-backward-name)
7906 ;; Skip over instantiation name
7907 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary
7908 ;; If there are parameterized instantiations
7909 (when (looking-at ")")
7910 (let ((end-pt (point))
7912 param-name paren-beg-pt param-value)
7913 (verilog-backward-open-paren)
7914 (while (verilog-re-search-forward-quick "\\." end-pt t)
7915 (verilog-re-search-forward-quick "\\([a-zA-Z0-9`_\$]\\)" nil nil)
7916 (skip-chars-backward "a-zA-Z0-9'_$")
7917 (looking-at "[a-zA-Z0-9`_\$]+")
7918 (setq param-name (buffer-substring-no-properties
7919 (match-beginning 0) (match-end 0)))
7920 (verilog-re-search-forward-quick "(" nil nil)
7921 (setq paren-beg-pt (point))
7922 (verilog-forward-close-paren)
7923 (setq param-value (verilog-string-remove-spaces
7924 (buffer-substring-no-properties
7925 paren-beg-pt (1- (point)))))
7926 (setq params (cons (list param-name param-value) params)))
7929 (defun verilog-read-auto-params (num-param &optional max-param)
7930 "Return parameter list inside auto.
7931 Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters."
7934 ;; /*AUTOPUNT("parameter", "parameter")*/
7936 (while (looking-at "(?\\s *\"\\([^\"]*\\)\"\\s *,?")
7937 (setq olist (cons (match-string 1) olist))
7938 (goto-char (match-end 0))))
7939 (or (eq nil num-param)
7940 (<= num-param (length olist))
7941 (error "%s: Expected %d parameters" (verilog-point-text) num-param))
7942 (if (eq max-param nil) (setq max-param num-param))
7943 (or (eq nil max-param)
7944 (>= max-param (length olist))
7945 (error "%s: Expected <= %d parameters" (verilog-point-text) max-param))
7948 (defun verilog-read-decls ()
7949 "Compute signal declaration information for the current module at point.
7950 Return an array of [outputs inouts inputs wire reg assign const]."
7951 (let ((end-mod-point (or (verilog-get-end-of-defun t) (point-max)))
7952 (functask 0) (paren 0) (sig-paren 0) (v2kargs-ok t)
7953 in-modport in-clocking ptype ign-prop
7954 sigs-in sigs-out sigs-inout sigs-var sigs-assign sigs-const
7955 sigs-gparam sigs-intf sigs-modports
7956 vec expect-signal keywd newsig rvalue enum io signed typedefed multidim
7960 (verilog-beg-of-defun-quick)
7961 (setq sigs-const (verilog-read-auto-constants (point) end-mod-point))
7962 (while (< (point) end-mod-point)
7963 ;;(if dbg (setq dbg (concat dbg (format "Pt %s Vec %s C%c Kwd'%s'\n" (point) vec (following-char) keywd))))
7966 (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
7967 (setq enum (match-string 2)))
7968 (search-forward "\n"))
7969 ((looking-at "/\\*")
7971 (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
7972 (setq enum (match-string 2)))
7973 (or (search-forward "*/")
7974 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
7975 ((looking-at "(\\*")
7976 ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
7978 (or (search-forward "*)")
7979 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
7980 ((eq ?\" (following-char))
7981 (or (re-search-forward "[^\\]\"" nil t) ;; don't forward-char first, since we look for a non backslash first
7982 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
7983 ((eq ?\; (following-char))
7984 (when (and in-modport (not (eq in-modport t))) ;; end of a modport declaration
7985 (verilog-modport-decls-set
7987 (verilog-decls-new sigs-out sigs-inout sigs-in
7988 nil nil nil nil nil nil))
7989 ;; Pop from varstack to restore state to pre-clocking
7990 (setq tmp (car varstack)
7991 varstack (cdr varstack)
7992 sigs-out (aref tmp 0)
7993 sigs-inout (aref tmp 1)
7994 sigs-in (aref tmp 2)))
7995 (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil
7996 v2kargs-ok nil in-modport nil ign-prop nil)
7998 ((eq ?= (following-char))
7999 (setq rvalue t newsig nil)
8001 ((and (eq ?, (following-char))
8002 (eq paren sig-paren))
8005 ;; ,'s can occur inside {} & funcs
8006 ((looking-at "[{(]")
8007 (setq paren (1+ paren))
8009 ((looking-at "[})]")
8010 (setq paren (1- paren))
8012 (when (< paren sig-paren)
8013 (setq expect-signal nil))) ; ) that ends variables inside v2k arg list
8014 ((looking-at "\\s-*\\(\\[[^]]+\\]\\)")
8015 (goto-char (match-end 0))
8016 (cond (newsig ; Memory, not just width. Patch last signal added's memory (nth 3)
8017 (setcar (cdr (cdr (cdr newsig)))
8018 (if (verilog-sig-memory newsig)
8019 (concat (verilog-sig-memory newsig) (match-string 1))
8021 (vec ;; Multidimensional
8022 (setq multidim (cons vec multidim))
8023 (setq vec (verilog-string-replace-matches
8024 "\\s-+" "" nil nil (match-string 1))))
8026 (setq vec (verilog-string-replace-matches
8027 "\\s-+" "" nil nil (match-string 1))))))
8028 ;; Normal or escaped identifier -- note we remember the \ if escaped
8029 ((looking-at "\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
8030 (goto-char (match-end 0))
8031 (setq keywd (match-string 1))
8032 (when (string-match "^\\\\" (match-string 1))
8033 (setq keywd (concat keywd " "))) ;; Escaped ID needs space at end
8034 ;; Add any :: package names to same identifier
8035 (while (looking-at "\\s-*::\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
8036 (goto-char (match-end 0))
8037 (setq keywd (concat keywd "::" (match-string 1)))
8038 (when (string-match "^\\\\" (match-string 1))
8039 (setq keywd (concat keywd " ")))) ;; Escaped ID needs space at end
8040 (cond ((equal keywd "input")
8041 (setq vec nil enum nil rvalue nil newsig nil signed nil
8042 typedefed nil multidim nil ptype nil modport nil
8043 expect-signal 'sigs-in io t sig-paren paren))
8044 ((equal keywd "output")
8045 (setq vec nil enum nil rvalue nil newsig nil signed nil
8046 typedefed nil multidim nil ptype nil modport nil
8047 expect-signal 'sigs-out io t sig-paren paren))
8048 ((equal keywd "inout")
8049 (setq vec nil enum nil rvalue nil newsig nil signed nil
8050 typedefed nil multidim nil ptype nil modport nil
8051 expect-signal 'sigs-inout io t sig-paren paren))
8052 ((equal keywd "parameter")
8053 (setq vec nil enum nil rvalue nil signed nil
8054 typedefed nil multidim nil ptype nil modport nil
8055 expect-signal 'sigs-gparam io t sig-paren paren))
8056 ((member keywd '("wire" "reg" ; Fast
8058 "tri" "tri0" "tri1" "triand" "trior" "trireg"
8059 "uwire" "wand" "wor"
8060 ;; integer_atom_type
8061 "byte" "shortint" "int" "longint" "integer" "time"
8063 ;; integer_vector_type - "reg" above
8066 "shortreal" "real" "realtime"
8068 "string" "event" "chandle"))
8071 (if typedefed (concat typedefed " " keywd) keywd)))
8072 (t (setq vec nil enum nil rvalue nil signed nil
8073 typedefed nil multidim nil sig-paren paren
8074 expect-signal 'sigs-var modport nil))))
8075 ((equal keywd "assign")
8076 (setq vec nil enum nil rvalue nil signed nil
8077 typedefed nil multidim nil ptype nil modport nil
8078 expect-signal 'sigs-assign sig-paren paren))
8079 ((member keywd '("localparam" "genvar"))
8081 (setq vec nil enum nil rvalue nil signed nil
8082 typedefed nil multidim nil ptype nil modport nil
8083 expect-signal 'sigs-const sig-paren paren)))
8084 ((member keywd '("signed" "unsigned"))
8085 (setq signed keywd))
8086 ((member keywd '("assert" "assume" "cover" "expect" "restrict"))
8088 ((member keywd '("class" "covergroup" "function"
8089 "property" "randsequence" "sequence" "task"))
8091 (setq functask (1+ functask))))
8092 ((member keywd '("endclass" "endgroup" "endfunction"
8093 "endproperty" "endsequence" "endtask"))
8094 (setq functask (1- functask)))
8095 ((equal keywd "modport")
8096 (setq in-modport t))
8097 ((equal keywd "clocking")
8098 (setq in-clocking t))
8099 ((equal keywd "type")
8101 ;; Ifdef? Ignore name of define
8102 ((member keywd '("`ifdef" "`ifndef" "`elsif"))
8106 (verilog-typedef-name-p keywd))
8107 (setq typedefed keywd))
8108 ;; Interface with optional modport in v2k arglist?
8109 ;; Skip over parsing modport, and take the interface name as the type
8113 (looking-at "\\s-*\\(\\.\\(\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*\\)\\|\\)\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*"))
8114 (when (match-end 2) (goto-char (match-end 2)))
8115 (setq vec nil enum nil rvalue nil signed nil
8116 typedefed keywd multidim nil ptype nil modport (match-string 2)
8117 newsig nil sig-paren paren
8118 expect-signal 'sigs-intf io t ))
8119 ;; Ignore dotted LHS assignments: "assign foo.bar = z;"
8120 ((looking-at "\\s-*\\.")
8121 (goto-char (match-end 0))
8123 (setq expect-signal nil)))
8124 ;; "modport <keywd>"
8125 ((and (eq in-modport t)
8126 (not (member keywd verilog-keywords)))
8127 (setq in-modport (verilog-modport-new keywd nil nil))
8128 (setq sigs-modports (cons in-modport sigs-modports))
8129 ;; Push old sig values to stack and point to new signal list
8130 (setq varstack (cons (vector sigs-out sigs-inout sigs-in)
8132 (setq sigs-in nil sigs-inout nil sigs-out nil))
8133 ;; "modport x (clocking <keywd>)"
8134 ((and in-modport in-clocking)
8135 (verilog-modport-clockings-add in-modport keywd)
8136 (setq in-clocking nil))
8139 (equal keywd "endclocking"))
8140 (unless (eq in-clocking t)
8141 (verilog-modport-decls-set
8143 (verilog-decls-new sigs-out sigs-inout sigs-in
8144 nil nil nil nil nil nil))
8145 ;; Pop from varstack to restore state to pre-clocking
8146 (setq tmp (car varstack)
8147 varstack (cdr varstack)
8148 sigs-out (aref tmp 0)
8149 sigs-inout (aref tmp 1)
8150 sigs-in (aref tmp 2)))
8151 (setq in-clocking nil))
8152 ;; "clocking <keywd>"
8153 ((and (eq in-clocking t)
8154 (not (member keywd verilog-keywords)))
8155 (setq in-clocking (verilog-modport-new keywd nil nil))
8156 (setq sigs-modports (cons in-clocking sigs-modports))
8157 ;; Push old sig values to stack and point to new signal list
8158 (setq varstack (cons (vector sigs-out sigs-inout sigs-in)
8160 (setq sigs-in nil sigs-inout nil sigs-out nil))
8161 ;; New signal, maybe?
8165 (not (member keywd verilog-keywords)))
8166 ;; Add new signal to expect-signal's variable
8167 (setq newsig (verilog-sig-new keywd vec nil nil enum signed typedefed multidim modport))
8168 (set expect-signal (cons newsig
8169 (symbol-value expect-signal))))))
8172 (skip-syntax-forward " "))
8174 (setq tmp (verilog-decls-new (nreverse sigs-out)
8175 (nreverse sigs-inout)
8178 (nreverse sigs-modports)
8179 (nreverse sigs-assign)
8180 (nreverse sigs-const)
8181 (nreverse sigs-gparam)
8182 (nreverse sigs-intf)))
8183 ;;(if dbg (verilog-decls-princ tmp))
8186 (defvar verilog-read-sub-decls-in-interfaced nil
8187 "For `verilog-read-sub-decls', process next signal as under interfaced block.")
8189 (defvar verilog-read-sub-decls-gate-ios nil
8190 "For `verilog-read-sub-decls', gate IO pins remaining, nil if non-primitive.")
8193 ;; Prevent compile warnings; these are let's, not globals
8194 ;; Do not remove the eval-when-compile
8195 ;; - we want an error when we are debugging this code if they are refed.
8200 (defvar sigs-intfd))
8202 (defun verilog-read-sub-decls-sig (submoddecls comment port sig vec multidim)
8203 "For `verilog-read-sub-decls-line', add a signal."
8204 ;; sig eq t to indicate .name syntax
8205 ;;(message "vrsds: %s(%S)" port sig)
8206 (let ((dotname (eq sig t))
8209 (setq port (verilog-symbol-detick-denumber port))
8210 (setq sig (if dotname port (verilog-symbol-detick-denumber sig)))
8211 (if vec (setq vec (verilog-symbol-detick-denumber vec)))
8212 (if multidim (setq multidim (mapcar `verilog-symbol-detick-denumber multidim)))
8213 (unless (or (not sig)
8214 (equal sig "")) ;; Ignore .foo(1'b1) assignments
8215 (cond ((or (setq portdata (assoc port (verilog-decls-get-inouts submoddecls)))
8216 (equal "inout" verilog-read-sub-decls-gate-ios))
8218 (cons (verilog-sig-new
8220 (if dotname (verilog-sig-bits portdata) vec)
8221 (concat "To/From " comment)
8222 (verilog-sig-memory portdata)
8224 (verilog-sig-signed portdata)
8225 (unless (member (verilog-sig-type portdata) '("wire" "reg"))
8226 (verilog-sig-type portdata))
8229 ((or (setq portdata (assoc port (verilog-decls-get-outputs submoddecls)))
8230 (equal "output" verilog-read-sub-decls-gate-ios))
8232 (cons (verilog-sig-new
8234 (if dotname (verilog-sig-bits portdata) vec)
8235 (concat "From " comment)
8236 (verilog-sig-memory portdata)
8238 (verilog-sig-signed portdata)
8239 ;; Though ok in SV, in V2K code, propagating the
8240 ;; "reg" in "output reg" upwards isn't legal.
8241 ;; Also for backwards compatibility we don't propagate
8242 ;; "input wire" upwards.
8243 ;; See also `verilog-signals-edit-wire-reg'.
8244 (unless (member (verilog-sig-type portdata) '("wire" "reg"))
8245 (verilog-sig-type portdata))
8248 ((or (setq portdata (assoc port (verilog-decls-get-inputs submoddecls)))
8249 (equal "input" verilog-read-sub-decls-gate-ios))
8251 (cons (verilog-sig-new
8253 (if dotname (verilog-sig-bits portdata) vec)
8254 (concat "To " comment)
8255 (verilog-sig-memory portdata)
8257 (verilog-sig-signed portdata)
8258 (unless (member (verilog-sig-type portdata) '("wire" "reg"))
8259 (verilog-sig-type portdata))
8262 ((setq portdata (assoc port (verilog-decls-get-interfaces submoddecls)))
8264 (cons (verilog-sig-new
8266 (if dotname (verilog-sig-bits portdata) vec)
8267 (concat "To/From " comment)
8268 (verilog-sig-memory portdata)
8270 (verilog-sig-signed portdata)
8271 (verilog-sig-type portdata)
8274 ((setq portdata (and verilog-read-sub-decls-in-interfaced
8275 (assoc port (verilog-decls-get-vars submoddecls))))
8277 (cons (verilog-sig-new
8279 (if dotname (verilog-sig-bits portdata) vec)
8280 (concat "To/From " comment)
8281 (verilog-sig-memory portdata)
8283 (verilog-sig-signed portdata)
8284 (verilog-sig-type portdata)
8287 ;; (t -- warning pin isn't defined.) ; Leave for lint tool
8290 (defun verilog-read-sub-decls-expr (submoddecls comment port expr)
8291 "For `verilog-read-sub-decls-line', parse a subexpression and add signals."
8292 ;;(message "vrsde: '%s'" expr)
8293 ;; Replace special /*[....]*/ comments inserted by verilog-auto-inst-port
8294 (setq expr (verilog-string-replace-matches "/\\*\\(\\[[^*]+\\]\\)\\*/" "\\1" nil nil expr))
8295 ;; Remove front operators
8296 (setq expr (verilog-string-replace-matches "^\\s-*[---+~!|&]+\\s-*" "" nil nil expr))
8299 ;; {..., a, b} requires us to recurse on a,b
8300 ;; To support {#{},{#{a,b}} we'll just split everything on [{},]
8301 ((string-match "^\\s-*{\\(.*\\)}\\s-*$" expr)
8302 (unless verilog-auto-ignore-concat
8303 (let ((mlst (split-string (match-string 1 expr) "[{},]"))
8305 (while (setq mstr (pop mlst))
8306 (verilog-read-sub-decls-expr submoddecls comment port mstr)))))
8308 (let (sig vec multidim)
8309 ;; Remove leading reduction operators, etc
8310 (setq expr (verilog-string-replace-matches "^\\s-*[---+~!|&]+\\s-*" "" nil nil expr))
8311 ;;(message "vrsde-ptop: '%s'" expr)
8312 (cond ;; Find \signal. Final space is part of escaped signal name
8313 ((string-match "^\\s-*\\(\\\\[^ \t\n\f]+\\s-\\)" expr)
8314 ;;(message "vrsde-s: '%s'" (match-string 1 expr))
8315 (setq sig (match-string 1 expr)
8316 expr (substring expr (match-end 0))))
8318 ((string-match "^\\s-*\\([a-zA-Z_][a-zA-Z_0-9]*\\)" expr)
8319 ;;(message "vrsde-s: '%s'" (match-string 1 expr))
8320 (setq sig (verilog-string-remove-spaces (match-string 1 expr))
8321 expr (substring expr (match-end 0)))))
8322 ;; Find [vector] or [multi][multi][multi][vector]
8323 (while (string-match "^\\s-*\\(\\[[^]]+\\]\\)" expr)
8324 ;;(message "vrsde-v: '%s'" (match-string 1 expr))
8325 (when vec (setq multidim (cons vec multidim)))
8326 (setq vec (match-string 1 expr)
8327 expr (substring expr (match-end 0))))
8328 ;; If found signal, and nothing unrecognized, add the signal
8329 ;;(message "vrsde-rem: '%s'" expr)
8330 (when (and sig (string-match "^\\s-*$" expr))
8331 (verilog-read-sub-decls-sig submoddecls comment port sig vec multidim))))))
8333 (defun verilog-read-sub-decls-line (submoddecls comment)
8334 "For `verilog-read-sub-decls', read lines of port defs until none match.
8335 Inserts the list of signals found, using submodi to look up each port."
8341 (cond ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*(\\s-*")
8342 (setq port (match-string 1))
8343 (goto-char (match-end 0)))
8345 ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*(\\s-*")
8346 (setq port (concat (match-string 1) " ")) ;; escaped id's need trailing space
8347 (goto-char (match-end 0)))
8349 ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*[,)/]")
8350 (verilog-read-sub-decls-sig
8351 submoddecls comment (match-string 1) t ; sig==t for .name
8352 nil nil) ; vec multidim
8355 ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*[,)/]")
8356 (verilog-read-sub-decls-sig
8357 submoddecls comment (concat (match-string 1) " ") t ; sig==t for .name
8358 nil nil) ; vec multidim
8361 ((looking-at "\\s-*\\.[^(]*(")
8362 (setq port nil) ;; skip this line
8363 (goto-char (match-end 0)))
8365 (setq port nil done t))) ;; Unknown, ignore rest of line
8366 ;; Get signal name. Point is at the first-non-space after (
8367 ;; We intentionally ignore (non-escaped) signals with .s in them
8368 ;; this prevents AUTOWIRE etc from noticing hierarchical sigs.
8370 (cond ((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*)")
8371 (verilog-read-sub-decls-sig
8372 submoddecls comment port
8373 (verilog-string-remove-spaces (match-string 1)) ; sig
8374 nil nil)) ; vec multidim
8376 ((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*)")
8377 (verilog-read-sub-decls-sig
8378 submoddecls comment port
8379 (verilog-string-remove-spaces (match-string 1)) ; sig
8380 (match-string 2) nil)) ; vec multidim
8381 ;; Fastpath was above looking-at's.
8382 ;; For something more complicated invoke a parser
8383 ((looking-at "[^)]+")
8384 (verilog-read-sub-decls-expr
8385 submoddecls comment port
8387 (point) (1- (progn (search-backward "(") ; start at (
8388 (verilog-forward-sexp-ign-cmt 1)
8389 (point)))))))) ; expr
8391 (forward-line 1)))))
8393 (defun verilog-read-sub-decls-gate (submoddecls comment submod end-inst-point)
8394 "For `verilog-read-sub-decls', read lines of UDP gate decl until none match.
8395 Inserts the list of signals found."
8397 (let ((iolist (cdr (assoc submod verilog-gate-ios))))
8398 (while (< (point) end-inst-point)
8399 ;; Get primitive's signal name, as will never have port, and no trailing )
8400 (cond ((looking-at "//")
8401 (search-forward "\n"))
8402 ((looking-at "/\\*")
8403 (or (search-forward "*/")
8404 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8405 ((looking-at "(\\*")
8406 ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
8408 (or (search-forward "*)")
8409 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
8410 ;; On pins, parse and advance to next pin
8411 ;; Looking at pin, but *not* an // Output comment, or ) to end the inst
8412 ((looking-at "\\s-*[a-zA-Z0-9`_$({}\\\\][^,]*")
8413 (goto-char (match-end 0))
8414 (setq verilog-read-sub-decls-gate-ios (or (car iolist) "input")
8415 iolist (cdr iolist))
8416 (verilog-read-sub-decls-expr
8417 submoddecls comment "primitive_port"
8421 (skip-syntax-forward " ")))))))
8423 (defun verilog-read-sub-decls ()
8424 "Internally parse signals going to modules under this module.
8425 Return an array of [ outputs inouts inputs ] signals for modules that are
8426 instantiated in this module. For example if declare A A (.B(SIG)) and SIG
8427 is an output, then SIG will be included in the list.
8429 This only works on instantiations created with /*AUTOINST*/ converted by
8430 \\[verilog-auto-inst]. Otherwise, it would have to read in the whole
8431 component library to determine connectivity of the design.
8433 One work around for this problem is to manually create // Inputs and //
8434 Outputs comments above subcell signals, for example:
8442 (let ((end-mod-point (verilog-get-end-of-defun t))
8443 st-point end-inst-point
8444 ;; below 3 modified by verilog-read-sub-decls-line
8445 sigs-out sigs-inout sigs-in sigs-intf sigs-intfd)
8446 (verilog-beg-of-defun-quick)
8447 (while (verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-mod-point t)
8449 (goto-char (match-beginning 0))
8450 (unless (verilog-inside-comment-or-string-p)
8451 ;; Attempt to snarf a comment
8452 (let* ((submod (verilog-read-inst-module))
8453 (inst (verilog-read-inst-name))
8454 (subprim (member submod verilog-gate-keywords))
8455 (comment (concat inst " of " submod ".v"))
8456 submodi submoddecls)
8459 (setq submodi `primitive
8460 submoddecls (verilog-decls-new nil nil nil nil nil nil nil nil nil)
8461 comment (concat inst " of " submod))
8462 (verilog-backward-open-paren)
8463 (setq end-inst-point (save-excursion (verilog-forward-sexp-ign-cmt 1)
8467 (verilog-read-sub-decls-gate submoddecls comment submod end-inst-point))
8470 (when (setq submodi (verilog-modi-lookup submod t))
8471 (setq submoddecls (verilog-modi-get-decls submodi)
8472 verilog-read-sub-decls-gate-ios nil)
8473 (verilog-backward-open-paren)
8474 (setq end-inst-point (save-excursion (verilog-forward-sexp-ign-cmt 1)
8477 ;; This could have used a list created by verilog-auto-inst
8478 ;; However I want it to be runnable even on user's manually added signals
8479 (let ((verilog-read-sub-decls-in-interfaced t))
8480 (while (re-search-forward "\\s *(?\\s *// Interfaced" end-inst-point t)
8481 (verilog-read-sub-decls-line submoddecls comment))) ;; Modifies sigs-ifd
8482 (goto-char st-point)
8483 (while (re-search-forward "\\s *(?\\s *// Interfaces" end-inst-point t)
8484 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-out
8485 (goto-char st-point)
8486 (while (re-search-forward "\\s *(?\\s *// Outputs" end-inst-point t)
8487 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-out
8488 (goto-char st-point)
8489 (while (re-search-forward "\\s *(?\\s *// Inouts" end-inst-point t)
8490 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-inout
8491 (goto-char st-point)
8492 (while (re-search-forward "\\s *(?\\s *// Inputs" end-inst-point t)
8493 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-in
8495 ;; Combine duplicate bits
8496 ;;(setq rr (vector sigs-out sigs-inout sigs-in))
8497 (verilog-subdecls-new
8498 (verilog-signals-combine-bus (nreverse sigs-out))
8499 (verilog-signals-combine-bus (nreverse sigs-inout))
8500 (verilog-signals-combine-bus (nreverse sigs-in))
8501 (verilog-signals-combine-bus (nreverse sigs-intf))
8502 (verilog-signals-combine-bus (nreverse sigs-intfd))))))
8504 (defun verilog-read-inst-pins ()
8505 "Return an array of [ pins ] for the current instantiation at point.
8506 For example if declare A A (.B(SIG)) then B will be included in the list."
8508 (let ((end-mod-point (point)) ;; presume at /*AUTOINST*/ point
8510 (verilog-backward-open-paren)
8511 (while (re-search-forward "\\.\\([^(,) \t\n\f]*\\)\\s-*" end-mod-point t)
8512 (setq pin (match-string 1))
8513 (unless (verilog-inside-comment-or-string-p)
8514 (setq pins (cons (list pin) pins))
8515 (when (looking-at "(")
8516 (verilog-forward-sexp-ign-cmt 1))))
8519 (defun verilog-read-arg-pins ()
8520 "Return an array of [ pins ] for the current argument declaration at point."
8522 (let ((end-mod-point (point)) ;; presume at /*AUTOARG*/ point
8524 (verilog-backward-open-paren)
8525 (while (re-search-forward "\\([a-zA-Z0-9$_.%`]+\\)" end-mod-point t)
8526 (setq pin (match-string 1))
8527 (unless (verilog-inside-comment-or-string-p)
8528 (setq pins (cons (list pin) pins))))
8531 (defun verilog-read-auto-constants (beg end-mod-point)
8532 "Return a list of AUTO_CONSTANTs used in the region from BEG to END-MOD-POINT."
8535 (let (sig-list tpl-end-pt)
8537 (while (re-search-forward "\\<AUTO_CONSTANT" end-mod-point t)
8538 (if (not (looking-at "\\s *("))
8539 (error "%s: Missing () after AUTO_CONSTANT" (verilog-point-text)))
8540 (search-forward "(" end-mod-point)
8541 (setq tpl-end-pt (save-excursion
8543 (verilog-forward-sexp-cmt 1) ;; Moves to paren that closes argdecl's
8546 (while (re-search-forward "\\s-*\\([\"a-zA-Z0-9$_.%`]+\\)\\s-*,*" tpl-end-pt t)
8547 (setq sig-list (cons (list (match-string 1) nil nil) sig-list))))
8550 (defvar verilog-cache-has-lisp nil "True if any AUTO_LISP in buffer.")
8551 (make-variable-buffer-local 'verilog-cache-has-lisp)
8553 (defun verilog-read-auto-lisp-present ()
8554 "Set `verilog-cache-has-lisp' if any AUTO_LISP in this buffer."
8556 (goto-char (point-min))
8557 (setq verilog-cache-has-lisp (re-search-forward "\\<AUTO_LISP(" nil t))))
8559 (defun verilog-read-auto-lisp (start end)
8560 "Look for and evaluate an AUTO_LISP between START and END.
8561 Must call `verilog-read-auto-lisp-present' before this function."
8562 ;; This function is expensive for large buffers, so we cache if any AUTO_LISP exists
8563 (when verilog-cache-has-lisp
8566 (while (re-search-forward "\\<AUTO_LISP(" end t)
8568 (let* ((beg-pt (prog1 (point)
8569 (verilog-forward-sexp-cmt 1))) ;; Closing paren
8571 (verilog-in-hooks t))
8572 (eval-region beg-pt end-pt nil))))))
8575 ;; Prevent compile warnings; these are let's, not globals
8576 ;; Do not remove the eval-when-compile
8577 ;; - we want an error when we are debugging this code if they are refed.
8581 (defvar sigs-out-unk)
8583 (defvar vector-skip-list))
8585 (defun verilog-read-always-signals-recurse
8586 (exit-keywd rvalue temp-next)
8587 "Recursive routine for parentheses/bracket matching.
8588 EXIT-KEYWD is expression to stop at, nil if top level.
8589 RVALUE is true if at right hand side of equal.
8590 IGNORE-NEXT is true to ignore next token, fake from inside case statement."
8591 (let* ((semi-rvalue (equal "endcase" exit-keywd)) ;; true if after a ; we are looking for rvalue
8592 keywd last-keywd sig-tolk sig-last-tolk gotend got-sig got-list end-else-check
8594 ;;(if dbg (setq dbg (concat dbg (format "Recursion %S %S %S\n" exit-keywd rvalue temp-next))))
8595 (while (not (or (eobp) gotend))
8598 (search-forward "\n"))
8599 ((looking-at "/\\*")
8600 (or (search-forward "*/")
8601 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8602 ((looking-at "(\\*")
8603 ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
8605 (or (search-forward "*)")
8606 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
8607 (t (setq keywd (buffer-substring-no-properties
8609 (save-excursion (when (eq 0 (skip-chars-forward "a-zA-Z0-9$_.%`"))
8612 sig-last-tolk sig-tolk
8614 ;;(if dbg (setq dbg (concat dbg (format "\tPt=%S %S\trv=%S in=%S ee=%S gs=%S\n" (point) keywd rvalue ignore-next end-else-check got-sig))))
8617 (or (re-search-forward "[^\\]\"" nil t)
8618 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
8619 ;; else at top level loop, keep parsing
8620 ((and end-else-check (equal keywd "else"))
8621 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else %s\n" keywd))))
8622 ;; no forward movement, want to see else in lower loop
8623 (setq end-else-check nil))
8624 ;; End at top level loop
8625 ((and end-else-check (looking-at "[^ \t\n\f]"))
8626 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else-other %s\n" keywd))))
8629 ((and exit-keywd (equal keywd exit-keywd))
8631 (forward-char (length keywd)))
8632 ;; Standard tokens...
8634 (setq ignore-next nil rvalue semi-rvalue)
8635 ;; Final statement at top level loop?
8636 (when (not exit-keywd)
8637 ;;(if dbg (setq dbg (concat dbg (format "\ttop-end-check %s\n" keywd))))
8638 (setq end-else-check t))
8641 (if (looking-at "'[sS]?[hdxboHDXBO]?[ \t]*[0-9a-fA-F_xzXZ?]+")
8642 (goto-char (match-end 0))
8644 ((equal keywd ":") ;; Case statement, begin/end label, x?y:z
8645 (cond ((equal "endcase" exit-keywd) ;; case x: y=z; statement next
8646 (setq ignore-next nil rvalue nil))
8647 ((equal "?" exit-keywd) ;; x?y:z rvalue
8649 ((equal "]" exit-keywd) ;; [x:y] rvalue
8651 (got-sig ;; label: statement
8652 (setq ignore-next nil rvalue semi-rvalue got-sig nil))
8653 ((not rvalue) ;; begin label
8654 (setq ignore-next t rvalue nil)))
8658 ;;(if dbg (setq dbg (concat dbg (format "\t\tequal got-sig=%S got-list=%s\n" got-sig got-list))))
8659 (set got-list (cons got-sig (symbol-value got-list)))
8662 (if (eq (char-before) ?< )
8663 (setq sigs-out-d (append sigs-out-d sigs-out-unk)
8665 (setq sigs-out-i (append sigs-out-i sigs-out-unk)
8667 (setq ignore-next nil rvalue t)
8671 (verilog-read-always-signals-recurse ":" rvalue nil))
8674 (verilog-read-always-signals-recurse "]" t nil))
8677 (cond (sig-last-tolk ;; Function call; zap last signal
8678 (setq got-sig nil)))
8679 (cond ((equal last-keywd "for")
8680 ;; temp-next: Variables on LHS are lvalues, but generally we want
8681 ;; to ignore them, assuming they are loop increments
8682 (verilog-read-always-signals-recurse ";" nil t)
8683 (verilog-read-always-signals-recurse ";" t nil)
8684 (verilog-read-always-signals-recurse ")" nil nil))
8685 (t (verilog-read-always-signals-recurse ")" t nil))))
8686 ((equal keywd "begin")
8687 (skip-syntax-forward "w_")
8688 (verilog-read-always-signals-recurse "end" nil nil)
8689 ;;(if dbg (setq dbg (concat dbg (format "\tgot-end %s\n" exit-keywd))))
8690 (setq ignore-next nil rvalue semi-rvalue)
8691 (if (not exit-keywd) (setq end-else-check t)))
8692 ((member keywd '("case" "casex" "casez"))
8693 (skip-syntax-forward "w_")
8694 (verilog-read-always-signals-recurse "endcase" t nil)
8695 (setq ignore-next nil rvalue semi-rvalue)
8696 (if (not exit-keywd) (setq gotend t))) ;; top level begin/end
8697 ((string-match "^[$`a-zA-Z_]" keywd) ;; not exactly word constituent
8698 (cond ((member keywd '("`ifdef" "`ifndef" "`elsif"))
8699 (setq ignore-next t))
8701 (member keywd verilog-keywords)
8702 (string-match "^\\$" keywd)) ;; PLI task
8703 (setq ignore-next nil))
8705 (setq keywd (verilog-symbol-detick-denumber keywd))
8707 (set got-list (cons got-sig (symbol-value got-list)))
8708 ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S got-list=%S\n" got-sig got-list))))
8710 (setq got-list (cond (temp-next 'sigs-temp)
8713 got-sig (if (or (not keywd)
8714 (assoc keywd (symbol-value got-list)))
8715 nil (list keywd nil nil))
8718 (skip-chars-forward "a-zA-Z0-9$_.%`"))
8721 ;; End of non-comment token
8722 (setq last-keywd keywd)))
8723 (skip-syntax-forward " "))
8724 ;; Append the final pending signal
8726 ;;(if dbg (setq dbg (concat dbg (format "\t\tfinal got-sig=%S got-list=%s\n" got-sig got-list))))
8727 (set got-list (cons got-sig (symbol-value got-list)))
8729 ;;(if dbg (setq dbg (concat dbg (format "ENDRecursion %s\n" exit-keywd))))
8732 (defun verilog-read-always-signals ()
8733 "Parse always block at point and return list of (outputs inout inputs)."
8736 sigs-out-d sigs-out-i sigs-out-unk sigs-temp sigs-in)
8737 (search-forward ")")
8738 (verilog-read-always-signals-recurse nil nil nil)
8739 (setq sigs-out-i (append sigs-out-i sigs-out-unk)
8741 ;;(if dbg (with-current-buffer (get-buffer-create "*vl-dbg*")) (delete-region (point-min) (point-max)) (insert dbg) (setq dbg ""))
8742 ;; Return what was found
8743 (verilog-alw-new sigs-out-d sigs-out-i sigs-temp sigs-in))))
8745 (defun verilog-read-instants ()
8746 "Parse module at point and return list of ( ( file instance ) ... )."
8747 (verilog-beg-of-defun-quick)
8748 (let* ((end-mod-point (verilog-get-end-of-defun t))
8750 (instants-list nil))
8752 (while (< (point) end-mod-point)
8753 ;; Stay at level 0, no comments
8755 (setq state (parse-partial-sexp (point) end-mod-point 0 t nil))
8756 (or (> (car state) 0) ; in parens
8757 (nth 5 state) ; comment
8761 (if (looking-at "^\\s-*\\([a-zA-Z0-9`_$]+\\)\\s-+\\([a-zA-Z0-9`_$]+\\)\\s-*(")
8762 ;;(if (looking-at "^\\(.+\\)$")
8763 (let ((module (match-string 1))
8764 (instant (match-string 2)))
8765 (if (not (member module verilog-keywords))
8766 (setq instants-list (cons (list module instant) instants-list)))))
8771 (defun verilog-read-auto-template-middle ()
8772 "With point in middle of an AUTO_TEMPLATE, parse it.
8773 Returns REGEXP and list of ( (signal_name connection_name)... )."
8776 (let ((tpl-regexp "\\([0-9]+\\)")
8777 (lineno -1) ; -1 to offset for the AUTO_TEMPLATE's newline
8779 tpl-sig-list tpl-wild-list tpl-end-pt rep)
8781 ;; We reserve @"..." for future lisp expressions that evaluate
8782 ;; once-per-AUTOINST
8783 (when (looking-at "\\s-*\"\\([^\"]*\\)\"")
8784 (setq tpl-regexp (match-string 1))
8785 (goto-char (match-end 0)))
8786 (search-forward "(")
8787 ;; Parse lines in the template
8788 (when (or verilog-auto-inst-template-numbers
8789 verilog-auto-template-warn-unused)
8791 (let ((pre-pt (point)))
8792 (goto-char (point-min))
8793 (while (search-forward "AUTO_TEMPLATE" pre-pt t)
8794 (setq templateno (1+ templateno)))
8795 (while (< (point) pre-pt)
8797 (setq lineno (1+ lineno))))))
8798 (setq tpl-end-pt (save-excursion
8800 (verilog-forward-sexp-cmt 1) ;; Moves to paren that closes argdecl's
8804 (while (< (point) tpl-end-pt)
8805 (cond ((looking-at "\\s-*\\.\\([a-zA-Z0-9`_$]+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
8808 (match-string-no-properties 1)
8809 (match-string-no-properties 2)
8812 (goto-char (match-end 0)))
8815 ;; Regexp bug in XEmacs disallows ][ inside [], and wants + last
8816 "\\s-*\\.\\(\\([a-zA-Z0-9`_$+@^.*?|---]+\\|[][]\\|\\\\[()|]\\)+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
8817 (setq rep (match-string-no-properties 3))
8818 (goto-char (match-end 0))
8822 (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil
8828 ((looking-at "[ \t\f]+")
8829 (goto-char (match-end 0)))
8831 (setq lineno (1+ lineno))
8832 (goto-char (match-end 0)))
8834 (search-forward "\n")
8835 (setq lineno (1+ lineno)))
8836 ((looking-at "/\\*")
8838 (or (search-forward "*/")
8839 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8841 (error "%s: AUTO_TEMPLATE parsing error: %s"
8842 (verilog-point-text)
8843 (progn (looking-at ".*$") (match-string 0))))))
8846 (list tpl-sig-list tpl-wild-list)))))
8848 (defun verilog-read-auto-template (module)
8849 "Look for an auto_template for the instantiation of the given MODULE.
8850 If found returns `verilog-read-auto-template-inside' structure."
8854 ;; Note this search is expensive, as we hunt from mod-begin to point
8855 ;; for every instantiation. Likewise in verilog-read-auto-lisp.
8856 ;; So, we look first for an exact string rather than a slow regexp.
8857 ;; Someday we may keep a cache of every template, but this would also
8858 ;; need to record the relative position of each AUTOINST, as multiple
8859 ;; templates exist for each module, and we're inserting lines.
8861 ;; See also regexp in `verilog-auto-template-lint'
8862 (verilog-re-search-backward-substr
8864 (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)
8865 ;; Also try forward of this AUTOINST
8866 ;; This is for historical support; this isn't speced as working
8869 (verilog-re-search-forward-substr
8871 (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)))
8872 (goto-char (match-end 0))
8873 (verilog-read-auto-template-middle))
8874 ;; If no template found
8875 (t (vector "" nil))))))
8876 ;;(progn (find-file "auto-template.v") (verilog-read-auto-template "ptl_entry"))
8878 (defvar verilog-auto-template-hits nil "Successful lookups with `verilog-read-auto-template-hit'.")
8879 (make-variable-buffer-local 'verilog-auto-template-hits)
8881 (defun verilog-read-auto-template-hit (tpl-ass)
8882 "Record that TPL-ASS template from `verilog-read-auto-template' was used."
8883 (when (eval-when-compile (fboundp 'make-hash-table)) ;; else feature not allowed
8884 (when verilog-auto-template-warn-unused
8885 (unless verilog-auto-template-hits
8886 (setq verilog-auto-template-hits
8887 (make-hash-table :test 'equal :rehash-size 4.0)))
8888 (puthash (vector (nth 2 tpl-ass) (nth 3 tpl-ass)) t
8889 verilog-auto-template-hits))))
8891 (defun verilog-set-define (defname defvalue &optional buffer enumname)
8892 "Set the definition DEFNAME to the DEFVALUE in the given BUFFER.
8893 Optionally associate it with the specified enumeration ENUMNAME."
8894 (with-current-buffer (or buffer (current-buffer))
8895 (let ((mac (intern (concat "vh-" defname))))
8896 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
8897 ;; Need to define to a constant if no value given
8898 (set (make-local-variable mac)
8899 (if (equal defvalue "") "1" defvalue)))
8901 (let ((enumvar (intern (concat "venum-" enumname))))
8902 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
8903 (unless (boundp enumvar) (set enumvar nil))
8904 (add-to-list (make-local-variable enumvar) defname)))))
8906 (defun verilog-read-defines (&optional filename recurse subcall)
8907 "Read `defines and parameters for the current file, or optional FILENAME.
8908 If the filename is provided, `verilog-library-flags' will be used to
8909 resolve it. If optional RECURSE is non-nil, recurse through `includes.
8911 Parameters must be simple assignments to constants, or have their own
8912 \"parameter\" label rather than a list of parameters. Thus:
8914 parameter X = 5, Y = 10; // Ok
8915 parameter X = {1'b1, 2'h2}; // Ok
8916 parameter X = {1'b1, 2'h2}, Y = 10; // Bad, make into 2 parameter lines
8918 Defines must be simple text substitutions, one on a line, starting
8919 at the beginning of the line. Any ifdefs or multiline comments around the
8922 Defines are stored inside Emacs variables using the name vh-{definename}.
8924 This function is useful for setting vh-* variables. The file variables
8925 feature can be used to set defines that `verilog-mode' can see; put at the
8926 *END* of your file something like:
8929 // vh-macro:\"macro_definition\"
8932 If macros are defined earlier in the same file and you want their values,
8933 you can read them automatically (provided `enable-local-eval' is on):
8936 // eval:(verilog-read-defines)
8937 // eval:(verilog-read-defines \"group_standard_includes.v\")
8940 Note these are only read when the file is first visited, you must use
8941 \\[find-alternate-file] RET to have these take effect after editing them!
8943 If you want to disable the \"Process `eval' or hook local variables\"
8944 warning message, you need to add to your init file:
8946 (setq enable-local-eval t)"
8947 (let ((origbuf (current-buffer)))
8949 (unless subcall (verilog-getopt-flags))
8951 (let ((fns (verilog-library-filenames filename (buffer-file-name))))
8953 (set-buffer (find-file-noselect (car fns)))
8954 (error (concat (verilog-point-text)
8955 ": Can't find verilog-read-defines file: " filename)))))
8957 (goto-char (point-min))
8958 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
8959 (let ((inc (verilog-string-replace-matches
8960 "\"" "" nil nil (match-string-no-properties 1))))
8961 (unless (verilog-inside-comment-or-string-p)
8962 (verilog-read-defines inc recurse t)))))
8964 ;; note we don't use verilog-re... it's faster this way, and that
8965 ;; function has problems when comments are at the end of the define
8966 (goto-char (point-min))
8967 (while (re-search-forward "^\\s-*`define\\s-+\\([a-zA-Z0-9_$]+\\)\\s-+\\(.*\\)$" nil t)
8968 (let ((defname (match-string-no-properties 1))
8969 (defvalue (match-string-no-properties 2)))
8970 (setq defvalue (verilog-string-replace-matches "\\s-*/[/*].*$" "" nil nil defvalue))
8971 (verilog-set-define defname defvalue origbuf)))
8972 ;; Hack: Read parameters
8973 (goto-char (point-min))
8974 (while (re-search-forward
8975 "^\\s-*\\(parameter\\|localparam\\)\\(\\s-*\\[[^]]*\\]\\)?\\s-*" nil t)
8977 ;; The primary way of getting defines is verilog-read-decls
8978 ;; However, that isn't called yet for included files, so we'll add another scheme
8979 (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
8980 (setq enumname (match-string-no-properties 2)))
8981 (forward-comment 99999)
8982 (while (looking-at (concat "\\s-*,?\\s-*\\(?:/[/*].*?$\\)?\\s-*\\([a-zA-Z0-9_$]+\\)"
8983 "\\s-*=\\s-*\\([^;,]*\\),?\\s-*\\(/[/*].*?$\\)?\\s-*"))
8984 (verilog-set-define (match-string-no-properties 1)
8985 (match-string-no-properties 2) origbuf enumname)
8986 (goto-char (match-end 0))
8987 (forward-comment 99999)))))))
8989 (defun verilog-read-includes ()
8990 "Read `includes for the current file.
8991 This will find all of the `includes which are at the beginning of lines,
8992 ignoring any ifdefs or multiline comments around them.
8993 `verilog-read-defines' is then performed on the current and each included
8996 It is often useful put at the *END* of your file something like:
8999 // eval:(verilog-read-defines)
9000 // eval:(verilog-read-includes)
9003 Note includes are only read when the file is first visited, you must use
9004 \\[find-alternate-file] RET to have these take effect after editing them!
9006 It is good to get in the habit of including all needed files in each .v
9007 file that needs it, rather than waiting for compile time. This will aid
9008 this process, Verilint, and readability. To prevent defining the same
9009 variable over and over when many modules are compiled together, put a test
9010 around the inside each include file:
9012 foo.v (an include file):
9013 `ifdef _FOO_V // include if not already included
9016 ... contents of file
9018 ;;slow: (verilog-read-defines nil t))
9020 (verilog-getopt-flags)
9021 (goto-char (point-min))
9022 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
9023 (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string 1))))
9024 (verilog-read-defines inc nil t)))))
9026 (defun verilog-read-signals (&optional start end)
9027 "Return a simple list of all possible signals in the file.
9028 Bounded by optional region from START to END. Overly aggressive but fast.
9029 Some macros and such are also found and included. For dinotrace.el."
9030 (let (sigs-all keywd)
9031 (progn;save-excursion
9032 (goto-char (or start (point-min)))
9033 (setq end (or end (point-max)))
9034 (while (re-search-forward "[\"/a-zA-Z_.%`]" end t)
9038 (search-forward "\n"))
9039 ((looking-at "/\\*")
9040 (search-forward "*/"))
9041 ((looking-at "(\\*")
9042 (or (looking-at "(\\*\\s-*)") ; It's a "always @ (*)"
9043 (search-forward "*)")))
9044 ((eq ?\" (following-char))
9045 (re-search-forward "[^\\]\"")) ;; don't forward-char first, since we look for a non backslash first
9046 ((looking-at "\\s-*\\([a-zA-Z0-9$_.%`]+\\)")
9047 (goto-char (match-end 0))
9048 (setq keywd (match-string-no-properties 1))
9049 (or (member keywd verilog-keywords)
9050 (member keywd sigs-all)
9051 (setq sigs-all (cons keywd sigs-all))))
9052 (t (forward-char 1))))
9057 ;; Argument file parsing
9060 (defun verilog-getopt (arglist)
9061 "Parse -f, -v etc arguments in ARGLIST list or string."
9062 (unless (listp arglist) (setq arglist (list arglist)))
9063 (let ((space-args '())
9065 ;; Split on spaces, so users can pass whole command lines
9067 (setq arg (car arglist)
9068 arglist (cdr arglist))
9069 (while (string-match "^\\([^ \t\n\f]+\\)[ \t\n\f]*\\(.*$\\)" arg)
9070 (setq space-args (append space-args
9071 (list (match-string-no-properties 1 arg))))
9072 (setq arg (match-string 2 arg))))
9075 (setq arg (car space-args)
9076 space-args (cdr space-args))
9080 (setq next-param arg))
9082 (setq next-param arg))
9084 (setq next-param arg))
9085 ;; +libext+(ext1)+(ext2)...
9086 ((string-match "^\\+libext\\+\\(.*\\)" arg)
9087 (setq arg (match-string 1 arg))
9088 (while (string-match "\\([^+]+\\)\\+?\\(.*\\)" arg)
9089 (verilog-add-list-unique `verilog-library-extensions
9090 (match-string 1 arg))
9091 (setq arg (match-string 2 arg))))
9093 ((or (string-match "^-D\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; -Ddefine=val
9094 (string-match "^-D\\([^+=]*\\)\\(\\)" arg) ;; -Ddefine
9095 (string-match "^\\+define\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; +define+val
9096 (string-match "^\\+define\\([^+=]*\\)\\(\\)" arg)) ;; +define+define
9097 (verilog-set-define (match-string 1 arg) (match-string 2 arg)))
9099 ((or (string-match "^\\+incdir\\+\\(.*\\)" arg) ;; +incdir+dir
9100 (string-match "^-I\\(.*\\)" arg)) ;; -Idir
9101 (verilog-add-list-unique `verilog-library-directories
9102 (match-string 1 (substitute-in-file-name arg))))
9104 ((equal "+librescan" arg))
9105 ((string-match "^-U\\(.*\\)" arg)) ;; -Udefine
9106 ;; Second parameters
9107 ((equal next-param "-f")
9108 (setq next-param nil)
9109 (verilog-getopt-file (substitute-in-file-name arg)))
9110 ((equal next-param "-v")
9111 (setq next-param nil)
9112 (verilog-add-list-unique `verilog-library-files
9113 (substitute-in-file-name arg)))
9114 ((equal next-param "-y")
9115 (setq next-param nil)
9116 (verilog-add-list-unique `verilog-library-directories
9117 (substitute-in-file-name arg)))
9119 ((string-match "^[^-+]" arg)
9120 (verilog-add-list-unique `verilog-library-files
9121 (substitute-in-file-name arg)))
9122 ;; Default - ignore; no warning
9124 ;;(verilog-getopt (list "+libext+.a+.b" "+incdir+foodir" "+define+a+aval" "-f" "otherf" "-v" "library" "-y" "dir"))
9126 (defun verilog-getopt-file (filename)
9127 "Read Verilog options from the specified FILENAME."
9129 (let ((fns (verilog-library-filenames filename (buffer-file-name)))
9130 (orig-buffer (current-buffer))
9133 (set-buffer (find-file-noselect (car fns)))
9134 (error (concat (verilog-point-text)
9135 ": Can't find verilog-getopt-file -f file: " filename)))
9136 (goto-char (point-min))
9138 (setq line (buffer-substring (point) (point-at-eol)))
9140 (when (string-match "//" line)
9141 (setq line (substring line 0 (match-beginning 0))))
9142 (with-current-buffer orig-buffer ; Variables are buffer-local, so need right context.
9143 (verilog-getopt line))))))
9145 (defun verilog-getopt-flags ()
9146 "Convert `verilog-library-flags' into standard library variables."
9147 ;; If the flags are local, then all the outputs should be local also
9148 (when (local-variable-p `verilog-library-flags (current-buffer))
9149 (mapc 'make-local-variable '(verilog-library-extensions
9150 verilog-library-directories
9151 verilog-library-files
9152 verilog-library-flags)))
9153 ;; Allow user to customize
9154 (verilog-run-hooks 'verilog-before-getopt-flags-hook)
9155 ;; Process arguments
9156 (verilog-getopt verilog-library-flags)
9157 ;; Allow user to customize
9158 (verilog-run-hooks 'verilog-getopt-flags-hook))
9160 (defun verilog-add-list-unique (varref object)
9161 "Append to VARREF list the given OBJECT,
9162 unless it is already a member of the variable's list."
9163 (unless (member object (symbol-value varref))
9164 (set varref (append (symbol-value varref) (list object))))
9166 ;;(progn (setq l '()) (verilog-add-list-unique `l "a") (verilog-add-list-unique `l "a") l)
9168 (defun verilog-current-flags ()
9169 "Convert `verilog-library-flags' and similar variables to command line.
9170 Used for __FLAGS__ in `verilog-expand-command'."
9171 (let ((cmd (mapconcat `concat verilog-library-flags " ")))
9172 (when (equal cmd "")
9174 "+libext+" (mapconcat `concat verilog-library-extensions "+")
9175 (mapconcat (lambda (i) (concat " -y " i " +incdir+" i))
9176 verilog-library-directories "")
9177 (mapconcat (lambda (i) (concat " -v " i))
9178 verilog-library-files ""))))
9180 ;;(verilog-current-flags)
9184 ;; Cached directory support
9187 (defvar verilog-dir-cache-preserving nil
9188 "If set, the directory cache is enabled, and file system changes are ignored.
9189 See `verilog-dir-exists-p' and `verilog-dir-files'.")
9191 ;; If adding new cached variable, add also to verilog-preserve-dir-cache
9192 (defvar verilog-dir-cache-list nil
9193 "Alist of (((Cwd Dirname) Results)...) for caching `verilog-dir-files'.")
9194 (defvar verilog-dir-cache-lib-filenames nil
9195 "Cached data for `verilog-library-filenames'.")
9197 (defmacro verilog-preserve-dir-cache (&rest body)
9198 "Execute the BODY forms, allowing directory cache preservation within BODY.
9199 This means that changes inside BODY made to the file system will not be
9200 seen by the `verilog-dir-files' and related functions."
9201 `(let ((verilog-dir-cache-preserving (current-buffer))
9202 verilog-dir-cache-list
9203 verilog-dir-cache-lib-filenames)
9206 (defun verilog-dir-files (dirname)
9207 "Return all filenames in the DIRNAME directory.
9208 Relative paths depend on the `default-directory'.
9209 Results are cached if inside `verilog-preserve-dir-cache'."
9210 (unless verilog-dir-cache-preserving
9211 (setq verilog-dir-cache-list nil)) ;; Cache disabled
9212 ;; We don't use expand-file-name on the dirname to make key, as it's slow
9213 (let* ((cache-key (list dirname default-directory))
9214 (fass (assoc cache-key verilog-dir-cache-list))
9216 (cond (fass ;; Return data from cache hit
9219 (setq exp-dirname (expand-file-name dirname)
9220 data (and (file-directory-p exp-dirname)
9221 (directory-files exp-dirname nil nil nil)))
9222 ;; Note we also encache nil for non-existing dirs.
9223 (setq verilog-dir-cache-list (cons (list cache-key data)
9224 verilog-dir-cache-list))
9226 ;; Miss-and-hit test:
9227 ;;(verilog-preserve-dir-cache (prin1 (verilog-dir-files "."))
9228 ;; (prin1 (verilog-dir-files ".")) nil)
9230 (defun verilog-dir-file-exists-p (filename)
9231 "Return true if FILENAME exists.
9232 Like `file-exists-p' but results are cached if inside
9233 `verilog-preserve-dir-cache'."
9234 (let* ((dirname (file-name-directory filename))
9235 ;; Correct for file-name-nondirectory returning same if no slash.
9236 (dirnamed (if (or (not dirname) (equal dirname filename))
9237 default-directory dirname))
9238 (flist (verilog-dir-files dirnamed)))
9240 (member (file-name-nondirectory filename) flist)
9242 ;;(verilog-dir-file-exists-p "verilog-mode.el")
9243 ;;(verilog-dir-file-exists-p "../verilog-mode/verilog-mode.el")
9247 ;; Module name lookup
9250 (defun verilog-module-inside-filename-p (module filename)
9251 "Return modi if MODULE is specified inside FILENAME, else nil.
9252 Allows version control to check out the file if need be."
9253 (and (or (file-exists-p filename)
9254 (and (fboundp 'vc-backend)
9255 (vc-backend filename)))
9257 (with-current-buffer (find-file-noselect filename)
9259 (goto-char (point-min))
9261 ;; It may be tempting to look for verilog-defun-re,
9262 ;; don't, it slows things down a lot!
9263 (verilog-re-search-forward-quick "\\<\\(module\\|interface\\|program\\)\\>" nil t)
9264 (setq type (match-string-no-properties 0))
9265 (verilog-re-search-forward-quick "[(;]" nil t))
9266 (if (equal module (verilog-read-module-name))
9267 (setq modi (verilog-modi-new module filename (point) type))))
9270 (defun verilog-is-number (symbol)
9271 "Return true if SYMBOL is number-like."
9272 (or (string-match "^[0-9 \t:]+$" symbol)
9273 (string-match "^[---]*[0-9]+$" symbol)
9274 (string-match "^[0-9 \t]+'s?[hdxbo][0-9a-fA-F_xz? \t]*$" symbol)))
9276 (defun verilog-symbol-detick (symbol wing-it)
9277 "Return an expanded SYMBOL name without any defines.
9278 If the variable vh-{symbol} is defined, return that value.
9279 If undefined, and WING-IT, return just SYMBOL without the tick, else nil."
9280 (while (and symbol (string-match "^`" symbol))
9281 (setq symbol (substring symbol 1))
9283 (if (boundp (intern (concat "vh-" symbol)))
9284 ;; Emacs has a bug where boundp on a buffer-local
9285 ;; variable in only one buffer returns t in another.
9286 ;; This can confuse, so check for nil.
9287 (let ((val (eval (intern (concat "vh-" symbol)))))
9289 (if wing-it symbol nil)
9291 (if wing-it symbol nil))))
9293 ;;(verilog-symbol-detick "`mod" nil)
9295 (defun verilog-symbol-detick-denumber (symbol)
9296 "Return SYMBOL with defines converted and any numbers dropped to nil."
9297 (when (string-match "^`" symbol)
9298 ;; This only will work if the define is a simple signal, not
9299 ;; something like a[b]. Sorry, it should be substituted into the parser
9301 (verilog-string-replace-matches
9302 "\[[^0-9: \t]+\]" "" nil nil
9303 (or (verilog-symbol-detick symbol nil)
9304 (if verilog-auto-sense-defines-constant
9307 (if (verilog-is-number symbol)
9311 (defun verilog-symbol-detick-text (text)
9312 "Return TEXT without any known defines.
9313 If the variable vh-{symbol} is defined, substitute that value."
9314 (let ((ok t) symbol val)
9315 (while (and ok (string-match "`\\([a-zA-Z0-9_]+\\)" text))
9316 (setq symbol (match-string 1 text))
9319 (boundp (intern (concat "vh-" symbol)))
9320 ;; Emacs has a bug where boundp on a buffer-local
9321 ;; variable in only one buffer returns t in another.
9322 ;; This can confuse, so check for nil.
9323 (setq val (eval (intern (concat "vh-" symbol)))))
9324 (setq text (replace-match val nil nil text)))
9325 (t (setq ok nil)))))
9327 ;;(progn (setq vh-mod "`foo" vh-foo "bar") (verilog-symbol-detick-text "bar `mod `undefed"))
9329 (defun verilog-expand-dirnames (&optional dirnames)
9330 "Return a list of existing directories given a list of wildcarded DIRNAMES.
9331 Or, just the existing dirnames themselves if there are no wildcards."
9332 ;; Note this function is performance critical.
9333 ;; Do not call anything that requires disk access that cannot be cached.
9335 (unless dirnames (error "`verilog-library-directories' should include at least '.'"))
9336 (setq dirnames (reverse dirnames)) ; not nreverse
9338 pattern dirfile dirfiles dirname root filename rest basefile)
9340 (setq dirname (substitute-in-file-name (car dirnames))
9341 dirnames (cdr dirnames))
9342 (cond ((string-match (concat "^\\(\\|[/\\]*[^*?]*[/\\]\\)" ;; root
9343 "\\([^/\\]*[*?][^/\\]*\\)" ;; filename with *?
9346 (setq root (match-string 1 dirname)
9347 filename (match-string 2 dirname)
9348 rest (match-string 3 dirname)
9350 ;; now replace those * and ? with .+ and .
9351 ;; use ^ and /> to get only whole file names
9352 (setq pattern (verilog-string-replace-matches "[*]" ".+" nil nil pattern)
9353 pattern (verilog-string-replace-matches "[?]" "." nil nil pattern)
9354 pattern (concat "^" pattern "$")
9355 dirfiles (verilog-dir-files root))
9357 (setq basefile (car dirfiles)
9358 dirfile (expand-file-name (concat root basefile rest))
9359 dirfiles (cdr dirfiles))
9360 (if (and (string-match pattern basefile)
9361 ;; Don't allow abc/*/rtl to match abc/rtl via ..
9362 (not (equal basefile "."))
9363 (not (equal basefile ".."))
9364 (file-directory-p dirfile))
9365 (setq dirlist (cons dirfile dirlist)))))
9368 (if (file-directory-p dirname)
9369 (setq dirlist (cons dirname dirlist))))))
9371 ;;(verilog-expand-dirnames (list "." ".." "nonexist" "../*" "/home/wsnyder/*/v"))
9373 (defun verilog-library-filenames (filename &optional current check-ext)
9374 "Return a search path to find the given FILENAME or module name.
9375 Uses the optional CURRENT filename or variable `buffer-file-name', plus
9376 `verilog-library-directories' and `verilog-library-extensions'
9377 variables to build the path. With optional CHECK-EXT also check
9378 `verilog-library-extensions'."
9379 (unless current (setq current (buffer-file-name)))
9380 (unless verilog-dir-cache-preserving
9381 (setq verilog-dir-cache-lib-filenames nil))
9382 (let* ((cache-key (list filename current check-ext))
9383 (fass (assoc cache-key verilog-dir-cache-lib-filenames))
9384 chkdirs chkdir chkexts fn outlist)
9385 (cond (fass ;; Return data from cache hit
9388 ;; Note this expand can't be easily cached, as we need to
9389 ;; pick up buffer-local variables for newly read sub-module files
9390 (setq chkdirs (verilog-expand-dirnames verilog-library-directories))
9392 (setq chkdir (expand-file-name (car chkdirs)
9393 (file-name-directory current))
9394 chkexts (if check-ext verilog-library-extensions `("")))
9396 (setq fn (expand-file-name (concat filename (car chkexts))
9398 ;;(message "Check for %s" fn)
9399 (if (verilog-dir-file-exists-p fn)
9400 (setq outlist (cons (expand-file-name
9401 fn (file-name-directory current))
9403 (setq chkexts (cdr chkexts)))
9404 (setq chkdirs (cdr chkdirs)))
9405 (setq outlist (nreverse outlist))
9406 (setq verilog-dir-cache-lib-filenames
9407 (cons (list cache-key outlist)
9408 verilog-dir-cache-lib-filenames))
9411 (defun verilog-module-filenames (module current)
9412 "Return a search path to find the given MODULE name.
9413 Uses the CURRENT filename, `verilog-library-extensions',
9414 `verilog-library-directories' and `verilog-library-files'
9415 variables to build the path."
9416 ;; Return search locations for it
9417 (append (list current) ; first, current buffer
9418 (verilog-library-filenames module current t)
9419 verilog-library-files)) ; finally, any libraries
9422 ;; Module Information
9424 ;; Many of these functions work on "modi" a module information structure
9425 ;; A modi is: [module-name-string file-name begin-point]
9427 (defvar verilog-cache-enabled t
9428 "Non-nil enables caching of signals, etc. Set to nil for debugging to make things SLOW!")
9430 (defvar verilog-modi-cache-list nil
9431 "Cache of ((Module Function) Buf-Tick Buf-Modtime Func-Returns)...
9432 For speeding up verilog-modi-get-* commands.
9434 (make-variable-buffer-local 'verilog-modi-cache-list)
9436 (defvar verilog-modi-cache-preserve-tick nil
9437 "Modification tick after which the cache is still considered valid.
9438 Use `verilog-preserve-modi-cache' to set it.")
9439 (defvar verilog-modi-cache-preserve-buffer nil
9440 "Modification tick after which the cache is still considered valid.
9441 Use `verilog-preserve-modi-cache' to set it.")
9442 (defvar verilog-modi-cache-current-enable nil
9443 "Non-nil means allow caching `verilog-modi-current', set by let().")
9444 (defvar verilog-modi-cache-current nil
9445 "Currently active `verilog-modi-current', if any, set by let().")
9446 (defvar verilog-modi-cache-current-max nil
9447 "Current endmodule point for `verilog-modi-cache-current', if any.")
9449 (defun verilog-modi-current ()
9450 "Return the modi structure for the module currently at point, possibly cached."
9451 (cond ((and verilog-modi-cache-current
9452 (>= (point) (verilog-modi-get-point verilog-modi-cache-current))
9453 (<= (point) verilog-modi-cache-current-max))
9454 ;; Slow assertion, for debugging the cache:
9455 ;;(or (equal verilog-modi-cache-current (verilog-modi-current-get)) (debug))
9456 verilog-modi-cache-current)
9457 (verilog-modi-cache-current-enable
9458 (setq verilog-modi-cache-current (verilog-modi-current-get)
9459 verilog-modi-cache-current-max
9460 ;; The cache expires when we pass "endmodule" as then the
9461 ;; current modi may change to the next module
9462 ;; This relies on the AUTOs generally inserting, not deleting text
9464 (verilog-re-search-forward-quick verilog-end-defun-re nil nil)))
9465 verilog-modi-cache-current)
9467 (verilog-modi-current-get))))
9469 (defun verilog-modi-current-get ()
9470 "Return the modi structure for the module currently at point."
9471 (let* (name type pt)
9472 ;; read current module's name
9474 (verilog-re-search-backward-quick verilog-defun-re nil nil)
9475 (setq type (match-string-no-properties 0))
9476 (verilog-re-search-forward-quick "(" nil nil)
9477 (setq name (verilog-read-module-name))
9479 ;; return modi - note this vector built two places
9480 (verilog-modi-new name (or (buffer-file-name) (current-buffer)) pt type)))
9482 (defvar verilog-modi-lookup-cache nil "Hash of (modulename modi).")
9483 (make-variable-buffer-local 'verilog-modi-lookup-cache)
9484 (defvar verilog-modi-lookup-last-current nil "Cache of `current-buffer' at last lookup.")
9485 (defvar verilog-modi-lookup-last-tick nil "Cache of `buffer-chars-modified-tick' at last lookup.")
9487 (defun verilog-modi-lookup (module allow-cache &optional ignore-error)
9488 "Find the file and point at which MODULE is defined.
9489 If ALLOW-CACHE is set, check and remember cache of previous lookups.
9490 Return modi if successful, else print message unless IGNORE-ERROR is true."
9491 (let* ((current (or (buffer-file-name) (current-buffer)))
9494 ;;(message "verilog-modi-lookup: %s" module)
9495 (cond ((and verilog-modi-lookup-cache
9496 verilog-cache-enabled
9498 (setq modi (gethash module verilog-modi-lookup-cache))
9499 (equal verilog-modi-lookup-last-current current)
9500 ;; Iff hit is in current buffer, then tick must match
9501 (or (equal verilog-modi-lookup-last-tick (buffer-chars-modified-tick))
9502 (not (equal current (verilog-modi-file-or-buffer modi)))))
9503 ;;(message "verilog-modi-lookup: HIT %S" modi)
9506 (t (let* ((realname (verilog-symbol-detick module t))
9507 (orig-filenames (verilog-module-filenames realname current))
9508 (filenames orig-filenames)
9510 (while (and filenames (not mif))
9511 (if (not (setq mif (verilog-module-inside-filename-p realname (car filenames))))
9512 (setq filenames (cdr filenames))))
9513 ;; mif has correct form to become later elements of modi
9514 (cond (mif (setq modi mif))
9517 (error (concat (verilog-point-text)
9518 ": Can't locate " module " module definition"
9519 (if (not (equal module realname))
9520 (concat " (Expanded macro to " realname ")")
9522 "\n Check the verilog-library-directories variable."
9523 "\n I looked in (if not listed, doesn't exist):\n\t"
9524 (mapconcat 'concat orig-filenames "\n\t"))))))
9525 (when (eval-when-compile (fboundp 'make-hash-table))
9526 (unless verilog-modi-lookup-cache
9527 (setq verilog-modi-lookup-cache
9528 (make-hash-table :test 'equal :rehash-size 4.0)))
9529 (puthash module modi verilog-modi-lookup-cache))
9530 (setq verilog-modi-lookup-last-current current
9531 verilog-modi-lookup-last-tick (buffer-chars-modified-tick)))))
9534 (defun verilog-modi-filename (modi)
9535 "Filename of MODI, or name of buffer if it's never been saved."
9536 (if (bufferp (verilog-modi-file-or-buffer modi))
9537 (or (buffer-file-name (verilog-modi-file-or-buffer modi))
9538 (buffer-name (verilog-modi-file-or-buffer modi)))
9539 (verilog-modi-file-or-buffer modi)))
9541 (defun verilog-modi-goto (modi)
9542 "Move point/buffer to specified MODI."
9543 (or modi (error "Passed unfound modi to goto, check earlier"))
9544 (set-buffer (if (bufferp (verilog-modi-file-or-buffer modi))
9545 (verilog-modi-file-or-buffer modi)
9546 (find-file-noselect (verilog-modi-file-or-buffer modi))))
9547 (or (equal major-mode `verilog-mode) ;; Put into Verilog mode to get syntax
9549 (goto-char (verilog-modi-get-point modi)))
9551 (defun verilog-goto-defun-file (module)
9552 "Move point to the file at which a given MODULE is defined."
9553 (interactive "sGoto File for Module: ")
9554 (let* ((modi (verilog-modi-lookup module nil)))
9556 (verilog-modi-goto modi)
9557 (switch-to-buffer (current-buffer)))))
9559 (defun verilog-modi-cache-results (modi function)
9560 "Run on MODI the given FUNCTION. Locate the module in a file.
9561 Cache the output of function so next call may have faster access."
9563 (save-excursion ;; Cache is buffer-local so can't avoid this.
9564 (verilog-modi-goto modi)
9565 (if (and (setq fass (assoc (list modi function)
9566 verilog-modi-cache-list))
9567 ;; Destroy caching when incorrect; Modified or file changed
9568 (not (and verilog-cache-enabled
9569 (or (equal (buffer-chars-modified-tick) (nth 1 fass))
9570 (and verilog-modi-cache-preserve-tick
9571 (<= verilog-modi-cache-preserve-tick (nth 1 fass))
9572 (equal verilog-modi-cache-preserve-buffer (current-buffer))))
9573 (equal (visited-file-modtime) (nth 2 fass)))))
9574 (setq verilog-modi-cache-list nil
9577 ;; Return data from cache hit
9581 ;; Clear then restore any highlighting to make emacs19 happy
9583 (verilog-save-font-mods
9584 (setq func-returns (funcall function)))
9585 ;; Cache for next time
9586 (setq verilog-modi-cache-list
9587 (cons (list (list modi function)
9588 (buffer-chars-modified-tick)
9589 (visited-file-modtime)
9591 verilog-modi-cache-list))
9594 (defun verilog-modi-cache-add (modi function element sig-list)
9595 "Add function return results to the module cache.
9596 Update MODI's cache for given FUNCTION so that the return ELEMENT of that
9597 function now contains the additional SIG-LIST parameters."
9600 (verilog-modi-goto modi)
9601 (if (setq fass (assoc (list modi function)
9602 verilog-modi-cache-list))
9603 (let ((func-returns (nth 3 fass)))
9604 (aset func-returns element
9605 (append sig-list (aref func-returns element))))))))
9607 (defmacro verilog-preserve-modi-cache (&rest body)
9608 "Execute the BODY forms, allowing cache preservation within BODY.
9609 This means that changes to the buffer will not result in the cache being
9610 flushed. If the changes affect the modsig state, they must call the
9611 modsig-cache-add-* function, else the results of later calls may be
9612 incorrect. Without this, changes are assumed to be adding/removing signals
9613 and invalidating the cache."
9614 `(let ((verilog-modi-cache-preserve-tick (buffer-chars-modified-tick))
9615 (verilog-modi-cache-preserve-buffer (current-buffer)))
9619 (defun verilog-modi-modport-lookup-one (modi name &optional ignore-error)
9620 "Given a MODI, return the declarations related to the given modport NAME."
9621 ;; Recursive routine - see below
9622 (let* ((realname (verilog-symbol-detick name t))
9623 (modport (assoc name (verilog-decls-get-modports (verilog-modi-get-decls modi)))))
9624 (or modport ignore-error
9625 (error (concat (verilog-point-text)
9626 ": Can't locate " name " modport definition"
9627 (if (not (equal name realname))
9628 (concat " (Expanded macro to " realname ")")
9630 (let* ((decls (verilog-modport-decls modport))
9631 (clks (verilog-modport-clockings modport)))
9632 ;; Now expand any clocking's
9634 (setq decls (verilog-decls-append
9636 (verilog-modi-modport-lookup-one modi (car clks) ignore-error)))
9637 (setq clks (cdr clks)))
9640 (defun verilog-modi-modport-lookup (modi name-re &optional ignore-error)
9641 "Given a MODI, return the declarations related to the given modport NAME-RE.
9642 If the modport points to any clocking blocks, expand the signals to include
9643 those clocking block's signals."
9644 ;; Recursive routine - see below
9645 (let* ((mod-decls (verilog-modi-get-decls modi))
9646 (clks (verilog-decls-get-modports mod-decls))
9647 (name-re (concat "^" name-re "$"))
9648 (decls (verilog-decls-new nil nil nil nil nil nil nil nil nil)))
9649 ;; Pull in all modports
9651 (when (string-match name-re (verilog-modport-name (car clks)))
9652 (setq decls (verilog-decls-append
9654 (verilog-modi-modport-lookup-one modi (verilog-modport-name (car clks)) ignore-error))))
9655 (setq clks (cdr clks)))
9658 (defun verilog-signals-matching-enum (in-list enum)
9659 "Return all signals in IN-LIST matching the given ENUM."
9662 (if (equal (verilog-sig-enum (car in-list)) enum)
9663 (setq out-list (cons (car in-list) out-list)))
9664 (setq in-list (cdr in-list)))
9666 (let* ((enumvar (intern (concat "venum-" enum)))
9667 (enumlist (and (boundp enumvar) (eval enumvar))))
9669 (add-to-list 'out-list (list (car enumlist)))
9670 (setq enumlist (cdr enumlist))))
9671 (nreverse out-list)))
9673 (defun verilog-signals-matching-regexp (in-list regexp)
9674 "Return all signals in IN-LIST matching the given REGEXP, if non-nil."
9675 (if (or (not regexp) (equal regexp ""))
9679 (if (string-match regexp (verilog-sig-name (car in-list)))
9680 (setq out-list (cons (car in-list) out-list)))
9681 (setq in-list (cdr in-list)))
9682 (nreverse out-list))))
9684 (defun verilog-signals-not-matching-regexp (in-list regexp)
9685 "Return all signals in IN-LIST not matching the given REGEXP, if non-nil."
9686 (if (or (not regexp) (equal regexp ""))
9690 (if (not (string-match regexp (verilog-sig-name (car in-list))))
9691 (setq out-list (cons (car in-list) out-list)))
9692 (setq in-list (cdr in-list)))
9693 (nreverse out-list))))
9695 (defun verilog-signals-matching-dir-re (in-list decl-type regexp)
9696 "Return all signals in IN-LIST matching the given DECL-TYPE and REGEXP,
9698 (if (or (not regexp) (equal regexp ""))
9700 (let (out-list to-match)
9702 ;; Note verilog-insert-one-definition matches on this order
9703 (setq to-match (concat
9705 " " (verilog-sig-signed (car in-list))
9706 " " (verilog-sig-multidim (car in-list))
9707 (verilog-sig-bits (car in-list))))
9708 (if (string-match regexp to-match)
9709 (setq out-list (cons (car in-list) out-list)))
9710 (setq in-list (cdr in-list)))
9711 (nreverse out-list))))
9713 (defun verilog-signals-edit-wire-reg (in-list)
9714 "Return all signals in IN-LIST with wire/reg data types made blank."
9715 (mapcar (lambda (sig)
9716 (when (member (verilog-sig-type sig) '("wire" "reg"))
9717 (verilog-sig-type-set sig nil))
9721 (defun verilog-decls-get-signals (decls)
9722 "Return all declared signals in DECLS, excluding 'assign' statements."
9724 (verilog-decls-get-outputs decls)
9725 (verilog-decls-get-inouts decls)
9726 (verilog-decls-get-inputs decls)
9727 (verilog-decls-get-vars decls)
9728 (verilog-decls-get-consts decls)
9729 (verilog-decls-get-gparams decls)))
9731 (defun verilog-decls-get-ports (decls)
9733 (verilog-decls-get-outputs decls)
9734 (verilog-decls-get-inouts decls)
9735 (verilog-decls-get-inputs decls)))
9737 (defun verilog-decls-get-iovars (decls)
9739 (verilog-decls-get-vars decls)
9740 (verilog-decls-get-outputs decls)
9741 (verilog-decls-get-inouts decls)
9742 (verilog-decls-get-inputs decls)))
9744 (defsubst verilog-modi-cache-add-outputs (modi sig-list)
9745 (verilog-modi-cache-add modi 'verilog-read-decls 0 sig-list))
9746 (defsubst verilog-modi-cache-add-inouts (modi sig-list)
9747 (verilog-modi-cache-add modi 'verilog-read-decls 1 sig-list))
9748 (defsubst verilog-modi-cache-add-inputs (modi sig-list)
9749 (verilog-modi-cache-add modi 'verilog-read-decls 2 sig-list))
9750 (defsubst verilog-modi-cache-add-vars (modi sig-list)
9751 (verilog-modi-cache-add modi 'verilog-read-decls 3 sig-list))
9752 (defsubst verilog-modi-cache-add-gparams (modi sig-list)
9753 (verilog-modi-cache-add modi 'verilog-read-decls 7 sig-list))
9757 ;; Auto creation utilities
9760 (defun verilog-auto-re-search-do (search-for func)
9761 "Search for the given auto text regexp SEARCH-FOR, and perform FUNC where it occurs."
9762 (goto-char (point-min))
9763 (while (verilog-re-search-forward-quick search-for nil t)
9766 (defun verilog-insert-one-definition (sig type indent-pt)
9767 "Print out a definition for SIG of the given TYPE,
9768 with appropriate INDENT-PT indentation."
9769 (indent-to indent-pt)
9770 ;; Note verilog-signals-matching-dir-re matches on this order
9772 (when (verilog-sig-modport sig)
9773 (insert "." (verilog-sig-modport sig)))
9774 (when (verilog-sig-signed sig)
9775 (insert " " (verilog-sig-signed sig)))
9776 (when (verilog-sig-multidim sig)
9777 (insert " " (verilog-sig-multidim-string sig)))
9778 (when (verilog-sig-bits sig)
9779 (insert " " (verilog-sig-bits sig)))
9780 (indent-to (max 24 (+ indent-pt 16)))
9781 (unless (= (char-syntax (preceding-char)) ?\ )
9782 (insert " ")) ; Need space between "]name" if indent-to did nothing
9783 (insert (verilog-sig-name sig))
9784 (when (verilog-sig-memory sig)
9785 (insert " " (verilog-sig-memory sig))))
9787 (defun verilog-insert-definition (modi sigs direction indent-pt v2k &optional dont-sort)
9788 "Print out a definition for MODI's list of SIGS of the given DIRECTION,
9789 with appropriate INDENT-PT indentation. If V2K, use Verilog 2001 I/O
9790 format. Sort unless DONT-SORT. DIRECTION is normally wire/reg/output.
9791 When MODI is non-null, also add to modi-cache, for tracking."
9793 (cond ((equal direction "wire")
9794 (verilog-modi-cache-add-vars modi sigs))
9795 ((equal direction "reg")
9796 (verilog-modi-cache-add-vars modi sigs))
9797 ((equal direction "output")
9798 (verilog-modi-cache-add-outputs modi sigs)
9799 (when verilog-auto-declare-nettype
9800 (verilog-modi-cache-add-vars modi sigs)))
9801 ((equal direction "input")
9802 (verilog-modi-cache-add-inputs modi sigs)
9803 (when verilog-auto-declare-nettype
9804 (verilog-modi-cache-add-vars modi sigs)))
9805 ((equal direction "inout")
9806 (verilog-modi-cache-add-inouts modi sigs)
9807 (when verilog-auto-declare-nettype
9808 (verilog-modi-cache-add-vars modi sigs)))
9809 ((equal direction "interface"))
9810 ((equal direction "parameter")
9811 (verilog-modi-cache-add-gparams modi sigs))
9813 (error "Unsupported verilog-insert-definition direction: %s" direction))))
9815 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
9817 (let ((sig (car sigs)))
9818 (verilog-insert-one-definition
9820 ;; Want "type x" or "output type x", not "wire type x"
9821 (cond ((or (verilog-sig-type sig)
9822 verilog-auto-wire-type)
9824 (when (member direction '("input" "output" "inout"))
9825 (concat direction " "))
9826 (or (verilog-sig-type sig)
9827 verilog-auto-wire-type)))
9828 ((and verilog-auto-declare-nettype
9829 (member direction '("input" "output" "inout")))
9830 (concat direction " " verilog-auto-declare-nettype))
9834 (insert (if v2k "," ";"))
9835 (if (or (not (verilog-sig-comment sig))
9836 (equal "" (verilog-sig-comment sig)))
9838 (indent-to (max 48 (+ indent-pt 40)))
9839 (verilog-insert "// " (verilog-sig-comment sig) "\n"))
9840 (setq sigs (cdr sigs)))))
9843 (if (not (boundp 'indent-pt))
9844 (defvar indent-pt nil "Local used by insert-indent")))
9846 (defun verilog-insert-indent (&rest stuff)
9847 "Indent to position stored in local `indent-pt' variable, then insert STUFF.
9848 Presumes that any newlines end a list element."
9849 (let ((need-indent t))
9851 (if need-indent (indent-to indent-pt))
9852 (setq need-indent nil)
9853 (verilog-insert (car stuff))
9854 (setq need-indent (string-match "\n$" (car stuff))
9855 stuff (cdr stuff)))))
9856 ;;(let ((indent-pt 10)) (verilog-insert-indent "hello\n" "addon" "there\n"))
9858 (defun verilog-forward-or-insert-line ()
9859 "Move forward a line, unless at EOB, then insert a newline."
9860 (if (eobp) (insert "\n")
9863 (defun verilog-repair-open-comma ()
9864 "Insert comma if previous argument is other than an open parenthesis or endif."
9865 ;; We can't just search backward for ) as it might be inside another expression.
9866 ;; Also want "`ifdef X input foo `endif" to just leave things to the human to deal with
9868 (verilog-backward-syntactic-ws-quick)
9869 (when (and (not (save-excursion ;; Not beginning (, or existing ,
9871 (looking-at "[(,]")))
9872 (not (save-excursion ;; Not `endif, or user define
9874 (skip-chars-backward "[a-zA-Z0-9_`]")
9878 (defun verilog-repair-close-comma ()
9879 "If point is at a comma followed by a close parenthesis, fix it.
9880 This repairs those mis-inserted by an AUTOARG."
9881 ;; It would be much nicer if Verilog allowed extra commas like Perl does!
9883 (verilog-forward-close-paren)
9885 (verilog-backward-syntactic-ws-quick)
9887 (when (looking-at ",")
9890 (defun verilog-get-list (start end)
9891 "Return the elements of a comma separated list between START and END."
9893 (let ((my-list (list))
9896 (while (< (point) end)
9897 (when (re-search-forward "\\([^,{]+\\)" end t)
9898 (setq my-string (verilog-string-remove-spaces (match-string 1)))
9899 (setq my-list (nconc my-list (list my-string) ))
9900 (goto-char (match-end 0))))
9903 (defun verilog-make-width-expression (range-exp)
9904 "Return an expression calculating the length of a range [x:y] in RANGE-EXP."
9906 (cond ((not range-exp)
9909 (if (string-match "^\\[\\(.*\\)\\]$" range-exp)
9910 (setq range-exp (match-string 1 range-exp)))
9911 (cond ((not range-exp)
9913 ;; [#:#] We can compute a numeric result
9914 ((string-match "^\\s *\\([0-9]+\\)\\s *:\\s *\\([0-9]+\\)\\s *$"
9917 (1+ (abs (- (string-to-number (match-string 1 range-exp))
9918 (string-to-number (match-string 2 range-exp)))))))
9919 ;; [PARAM-1:0] can just return PARAM
9920 ((string-match "^\\s *\\([a-zA-Z_][a-zA-Z0-9_]*\\)\\s *-\\s *1\\s *:\\s *0\\s *$" range-exp)
9921 (match-string 1 range-exp))
9922 ;; [arbitrary] need math
9923 ((string-match "^\\(.*\\)\\s *:\\s *\\(.*\\)\\s *$" range-exp)
9924 (concat "(1+(" (match-string 1 range-exp) ")"
9925 (if (equal "0" (match-string 2 range-exp))
9926 "" ;; Don't bother with -(0)
9927 (concat "-(" (match-string 2 range-exp) ")"))
9930 ;;(verilog-make-width-expression "`A:`B")
9932 (defun verilog-simplify-range-expression (expr)
9933 "Return a simplified range expression with constants eliminated from EXPR."
9934 ;; Note this is always called with brackets; ie [z] or [z:z]
9935 (if (not (string-match "[---+*()]" expr))
9936 expr ;; short-circuit
9939 (while (not (equal last-pass out))
9940 (setq last-pass out)
9941 ;; Prefix regexp needs beginning of match, or some symbol of
9942 ;; lesser or equal precedence. We assume the [:]'s exist in expr.
9944 (while (string-match
9945 (concat "\\([[({:*+-]\\)" ; - must be last
9946 "(\\<\\([0-9A-Za-z_]+\\))"
9949 (setq out (replace-match "\\1\\2\\3" nil nil out)))
9950 (while (string-match
9951 (concat "\\([[({:*+-]\\)" ; - must be last
9952 "\\$clog2\\s *(\\<\\([0-9]+\\))"
9955 (setq out (replace-match
9957 (match-string 1 out)
9958 (int-to-string (verilog-clog2 (string-to-number (match-string 2 out))))
9959 (match-string 3 out))
9961 ;; For precedence do * before +/-
9962 (while (string-match
9963 (concat "\\([[({:*+-]\\)"
9964 "\\([0-9]+\\)\\s *\\([*]\\)\\s *\\([0-9]+\\)"
9967 (setq out (replace-match
9968 (concat (match-string 1 out)
9969 (int-to-string (* (string-to-number (match-string 2 out))
9970 (string-to-number (match-string 4 out))))
9971 (match-string 5 out))
9973 (while (string-match
9974 (concat "\\([[({:+-]\\)" ; No * here as higher prec
9975 "\\([0-9]+\\)\\s *\\([---+]\\)\\s *\\([0-9]+\\)"
9978 (let ((pre (match-string 1 out))
9979 (lhs (string-to-number (match-string 2 out)))
9980 (rhs (string-to-number (match-string 4 out)))
9981 (post (match-string 5 out))
9983 (when (equal pre "-")
9985 (setq val (if (equal (match-string 3 out) "-")
9989 (concat (if (and (equal pre "-")
9991 "" ;; Not "--20" but just "-20"
9998 ;;(verilog-simplify-range-expression "[1:3]") ;; 1
9999 ;;(verilog-simplify-range-expression "[(1):3]") ;; 1
10000 ;;(verilog-simplify-range-expression "[(((16)+1)+1+(1+1))]") ;;20
10001 ;;(verilog-simplify-range-expression "[(2*3+6*7)]") ;; 48
10002 ;;(verilog-simplify-range-expression "[(FOO*4-1*2)]") ;; FOO*4-2
10003 ;;(verilog-simplify-range-expression "[(FOO*4+1-1)]") ;; FOO*4+0
10004 ;;(verilog-simplify-range-expression "[(func(BAR))]") ;; func(BAR)
10005 ;;(verilog-simplify-range-expression "[FOO-1+1-1+1]") ;; FOO-0
10006 ;;(verilog-simplify-range-expression "[$clog2(2)]") ;; 1
10007 ;;(verilog-simplify-range-expression "[$clog2(7)]") ;; 3
10009 (defun verilog-clog2 (value)
10010 "Compute $clog2 - ceiling log2 of VALUE."
10013 (ceiling (/ (log value) (log 2)))))
10015 (defun verilog-typedef-name-p (variable-name)
10016 "Return true if the VARIABLE-NAME is a type definition."
10017 (when verilog-typedef-regexp
10018 (string-match verilog-typedef-regexp variable-name)))
10024 (defun verilog-delete-autos-lined ()
10025 "Delete autos that occupy multiple lines, between begin and end comments."
10026 ;; The newline must not have a comment property, so we must
10027 ;; delete the end auto's newline, not the first newline
10029 (let ((pt (point)))
10031 (looking-at "\\s-*// Beginning")
10032 (search-forward "// End of automatic" nil t))
10036 (delete-region pt (point)))))
10038 (defun verilog-delete-empty-auto-pair ()
10039 "Delete begin/end auto pair at point, if empty."
10041 (when (looking-at (concat "\\s-*// Beginning of automatic.*\n"
10042 "\\s-*// End of automatics\n"))
10043 (delete-region (point) (save-excursion (forward-line 2) (point)))))
10045 (defun verilog-forward-close-paren ()
10046 "Find the close parenthesis that match the current point.
10047 Ignore other close parenthesis with matching open parens."
10049 (while (> parens 0)
10050 (unless (verilog-re-search-forward-quick "[()]" nil t)
10051 (error "%s: Mismatching ()" (verilog-point-text)))
10052 (cond ((= (preceding-char) ?\( )
10053 (setq parens (1+ parens)))
10054 ((= (preceding-char) ?\) )
10055 (setq parens (1- parens)))))))
10057 (defun verilog-backward-open-paren ()
10058 "Find the open parenthesis that match the current point.
10059 Ignore other open parenthesis with matching close parens."
10061 (while (> parens 0)
10062 (unless (verilog-re-search-backward-quick "[()]" nil t)
10063 (error "%s: Mismatching ()" (verilog-point-text)))
10064 (cond ((= (following-char) ?\) )
10065 (setq parens (1+ parens)))
10066 ((= (following-char) ?\( )
10067 (setq parens (1- parens)))))))
10069 (defun verilog-backward-open-bracket ()
10070 "Find the open bracket that match the current point.
10071 Ignore other open bracket with matching close bracket."
10073 (while (> parens 0)
10074 (unless (verilog-re-search-backward-quick "[][]" nil t)
10075 (error "%s: Mismatching []" (verilog-point-text)))
10076 (cond ((= (following-char) ?\] )
10077 (setq parens (1+ parens)))
10078 ((= (following-char) ?\[ )
10079 (setq parens (1- parens)))))))
10081 (defun verilog-delete-to-paren ()
10082 "Delete the automatic inst/sense/arg created by autos.
10083 Deletion stops at the matching end parenthesis, outside comments."
10084 (delete-region (point)
10086 (verilog-backward-open-paren)
10087 (verilog-forward-sexp-ign-cmt 1) ;; Moves to paren that closes argdecl's
10091 (defun verilog-auto-star-safe ()
10092 "Return if a .* AUTOINST is safe to delete or expand.
10093 It was created by the AUTOS themselves, or by the user."
10094 (and verilog-auto-star-expand
10096 (concat "[ \t\n\f,]*\\([)]\\|// " verilog-inst-comment-re "\\)"))))
10098 (defun verilog-delete-auto-star-all ()
10099 "Delete a .* AUTOINST, if it is safe."
10100 (when (verilog-auto-star-safe)
10101 (verilog-delete-to-paren)))
10103 (defun verilog-delete-auto-star-implicit ()
10104 "Delete all .* implicit connections created by `verilog-auto-star'.
10105 This function will be called automatically at save unless
10106 `verilog-auto-star-save' is set, any non-templated expanded pins will be
10109 (let (paren-pt indent have-close-paren)
10111 (goto-char (point-min))
10112 ;; We need to match these even outside of comments.
10113 ;; For reasonable performance, we don't check if inside comments, sorry.
10114 (while (re-search-forward "// Implicit \\.\\*" nil t)
10115 (setq paren-pt (point))
10116 (beginning-of-line)
10117 (setq have-close-paren
10119 (when (search-forward ");" paren-pt t)
10120 (setq indent (current-indentation))
10122 (delete-region (point) (+ 1 paren-pt)) ; Nuke line incl CR
10123 (when have-close-paren
10124 ;; Delete extra commentary
10128 (looking-at (concat "\\s *//\\s *" verilog-inst-comment-re "\n")))
10129 (delete-region (match-beginning 0) (match-end 0))))
10130 ;; If it is simple, we can put the ); on the same line as the last text
10131 (let ((rtn-pt (point)))
10133 (while (progn (backward-char 1)
10134 (looking-at "[ \t\n\f]")))
10135 (when (looking-at ",")
10136 (delete-region (+ 1 (point)) rtn-pt))))
10138 (indent-to indent))
10140 ;; Still need to kill final comma - always is one as we put one after the .*
10141 (re-search-backward ",")
10142 (delete-char 1))))))
10144 (defun verilog-delete-auto ()
10145 "Delete the automatic outputs, regs, and wires created by \\[verilog-auto].
10146 Use \\[verilog-auto] to re-insert the updated AUTOs.
10148 The hooks `verilog-before-delete-auto-hook' and `verilog-delete-auto-hook' are
10149 called before and after this function, respectively."
10152 (if (buffer-file-name)
10153 (find-file-noselect (buffer-file-name))) ;; To check we have latest version
10154 (verilog-save-no-change-functions
10155 (verilog-save-scan-cache
10156 ;; Allow user to customize
10157 (verilog-run-hooks 'verilog-before-delete-auto-hook)
10159 ;; Remove those that have multi-line insertions, possibly with parameters
10160 ;; We allow anything beginning with AUTO, so that users can add their own
10162 (verilog-auto-re-search-do
10163 (concat "/\\*AUTO[A-Za-z0-9_]+"
10164 ;; Optional parens or quoted parameter or .* for (((...)))
10165 "\\(\\|([^)]*)\\|(\"[^\"]*\")\\).*?"
10167 'verilog-delete-autos-lined)
10168 ;; Remove those that are in parenthesis
10169 (verilog-auto-re-search-do
10172 (verilog-regexp-words
10173 `("AS" "AUTOARG" "AUTOCONCATWIDTH" "AUTOINST" "AUTOINSTPARAM"
10176 'verilog-delete-to-paren)
10177 ;; Do .* instantiations, but avoid removing any user pins by looking for our magic comments
10178 (verilog-auto-re-search-do "\\.\\*"
10179 'verilog-delete-auto-star-all)
10180 ;; Remove template comments ... anywhere in case was pasted after AUTOINST removed
10181 (goto-char (point-min))
10182 (while (re-search-forward "\\s-*// \\(Templated\\|Implicit \\.\\*\\)\\([ \tLT0-9]*\\| LHS: .*\\)?$" nil t)
10183 (replace-match ""))
10186 (verilog-run-hooks 'verilog-delete-auto-hook)))))
10192 (defun verilog-inject-auto ()
10193 "Examine legacy non-AUTO code and insert AUTOs in appropriate places.
10195 Any always @ blocks with sensitivity lists that match computed lists will
10196 be replaced with /*AS*/ comments.
10198 Any cells will get /*AUTOINST*/ added to the end of the pin list.
10199 Pins with have identical names will be deleted.
10201 Argument lists will not be deleted, /*AUTOARG*/ will only be inserted to
10202 support adding new ports. You may wish to delete older ports yourself.
10206 module ExampInject (i, o);
10212 InstModule instName
10217 Typing \\[verilog-inject-auto] will make this into:
10219 module ExampInject (i, o/*AUTOARG*/
10224 always @ (/*AS*/i or j)
10226 InstModule instName
10235 (defun verilog-inject-arg ()
10236 "Inject AUTOARG into new code. See `verilog-inject-auto'."
10237 ;; Presume one module per file.
10239 (goto-char (point-min))
10240 (while (verilog-re-search-forward-quick "\\<module\\>" nil t)
10241 (let ((endmodp (save-excursion
10242 (verilog-re-search-forward-quick "\\<endmodule\\>" nil t)
10244 ;; See if there's already a comment .. inside a comment so not verilog-re-search
10245 (when (not (re-search-forward "/\\*AUTOARG\\*/" endmodp t))
10246 (verilog-re-search-forward-quick ";" nil t)
10248 (verilog-backward-syntactic-ws-quick)
10249 (backward-char 1) ; Moves to paren that closes argdecl's
10250 (when (looking-at ")")
10251 (verilog-insert "/*AUTOARG*/")))))))
10253 (defun verilog-inject-sense ()
10254 "Inject AUTOSENSE into new code. See `verilog-inject-auto'."
10256 (goto-char (point-min))
10257 (while (verilog-re-search-forward-quick "\\<always\\s *@\\s *(" nil t)
10258 (let* ((start-pt (point))
10259 (modi (verilog-modi-current))
10260 (moddecls (verilog-modi-get-decls modi))
10264 (verilog-forward-sexp-ign-cmt 1)
10265 (backward-char 1) ;; End )
10266 (when (not (verilog-re-search-backward-quick "/\\*\\(AUTOSENSE\\|AS\\)\\*/" start-pt t))
10267 (setq pre-sigs (verilog-signals-from-signame
10268 (verilog-read-signals start-pt (point)))
10269 got-sigs (verilog-auto-sense-sigs moddecls nil))
10270 (when (not (or (verilog-signals-not-in pre-sigs got-sigs) ; Both are equal?
10271 (verilog-signals-not-in got-sigs pre-sigs)))
10272 (delete-region start-pt (point))
10273 (verilog-insert "/*AS*/")))))))
10275 (defun verilog-inject-inst ()
10276 "Inject AUTOINST into new code. See `verilog-inject-auto'."
10278 (goto-char (point-min))
10279 ;; It's hard to distinguish modules; we'll instead search for pins.
10280 (while (verilog-re-search-forward-quick "\\.\\s *[a-zA-Z0-9`_\$]+\\s *(\\s *[a-zA-Z0-9`_\$]+\\s *)" nil t)
10281 (verilog-backward-open-paren) ;; Inst start
10283 ((= (preceding-char) ?\#) ;; #(...) parameter section, not pin. Skip.
10285 (verilog-forward-close-paren)) ;; Parameters done
10288 (let ((indent-pt (+ (current-column)))
10289 (end-pt (save-excursion (verilog-forward-close-paren) (point))))
10290 (cond ((verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-pt t)
10291 (goto-char end-pt)) ;; Already there, continue search with next instance
10293 ;; Delete identical interconnect
10294 (let ((case-fold-search nil)) ;; So we don't convert upper-to-lower, etc
10295 (while (verilog-re-search-forward-quick "\\.\\s *\\([a-zA-Z0-9`_\$]+\\)*\\s *(\\s *\\1\\s *)\\s *" end-pt t)
10296 (delete-region (match-beginning 0) (match-end 0))
10297 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))) ;; Keep it correct
10298 (while (or (looking-at "[ \t\n\f,]+")
10299 (looking-at "//[^\n]*"))
10300 (delete-region (match-beginning 0) (match-end 0))
10301 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))))))
10302 (verilog-forward-close-paren)
10304 ;; Not verilog-re-search, as we don't want to strip comments
10305 (while (re-search-backward "[ \t\n\f]+" (- (point) 1) t)
10306 (delete-region (match-beginning 0) (match-end 0)))
10307 (verilog-insert "\n")
10308 (verilog-insert-indent "/*AUTOINST*/")))))))))
10314 (defun verilog-diff-buffers-p (b1 b2 &optional whitespace)
10315 "Return nil if buffers B1 and B2 have same contents.
10316 Else, return point in B1 that first mismatches.
10317 If optional WHITESPACE true, ignore whitespace."
10319 (let* ((case-fold-search nil) ;; compare-buffer-substrings cares
10320 (p1 (with-current-buffer b1 (goto-char (point-min))))
10321 (p2 (with-current-buffer b2 (goto-char (point-min))))
10322 (maxp1 (with-current-buffer b1 (point-max)))
10323 (maxp2 (with-current-buffer b2 (point-max)))
10326 (while (not (and (eq p1 op1) (eq p2 op2)))
10327 ;; If both windows have whitespace optionally skip over it.
10329 ;; skip-syntax-* doesn't count \n
10330 (with-current-buffer b1
10332 (skip-chars-forward " \t\n\r\f\v")
10334 (with-current-buffer b2
10336 (skip-chars-forward " \t\n\r\f\v")
10337 (setq p2 (point))))
10338 (setq size (min (- maxp1 p1) (- maxp2 p2)))
10339 (setq progress (compare-buffer-substrings b2 p2 (+ size p2)
10340 b1 p1 (+ size p1)))
10341 (setq progress (if (zerop progress) size (1- (abs progress))))
10342 (setq op1 p1 op2 p2
10344 p2 (+ p2 progress)))
10346 (if (and (eq p1 maxp1) (eq p2 maxp2))
10349 (defun verilog-diff-file-with-buffer (f1 b2 &optional whitespace show)
10350 "View the differences between file F1 and buffer B2.
10351 This requires the external program `diff-command' to be in your `exec-path',
10352 and uses `diff-switches' in which you may want to have \"-u\" flag.
10353 Ignores WHITESPACE if t, and writes output to stdout if SHOW."
10354 ;; Similar to `diff-buffer-with-file' but works on XEmacs, and doesn't
10355 ;; call `diff' as `diff' has different calling semantics on different
10356 ;; versions of Emacs.
10357 (if (not (file-exists-p f1))
10358 (message "Buffer %s has no associated file on disc" (buffer-name b2))
10359 (with-temp-buffer "*Verilog-Diff*"
10360 (let ((outbuf (current-buffer))
10361 (f2 (make-temp-file "vm-diff-auto-")))
10364 (with-current-buffer b2
10367 (write-region (point-min) (point-max) f2 nil 'nomessage)))
10368 (call-process diff-command nil outbuf t
10369 diff-switches ;; User may want -u in diff-switches
10370 (if whitespace "-b" "")
10372 ;; Print out results. Alternatively we could have call-processed
10373 ;; ourself, but this way we can reuse diff switches
10375 (with-current-buffer outbuf (message "%s" (buffer-string))))))
10377 (when (file-exists-p f2)
10378 (delete-file f2))))))
10380 (defun verilog-diff-report (b1 b2 diffpt)
10381 "Report differences detected with `verilog-diff-auto'.
10382 Differences are between buffers B1 and B2, starting at point
10383 DIFFPT. This function is called via `verilog-diff-function'."
10384 (let ((name1 (with-current-buffer b1 (buffer-file-name))))
10385 (verilog-warn "%s:%d: Difference in AUTO expansion found"
10386 name1 (with-current-buffer b1
10387 (1+ (count-lines (point-min) (point)))))
10388 (cond (noninteractive
10389 (verilog-diff-file-with-buffer name1 b2 t t))
10391 (ediff-buffers b1 b2)))))
10393 (defun verilog-diff-auto ()
10394 "Expand AUTOs in a temporary buffer and indicate any change.
10395 Whitespace differences are ignored to determine identicalness, but
10396 once a difference is detected, whitespace differences may be shown.
10398 To call this from the command line, see \\[verilog-batch-diff-auto].
10400 The action on differences is selected with
10401 `verilog-diff-function'. The default is `verilog-diff-report'
10402 which will report an error and run `ediff' in interactive mode,
10403 or `diff' in batch mode."
10405 (let ((b1 (current-buffer)) b2 diffpt
10406 (name1 (buffer-file-name))
10407 (newname "*Verilog-Diff*"))
10409 (when (get-buffer newname)
10410 (kill-buffer newname))
10411 (setq b2 (let (buffer-file-name) ;; Else clone is upset
10412 (clone-buffer newname)))
10413 (with-current-buffer b2
10414 ;; auto requires the filename, but can't have same filename in two
10415 ;; buffers; so override both b1 and b2's names
10416 (let ((buffer-file-name name1))
10419 (with-current-buffer b1 (setq buffer-file-name nil))
10421 (when (not verilog-auto-star-save)
10422 (verilog-delete-auto-star-implicit)))
10423 ;; Restore name if unwind
10424 (with-current-buffer b1 (setq buffer-file-name name1)))))
10426 (setq diffpt (verilog-diff-buffers-p b1 b2 t))
10427 (cond ((not diffpt)
10428 (unless noninteractive (message "AUTO expansion identical"))
10429 (kill-buffer newname)) ;; Nice to cleanup after oneself
10431 (funcall verilog-diff-function b1 b2 diffpt)))
10432 ;; Return result of compare
10440 (defun verilog-auto-save-check ()
10441 "On saving see if we need auto update."
10442 (cond ((not verilog-auto-save-policy)) ; disabled
10443 ((not (save-excursion
10445 (let ((case-fold-search nil))
10446 (goto-char (point-min))
10447 (re-search-forward "AUTO" nil t))))))
10448 ((eq verilog-auto-save-policy 'force)
10450 ((not (buffer-modified-p)))
10451 ((eq verilog-auto-update-tick (buffer-chars-modified-tick))) ; up-to-date
10452 ((eq verilog-auto-save-policy 'detect)
10455 (when (yes-or-no-p "AUTO statements not recomputed, do it now? ")
10457 ;; Don't ask again if didn't update
10458 (set (make-local-variable 'verilog-auto-update-tick) (buffer-chars-modified-tick))))
10459 (when (not verilog-auto-star-save)
10460 (verilog-delete-auto-star-implicit))
10461 nil) ;; Always return nil -- we don't write the file ourselves
10463 (defun verilog-auto-read-locals ()
10464 "Return file local variable segment at bottom of file."
10466 (goto-char (point-max))
10467 (if (re-search-backward "Local Variables:" nil t)
10468 (buffer-substring-no-properties (point) (point-max))
10471 (defun verilog-auto-reeval-locals (&optional force)
10472 "Read file local variable segment at bottom of file if it has changed.
10473 If FORCE, always reread it."
10474 (let ((curlocal (verilog-auto-read-locals)))
10475 (when (or force (not (equal verilog-auto-last-file-locals curlocal)))
10476 (set (make-local-variable 'verilog-auto-last-file-locals) curlocal)
10477 ;; Note this may cause this function to be recursively invoked,
10478 ;; because hack-local-variables may call (verilog-mode)
10479 ;; The above when statement will prevent it from recursing forever.
10480 (hack-local-variables)
10487 (defun verilog-auto-arg-ports (sigs message indent-pt)
10488 "Print a list of ports for an AUTOINST.
10489 Takes SIGS list, adds MESSAGE to front and inserts each at INDENT-PT."
10491 (when verilog-auto-arg-sort
10492 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
10494 (indent-to indent-pt)
10498 (indent-to indent-pt)
10500 (cond ((> (+ 2 (current-column) (length (verilog-sig-name (car sigs)))) fill-column)
10502 (indent-to indent-pt))
10503 (t (insert space)))
10504 (insert (verilog-sig-name (car sigs)) ",")
10505 (setq sigs (cdr sigs)
10508 (defun verilog-auto-arg ()
10509 "Expand AUTOARG statements.
10510 Replace the argument declarations at the beginning of the
10511 module with ones automatically derived from input and output
10512 statements. This can be dangerous if the module is instantiated
10513 using position-based connections, so use only name-based when
10514 instantiating the resulting module. Long lines are split based
10515 on the `fill-column', see \\[set-fill-column].
10518 Concatenation and outputting partial buses is not supported.
10520 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
10524 module ExampArg (/*AUTOARG*/);
10529 Typing \\[verilog-auto] will make this into:
10531 module ExampArg (/*AUTOARG*/
10541 The argument declarations may be printed in declaration order to best suit
10542 order based instantiations, or alphabetically, based on the
10543 `verilog-auto-arg-sort' variable.
10545 Any ports declared between the ( and /*AUTOARG*/ are presumed to be
10546 predeclared and are not redeclared by AUTOARG. AUTOARG will make a
10547 conservative guess on adding a comma for the first signal, if you have
10548 any ifdefs or complicated expressions before the AUTOARG you will need
10549 to choose the comma yourself.
10551 Avoid declaring ports manually, as it makes code harder to maintain."
10553 (let* ((modi (verilog-modi-current))
10554 (moddecls (verilog-modi-get-decls modi))
10555 (skip-pins (aref (verilog-read-arg-pins) 0)))
10556 (verilog-repair-open-comma)
10557 (verilog-auto-arg-ports (verilog-signals-not-in
10558 (verilog-decls-get-outputs moddecls)
10561 verilog-indent-level-declaration)
10562 (verilog-auto-arg-ports (verilog-signals-not-in
10563 (verilog-decls-get-inouts moddecls)
10566 verilog-indent-level-declaration)
10567 (verilog-auto-arg-ports (verilog-signals-not-in
10568 (verilog-decls-get-inputs moddecls)
10571 verilog-indent-level-declaration)
10572 (verilog-repair-close-comma)
10573 (unless (eq (char-before) ?/ )
10575 (indent-to verilog-indent-level-declaration))))
10577 (defun verilog-auto-assign-modport ()
10578 "Expand AUTOASSIGNMODPORT statements, as part of \\[verilog-auto].
10579 Take input/output/inout statements from the specified interface
10580 and modport and use to build assignments into the modport, for
10581 making verification modules that connect to UVM interfaces.
10583 The first parameter is the name of an interface.
10585 The second parameter is a regexp of modports to read from in
10588 The third parameter is the instance name to use to dot reference into.
10590 The optional fourth parameter is a regular expression, and only
10591 signals matching the regular expression will be included.
10595 Interface names must be resolvable to filenames. See `verilog-auto-inst'.
10597 Inouts are not supported, as assignments must be unidirectional.
10599 If a signal is part of the interface header and in both a
10600 modport and the interface itself, it will not be listed. (As
10601 this would result in a syntax error when the connections are
10604 See the example in `verilog-auto-inout-modport'."
10606 (let* ((params (verilog-read-auto-params 3 4))
10607 (submod (nth 0 params))
10608 (modport-re (nth 1 params))
10609 (inst-name (nth 2 params))
10610 (regexp (nth 3 params))
10611 direction-re submodi) ;; direction argument not supported until requested
10612 ;; Lookup position, etc of co-module
10613 ;; Note this may raise an error
10614 (when (setq submodi (verilog-modi-lookup submod t))
10615 (let* ((indent-pt (current-indentation))
10616 (modi (verilog-modi-current))
10617 (submoddecls (verilog-modi-get-decls submodi))
10618 (submodportdecls (verilog-modi-modport-lookup submodi modport-re))
10619 (sig-list-i (verilog-signals-in ;; Decls doesn't have data types, must resolve
10620 (verilog-decls-get-vars submoddecls)
10621 (verilog-signals-not-in
10622 (verilog-decls-get-inputs submodportdecls)
10623 (verilog-decls-get-ports submoddecls))))
10624 (sig-list-o (verilog-signals-in ;; Decls doesn't have data types, must resolve
10625 (verilog-decls-get-vars submoddecls)
10626 (verilog-signals-not-in
10627 (verilog-decls-get-outputs submodportdecls)
10628 (verilog-decls-get-ports submoddecls)))))
10630 (setq sig-list-i (verilog-signals-edit-wire-reg
10631 (verilog-signals-matching-dir-re
10632 (verilog-signals-matching-regexp sig-list-i regexp)
10633 "input" direction-re))
10634 sig-list-o (verilog-signals-edit-wire-reg
10635 (verilog-signals-matching-dir-re
10636 (verilog-signals-matching-regexp sig-list-o regexp)
10637 "output" direction-re)))
10638 (setq sig-list-i (sort (copy-alist sig-list-i) `verilog-signals-sort-compare))
10639 (setq sig-list-o (sort (copy-alist sig-list-o) `verilog-signals-sort-compare))
10640 (when (or sig-list-i sig-list-o)
10641 (verilog-insert-indent "// Beginning of automatic assignments from modport\n")
10642 ;; Don't sort them so an upper AUTOINST will match the main module
10643 (let ((sigs sig-list-o))
10645 (verilog-insert-indent "assign " (verilog-sig-name (car sigs))
10647 "." (verilog-sig-name (car sigs)) ";\n")
10648 (setq sigs (cdr sigs))))
10649 (let ((sigs sig-list-i))
10651 (verilog-insert-indent "assign " inst-name
10652 "." (verilog-sig-name (car sigs))
10653 " = " (verilog-sig-name (car sigs)) ";\n")
10654 (setq sigs (cdr sigs))))
10655 (verilog-insert-indent "// End of automatics\n")))))))
10657 (defun verilog-auto-inst-port-map (port-st)
10660 (defvar vl-cell-type nil "See `verilog-auto-inst'.") ; Prevent compile warning
10661 (defvar vl-cell-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
10662 (defvar vl-modport nil "See `verilog-auto-inst'.") ; Prevent compile warning
10663 (defvar vl-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
10664 (defvar vl-width nil "See `verilog-auto-inst'.") ; Prevent compile warning
10665 (defvar vl-dir nil "See `verilog-auto-inst'.") ; Prevent compile warning
10666 (defvar vl-bits nil "See `verilog-auto-inst'.") ; Prevent compile warning
10667 (defvar vl-mbits nil "See `verilog-auto-inst'.") ; Prevent compile warning
10669 (defun verilog-auto-inst-port (port-st indent-pt tpl-list tpl-num for-star par-values)
10670 "Print out an instantiation connection for this PORT-ST.
10671 Insert to INDENT-PT, use template TPL-LIST.
10672 @ are instantiation numbers, replaced with TPL-NUM.
10673 @\"(expression @)\" are evaluated, with @ as a variable.
10674 If FOR-STAR add comment it is a .* expansion.
10675 If PAR-VALUES replace final strings with these parameter values."
10676 (let* ((port (verilog-sig-name port-st))
10677 (tpl-ass (or (assoc port (car tpl-list))
10678 (verilog-auto-inst-port-map port-st)))
10679 ;; vl-* are documented for user use
10680 (vl-name (verilog-sig-name port-st))
10681 (vl-width (verilog-sig-width port-st))
10682 (vl-modport (verilog-sig-modport port-st))
10683 (vl-mbits (if (verilog-sig-multidim port-st)
10684 (verilog-sig-multidim-string port-st) ""))
10685 (vl-bits (if (or verilog-auto-inst-vector
10686 (not (assoc port vector-skip-list))
10687 (not (equal (verilog-sig-bits port-st)
10688 (verilog-sig-bits (assoc port vector-skip-list)))))
10689 (or (verilog-sig-bits port-st) "")
10691 (case-fold-search nil)
10692 (check-values par-values)
10694 ;; Replace parameters in bit-width
10695 (when (and check-values
10696 (not (equal vl-bits "")))
10697 (while check-values
10698 (setq vl-bits (verilog-string-replace-matches
10699 (concat "\\<" (nth 0 (car check-values)) "\\>")
10700 (concat "(" (nth 1 (car check-values)) ")")
10702 vl-mbits (verilog-string-replace-matches
10703 (concat "\\<" (nth 0 (car check-values)) "\\>")
10704 (concat "(" (nth 1 (car check-values)) ")")
10706 check-values (cdr check-values)))
10707 (setq vl-bits (verilog-simplify-range-expression vl-bits)
10708 vl-mbits (verilog-simplify-range-expression vl-mbits)
10709 vl-width (verilog-make-width-expression vl-bits))) ; Not in the loop for speed
10710 ;; Default net value if not found
10711 (setq tpl-net (concat port
10712 (if vl-modport (concat "." vl-modport) "")
10713 (if (verilog-sig-multidim port-st)
10714 (concat "/*" vl-mbits vl-bits "*/")
10715 (concat vl-bits))))
10717 (cond (tpl-ass ; Template of exact port name
10718 (setq tpl-net (nth 1 tpl-ass)))
10719 ((nth 1 tpl-list) ; Wildcards in template, search them
10720 (let ((wildcards (nth 1 tpl-list)))
10722 (when (string-match (nth 0 (car wildcards)) port)
10723 (setq tpl-ass (car wildcards) ; so allow @ parsing
10724 tpl-net (replace-match (nth 1 (car wildcards))
10726 (setq wildcards (cdr wildcards))))))
10727 ;; Parse Templated variable
10729 ;; Evaluate @"(lispcode)"
10730 (when (string-match "@\".*[^\\]\"" tpl-net)
10731 (while (string-match "@\"\\(\\([^\\\"]*\\(\\\\.\\)*\\)*\\)\"" tpl-net)
10734 (substring tpl-net 0 (match-beginning 0))
10736 (let* ((expr (match-string 1 tpl-net))
10739 (setq expr (verilog-string-replace-matches "\\\\\"" "\"" nil nil expr))
10740 (setq expr (verilog-string-replace-matches "@" tpl-num nil nil expr))
10741 (prin1 (eval (car (read-from-string expr)))
10742 (lambda (ch) ())))))
10743 (if (numberp value) (setq value (number-to-string value)))
10745 (substring tpl-net (match-end 0))))))
10746 ;; Replace @ and [] magic variables in final output
10747 (setq tpl-net (verilog-string-replace-matches "@" tpl-num nil nil tpl-net))
10748 (setq tpl-net (verilog-string-replace-matches "\\[\\]" vl-bits nil nil tpl-net)))
10750 (indent-to indent-pt)
10752 (unless (and verilog-auto-inst-dot-name
10753 (equal port tpl-net))
10754 (indent-to verilog-auto-inst-column)
10755 (insert "(" tpl-net ")"))
10758 (verilog-read-auto-template-hit tpl-ass)
10759 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
10760 verilog-auto-inst-column))
10761 ;; verilog-insert requires the complete comment in one call - including the newline
10762 (cond ((equal verilog-auto-inst-template-numbers `lhs)
10763 (verilog-insert " // Templated"
10764 " LHS: " (nth 0 tpl-ass)
10766 (verilog-auto-inst-template-numbers
10767 (verilog-insert " // Templated"
10768 " T" (int-to-string (nth 2 tpl-ass))
10769 " L" (int-to-string (nth 3 tpl-ass))
10772 (verilog-insert " // Templated\n"))))
10774 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
10775 verilog-auto-inst-column))
10776 (verilog-insert " // Implicit .\*\n")) ;For some reason the . or * must be escaped...
10779 ;;(verilog-auto-inst-port (list "foo" "[5:0]") 10 (list (list "foo" "a@\"(% (+ @ 1) 4)\"a")) "3")
10780 ;;(x "incom[@\"(+ (* 8 @) 7)\":@\"(* 8 @)\"]")
10781 ;;(x ".out (outgo[@\"(concat (+ (* 8 @) 7) \\\":\\\" ( * 8 @))\"]));")
10783 (defun verilog-auto-inst-port-list (sig-list indent-pt tpl-list tpl-num for-star par-values)
10784 "For `verilog-auto-inst' print a list of ports using `verilog-auto-inst-port'."
10785 (when verilog-auto-inst-sort
10786 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare)))
10787 (mapc (lambda (port)
10788 (verilog-auto-inst-port port indent-pt
10789 tpl-list tpl-num for-star par-values))
10792 (defun verilog-auto-inst-first ()
10793 "Insert , etc before first ever port in this instant, as part of \\[verilog-auto-inst]."
10794 ;; Do we need a trailing comma?
10795 ;; There maybe an ifdef or something similar before us. What a mess. Thus
10796 ;; to avoid trouble we only insert on preceding ) or *.
10797 ;; Insert first port on new line
10798 (insert "\n") ;; Must insert before search, so point will move forward if insert comma
10800 (verilog-re-search-backward-quick "[^ \t\n\f]" nil nil)
10801 (when (looking-at ")\\|\\*") ;; Generally don't insert, unless we are fairly sure
10805 (defun verilog-auto-star ()
10806 "Expand SystemVerilog .* pins, as part of \\[verilog-auto].
10808 If `verilog-auto-star-expand' is set, .* pins are treated if they were
10809 AUTOINST statements, otherwise they are ignored. For safety, Verilog mode
10810 will also ignore any .* that are not last in your pin list (this prevents
10811 it from deleting pins following the .* when it expands the AUTOINST.)
10813 On writing your file, unless `verilog-auto-star-save' is set, any
10814 non-templated expanded pins will be removed. You may do this at any time
10815 with \\[verilog-delete-auto-star-implicit].
10817 If you are converting a module to use .* for the first time, you may wish
10818 to use \\[verilog-inject-auto] and then replace the created AUTOINST with .*.
10820 See `verilog-auto-inst' for examples, templates, and more information."
10821 (when (verilog-auto-star-safe)
10822 (verilog-auto-inst)))
10824 (defun verilog-auto-inst ()
10825 "Expand AUTOINST statements, as part of \\[verilog-auto].
10826 Replace the pin connections to an instantiation or interface
10827 declaration with ones automatically derived from the module or
10828 interface header of the instantiated item.
10830 If `verilog-auto-star-expand' is set, also expand SystemVerilog .* ports,
10831 and delete them before saving unless `verilog-auto-star-save' is set.
10832 See `verilog-auto-star' for more information.
10834 The pins are printed in declaration order or alphabetically,
10835 based on the `verilog-auto-inst-sort' variable.
10838 Module names must be resolvable to filenames by adding a
10839 `verilog-library-extensions', and being found in the same directory, or
10840 by changing the variable `verilog-library-flags' or
10841 `verilog-library-directories'. Macros `modname are translated through the
10842 vh-{name} Emacs variable, if that is not found, it just ignores the `.
10844 In templates you must have one signal per line, ending in a ), or ));,
10845 and have proper () nesting, including a final ); to end the template.
10847 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
10849 SystemVerilog multidimensional input/output has only experimental support.
10851 SystemVerilog .name syntax is used if `verilog-auto-inst-dot-name' is set.
10853 Parameters referenced by the instantiation will remain symbolic, unless
10854 `verilog-auto-inst-param-value' is set.
10856 Gate primitives (and/or) may have AUTOINST for the purpose of
10857 AUTOWIRE declarations, etc. Gates are the only case when
10858 position based connections are passed.
10860 For example, first take the submodule InstModule.v:
10862 module InstModule (o,i);
10865 wire [31:0] o = {32{i}};
10868 This is then used in an upper level module:
10870 module ExampInst (o,i);
10873 InstModule instName
10877 Typing \\[verilog-auto] will make this into:
10879 module ExampInst (o,i);
10882 InstModule instName
10890 Where the list of inputs and outputs came from the inst module.
10894 Unless you are instantiating a module multiple times, or the module is
10895 something trivial like an adder, DO NOT CHANGE SIGNAL NAMES ACROSS HIERARCHY.
10896 It just makes for unmaintainable code. To sanitize signal names, try
10897 vrename from URL `http://www.veripool.org'.
10899 When you need to violate this suggestion there are two ways to list
10900 exceptions, placing them before the AUTOINST, or using templates.
10902 Any ports defined before the /*AUTOINST*/ are not included in the list of
10903 automatics. This is similar to making a template as described below, but
10904 is restricted to simple connections just like you normally make. Also note
10905 that any signals before the AUTOINST will only be picked up by AUTOWIRE if
10906 you have the appropriate // Input or // Output comment, and exactly the
10907 same line formatting as AUTOINST itself uses.
10909 InstModule instName
10911 .i (my_i_dont_mess_with_it),
10919 For multiple instantiations based upon a single template, create a
10920 commented out template:
10922 /* InstModule AUTO_TEMPLATE (
10927 Templates go ABOVE the instantiation(s). When an instantiation is
10928 expanded `verilog-mode' simply searches up for the closest template.
10929 Thus you can have multiple templates for the same module, just alternate
10930 between the template for an instantiation and the instantiation itself.
10931 (For backward compatibility if no template is found above, it
10932 will also look below, but do not use this behavior in new designs.)
10934 The module name must be the same as the name of the module in the
10935 instantiation name, and the code \"AUTO_TEMPLATE\" must be in these exact
10936 words and capitalized. Only signals that must be different for each
10937 instantiation need to be listed.
10939 Inside a template, a [] in a connection name (with nothing else inside
10940 the brackets) will be replaced by the same bus subscript as it is being
10941 connected to, or the [] will be removed if it is a single bit signal.
10942 Generally it is a good idea to do this for all connections in a template,
10943 as then they will work for any width signal, and with AUTOWIRE. See
10944 PTL_BUS becoming PTL_BUSNEW below.
10946 If you have a complicated template, set `verilog-auto-inst-template-numbers'
10947 to see which regexps are matching. Don't leave that mode set after
10948 debugging is completed though, it will result in lots of extra differences
10949 and merge conflicts.
10951 Setting `verilog-auto-template-warn-unused' will report errors
10952 if any template lines are unused.
10956 /* InstModule AUTO_TEMPLATE (
10957 .ptl_bus (ptl_busnew[]),
10960 InstModule ms2m (/*AUTOINST*/);
10962 Typing \\[verilog-auto] will make this into:
10964 InstModule ms2m (/*AUTOINST*/
10966 .NotInTemplate (NotInTemplate),
10967 .ptl_bus (ptl_busnew[3:0]), // Templated
10971 Multiple Module Templates:
10973 The same template lines can be applied to multiple modules with
10974 the syntax as follows:
10976 /* InstModuleA AUTO_TEMPLATE
10977 InstModuleB AUTO_TEMPLATE
10978 InstModuleC AUTO_TEMPLATE
10979 InstModuleD AUTO_TEMPLATE (
10980 .ptl_bus (ptl_busnew[]),
10984 Note there is only one AUTO_TEMPLATE opening parenthesis.
10988 It is common to instantiate a cell multiple times, so templates make it
10989 trivial to substitute part of the cell name into the connection name.
10991 /* InstName AUTO_TEMPLATE <optional \"REGEXP\"> (
10993 .sig2 (sigy[@\"(% (+ 1 @) 4)\"]),
10997 If no regular expression is provided immediately after the AUTO_TEMPLATE
10998 keyword, then the @ character in any connection names will be replaced
10999 with the instantiation number; the first digits found in the cell's
11000 instantiation name.
11002 If a regular expression is provided, the @ character will be replaced
11003 with the first \(\) grouping that matches against the cell name. Using a
11004 regexp of \"\\([0-9]+\\)\" provides identical values for @ as when no
11005 regexp is provided. If you use multiple layers of parenthesis,
11006 \"test\\([^0-9]+\\)_\\([0-9]+\\)\" would replace @ with non-number
11007 characters after test and before _, whereas
11008 \"\\(test\\([a-z]+\\)_\\([0-9]+\\)\\)\" would replace @ with the entire
11013 /* InstModule AUTO_TEMPLATE (
11014 .ptl_mapvalidx (ptl_mapvalid[@]),
11015 .ptl_mapvalidp1x (ptl_mapvalid[@\"(% (+ 1 @) 4)\"]),
11018 InstModule ms2m (/*AUTOINST*/);
11020 Typing \\[verilog-auto] will make this into:
11022 InstModule ms2m (/*AUTOINST*/
11024 .ptl_mapvalidx (ptl_mapvalid[2]),
11025 .ptl_mapvalidp1x (ptl_mapvalid[3]));
11027 Note the @ character was replaced with the 2 from \"ms2m\".
11029 Alternatively, using a regular expression for @:
11031 /* InstModule AUTO_TEMPLATE \"_\\([a-z]+\\)\" (
11032 .ptl_mapvalidx (@_ptl_mapvalid),
11033 .ptl_mapvalidp1x (ptl_mapvalid_@),
11036 InstModule ms2_FOO (/*AUTOINST*/);
11037 InstModule ms2_BAR (/*AUTOINST*/);
11039 Typing \\[verilog-auto] will make this into:
11041 InstModule ms2_FOO (/*AUTOINST*/
11043 .ptl_mapvalidx (FOO_ptl_mapvalid),
11044 .ptl_mapvalidp1x (ptl_mapvalid_FOO));
11045 InstModule ms2_BAR (/*AUTOINST*/
11047 .ptl_mapvalidx (BAR_ptl_mapvalid),
11048 .ptl_mapvalidp1x (ptl_mapvalid_BAR));
11053 A template entry of the form
11055 .pci_req\\([0-9]+\\)_l (pci_req_jtag_[\\1]),
11057 will apply an Emacs style regular expression search for any port beginning
11058 in pci_req followed by numbers and ending in _l and connecting that to
11059 the pci_req_jtag_[] net, with the bus subscript coming from what matches
11060 inside the first set of \\( \\). Thus pci_req2_l becomes pci_req_jtag_[2].
11062 Since \\([0-9]+\\) is so common and ugly to read, a @ in the port name
11063 does the same thing. (Note a @ in the connection/replacement text is
11064 completely different -- still use \\1 there!) Thus this is the same as
11065 the above template:
11067 .pci_req@_l (pci_req_jtag_[\\1]),
11069 Here's another example to remove the _l, useful when naming conventions
11070 specify _ alone to mean active low. Note the use of [] to keep the bus
11073 .\\(.*\\)_l (\\1_[]),
11077 First any regular expression template is expanded.
11079 If the syntax @\"( ... )\" is found in a connection, the expression in
11080 quotes will be evaluated as a Lisp expression, with @ replaced by the
11081 instantiation number. The MAPVALIDP1X example above would put @+1 modulo
11082 4 into the brackets. Quote all double-quotes inside the expression with
11083 a leading backslash (\\\"...\\\"); or if the Lisp template is also a
11084 regexp template backslash the backslash quote (\\\\\"...\\\\\").
11086 There are special variables defined that are useful in these
11089 vl-name Name portion of the input/output port.
11090 vl-bits Bus bits portion of the input/output port ('[2:0]').
11091 vl-mbits Multidimensional array bits for port ('[2:0][3:0]').
11092 vl-width Width of the input/output port ('3' for [2:0]).
11093 May be a (...) expression if bits isn't a constant.
11094 vl-dir Direction of the pin input/output/inout/interface.
11095 vl-modport The modport, if an interface with a modport.
11096 vl-cell-type Module name/type of the cell ('InstModule').
11097 vl-cell-name Instance name of the cell ('instName').
11099 Normal Lisp variables may be used in expressions. See
11100 `verilog-read-defines' which can set vh-{definename} variables for use
11101 here. Also, any comments of the form:
11103 /*AUTO_LISP(setq foo 1)*/
11105 will evaluate any Lisp expression inside the parenthesis between the
11106 beginning of the buffer and the point of the AUTOINST. This allows
11107 functions to be defined or variables to be changed between instantiations.
11108 (See also `verilog-auto-insert-lisp' if you want the output from your
11109 lisp function to be inserted.)
11111 Note that when using lisp expressions errors may occur when @ is not a
11112 number; you may need to use the standard Emacs Lisp functions
11113 `number-to-string' and `string-to-number'.
11115 After the evaluation is completed, @ substitution and [] substitution
11118 For more information see the \\[verilog-faq] and forums at URL
11119 `http://www.veripool.org'."
11122 (let* ((pt (point))
11123 (for-star (save-excursion (backward-char 2) (looking-at "\\.\\*")))
11124 (indent-pt (save-excursion (verilog-backward-open-paren)
11125 (1+ (current-column))))
11126 (verilog-auto-inst-column (max verilog-auto-inst-column
11127 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
11128 (modi (verilog-modi-current))
11129 (moddecls (verilog-modi-get-decls modi))
11130 (vector-skip-list (unless verilog-auto-inst-vector
11131 (verilog-decls-get-signals moddecls)))
11132 submod submodi submoddecls
11133 inst skip-pins tpl-list tpl-num did-first par-values)
11135 ;; Find module name that is instantiated
11136 (setq submod (verilog-read-inst-module)
11137 inst (verilog-read-inst-name)
11138 vl-cell-type submod
11140 skip-pins (aref (verilog-read-inst-pins) 0))
11142 ;; Parse any AUTO_LISP() before here
11143 (verilog-read-auto-lisp (point-min) pt)
11145 ;; Read parameters (after AUTO_LISP)
11146 (setq par-values (and verilog-auto-inst-param-value
11147 (verilog-read-inst-param-value)))
11149 ;; Lookup position, etc of submodule
11150 ;; Note this may raise an error
11151 (when (and (not (member submod verilog-gate-keywords))
11152 (setq submodi (verilog-modi-lookup submod t)))
11153 (setq submoddecls (verilog-modi-get-decls submodi))
11154 ;; If there's a number in the instantiation, it may be an argument to the
11155 ;; automatic variable instantiation program.
11156 (let* ((tpl-info (verilog-read-auto-template submod))
11157 (tpl-regexp (aref tpl-info 0)))
11158 (setq tpl-num (if (string-match tpl-regexp inst)
11159 (match-string 1 inst)
11161 tpl-list (aref tpl-info 1)))
11162 ;; Find submodule's signals and dump
11163 (let ((sig-list (and (equal (verilog-modi-get-type submodi) "interface")
11164 (verilog-signals-not-in
11165 (verilog-decls-get-vars submoddecls)
11167 (vl-dir "interfaced"))
11168 (when (and sig-list
11169 verilog-auto-inst-interfaced-ports)
11170 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11171 ;; Note these are searched for in verilog-read-sub-decls.
11172 (verilog-insert-indent "// Interfaced\n")
11173 (verilog-auto-inst-port-list sig-list indent-pt
11174 tpl-list tpl-num for-star par-values)))
11175 (let ((sig-list (verilog-signals-not-in
11176 (verilog-decls-get-interfaces submoddecls)
11178 (vl-dir "interface"))
11180 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11181 ;; Note these are searched for in verilog-read-sub-decls.
11182 (verilog-insert-indent "// Interfaces\n")
11183 (verilog-auto-inst-port-list sig-list indent-pt
11184 tpl-list tpl-num for-star par-values)))
11185 (let ((sig-list (verilog-signals-not-in
11186 (verilog-decls-get-outputs submoddecls)
11190 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11191 (verilog-insert-indent "// Outputs\n")
11192 (verilog-auto-inst-port-list sig-list indent-pt
11193 tpl-list tpl-num for-star par-values)))
11194 (let ((sig-list (verilog-signals-not-in
11195 (verilog-decls-get-inouts submoddecls)
11199 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11200 (verilog-insert-indent "// Inouts\n")
11201 (verilog-auto-inst-port-list sig-list indent-pt
11202 tpl-list tpl-num for-star par-values)))
11203 (let ((sig-list (verilog-signals-not-in
11204 (verilog-decls-get-inputs submoddecls)
11208 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11209 (verilog-insert-indent "// Inputs\n")
11210 (verilog-auto-inst-port-list sig-list indent-pt
11211 tpl-list tpl-num for-star par-values)))
11215 (re-search-backward "," pt t)
11218 (search-forward "\n") ;; Added by inst-port
11220 (if (search-forward ")" nil t) ;; From user, moved up a line
11222 (if (search-forward ";" nil t) ;; Don't error if user had syntax error and forgot it
11223 (delete-char -1)))))))))
11225 (defun verilog-auto-inst-param ()
11226 "Expand AUTOINSTPARAM statements, as part of \\[verilog-auto].
11227 Replace the parameter connections to an instantiation with ones
11228 automatically derived from the module header of the instantiated netlist.
11230 See \\[verilog-auto-inst] for limitations, and templates to customize the
11233 For example, first take the submodule InstModule.v:
11235 module InstModule (o,i);
11239 This is then used in an upper level module:
11241 module ExampInst (o,i);
11243 InstModule #(/*AUTOINSTPARAM*/)
11244 instName (/*AUTOINST*/);
11247 Typing \\[verilog-auto] will make this into:
11249 module ExampInst (o,i);
11252 InstModule #(/*AUTOINSTPARAM*/
11255 instName (/*AUTOINST*/);
11258 Where the list of parameter connections come from the inst module.
11262 You can customize the parameter connections using AUTO_TEMPLATEs,
11263 just as you would with \\[verilog-auto-inst]."
11266 (let* ((pt (point))
11267 (indent-pt (save-excursion (verilog-backward-open-paren)
11268 (1+ (current-column))))
11269 (verilog-auto-inst-column (max verilog-auto-inst-column
11270 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
11271 (modi (verilog-modi-current))
11272 (moddecls (verilog-modi-get-decls modi))
11273 (vector-skip-list (unless verilog-auto-inst-vector
11274 (verilog-decls-get-signals moddecls)))
11275 submod submodi submoddecls
11276 inst skip-pins tpl-list tpl-num did-first)
11277 ;; Find module name that is instantiated
11278 (setq submod (save-excursion
11279 ;; Get to the point where AUTOINST normally is to read the module
11280 (verilog-re-search-forward-quick "[(;]" nil nil)
11281 (verilog-read-inst-module))
11282 inst (save-excursion
11283 ;; Get to the point where AUTOINST normally is to read the module
11284 (verilog-re-search-forward-quick "[(;]" nil nil)
11285 (verilog-read-inst-name))
11286 vl-cell-type submod
11288 skip-pins (aref (verilog-read-inst-pins) 0))
11290 ;; Parse any AUTO_LISP() before here
11291 (verilog-read-auto-lisp (point-min) pt)
11293 ;; Lookup position, etc of submodule
11294 ;; Note this may raise an error
11295 (when (setq submodi (verilog-modi-lookup submod t))
11296 (setq submoddecls (verilog-modi-get-decls submodi))
11297 ;; If there's a number in the instantiation, it may be an argument to the
11298 ;; automatic variable instantiation program.
11299 (let* ((tpl-info (verilog-read-auto-template submod))
11300 (tpl-regexp (aref tpl-info 0)))
11301 (setq tpl-num (if (string-match tpl-regexp inst)
11302 (match-string 1 inst)
11304 tpl-list (aref tpl-info 1)))
11305 ;; Find submodule's signals and dump
11306 (let ((sig-list (verilog-signals-not-in
11307 (verilog-decls-get-gparams submoddecls)
11309 (vl-dir "parameter"))
11311 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11312 ;; Note these are searched for in verilog-read-sub-decls.
11313 (verilog-insert-indent "// Parameters\n")
11314 (verilog-auto-inst-port-list sig-list indent-pt
11315 tpl-list tpl-num nil nil)))
11319 (re-search-backward "," pt t)
11322 (search-forward "\n") ;; Added by inst-port
11324 (if (search-forward ")" nil t) ;; From user, moved up a line
11325 (delete-char -1)))))))))
11327 (defun verilog-auto-reg ()
11328 "Expand AUTOREG statements, as part of \\[verilog-auto].
11329 Make reg statements for any output that isn't already declared,
11330 and isn't a wire output from a block. `verilog-auto-wire-type'
11331 may be used to change the datatype of the declarations.
11334 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
11336 This does NOT work on memories, declare those yourself.
11340 module ExampReg (o,i);
11347 Typing \\[verilog-auto] will make this into:
11349 module ExampReg (o,i);
11353 // Beginning of automatic regs (for this module's undeclared outputs)
11355 // End of automatics
11359 ;; Point must be at insertion point.
11360 (let* ((indent-pt (current-indentation))
11361 (modi (verilog-modi-current))
11362 (moddecls (verilog-modi-get-decls modi))
11363 (modsubdecls (verilog-modi-get-sub-decls modi))
11364 (sig-list (verilog-signals-not-in
11365 (verilog-decls-get-outputs moddecls)
11366 (append (verilog-signals-with ;; ignore typed signals
11368 (verilog-decls-get-outputs moddecls))
11369 (verilog-decls-get-vars moddecls)
11370 (verilog-decls-get-assigns moddecls)
11371 (verilog-decls-get-consts moddecls)
11372 (verilog-decls-get-gparams moddecls)
11373 (verilog-subdecls-get-interfaced modsubdecls)
11374 (verilog-subdecls-get-outputs modsubdecls)
11375 (verilog-subdecls-get-inouts modsubdecls)))))
11377 (verilog-forward-or-insert-line)
11378 (verilog-insert-indent "// Beginning of automatic regs (for this module's undeclared outputs)\n")
11379 (verilog-insert-definition modi sig-list "reg" indent-pt nil)
11380 (verilog-insert-indent "// End of automatics\n")))))
11382 (defun verilog-auto-reg-input ()
11383 "Expand AUTOREGINPUT statements, as part of \\[verilog-auto].
11384 Make reg statements instantiation inputs that aren't already declared.
11385 This is useful for making a top level shell for testing the module that is
11386 to be instantiated.
11389 This ONLY detects inputs of AUTOINSTants (see `verilog-read-sub-decls').
11391 This does NOT work on memories, declare those yourself.
11393 An example (see `verilog-auto-inst' for what else is going on here):
11395 module ExampRegInput (o,i);
11399 InstModule instName
11403 Typing \\[verilog-auto] will make this into:
11405 module ExampRegInput (o,i);
11409 // Beginning of automatic reg inputs (for undeclared ...
11410 reg [31:0] iv; // From inst of inst.v
11411 // End of automatics
11412 InstModule instName
11420 ;; Point must be at insertion point.
11421 (let* ((indent-pt (current-indentation))
11422 (modi (verilog-modi-current))
11423 (moddecls (verilog-modi-get-decls modi))
11424 (modsubdecls (verilog-modi-get-sub-decls modi))
11425 (sig-list (verilog-signals-combine-bus
11426 (verilog-signals-not-in
11427 (append (verilog-subdecls-get-inputs modsubdecls)
11428 (verilog-subdecls-get-inouts modsubdecls))
11429 (append (verilog-decls-get-signals moddecls)
11430 (verilog-decls-get-assigns moddecls))))))
11432 (verilog-forward-or-insert-line)
11433 (verilog-insert-indent "// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)\n")
11434 (verilog-insert-definition modi sig-list "reg" indent-pt nil)
11435 (verilog-insert-indent "// End of automatics\n")))))
11437 (defun verilog-auto-logic-setup ()
11438 "Prepare variables due to AUTOLOGIC."
11439 (unless verilog-auto-wire-type
11440 (set (make-local-variable 'verilog-auto-wire-type)
11443 (defun verilog-auto-logic ()
11444 "Expand AUTOLOGIC statements, as part of \\[verilog-auto].
11445 Make wire statements using the SystemVerilog logic keyword.
11446 This is currently equivalent to:
11450 with the below at the bottom of the file
11452 // Local Variables:
11453 // verilog-auto-logic-type:\"logic\"
11456 In the future AUTOLOGIC may declare additional identifiers,
11457 while AUTOWIRE will not."
11459 (verilog-auto-logic-setup)
11460 (verilog-auto-wire)))
11462 (defun verilog-auto-wire ()
11463 "Expand AUTOWIRE statements, as part of \\[verilog-auto].
11464 Make wire statements for instantiations outputs that aren't
11465 already declared. `verilog-auto-wire-type' may be used to change
11466 the datatype of the declarations.
11469 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'),
11470 and all buses must have widths, such as those from AUTOINST, or using []
11473 This does NOT work on memories or SystemVerilog .name connections,
11474 declare those yourself.
11476 Verilog mode will add \"Couldn't Merge\" comments to signals it cannot
11477 determine how to bus together. This occurs when you have ports with
11478 non-numeric or non-sequential bus subscripts. If Verilog mode
11479 mis-guessed, you'll have to declare them yourself.
11481 An example (see `verilog-auto-inst' for what else is going on here):
11483 module ExampWire (o,i);
11487 InstModule instName
11491 Typing \\[verilog-auto] will make this into:
11493 module ExampWire (o,i);
11497 // Beginning of automatic wires
11498 wire [31:0] ov; // From inst of inst.v
11499 // End of automatics
11500 InstModule instName
11509 ;; Point must be at insertion point.
11510 (let* ((indent-pt (current-indentation))
11511 (modi (verilog-modi-current))
11512 (moddecls (verilog-modi-get-decls modi))
11513 (modsubdecls (verilog-modi-get-sub-decls modi))
11514 (sig-list (verilog-signals-combine-bus
11515 (verilog-signals-not-in
11516 (append (verilog-subdecls-get-outputs modsubdecls)
11517 (verilog-subdecls-get-inouts modsubdecls))
11518 (verilog-decls-get-signals moddecls)))))
11520 (verilog-forward-or-insert-line)
11521 (verilog-insert-indent "// Beginning of automatic wires (for undeclared instantiated-module outputs)\n")
11522 (verilog-insert-definition modi sig-list "wire" indent-pt nil)
11523 (verilog-insert-indent "// End of automatics\n")
11524 ;; We used to optionally call verilog-pretty-declarations and
11525 ;; verilog-pretty-expr here, but it's too slow on huge modules,
11526 ;; plus makes everyone's module change. Finally those call
11527 ;; syntax-ppss which is broken when change hooks are disabled.
11530 (defun verilog-auto-output ()
11531 "Expand AUTOOUTPUT statements, as part of \\[verilog-auto].
11532 Make output statements for any output signal from an /*AUTOINST*/ that
11533 isn't an input to another AUTOINST. This is useful for modules which
11534 only instantiate other modules.
11537 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
11539 If placed inside the parenthesis of a module declaration, it creates
11540 Verilog 2001 style, else uses Verilog 1995 style.
11542 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
11543 instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
11545 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
11547 Signals matching `verilog-auto-output-ignore-regexp' are not included.
11549 An example (see `verilog-auto-inst' for what else is going on here):
11551 module ExampOutput (ov,i);
11554 InstModule instName
11558 Typing \\[verilog-auto] will make this into:
11560 module ExampOutput (ov,i);
11563 // Beginning of automatic outputs (from unused autoinst outputs)
11564 output [31:0] ov; // From inst of inst.v
11565 // End of automatics
11566 InstModule instName
11574 You may also provide an optional regular expression, in which case only
11575 signals matching the regular expression will be included. For example the
11576 same expansion will result from only extracting outputs starting with ov:
11578 /*AUTOOUTPUT(\"^ov\")*/"
11580 ;; Point must be at insertion point.
11581 (let* ((indent-pt (current-indentation))
11582 (params (verilog-read-auto-params 0 1))
11583 (regexp (nth 0 params))
11584 (v2k (verilog-in-paren-quick))
11585 (modi (verilog-modi-current))
11586 (moddecls (verilog-modi-get-decls modi))
11587 (modsubdecls (verilog-modi-get-sub-decls modi))
11588 (sig-list (verilog-signals-not-in
11589 (verilog-subdecls-get-outputs modsubdecls)
11590 (append (verilog-decls-get-outputs moddecls)
11591 (verilog-decls-get-inouts moddecls)
11592 (verilog-subdecls-get-inputs modsubdecls)
11593 (verilog-subdecls-get-inouts modsubdecls)))))
11595 (setq sig-list (verilog-signals-matching-regexp
11597 (setq sig-list (verilog-signals-not-matching-regexp
11598 sig-list verilog-auto-output-ignore-regexp))
11599 (verilog-forward-or-insert-line)
11600 (when v2k (verilog-repair-open-comma))
11602 (verilog-insert-indent "// Beginning of automatic outputs (from unused autoinst outputs)\n")
11603 (verilog-insert-definition modi sig-list "output" indent-pt v2k)
11604 (verilog-insert-indent "// End of automatics\n"))
11605 (when v2k (verilog-repair-close-comma)))))
11607 (defun verilog-auto-output-every ()
11608 "Expand AUTOOUTPUTEVERY statements, as part of \\[verilog-auto].
11609 Make output statements for any signals that aren't primary inputs or
11610 outputs already. This makes every signal in the design an output. This is
11611 useful to get Synopsys to preserve every signal in the design, since it
11612 won't optimize away the outputs.
11616 module ExampOutputEvery (o,i,tempa,tempb);
11619 /*AUTOOUTPUTEVERY*/
11621 wire tempb = tempa;
11625 Typing \\[verilog-auto] will make this into:
11627 module ExampOutputEvery (o,i,tempa,tempb);
11630 /*AUTOOUTPUTEVERY*/
11631 // Beginning of automatic outputs (every signal)
11634 // End of automatics
11636 wire tempb = tempa;
11640 ;;Point must be at insertion point
11641 (let* ((indent-pt (current-indentation))
11642 (v2k (verilog-in-paren-quick))
11643 (modi (verilog-modi-current))
11644 (moddecls (verilog-modi-get-decls modi))
11645 (sig-list (verilog-signals-combine-bus
11646 (verilog-signals-not-in
11647 (verilog-decls-get-signals moddecls)
11648 (verilog-decls-get-ports moddecls)))))
11649 (verilog-forward-or-insert-line)
11650 (when v2k (verilog-repair-open-comma))
11652 (verilog-insert-indent "// Beginning of automatic outputs (every signal)\n")
11653 (verilog-insert-definition modi sig-list "output" indent-pt v2k)
11654 (verilog-insert-indent "// End of automatics\n"))
11655 (when v2k (verilog-repair-close-comma)))))
11657 (defun verilog-auto-input ()
11658 "Expand AUTOINPUT statements, as part of \\[verilog-auto].
11659 Make input statements for any input signal into an /*AUTOINST*/ that
11660 isn't declared elsewhere inside the module. This is useful for modules which
11661 only instantiate other modules.
11664 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
11666 If placed inside the parenthesis of a module declaration, it creates
11667 Verilog 2001 style, else uses Verilog 1995 style.
11669 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
11670 instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
11672 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
11674 Signals matching `verilog-auto-input-ignore-regexp' are not included.
11676 An example (see `verilog-auto-inst' for what else is going on here):
11678 module ExampInput (ov,i);
11681 InstModule instName
11685 Typing \\[verilog-auto] will make this into:
11687 module ExampInput (ov,i);
11690 // Beginning of automatic inputs (from unused autoinst inputs)
11691 input i; // From inst of inst.v
11692 // End of automatics
11693 InstModule instName
11701 You may also provide an optional regular expression, in which case only
11702 signals matching the regular expression will be included. For example the
11703 same expansion will result from only extracting inputs starting with i:
11705 /*AUTOINPUT(\"^i\")*/"
11707 (let* ((indent-pt (current-indentation))
11708 (params (verilog-read-auto-params 0 1))
11709 (regexp (nth 0 params))
11710 (v2k (verilog-in-paren-quick))
11711 (modi (verilog-modi-current))
11712 (moddecls (verilog-modi-get-decls modi))
11713 (modsubdecls (verilog-modi-get-sub-decls modi))
11714 (sig-list (verilog-signals-not-in
11715 (verilog-subdecls-get-inputs modsubdecls)
11716 (append (verilog-decls-get-inputs moddecls)
11717 (verilog-decls-get-inouts moddecls)
11718 (verilog-decls-get-vars moddecls)
11719 (verilog-decls-get-consts moddecls)
11720 (verilog-decls-get-gparams moddecls)
11721 (verilog-subdecls-get-interfaced modsubdecls)
11722 (verilog-subdecls-get-outputs modsubdecls)
11723 (verilog-subdecls-get-inouts modsubdecls)))))
11725 (setq sig-list (verilog-signals-matching-regexp
11727 (setq sig-list (verilog-signals-not-matching-regexp
11728 sig-list verilog-auto-input-ignore-regexp))
11729 (verilog-forward-or-insert-line)
11730 (when v2k (verilog-repair-open-comma))
11732 (verilog-insert-indent "// Beginning of automatic inputs (from unused autoinst inputs)\n")
11733 (verilog-insert-definition modi sig-list "input" indent-pt v2k)
11734 (verilog-insert-indent "// End of automatics\n"))
11735 (when v2k (verilog-repair-close-comma)))))
11737 (defun verilog-auto-inout ()
11738 "Expand AUTOINOUT statements, as part of \\[verilog-auto].
11739 Make inout statements for any inout signal in an /*AUTOINST*/ that
11740 isn't declared elsewhere inside the module.
11743 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
11745 If placed inside the parenthesis of a module declaration, it creates
11746 Verilog 2001 style, else uses Verilog 1995 style.
11748 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
11749 instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
11751 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
11753 Signals matching `verilog-auto-inout-ignore-regexp' are not included.
11755 An example (see `verilog-auto-inst' for what else is going on here):
11757 module ExampInout (ov,i);
11760 InstModule instName
11764 Typing \\[verilog-auto] will make this into:
11766 module ExampInout (ov,i);
11769 // Beginning of automatic inouts (from unused autoinst inouts)
11770 inout [31:0] ov; // From inst of inst.v
11771 // End of automatics
11772 InstModule instName
11780 You may also provide an optional regular expression, in which case only
11781 signals matching the regular expression will be included. For example the
11782 same expansion will result from only extracting inouts starting with i:
11784 /*AUTOINOUT(\"^i\")*/"
11786 ;; Point must be at insertion point.
11787 (let* ((indent-pt (current-indentation))
11788 (params (verilog-read-auto-params 0 1))
11789 (regexp (nth 0 params))
11790 (v2k (verilog-in-paren-quick))
11791 (modi (verilog-modi-current))
11792 (moddecls (verilog-modi-get-decls modi))
11793 (modsubdecls (verilog-modi-get-sub-decls modi))
11794 (sig-list (verilog-signals-not-in
11795 (verilog-subdecls-get-inouts modsubdecls)
11796 (append (verilog-decls-get-outputs moddecls)
11797 (verilog-decls-get-inouts moddecls)
11798 (verilog-decls-get-inputs moddecls)
11799 (verilog-subdecls-get-inputs modsubdecls)
11800 (verilog-subdecls-get-outputs modsubdecls)))))
11802 (setq sig-list (verilog-signals-matching-regexp
11804 (setq sig-list (verilog-signals-not-matching-regexp
11805 sig-list verilog-auto-inout-ignore-regexp))
11806 (verilog-forward-or-insert-line)
11807 (when v2k (verilog-repair-open-comma))
11809 (verilog-insert-indent "// Beginning of automatic inouts (from unused autoinst inouts)\n")
11810 (verilog-insert-definition modi sig-list "inout" indent-pt v2k)
11811 (verilog-insert-indent "// End of automatics\n"))
11812 (when v2k (verilog-repair-close-comma)))))
11814 (defun verilog-auto-inout-module (&optional complement all-in)
11815 "Expand AUTOINOUTMODULE statements, as part of \\[verilog-auto].
11816 Take input/output/inout statements from the specified module and insert
11817 into the current module. This is useful for making null templates and
11818 shell modules which need to have identical I/O with another module.
11819 Any I/O which are already defined in this module will not be redefined.
11820 For the complement of this function, see `verilog-auto-inout-comp',
11821 and to make monitors with all inputs, see `verilog-auto-inout-in'.
11824 If placed inside the parenthesis of a module declaration, it creates
11825 Verilog 2001 style, else uses Verilog 1995 style.
11827 Concatenation and outputting partial buses is not supported.
11829 Module names must be resolvable to filenames. See `verilog-auto-inst'.
11831 Signals are not inserted in the same order as in the original module,
11832 though they will appear to be in the same order to an AUTOINST
11833 instantiating either module.
11835 Signals declared as \"output reg\" or \"output wire\" etc will
11836 lose the wire/reg declaration so that shell modules may
11837 generate those outputs differently. However, \"output logic\"
11842 module ExampShell (/*AUTOARG*/);
11843 /*AUTOINOUTMODULE(\"ExampMain\")*/
11846 module ExampMain (i,o,io);
11852 Typing \\[verilog-auto] will make this into:
11854 module ExampShell (/*AUTOARG*/i,o,io);
11855 /*AUTOINOUTMODULE(\"ExampMain\")*/
11856 // Beginning of automatic in/out/inouts (from specific module)
11860 // End of automatics
11863 You may also provide an optional regular expression, in which case only
11864 signals matching the regular expression will be included. For example the
11865 same expansion will result from only extracting signals starting with i:
11867 /*AUTOINOUTMODULE(\"ExampMain\",\"^i\")*/
11869 You may also provide an optional second regular expression, in
11870 which case only signals which have that pin direction and data
11871 type will be included. This matches against everything before
11872 the signal name in the declaration, for example against
11873 \"input\" (single bit), \"output logic\" (direction and type) or
11874 \"output [1:0]\" (direction and implicit type). You also
11875 probably want to skip spaces in your regexp.
11877 For example, the below will result in matching the output \"o\"
11878 against the previous example's module:
11880 /*AUTOINOUTMODULE(\"ExampMain\",\"\",\"^output.*\")*/"
11882 (let* ((params (verilog-read-auto-params 1 3))
11883 (submod (nth 0 params))
11884 (regexp (nth 1 params))
11885 (direction-re (nth 2 params))
11887 ;; Lookup position, etc of co-module
11888 ;; Note this may raise an error
11889 (when (setq submodi (verilog-modi-lookup submod t))
11890 (let* ((indent-pt (current-indentation))
11891 (v2k (verilog-in-paren-quick))
11892 (modi (verilog-modi-current))
11893 (moddecls (verilog-modi-get-decls modi))
11894 (submoddecls (verilog-modi-get-decls submodi))
11895 (sig-list-i (verilog-signals-not-in
11898 (verilog-decls-get-inputs submoddecls)
11899 (verilog-decls-get-inouts submoddecls)
11900 (verilog-decls-get-outputs submoddecls)))
11902 (verilog-decls-get-outputs submoddecls))
11903 (t (verilog-decls-get-inputs submoddecls)))
11904 (append (verilog-decls-get-inputs moddecls))))
11905 (sig-list-o (verilog-signals-not-in
11908 (verilog-decls-get-inputs submoddecls))
11909 (t (verilog-decls-get-outputs submoddecls)))
11910 (append (verilog-decls-get-outputs moddecls))))
11911 (sig-list-io (verilog-signals-not-in
11913 (t (verilog-decls-get-inouts submoddecls)))
11914 (append (verilog-decls-get-inouts moddecls))))
11915 (sig-list-if (verilog-signals-not-in
11916 (verilog-decls-get-interfaces submoddecls)
11917 (append (verilog-decls-get-interfaces moddecls)))))
11919 (setq sig-list-i (verilog-signals-edit-wire-reg
11920 (verilog-signals-matching-dir-re
11921 (verilog-signals-matching-regexp sig-list-i regexp)
11922 "input" direction-re))
11923 sig-list-o (verilog-signals-edit-wire-reg
11924 (verilog-signals-matching-dir-re
11925 (verilog-signals-matching-regexp sig-list-o regexp)
11926 "output" direction-re))
11927 sig-list-io (verilog-signals-edit-wire-reg
11928 (verilog-signals-matching-dir-re
11929 (verilog-signals-matching-regexp sig-list-io regexp)
11930 "inout" direction-re))
11931 sig-list-if (verilog-signals-matching-dir-re
11932 (verilog-signals-matching-regexp sig-list-if regexp)
11933 "interface" direction-re))
11934 (when v2k (verilog-repair-open-comma))
11935 (when (or sig-list-i sig-list-o sig-list-io)
11936 (verilog-insert-indent "// Beginning of automatic in/out/inouts (from specific module)\n")
11937 ;; Don't sort them so an upper AUTOINST will match the main module
11938 (verilog-insert-definition modi sig-list-o "output" indent-pt v2k t)
11939 (verilog-insert-definition modi sig-list-io "inout" indent-pt v2k t)
11940 (verilog-insert-definition modi sig-list-i "input" indent-pt v2k t)
11941 (verilog-insert-definition modi sig-list-if "interface" indent-pt v2k t)
11942 (verilog-insert-indent "// End of automatics\n"))
11943 (when v2k (verilog-repair-close-comma)))))))
11945 (defun verilog-auto-inout-comp ()
11946 "Expand AUTOINOUTCOMP statements, as part of \\[verilog-auto].
11947 Take input/output/inout statements from the specified module and
11948 insert the inverse into the current module (inputs become outputs
11949 and vice-versa.) This is useful for making test and stimulus
11950 modules which need to have complementing I/O with another module.
11951 Any I/O which are already defined in this module will not be
11952 redefined. For the complement of this function, see
11953 `verilog-auto-inout-module'.
11956 If placed inside the parenthesis of a module declaration, it creates
11957 Verilog 2001 style, else uses Verilog 1995 style.
11959 Concatenation and outputting partial buses is not supported.
11961 Module names must be resolvable to filenames. See `verilog-auto-inst'.
11963 Signals are not inserted in the same order as in the original module,
11964 though they will appear to be in the same order to an AUTOINST
11965 instantiating either module.
11969 module ExampShell (/*AUTOARG*/);
11970 /*AUTOINOUTCOMP(\"ExampMain\")*/
11973 module ExampMain (i,o,io);
11979 Typing \\[verilog-auto] will make this into:
11981 module ExampShell (/*AUTOARG*/i,o,io);
11982 /*AUTOINOUTCOMP(\"ExampMain\")*/
11983 // Beginning of automatic in/out/inouts (from specific module)
11987 // End of automatics
11990 You may also provide an optional regular expression, in which case only
11991 signals matching the regular expression will be included. For example the
11992 same expansion will result from only extracting signals starting with i:
11994 /*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/"
11995 (verilog-auto-inout-module t nil))
11997 (defun verilog-auto-inout-in ()
11998 "Expand AUTOINOUTIN statements, as part of \\[verilog-auto].
11999 Take input/output/inout statements from the specified module and
12000 insert them as all inputs into the current module. This is
12001 useful for making monitor modules which need to see all signals
12002 as inputs based on another module. Any I/O which are already
12003 defined in this module will not be redefined. See also
12004 `verilog-auto-inout-module'.
12007 If placed inside the parenthesis of a module declaration, it creates
12008 Verilog 2001 style, else uses Verilog 1995 style.
12010 Concatenation and outputting partial buses is not supported.
12012 Module names must be resolvable to filenames. See `verilog-auto-inst'.
12014 Signals are not inserted in the same order as in the original module,
12015 though they will appear to be in the same order to an AUTOINST
12016 instantiating either module.
12020 module ExampShell (/*AUTOARG*/);
12021 /*AUTOINOUTIN(\"ExampMain\")*/
12024 module ExampMain (i,o,io);
12030 Typing \\[verilog-auto] will make this into:
12032 module ExampShell (/*AUTOARG*/i,o,io);
12033 /*AUTOINOUTIN(\"ExampMain\")*/
12034 // Beginning of automatic in/out/inouts (from specific module)
12038 // End of automatics
12041 You may also provide an optional regular expression, in which case only
12042 signals matching the regular expression will be included. For example the
12043 same expansion will result from only extracting signals starting with i:
12045 /*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/"
12046 (verilog-auto-inout-module nil t))
12048 (defun verilog-auto-inout-param ()
12049 "Expand AUTOINOUTPARAM statements, as part of \\[verilog-auto].
12050 Take input/output/inout statements from the specified module and insert
12051 into the current module. This is useful for making null templates and
12052 shell modules which need to have identical I/O with another module.
12053 Any I/O which are already defined in this module will not be redefined.
12054 For the complement of this function, see `verilog-auto-inout-comp',
12055 and to make monitors with all inputs, see `verilog-auto-inout-in'.
12058 If placed inside the parenthesis of a module declaration, it creates
12059 Verilog 2001 style, else uses Verilog 1995 style.
12061 Concatenation and outputting partial buses is not supported.
12063 Module names must be resolvable to filenames. See `verilog-auto-inst'.
12065 Signals are not inserted in the same order as in the original module,
12066 though they will appear to be in the same order to an AUTOINST
12067 instantiating either module.
12069 Signals declared as \"output reg\" or \"output wire\" etc will
12070 lose the wire/reg declaration so that shell modules may
12071 generate those outputs differently. However, \"output logic\"
12076 module ExampShell (/*AUTOARG*/);
12077 /*AUTOINOUTMODULE(\"ExampMain\")*/
12080 module ExampMain (i,o,io);
12086 Typing \\[verilog-auto] will make this into:
12088 module ExampShell (/*AUTOARG*/i,o,io);
12089 /*AUTOINOUTMODULE(\"ExampMain\")*/
12090 // Beginning of automatic in/out/inouts (from specific module)
12094 // End of automatics
12097 You may also provide an optional regular expression, in which case only
12098 signals matching the regular expression will be included. For example the
12099 same expansion will result from only extracting signals starting with i:
12101 /*AUTOINOUTMODULE(\"ExampMain\",\"^i\")*/
12103 You may also provide an optional second regular expression, in
12104 which case only signals which have that pin direction and data
12105 type will be included. This matches against everything before
12106 the signal name in the declaration, for example against
12107 \"input\" (single bit), \"output logic\" (direction and type) or
12108 \"output [1:0]\" (direction and implicit type). You also
12109 probably want to skip spaces in your regexp.
12111 For example, the below will result in matching the output \"o\"
12112 against the previous example's module:
12114 /*AUTOINOUTMODULE(\"ExampMain\",\"\",\"^output.*\")*/
12116 You may also provide an optional third regular expression, in
12117 which case any parameter names that match the given regexp will
12118 be included. Including parameters is off by default. To include
12119 all signals and parameters, use:
12121 /*AUTOINOUTMODULE(\"ExampMain\",\".*\",\".*\",\".*\")*/"
12123 (let* ((params (verilog-read-auto-params 1 2))
12124 (submod (nth 0 params))
12125 (regexp (nth 1 params))
12127 ;; Lookup position, etc of co-module
12128 ;; Note this may raise an error
12129 (when (setq submodi (verilog-modi-lookup submod t))
12130 (let* ((indent-pt (current-indentation))
12131 (v2k (verilog-in-paren-quick))
12132 (modi (verilog-modi-current))
12133 (moddecls (verilog-modi-get-decls modi))
12134 (submoddecls (verilog-modi-get-decls submodi))
12135 (sig-list-p (verilog-signals-not-in
12136 (verilog-decls-get-gparams submoddecls)
12137 (append (verilog-decls-get-gparams moddecls)))))
12139 (setq sig-list-p (verilog-signals-matching-regexp sig-list-p regexp))
12140 (when v2k (verilog-repair-open-comma))
12142 (verilog-insert-indent "// Beginning of automatic parameters (from specific module)\n")
12143 ;; Don't sort them so an upper AUTOINST will match the main module
12144 (verilog-insert-definition modi sig-list-p "parameter" indent-pt v2k t)
12145 (verilog-insert-indent "// End of automatics\n"))
12146 (when v2k (verilog-repair-close-comma)))))))
12148 (defun verilog-auto-inout-modport ()
12149 "Expand AUTOINOUTMODPORT statements, as part of \\[verilog-auto].
12150 Take input/output/inout statements from the specified interface
12151 and modport and insert into the current module. This is useful
12152 for making verification modules that connect to UVM interfaces.
12154 The first parameter is the name of an interface.
12156 The second parameter is a regexp of modports to read from in
12159 The optional third parameter is a regular expression, and only
12160 signals matching the regular expression will be included.
12163 If placed inside the parenthesis of a module declaration, it creates
12164 Verilog 2001 style, else uses Verilog 1995 style.
12166 Interface names must be resolvable to filenames. See `verilog-auto-inst'.
12168 As with other autos, any inputs/outputs declared in the module
12169 will suppress the AUTO from redeclaring an input/output by
12175 ( input logic clk );
12177 logic [7:0] req_dat;
12178 clocking mon_clkblk @(posedge clk);
12182 modport mp(clocking mon_clkblk);
12187 /*AUTOINOUTMODPORT(\"ExampIf\" \"mp\")*/
12188 // Beginning of automatic in/out/inouts (from modport)
12189 input [7:0] req_dat,
12191 // End of automatics
12193 /*AUTOASSIGNMODPORT(\"ExampIf\" \"mp\")*/
12196 Typing \\[verilog-auto] will make this into:
12201 /*AUTOINOUTMODPORT(\"ExampIf\" \"mp\")*/
12202 // Beginning of automatic in/out/inouts (from modport)
12205 // End of automatics
12208 If the modport is part of a UVM monitor/driver class, this
12209 creates a wrapper module that may be used to instantiate the
12210 driver/monitor using AUTOINST in the testbench."
12212 (let* ((params (verilog-read-auto-params 2 3))
12213 (submod (nth 0 params))
12214 (modport-re (nth 1 params))
12215 (regexp (nth 2 params))
12216 direction-re submodi) ;; direction argument not supported until requested
12217 ;; Lookup position, etc of co-module
12218 ;; Note this may raise an error
12219 (when (setq submodi (verilog-modi-lookup submod t))
12220 (let* ((indent-pt (current-indentation))
12221 (v2k (verilog-in-paren-quick))
12222 (modi (verilog-modi-current))
12223 (moddecls (verilog-modi-get-decls modi))
12224 (submoddecls (verilog-modi-get-decls submodi))
12225 (submodportdecls (verilog-modi-modport-lookup submodi modport-re))
12226 (sig-list-i (verilog-signals-in ;; Decls doesn't have data types, must resolve
12227 (verilog-decls-get-vars submoddecls)
12228 (verilog-signals-not-in
12229 (verilog-decls-get-inputs submodportdecls)
12230 (append (verilog-decls-get-ports submoddecls)
12231 (verilog-decls-get-ports moddecls)))))
12232 (sig-list-o (verilog-signals-in ;; Decls doesn't have data types, must resolve
12233 (verilog-decls-get-vars submoddecls)
12234 (verilog-signals-not-in
12235 (verilog-decls-get-outputs submodportdecls)
12236 (append (verilog-decls-get-ports submoddecls)
12237 (verilog-decls-get-ports moddecls)))))
12238 (sig-list-io (verilog-signals-in ;; Decls doesn't have data types, must resolve
12239 (verilog-decls-get-vars submoddecls)
12240 (verilog-signals-not-in
12241 (verilog-decls-get-inouts submodportdecls)
12242 (append (verilog-decls-get-ports submoddecls)
12243 (verilog-decls-get-ports moddecls))))))
12245 (setq sig-list-i (verilog-signals-edit-wire-reg
12246 (verilog-signals-matching-dir-re
12247 (verilog-signals-matching-regexp sig-list-i regexp)
12248 "input" direction-re))
12249 sig-list-o (verilog-signals-edit-wire-reg
12250 (verilog-signals-matching-dir-re
12251 (verilog-signals-matching-regexp sig-list-o regexp)
12252 "output" direction-re))
12253 sig-list-io (verilog-signals-edit-wire-reg
12254 (verilog-signals-matching-dir-re
12255 (verilog-signals-matching-regexp sig-list-io regexp)
12256 "inout" direction-re)))
12257 (when v2k (verilog-repair-open-comma))
12258 (when (or sig-list-i sig-list-o sig-list-io)
12259 (verilog-insert-indent "// Beginning of automatic in/out/inouts (from modport)\n")
12260 ;; Don't sort them so an upper AUTOINST will match the main module
12261 (verilog-insert-definition modi sig-list-o "output" indent-pt v2k t)
12262 (verilog-insert-definition modi sig-list-io "inout" indent-pt v2k t)
12263 (verilog-insert-definition modi sig-list-i "input" indent-pt v2k t)
12264 (verilog-insert-indent "// End of automatics\n"))
12265 (when v2k (verilog-repair-close-comma)))))))
12267 (defun verilog-auto-insert-lisp ()
12268 "Expand AUTOINSERTLISP statements, as part of \\[verilog-auto].
12269 The Lisp code provided is called, and the Lisp code calls
12270 `insert` to insert text into the current file beginning on the
12271 line after the AUTOINSERTLISP.
12273 See also AUTO_LISP, which takes a Lisp expression and evaluates
12274 it during `verilog-auto-inst' but does not insert any text.
12278 module ExampInsertLisp;
12279 /*AUTOINSERTLISP(my-verilog-insert-hello \"world\")*/
12282 // For this example we declare the function in the
12283 // module's file itself. Often you'd define it instead
12284 // in a site-start.el or init file.
12288 (defun my-verilog-insert-hello (who)
12289 (insert (concat \"initial $write(\\\"hello \" who \"\\\");\\n\")))
12293 Typing \\[verilog-auto] will call my-verilog-insert-hello and
12294 expand the above into:
12296 // Beginning of automatic insert lisp
12297 initial $write(\"hello world\");
12298 // End of automatics
12300 You can also call an external program and insert the returned
12303 /*AUTOINSERTLISP(insert (shell-command-to-string \"echo //hello\"))*/
12304 // Beginning of automatic insert lisp
12306 // End of automatics"
12308 ;; Point is at end of /*AUTO...*/
12309 (let* ((indent-pt (current-indentation))
12310 (cmd-end-pt (save-excursion (search-backward ")")
12312 (point))) ;; Closing paren
12313 (cmd-beg-pt (save-excursion (goto-char cmd-end-pt)
12314 (backward-sexp 1) ;; Inside comment
12315 (point))) ;; Beginning paren
12316 (cmd (buffer-substring-no-properties cmd-beg-pt cmd-end-pt)))
12317 (verilog-forward-or-insert-line)
12318 ;; Some commands don't move point (like insert-file) so we always
12319 ;; add the begin/end comments, then delete it if not needed
12320 (verilog-insert-indent "// Beginning of automatic insert lisp\n")
12321 (verilog-insert-indent "// End of automatics\n")
12325 (setq verilog-scan-cache-tick nil) ;; Clear cache; inserted unknown text
12326 (verilog-delete-empty-auto-pair))))
12328 (defun verilog-auto-sense-sigs (moddecls presense-sigs)
12329 "Return list of signals for current AUTOSENSE block."
12330 (let* ((sigss (verilog-read-always-signals))
12331 (sig-list (verilog-signals-not-params
12332 (verilog-signals-not-in (verilog-alw-get-inputs sigss)
12333 (append (and (not verilog-auto-sense-include-inputs)
12334 (verilog-alw-get-outputs-delayed sigss))
12335 (and (not verilog-auto-sense-include-inputs)
12336 (verilog-alw-get-outputs-immediate sigss))
12337 (verilog-alw-get-temps sigss)
12338 (verilog-decls-get-consts moddecls)
12339 (verilog-decls-get-gparams moddecls)
12343 (defun verilog-auto-sense ()
12344 "Expand AUTOSENSE statements, as part of \\[verilog-auto].
12345 Replace the always (/*AUTOSENSE*/) sensitivity list (/*AS*/ for short)
12346 with one automatically derived from all inputs declared in the always
12347 statement. Signals that are generated within the same always block are NOT
12348 placed into the sensitivity list (see `verilog-auto-sense-include-inputs').
12349 Long lines are split based on the `fill-column', see \\[set-fill-column].
12352 Verilog does not allow memories (multidimensional arrays) in sensitivity
12353 lists. AUTOSENSE will thus exclude them, and add a /*memory or*/ comment.
12356 AUTOSENSE cannot always determine if a `define is a constant or a signal
12357 (it could be in an include file for example). If a `define or other signal
12358 is put into the AUTOSENSE list and is not desired, use the AUTO_CONSTANT
12359 declaration anywhere in the module (parenthesis are required):
12361 /* AUTO_CONSTANT ( `this_is_really_constant_dont_autosense_it ) */
12363 Better yet, use a parameter, which will be understood to be constant
12367 If AUTOSENSE makes a mistake, please report it. (First try putting
12368 a begin/end after your always!) As a workaround, if a signal that
12369 shouldn't be in the sensitivity list was, use the AUTO_CONSTANT above.
12370 If a signal should be in the sensitivity list wasn't, placing it before
12371 the /*AUTOSENSE*/ comment will prevent it from being deleted when the
12372 autos are updated (or added if it occurs there already).
12376 always @ (/*AS*/) begin
12377 /* AUTO_CONSTANT (`constant) */
12378 outin = ina | inb | `constant;
12382 Typing \\[verilog-auto] will make this into:
12384 always @ (/*AS*/ina or inb) begin
12385 /* AUTO_CONSTANT (`constant) */
12386 outin = ina | inb | `constant;
12390 Note in Verilog 2001, you can often get the same result from the new @*
12391 operator. (This was added to the language in part due to AUTOSENSE!)
12394 outin = ina | inb | `constant;
12399 (let* ((start-pt (save-excursion
12400 (verilog-re-search-backward-quick "(" nil t)
12402 (indent-pt (save-excursion
12403 (or (and (goto-char start-pt) (1+ (current-column)))
12404 (current-indentation))))
12405 (modi (verilog-modi-current))
12406 (moddecls (verilog-modi-get-decls modi))
12407 (sig-memories (verilog-signals-memory
12408 (verilog-decls-get-vars moddecls)))
12409 sig-list not-first presense-sigs)
12410 ;; Read signals in always, eliminate outputs from sense list
12411 (setq presense-sigs (verilog-signals-from-signame
12413 (verilog-read-signals start-pt (point)))))
12414 (setq sig-list (verilog-auto-sense-sigs moddecls presense-sigs))
12416 (let ((tlen (length sig-list)))
12417 (setq sig-list (verilog-signals-not-in sig-list sig-memories))
12418 (if (not (eq tlen (length sig-list))) (verilog-insert " /*memory or*/ "))))
12419 (if (and presense-sigs ;; Add a "or" if not "(.... or /*AUTOSENSE*/"
12420 (save-excursion (goto-char (point))
12421 (verilog-re-search-backward-quick "[a-zA-Z0-9$_.%`]+" start-pt t)
12422 (verilog-re-search-backward-quick "\\s-" start-pt t)
12423 (while (looking-at "\\s-`endif")
12424 (verilog-re-search-backward-quick "[a-zA-Z0-9$_.%`]+" start-pt t)
12425 (verilog-re-search-backward-quick "\\s-" start-pt t))
12426 (not (looking-at "\\s-or\\b"))))
12427 (setq not-first t))
12428 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
12430 (cond ((> (+ 4 (current-column) (length (verilog-sig-name (car sig-list)))) fill-column) ;+4 for width of or
12432 (indent-to indent-pt)
12433 (if not-first (insert "or ")))
12434 (not-first (insert " or ")))
12435 (insert (verilog-sig-name (car sig-list)))
12436 (setq sig-list (cdr sig-list)
12439 (defun verilog-auto-reset ()
12440 "Expand AUTORESET statements, as part of \\[verilog-auto].
12441 Replace the /*AUTORESET*/ comment with code to initialize all
12442 registers set elsewhere in the always block.
12445 AUTORESET will not clear memories.
12447 AUTORESET uses <= if the signal has a <= assignment in the block,
12450 If <= is used, all = assigned variables are ignored if
12451 `verilog-auto-reset-blocking-in-non' is nil; they are presumed
12454 /*AUTORESET*/ presumes that any signals mentioned between the previous
12455 begin/case/if statement and the AUTORESET comment are being reset manually
12456 and should not be automatically reset. This includes omitting any signals
12457 used on the right hand side of assignments.
12459 By default, AUTORESET will include the width of the signal in the
12460 autos, SystemVerilog designs may want to change this. To control
12461 this behavior, see `verilog-auto-reset-widths'.
12463 AUTORESET ties signals to deasserted, which is presumed to be zero.
12464 Signals that match `verilog-active-low-regexp' will be deasserted by tying
12469 always @(posedge clk or negedge reset_l) begin
12470 if (!reset_l) begin
12481 Typing \\[verilog-auto] will make this into:
12483 always @(posedge core_clk or negedge reset_l) begin
12484 if (!reset_l) begin
12487 // Beginning of autoreset for uninitialized flops
12489 b = 0; // if `verilog-auto-reset-blocking-in-non' true
12490 // End of automatics
12502 (let* ((indent-pt (current-indentation))
12503 (modi (verilog-modi-current))
12504 (moddecls (verilog-modi-get-decls modi))
12505 (all-list (verilog-decls-get-signals moddecls))
12506 sigss sig-list dly-list prereset-sigs)
12507 ;; Read signals in always, eliminate outputs from reset list
12508 (setq prereset-sigs (verilog-signals-from-signame
12510 (verilog-read-signals
12512 (verilog-re-search-backward-quick "\\(@\\|\\<begin\\>\\|\\<if\\>\\|\\<case\\>\\)" nil t)
12516 (verilog-re-search-backward-quick "@" nil t)
12517 (setq sigss (verilog-read-always-signals)))
12518 (setq dly-list (verilog-alw-get-outputs-delayed sigss))
12519 (setq sig-list (verilog-signals-not-in (append
12520 (verilog-alw-get-outputs-delayed sigss)
12521 (when (or (not (verilog-alw-get-uses-delayed sigss))
12522 verilog-auto-reset-blocking-in-non)
12523 (verilog-alw-get-outputs-immediate sigss)))
12525 (verilog-alw-get-temps sigss)
12527 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
12530 (verilog-insert-indent "// Beginning of autoreset for uninitialized flops\n");
12532 (let ((sig (or (assoc (verilog-sig-name (car sig-list)) all-list) ;; As sig-list has no widths
12534 (indent-to indent-pt)
12535 (insert (verilog-sig-name sig)
12536 (if (assoc (verilog-sig-name sig) dly-list)
12537 (concat " <= " verilog-assignment-delay)
12539 (verilog-sig-tieoff sig)
12541 (setq sig-list (cdr sig-list))))
12542 (verilog-insert-indent "// End of automatics")))))
12544 (defun verilog-auto-tieoff ()
12545 "Expand AUTOTIEOFF statements, as part of \\[verilog-auto].
12546 Replace the /*AUTOTIEOFF*/ comment with code to wire-tie all unused output
12547 signals to deasserted.
12549 /*AUTOTIEOFF*/ is used to make stub modules; modules that have the same
12550 input/output list as another module, but no internals. Specifically, it
12551 finds all outputs in the module, and if that input is not otherwise declared
12552 as a register or wire, creates a tieoff.
12554 AUTORESET ties signals to deasserted, which is presumed to be zero.
12555 Signals that match `verilog-active-low-regexp' will be deasserted by tying
12558 You can add signals you do not want included in AUTOTIEOFF with
12559 `verilog-auto-tieoff-ignore-regexp'.
12561 `verilog-auto-wire-type' may be used to change the datatype of
12564 `verilog-auto-reset-widths' may be used to change how the tieoff
12565 value's width is generated.
12567 An example of making a stub for another module:
12569 module ExampStub (/*AUTOINST*/);
12570 /*AUTOINOUTPARAM(\"Foo\")*/
12571 /*AUTOINOUTMODULE(\"Foo\")*/
12573 // verilator lint_off UNUSED
12574 wire _unused_ok = &{1'b0,
12577 // verilator lint_on UNUSED
12580 Typing \\[verilog-auto] will make this into:
12582 module ExampStub (/*AUTOINST*/...);
12583 /*AUTOINOUTPARAM(\"Foo\")*/
12584 /*AUTOINOUTMODULE(\"Foo\")*/
12585 // Beginning of autotieoff
12587 // End of automatics
12590 // Beginning of autotieoff
12591 wire [2:0] foo = 3'b0;
12592 // End of automatics
12598 (let* ((indent-pt (current-indentation))
12599 (modi (verilog-modi-current))
12600 (moddecls (verilog-modi-get-decls modi))
12601 (modsubdecls (verilog-modi-get-sub-decls modi))
12602 (sig-list (verilog-signals-not-in
12603 (verilog-decls-get-outputs moddecls)
12604 (append (verilog-decls-get-vars moddecls)
12605 (verilog-decls-get-assigns moddecls)
12606 (verilog-decls-get-consts moddecls)
12607 (verilog-decls-get-gparams moddecls)
12608 (verilog-subdecls-get-interfaced modsubdecls)
12609 (verilog-subdecls-get-outputs modsubdecls)
12610 (verilog-subdecls-get-inouts modsubdecls)))))
12611 (setq sig-list (verilog-signals-not-matching-regexp
12612 sig-list verilog-auto-tieoff-ignore-regexp))
12614 (verilog-forward-or-insert-line)
12615 (verilog-insert-indent "// Beginning of automatic tieoffs (for this module's unterminated outputs)\n")
12616 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
12617 (verilog-modi-cache-add-vars modi sig-list) ; Before we trash list
12619 (let ((sig (car sig-list)))
12620 (cond ((equal verilog-auto-tieoff-declaration "assign")
12621 (indent-to indent-pt)
12622 (insert "assign " (verilog-sig-name sig)))
12624 (verilog-insert-one-definition sig verilog-auto-tieoff-declaration indent-pt)))
12625 (indent-to (max 48 (+ indent-pt 40)))
12626 (insert "= " (verilog-sig-tieoff sig)
12628 (setq sig-list (cdr sig-list))))
12629 (verilog-insert-indent "// End of automatics\n")))))
12631 (defun verilog-auto-undef ()
12632 "Expand AUTOUNDEF statements, as part of \\[verilog-auto].
12633 Take any `defines since the last AUTOUNDEF in the current file
12634 and create `undefs for them. This is used to insure that
12635 file-local defines do not pollute the global `define name space.
12638 AUTOUNDEF presumes any identifier following `define is the
12639 name of a define. Any `ifdefs are ignored.
12641 AUTOUNDEF suppresses creating an `undef for any define that was
12642 `undefed before the AUTOUNDEF. This may be used to work around
12643 the ignoring of `ifdefs as shown below.
12652 `undef M_BAZ // Emacs will see this and not `undef M_BAZ
12657 Typing \\[verilog-auto] will make this into:
12661 // Beginning of automatic undefs
12664 // End of automatics
12666 You may also provide an optional regular expression, in which case only
12667 defines the regular expression will be undefed."
12669 (let* ((params (verilog-read-auto-params 0 1))
12670 (regexp (nth 0 params))
12671 (indent-pt (current-indentation))
12675 ;; Scan from start of file, or last AUTOUNDEF
12676 (or (verilog-re-search-backward-quick "/\\*AUTOUNDEF\\>" end-pt t)
12677 (goto-char (point-min)))
12678 (while (verilog-re-search-forward-quick
12679 "`\\(define\\|undef\\)\\s-*\\([a-zA-Z_][a-zA-Z_0-9]*\\)" end-pt t)
12680 (cond ((equal (match-string-no-properties 1) "define")
12681 (setq def (match-string-no-properties 2))
12682 (when (and (or (not regexp)
12683 (string-match regexp def))
12684 (not (member def defs))) ;; delete-dups not in 21.1
12685 (setq defs (cons def defs))))
12687 (setq defs (delete (match-string-no-properties 2) defs))))))
12689 (setq defs (sort defs 'string<))
12691 (verilog-forward-or-insert-line)
12692 (verilog-insert-indent "// Beginning of automatic undefs\n")
12694 (verilog-insert-indent "`undef " (car defs) "\n")
12695 (setq defs (cdr defs)))
12696 (verilog-insert-indent "// End of automatics\n")))))
12698 (defun verilog-auto-unused ()
12699 "Expand AUTOUNUSED statements, as part of \\[verilog-auto].
12700 Replace the /*AUTOUNUSED*/ comment with a comma separated list of all unused
12701 input and inout signals.
12703 /*AUTOUNUSED*/ is used to make stub modules; modules that have the same
12704 input/output list as another module, but no internals. Specifically, it
12705 finds all inputs and inouts in the module, and if that input is not otherwise
12706 used, adds it to a comma separated list.
12708 The comma separated list is intended to be used to create a _unused_ok
12709 signal. Using the exact name \"_unused_ok\" for name of the temporary
12710 signal is recommended as it will insure maximum forward compatibility, it
12711 also makes lint warnings easy to understand; ignore any unused warnings
12712 with \"unused\" in the signal name.
12714 To reduce simulation time, the _unused_ok signal should be forced to a
12715 constant to prevent wiggling. The easiest thing to do is use a
12716 reduction-and with 1'b0 as shown.
12718 This way all unused signals are in one place, making it convenient to add
12719 your tool's specific pragmas around the assignment to disable any unused
12722 You can add signals you do not want included in AUTOUNUSED with
12723 `verilog-auto-unused-ignore-regexp'.
12725 An example of making a stub for another module:
12727 module ExampStub (/*AUTOINST*/);
12728 /*AUTOINOUTPARAM(\"Examp\")*/
12729 /*AUTOINOUTMODULE(\"Examp\")*/
12731 // verilator lint_off UNUSED
12732 wire _unused_ok = &{1'b0,
12735 // verilator lint_on UNUSED
12738 Typing \\[verilog-auto] will make this into:
12741 // verilator lint_off UNUSED
12742 wire _unused_ok = &{1'b0,
12744 // Beginning of automatics
12748 // End of automatics
12750 // verilator lint_on UNUSED
12755 (let* ((indent-pt (progn (search-backward "/*") (current-column)))
12756 (modi (verilog-modi-current))
12757 (moddecls (verilog-modi-get-decls modi))
12758 (modsubdecls (verilog-modi-get-sub-decls modi))
12759 (sig-list (verilog-signals-not-in
12760 (append (verilog-decls-get-inputs moddecls)
12761 (verilog-decls-get-inouts moddecls))
12762 (append (verilog-subdecls-get-inputs modsubdecls)
12763 (verilog-subdecls-get-inouts modsubdecls)))))
12764 (setq sig-list (verilog-signals-not-matching-regexp
12765 sig-list verilog-auto-unused-ignore-regexp))
12767 (verilog-forward-or-insert-line)
12768 (verilog-insert-indent "// Beginning of automatic unused inputs\n")
12769 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
12771 (let ((sig (car sig-list)))
12772 (indent-to indent-pt)
12773 (insert (verilog-sig-name sig) ",\n")
12774 (setq sig-list (cdr sig-list))))
12775 (verilog-insert-indent "// End of automatics\n")))))
12777 (defun verilog-enum-ascii (signm elim-regexp)
12778 "Convert an enum name SIGNM to an ascii string for insertion.
12779 Remove user provided prefix ELIM-REGEXP."
12780 (or elim-regexp (setq elim-regexp "_ DONT MATCH IT_"))
12781 (let ((case-fold-search t))
12782 ;; All upper becomes all lower for readability
12783 (downcase (verilog-string-replace-matches elim-regexp "" nil nil signm))))
12785 (defun verilog-auto-ascii-enum ()
12786 "Expand AUTOASCIIENUM statements, as part of \\[verilog-auto].
12787 Create a register to contain the ASCII decode of an enumerated signal type.
12788 This will allow trace viewers to show the ASCII name of states.
12790 First, parameters are built into an enumeration using the synopsys enum
12791 comment. The comment must be between the keyword and the symbol.
12792 \(Annoying, but that's what Synopsys's dc_shell FSM reader requires.)
12794 Next, registers which that enum applies to are also tagged with the same
12797 Finally, an AUTOASCIIENUM command is used.
12799 The first parameter is the name of the signal to be decoded.
12801 The second parameter is the name to store the ASCII code into. For the
12802 signal foo, I suggest the name _foo__ascii, where the leading _ indicates
12803 a signal that is just for simulation, and the magic characters _ascii
12804 tell viewers like Dinotrace to display in ASCII format.
12806 The third optional parameter is a string which will be removed
12807 from the state names. It defaults to \"\" which removes nothing.
12809 The fourth optional parameter is \"onehot\" to force one-hot
12810 decoding. If unspecified, if and only if the first parameter
12811 width is 2^(number of states in enum) and does NOT match the
12812 width of the enum, the signal is assumed to be a one-hot
12813 decode. Otherwise, it's a normal encoded state vector.
12815 `verilog-auto-wire-type' may be used to change the datatype of
12818 \"auto enum\" may be used in place of \"synopsys enum\".
12822 //== State enumeration
12823 parameter [2:0] // synopsys enum state_info
12827 //== State variables
12828 reg [2:0] /* synopsys enum state_info */
12829 state_r; /* synopsys state_vector state_r */
12830 reg [2:0] /* synopsys enum state_info */
12833 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
12835 Typing \\[verilog-auto] will make this into:
12837 ... same front matter ...
12839 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
12840 // Beginning of automatic ASCII enum decoding
12841 reg [39:0] state_ascii_r; // Decode of state_r
12842 always @(state_r) begin
12844 SM_IDLE: state_ascii_r = \"idle \";
12845 SM_SEND: state_ascii_r = \"send \";
12846 SM_WAIT1: state_ascii_r = \"wait1\";
12847 default: state_ascii_r = \"%Erro\";
12850 // End of automatics"
12852 (let* ((params (verilog-read-auto-params 2 4))
12853 (undecode-name (nth 0 params))
12854 (ascii-name (nth 1 params))
12855 (elim-regexp (and (nth 2 params)
12856 (not (equal (nth 2 params) ""))
12858 (one-hot-flag (nth 3 params))
12860 (indent-pt (current-indentation))
12861 (modi (verilog-modi-current))
12862 (moddecls (verilog-modi-get-decls modi))
12864 (sig-list-consts (append (verilog-decls-get-consts moddecls)
12865 (verilog-decls-get-gparams moddecls)))
12866 (sig-list-all (verilog-decls-get-iovars moddecls))
12868 (undecode-sig (or (assoc undecode-name sig-list-all)
12869 (error "%s: Signal %s not found in design" (verilog-point-text) undecode-name)))
12870 (undecode-enum (or (verilog-sig-enum undecode-sig)
12871 (error "%s: Signal %s does not have an enum tag" (verilog-point-text) undecode-name)))
12873 (enum-sigs (verilog-signals-not-in
12874 (or (verilog-signals-matching-enum sig-list-consts undecode-enum)
12875 (error "%s: No state definitions for %s" (verilog-point-text) undecode-enum))
12879 (string-match "onehot" (or one-hot-flag ""))
12880 (and ;; width(enum) != width(sig)
12881 (or (not (verilog-sig-bits (car enum-sigs)))
12882 (not (equal (verilog-sig-width (car enum-sigs))
12883 (verilog-sig-width undecode-sig))))
12884 ;; count(enums) == width(sig)
12885 (equal (number-to-string (length enum-sigs))
12886 (verilog-sig-width undecode-sig)))))
12890 ;; Find number of ascii chars needed
12891 (let ((tmp-sigs enum-sigs))
12893 (setq enum-chars (max enum-chars (length (verilog-sig-name (car tmp-sigs))))
12894 ascii-chars (max ascii-chars (length (verilog-enum-ascii
12895 (verilog-sig-name (car tmp-sigs))
12897 tmp-sigs (cdr tmp-sigs))))
12899 (verilog-forward-or-insert-line)
12900 (verilog-insert-indent "// Beginning of automatic ASCII enum decoding\n")
12901 (let ((decode-sig-list (list (list ascii-name (format "[%d:0]" (- (* ascii-chars 8) 1))
12902 (concat "Decode of " undecode-name) nil nil))))
12903 (verilog-insert-definition modi decode-sig-list "reg" indent-pt nil))
12905 (verilog-insert-indent "always @(" undecode-name ") begin\n")
12906 (setq indent-pt (+ indent-pt verilog-indent-level))
12907 (verilog-insert-indent "case ({" undecode-name "})\n")
12908 (setq indent-pt (+ indent-pt verilog-case-indent))
12910 (let ((tmp-sigs enum-sigs)
12911 (chrfmt (format "%%-%ds %s = \"%%-%ds\";\n"
12912 (+ (if one-hot 9 1) (max 8 enum-chars))
12913 ascii-name ascii-chars))
12914 (errname (substring "%Error" 0 (min 6 ascii-chars))))
12916 (verilog-insert-indent
12919 (concat (if one-hot "(")
12920 ;; Use enum-sigs length as that's numeric
12921 ;; verilog-sig-width undecode-sig might not be.
12922 (if one-hot (number-to-string (length enum-sigs)))
12923 ;; We use a shift instead of var[index]
12924 ;; so that a non-one hot value will show as error.
12925 (if one-hot "'b1<<")
12926 (verilog-sig-name (car tmp-sigs))
12927 (if one-hot ")") ":")
12928 (verilog-enum-ascii (verilog-sig-name (car tmp-sigs))
12930 (setq tmp-sigs (cdr tmp-sigs)))
12931 (verilog-insert-indent (format chrfmt "default:" errname)))
12933 (setq indent-pt (- indent-pt verilog-case-indent))
12934 (verilog-insert-indent "endcase\n")
12935 (setq indent-pt (- indent-pt verilog-indent-level))
12936 (verilog-insert-indent "end\n"
12937 "// End of automatics\n"))))
12939 (defun verilog-auto-templated-rel ()
12940 "Replace Templated relative line numbers with absolute line numbers.
12941 Internal use only. This hacks around the line numbers in AUTOINST Templates
12942 being different from the final output's line numbering."
12943 (let ((templateno 0) (template-line (list 0)) (buf-line 1))
12944 ;; Find line number each template is on
12945 ;; Count lines as we go, as otherwise it's O(n^2) to use count-lines
12946 (goto-char (point-min))
12947 (while (not (eobp))
12948 (when (looking-at ".*AUTO_TEMPLATE")
12949 (setq templateno (1+ templateno))
12950 (setq template-line (cons buf-line template-line)))
12951 (setq buf-line (1+ buf-line))
12953 (setq template-line (nreverse template-line))
12954 ;; Replace T# L# with absolute line number
12955 (goto-char (point-min))
12956 (while (re-search-forward " Templated T\\([0-9]+\\) L\\([0-9]+\\)" nil t)
12958 (concat " Templated "
12959 (int-to-string (+ (nth (string-to-number (match-string 1))
12961 (string-to-number (match-string 2)))))
12964 (defun verilog-auto-template-lint ()
12965 "Check AUTO_TEMPLATEs for unused lines.
12966 Enable with `verilog-auto-template-warn-unused'."
12967 (let ((name1 (or (buffer-file-name) (buffer-name))))
12969 (goto-char (point-min))
12970 (while (re-search-forward
12971 "^\\s-*/?\\*?\\s-*[a-zA-Z0-9`_$]+\\s-+AUTO_TEMPLATE" nil t)
12972 (let* ((tpl-info (verilog-read-auto-template-middle))
12973 (tpl-list (aref tpl-info 1))
12974 (tlines (append (nth 0 tpl-list) (nth 1 tpl-list)))
12977 (setq tpl-ass (car tlines)
12978 tlines (cdr tlines))
12980 (unless (or (not (eval-when-compile (fboundp 'make-hash-table))) ;; Not supported, no warning
12981 (not verilog-auto-template-hits)
12982 (gethash (vector (nth 2 tpl-ass) (nth 3 tpl-ass))
12983 verilog-auto-template-hits))
12984 (verilog-warn-error "%s:%d: AUTO_TEMPLATE line unused: \".%s (%s)\""
12986 (+ (elt tpl-ass 3) ;; Template line number
12987 (count-lines (point-min) (point)))
12988 (elt tpl-ass 0) (elt tpl-ass 1))
12996 (defun verilog-auto (&optional inject) ; Use verilog-inject-auto instead of passing an arg
12997 "Expand AUTO statements.
12998 Look for any /*AUTO...*/ commands in the code, as used in
12999 instantiations or argument headers. Update the list of signals
13000 following the /*AUTO...*/ command.
13002 Use \\[verilog-delete-auto] to remove the AUTOs.
13004 Use \\[verilog-diff-auto] to see differences in AUTO expansion.
13006 Use \\[verilog-inject-auto] to insert AUTOs for the first time.
13008 Use \\[verilog-faq] for a pointer to frequently asked questions.
13010 The hooks `verilog-before-auto-hook' and `verilog-auto-hook' are
13011 called before and after this function, respectively.
13014 module ModuleName (/*AUTOARG*/);
13019 InstMod instName #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);
13021 You can also update the AUTOs from the shell using:
13022 emacs --batch <filenames.v> -f verilog-batch-auto
13023 Or fix indentation with:
13024 emacs --batch <filenames.v> -f verilog-batch-indent
13025 Likewise, you can delete or inject AUTOs with:
13026 emacs --batch <filenames.v> -f verilog-batch-delete-auto
13027 emacs --batch <filenames.v> -f verilog-batch-inject-auto
13028 Or check if AUTOs have the same expansion
13029 emacs --batch <filenames.v> -f verilog-batch-diff-auto
13031 Using \\[describe-function], see also:
13032 `verilog-auto-arg' for AUTOARG module instantiations
13033 `verilog-auto-ascii-enum' for AUTOASCIIENUM enumeration decoding
13034 `verilog-auto-assign-modport' for AUTOASSIGNMODPORT assignment to/from modport
13035 `verilog-auto-inout-comp' for AUTOINOUTCOMP copy complemented i/o
13036 `verilog-auto-inout-in' for AUTOINOUTIN inputs for all i/o
13037 `verilog-auto-inout-modport' for AUTOINOUTMODPORT i/o from an interface modport
13038 `verilog-auto-inout-module' for AUTOINOUTMODULE copying i/o from elsewhere
13039 `verilog-auto-inout-param' for AUTOINOUTPARAM copying params from elsewhere
13040 `verilog-auto-inout' for AUTOINOUT making hierarchy inouts
13041 `verilog-auto-input' for AUTOINPUT making hierarchy inputs
13042 `verilog-auto-insert-lisp' for AUTOINSERTLISP insert code from lisp function
13043 `verilog-auto-inst' for AUTOINST instantiation pins
13044 `verilog-auto-star' for AUTOINST .* SystemVerilog pins
13045 `verilog-auto-inst-param' for AUTOINSTPARAM instantiation params
13046 `verilog-auto-logic' for AUTOLOGIC declaring logic signals
13047 `verilog-auto-output' for AUTOOUTPUT making hierarchy outputs
13048 `verilog-auto-output-every' for AUTOOUTPUTEVERY making all outputs
13049 `verilog-auto-reg' for AUTOREG registers
13050 `verilog-auto-reg-input' for AUTOREGINPUT instantiation registers
13051 `verilog-auto-reset' for AUTORESET flop resets
13052 `verilog-auto-sense' for AUTOSENSE always sensitivity lists
13053 `verilog-auto-tieoff' for AUTOTIEOFF output tieoffs
13054 `verilog-auto-undef' for AUTOUNDEF `undef of local `defines
13055 `verilog-auto-unused' for AUTOUNUSED unused inputs/inouts
13056 `verilog-auto-wire' for AUTOWIRE instantiation wires
13058 `verilog-read-defines' for reading `define values
13059 `verilog-read-includes' for reading `includes
13061 If you have bugs with these autos, please file an issue at
13062 URL `http://www.veripool.org/verilog-mode' or contact the AUTOAUTHOR
13063 Wilson Snyder (wsnyder@wsnyder.org)."
13065 (unless noninteractive (message "Updating AUTOs..."))
13066 (if (fboundp 'dinotrace-unannotate-all)
13067 (dinotrace-unannotate-all))
13068 (verilog-save-font-mods
13069 (let ((oldbuf (if (not (buffer-modified-p))
13071 ;; Cache directories; we don't write new files, so can't change
13072 (verilog-dir-cache-preserving t)
13073 ;; Cache current module
13074 (verilog-modi-cache-current-enable t)
13075 (verilog-modi-cache-current-max (point-min)) ; IE it's invalid
13076 verilog-modi-cache-current)
13078 ;; Disable change hooks for speed
13079 ;; This let can't be part of above let; must restore
13080 ;; after-change-functions before font-lock resumes
13081 (verilog-save-no-change-functions
13082 (verilog-save-scan-cache
13084 ;; Wipe cache; otherwise if we AUTOed a block above this one,
13085 ;; we'll misremember we have generated IOs, confusing AUTOOUTPUT
13086 (setq verilog-modi-cache-list nil)
13088 (setq verilog-auto-template-hits nil)
13089 ;; If we're not in verilog-mode, change syntax table so parsing works right
13090 (unless (eq major-mode `verilog-mode) (verilog-mode))
13091 ;; Allow user to customize
13092 (verilog-run-hooks 'verilog-before-auto-hook)
13093 ;; Try to save the user from needing to revert-file to reread file local-variables
13094 (verilog-auto-reeval-locals)
13095 (verilog-read-auto-lisp-present)
13096 (verilog-read-auto-lisp (point-min) (point-max))
13097 (verilog-getopt-flags)
13098 ;; From here on out, we can cache anything we read from disk
13099 (verilog-preserve-dir-cache
13100 ;; These two may seem obvious to do always, but on large includes it can be way too slow
13101 (when verilog-auto-read-includes
13102 (verilog-read-includes)
13103 (verilog-read-defines nil nil t))
13104 ;; Setup variables due to SystemVerilog expansion
13105 (verilog-auto-re-search-do "/\\*AUTOLOGIC\\*/" 'verilog-auto-logic-setup)
13106 ;; This particular ordering is important
13107 ;; INST: Lower modules correct, no internal dependencies, FIRST
13108 (verilog-preserve-modi-cache
13109 ;; Clear existing autos else we'll be screwed by existing ones
13110 (verilog-delete-auto)
13111 ;; Injection if appropriate
13113 (verilog-inject-inst)
13114 (verilog-inject-sense)
13115 (verilog-inject-arg))
13117 ;; Do user inserts first, so their code can insert AUTOs
13118 ;; We may provide an AUTOINSERTLISPLAST if another cleanup pass is needed
13119 (verilog-auto-re-search-do "/\\*AUTOINSERTLISP(.*?)\\*/"
13120 'verilog-auto-insert-lisp)
13121 ;; Expand instances before need the signals the instances input/output
13122 (verilog-auto-re-search-do "/\\*AUTOINSTPARAM\\*/" 'verilog-auto-inst-param)
13123 (verilog-auto-re-search-do "/\\*AUTOINST\\*/" 'verilog-auto-inst)
13124 (verilog-auto-re-search-do "\\.\\*" 'verilog-auto-star)
13125 ;; Doesn't matter when done, but combine it with a common changer
13126 (verilog-auto-re-search-do "/\\*\\(AUTOSENSE\\|AS\\)\\*/" 'verilog-auto-sense)
13127 (verilog-auto-re-search-do "/\\*AUTORESET\\*/" 'verilog-auto-reset)
13128 ;; Must be done before autoin/out as creates a reg
13129 (verilog-auto-re-search-do "/\\*AUTOASCIIENUM(.*?)\\*/" 'verilog-auto-ascii-enum)
13131 ;; first in/outs from other files
13132 (verilog-auto-re-search-do "/\\*AUTOINOUTMODPORT(.*?)\\*/" 'verilog-auto-inout-modport)
13133 (verilog-auto-re-search-do "/\\*AUTOINOUTMODULE(.*?)\\*/" 'verilog-auto-inout-module)
13134 (verilog-auto-re-search-do "/\\*AUTOINOUTCOMP(.*?)\\*/" 'verilog-auto-inout-comp)
13135 (verilog-auto-re-search-do "/\\*AUTOINOUTIN(.*?)\\*/" 'verilog-auto-inout-in)
13136 (verilog-auto-re-search-do "/\\*AUTOINOUTPARAM(.*?)\\*/" 'verilog-auto-inout-param)
13137 ;; next in/outs which need previous sucked inputs first
13138 (verilog-auto-re-search-do "/\\*AUTOOUTPUT\\((.*?)\\)?\\*/" 'verilog-auto-output)
13139 (verilog-auto-re-search-do "/\\*AUTOINPUT\\((.*?)\\)?\\*/" 'verilog-auto-input)
13140 (verilog-auto-re-search-do "/\\*AUTOINOUT\\((.*?)\\)?\\*/" 'verilog-auto-inout)
13141 ;; Then tie off those in/outs
13142 (verilog-auto-re-search-do "/\\*AUTOTIEOFF\\*/" 'verilog-auto-tieoff)
13143 ;; These can be anywhere after AUTOINSERTLISP
13144 (verilog-auto-re-search-do "/\\*AUTOUNDEF\\((.*?)\\)?\\*/" 'verilog-auto-undef)
13145 ;; Wires/regs must be after inputs/outputs
13146 (verilog-auto-re-search-do "/\\*AUTOASSIGNMODPORT(.*?)\\*/" 'verilog-auto-assign-modport)
13147 (verilog-auto-re-search-do "/\\*AUTOLOGIC\\*/" 'verilog-auto-logic)
13148 (verilog-auto-re-search-do "/\\*AUTOWIRE\\*/" 'verilog-auto-wire)
13149 (verilog-auto-re-search-do "/\\*AUTOREG\\*/" 'verilog-auto-reg)
13150 (verilog-auto-re-search-do "/\\*AUTOREGINPUT\\*/" 'verilog-auto-reg-input)
13151 ;; outputevery needs AUTOOUTPUTs done first
13152 (verilog-auto-re-search-do "/\\*AUTOOUTPUTEVERY\\*/" 'verilog-auto-output-every)
13153 ;; After we've created all new variables
13154 (verilog-auto-re-search-do "/\\*AUTOUNUSED\\*/" 'verilog-auto-unused)
13155 ;; Must be after all inputs outputs are generated
13156 (verilog-auto-re-search-do "/\\*AUTOARG\\*/" 'verilog-auto-arg)
13157 ;; Fix line numbers (comments only)
13158 (when verilog-auto-inst-template-numbers
13159 (verilog-auto-templated-rel))
13160 (when verilog-auto-template-warn-unused
13161 (verilog-auto-template-lint))))
13163 (verilog-run-hooks 'verilog-auto-hook)
13165 (when verilog-auto-delete-trailing-whitespace
13166 (verilog-delete-trailing-whitespace))
13168 (set (make-local-variable 'verilog-auto-update-tick) (buffer-chars-modified-tick))
13170 ;; If end result is same as when started, clear modified flag
13171 (cond ((and oldbuf (equal oldbuf (buffer-string)))
13172 (set-buffer-modified-p nil)
13173 (unless noninteractive (message "Updating AUTOs...done (no changes)")))
13174 (t (unless noninteractive (message "Updating AUTOs...done"))))
13175 ;; End of after-change protection
13178 ;; Currently handled in verilog-save-font-mods
13183 ;; Skeleton based code insertion
13185 (defvar verilog-template-map
13186 (let ((map (make-sparse-keymap)))
13187 (define-key map "a" 'verilog-sk-always)
13188 (define-key map "b" 'verilog-sk-begin)
13189 (define-key map "c" 'verilog-sk-case)
13190 (define-key map "f" 'verilog-sk-for)
13191 (define-key map "g" 'verilog-sk-generate)
13192 (define-key map "h" 'verilog-sk-header)
13193 (define-key map "i" 'verilog-sk-initial)
13194 (define-key map "j" 'verilog-sk-fork)
13195 (define-key map "m" 'verilog-sk-module)
13196 (define-key map "o" 'verilog-sk-ovm-class)
13197 (define-key map "p" 'verilog-sk-primitive)
13198 (define-key map "r" 'verilog-sk-repeat)
13199 (define-key map "s" 'verilog-sk-specify)
13200 (define-key map "t" 'verilog-sk-task)
13201 (define-key map "u" 'verilog-sk-uvm-class)
13202 (define-key map "w" 'verilog-sk-while)
13203 (define-key map "x" 'verilog-sk-casex)
13204 (define-key map "z" 'verilog-sk-casez)
13205 (define-key map "?" 'verilog-sk-if)
13206 (define-key map ":" 'verilog-sk-else-if)
13207 (define-key map "/" 'verilog-sk-comment)
13208 (define-key map "A" 'verilog-sk-assign)
13209 (define-key map "F" 'verilog-sk-function)
13210 (define-key map "I" 'verilog-sk-input)
13211 (define-key map "O" 'verilog-sk-output)
13212 (define-key map "S" 'verilog-sk-state-machine)
13213 (define-key map "=" 'verilog-sk-inout)
13214 (define-key map "W" 'verilog-sk-wire)
13215 (define-key map "R" 'verilog-sk-reg)
13216 (define-key map "D" 'verilog-sk-define-signal)
13218 "Keymap used in Verilog mode for smart template operations.")
13222 ;; Place the templates into Verilog Mode. They may be inserted under any key.
13223 ;; C-c C-t will be the default. If you use templates a lot, you
13224 ;; may want to consider moving the binding to another key in your init
13227 ;; Note \C-c and letter are reserved for users
13228 (define-key verilog-mode-map "\C-c\C-t" verilog-template-map)
13230 ;;; ---- statement skeletons ------------------------------------------
13232 (define-skeleton verilog-sk-prompt-condition
13233 "Prompt for the loop condition."
13234 "[condition]: " str )
13236 (define-skeleton verilog-sk-prompt-init
13237 "Prompt for the loop init statement."
13238 "[initial statement]: " str )
13240 (define-skeleton verilog-sk-prompt-inc
13241 "Prompt for the loop increment statement."
13242 "[increment statement]: " str )
13244 (define-skeleton verilog-sk-prompt-name
13245 "Prompt for the name of something."
13248 (define-skeleton verilog-sk-prompt-clock
13249 "Prompt for the name of something."
13250 "name and edge of clock(s): " str)
13252 (defvar verilog-sk-reset nil)
13253 (defun verilog-sk-prompt-reset ()
13254 "Prompt for the name of a state machine reset."
13255 (setq verilog-sk-reset (read-string "name of reset: " "rst")))
13258 (define-skeleton verilog-sk-prompt-state-selector
13259 "Prompt for the name of a state machine selector."
13260 "name of selector (eg {a,b,c,d}): " str )
13262 (define-skeleton verilog-sk-prompt-output
13263 "Prompt for the name of something."
13266 (define-skeleton verilog-sk-prompt-msb
13267 "Prompt for most significant bit specification."
13268 "msb:" str & ?: & '(verilog-sk-prompt-lsb) | -1 )
13270 (define-skeleton verilog-sk-prompt-lsb
13271 "Prompt for least significant bit specification."
13274 (defvar verilog-sk-p nil)
13275 (define-skeleton verilog-sk-prompt-width
13276 "Prompt for a width specification."
13279 (setq verilog-sk-p (point))
13280 (verilog-sk-prompt-msb)
13281 (if (> (point) verilog-sk-p) "] " " ")))
13283 (defun verilog-sk-header ()
13284 "Insert a descriptive header at the top of the file.
13285 See also `verilog-header' for an alternative format."
13288 (goto-char (point-min))
13289 (verilog-sk-header-tmpl)))
13291 (define-skeleton verilog-sk-header-tmpl
13292 "Insert a comment block containing the module title, author, etc."
13294 "// -*- Mode: Verilog -*-"
13295 "\n// Filename : " (buffer-name)
13296 "\n// Description : " str
13297 "\n// Author : " (user-full-name)
13298 "\n// Created On : " (current-time-string)
13299 "\n// Last Modified By: " (user-full-name)
13300 "\n// Last Modified On: " (current-time-string)
13301 "\n// Update Count : 0"
13302 "\n// Status : Unknown, Use with caution!"
13305 (define-skeleton verilog-sk-module
13306 "Insert a module definition."
13308 > "module " '(verilog-sk-prompt-name) " (/*AUTOARG*/ ) ;" \n
13310 > (- verilog-indent-level-behavioral) "endmodule" (progn (electric-verilog-terminate-line) nil))
13312 ;;; ------------------------------------------------------------------------
13313 ;;; Define a default OVM class, with macros and new()
13314 ;;; ------------------------------------------------------------------------
13316 (define-skeleton verilog-sk-ovm-class
13317 "Insert a class definition"
13319 > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n
13321 > "`ovm_object_utils_begin(" name ")" \n
13322 > (- verilog-indent-level) " `ovm_object_utils_end" \n
13324 > "function new(name=\"" name "\");" \n
13325 > "super.new(name);" \n
13326 > (- verilog-indent-level) "endfunction" \n
13328 > "endclass" (progn (electric-verilog-terminate-line) nil))
13330 (define-skeleton verilog-sk-uvm-class
13331 "Insert a class definition"
13333 > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n
13335 > "`uvm_object_utils_begin(" name ")" \n
13336 > (- verilog-indent-level) " `uvm_object_utils_end" \n
13338 > "function new(name=\"" name "\");" \n
13339 > "super.new(name);" \n
13340 > (- verilog-indent-level) "endfunction" \n
13342 > "endclass" (progn (electric-verilog-terminate-line) nil))
13344 (define-skeleton verilog-sk-primitive
13345 "Insert a task definition."
13347 > "primitive " '(verilog-sk-prompt-name) " ( " '(verilog-sk-prompt-output) ("input:" ", " str ) " );"\n
13349 > (- verilog-indent-level-behavioral) "endprimitive" (progn (electric-verilog-terminate-line) nil))
13351 (define-skeleton verilog-sk-task
13352 "Insert a task definition."
13354 > "task " '(verilog-sk-prompt-name) & ?; \n
13358 > (- verilog-indent-level-behavioral) "end" \n
13359 > (- verilog-indent-level-behavioral) "endtask" (progn (electric-verilog-terminate-line) nil))
13361 (define-skeleton verilog-sk-function
13362 "Insert a function definition."
13364 > "function [" '(verilog-sk-prompt-width) | -1 '(verilog-sk-prompt-name) ?; \n
13368 > (- verilog-indent-level-behavioral) "end" \n
13369 > (- verilog-indent-level-behavioral) "endfunction" (progn (electric-verilog-terminate-line) nil))
13371 (define-skeleton verilog-sk-always
13372 "Insert always block. Uses the minibuffer to prompt
13373 for sensitivity list."
13375 > "always @ ( /*AUTOSENSE*/ ) begin\n"
13377 > (- verilog-indent-level-behavioral) "end" \n >
13380 (define-skeleton verilog-sk-initial
13381 "Insert an initial block."
13383 > "initial begin\n"
13385 > (- verilog-indent-level-behavioral) "end" \n > )
13387 (define-skeleton verilog-sk-specify
13388 "Insert specify block. "
13392 > (- verilog-indent-level-behavioral) "endspecify" \n > )
13394 (define-skeleton verilog-sk-generate
13395 "Insert generate block. "
13399 > (- verilog-indent-level-behavioral) "endgenerate" \n > )
13401 (define-skeleton verilog-sk-begin
13402 "Insert begin end block. Uses the minibuffer to prompt for name."
13404 > "begin" '(verilog-sk-prompt-name) \n
13406 > (- verilog-indent-level-behavioral) "end"
13409 (define-skeleton verilog-sk-fork
13410 "Insert a fork join block."
13415 > (- verilog-indent-level-behavioral) "end" \n
13418 > (- verilog-indent-level-behavioral) "end" \n
13419 > (- verilog-indent-level-behavioral) "join" \n
13423 (define-skeleton verilog-sk-case
13424 "Build skeleton case statement, prompting for the selector expression,
13425 and the case items."
13426 "[selector expression]: "
13427 > "case (" str ") " \n
13428 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
13429 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
13431 (define-skeleton verilog-sk-casex
13432 "Build skeleton casex statement, prompting for the selector expression,
13433 and the case items."
13434 "[selector expression]: "
13435 > "casex (" str ") " \n
13436 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
13437 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
13439 (define-skeleton verilog-sk-casez
13440 "Build skeleton casez statement, prompting for the selector expression,
13441 and the case items."
13442 "[selector expression]: "
13443 > "casez (" str ") " \n
13444 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
13445 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
13447 (define-skeleton verilog-sk-if
13448 "Insert a skeleton if statement."
13449 > "if (" '(verilog-sk-prompt-condition) & ")" " begin" \n
13451 > (- verilog-indent-level-behavioral) "end " \n )
13453 (define-skeleton verilog-sk-else-if
13454 "Insert a skeleton else if statement."
13455 > (verilog-indent-line) "else if ("
13456 (progn (setq verilog-sk-p (point)) nil) '(verilog-sk-prompt-condition) (if (> (point) verilog-sk-p) ") " -1 ) & " begin" \n
13458 > "end" (progn (electric-verilog-terminate-line) nil))
13460 (define-skeleton verilog-sk-datadef
13461 "Common routine to get data definition."
13463 '(verilog-sk-prompt-width) | -1 ("name (RET to end):" str ", ") -2 ";" \n)
13465 (define-skeleton verilog-sk-input
13466 "Insert an input definition."
13468 > "input [" '(verilog-sk-datadef))
13470 (define-skeleton verilog-sk-output
13471 "Insert an output definition."
13473 > "output [" '(verilog-sk-datadef))
13475 (define-skeleton verilog-sk-inout
13476 "Insert an inout definition."
13478 > "inout [" '(verilog-sk-datadef))
13480 (defvar verilog-sk-signal nil)
13481 (define-skeleton verilog-sk-def-reg
13482 "Insert a reg definition."
13484 > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-signal ";" \n (verilog-pretty-declarations-auto) )
13486 (defun verilog-sk-define-signal ()
13487 "Insert a definition of signal under point at top of module."
13489 (let* ((sig-re "[a-zA-Z0-9_]*")
13490 (v1 (buffer-substring
13492 (skip-chars-backward sig-re)
13495 (skip-chars-forward sig-re)
13497 (if (not (member v1 verilog-keywords))
13499 (setq verilog-sk-signal v1)
13500 (verilog-beg-of-defun)
13501 (verilog-end-of-statement)
13502 (verilog-forward-syntactic-ws)
13503 (verilog-sk-def-reg)
13504 (message "signal at point is %s" v1))
13505 (message "object at point (%s) is a keyword" v1))))
13507 (define-skeleton verilog-sk-wire
13508 "Insert a wire definition."
13510 > "wire [" '(verilog-sk-datadef))
13512 (define-skeleton verilog-sk-reg
13513 "Insert a reg definition."
13515 > "reg [" '(verilog-sk-datadef))
13517 (define-skeleton verilog-sk-assign
13518 "Insert a skeleton assign statement."
13520 > "assign " '(verilog-sk-prompt-name) " = " _ ";" \n)
13522 (define-skeleton verilog-sk-while
13523 "Insert a skeleton while loop statement."
13525 > "while (" '(verilog-sk-prompt-condition) ") begin" \n
13527 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
13529 (define-skeleton verilog-sk-repeat
13530 "Insert a skeleton repeat loop statement."
13532 > "repeat (" '(verilog-sk-prompt-condition) ") begin" \n
13534 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
13536 (define-skeleton verilog-sk-for
13537 "Insert a skeleton while loop statement."
13540 '(verilog-sk-prompt-init) "; "
13541 '(verilog-sk-prompt-condition) "; "
13542 '(verilog-sk-prompt-inc)
13545 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
13547 (define-skeleton verilog-sk-comment
13548 "Inserts three comment lines, making a display comment."
13554 (define-skeleton verilog-sk-state-machine
13555 "Insert a state machine definition."
13556 "Name of state variable: "
13557 '(setq input "state")
13558 > "// State registers for " str | -23 \n
13559 '(setq verilog-sk-state str)
13560 > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-state ", next_" verilog-sk-state ?; \n
13563 > "// State FF for " verilog-sk-state \n
13564 > "always @ ( " (read-string "clock:" "posedge clk") " or " (verilog-sk-prompt-reset) " ) begin" \n
13565 > "if ( " verilog-sk-reset " ) " verilog-sk-state " = 0; else" \n
13566 > verilog-sk-state " = next_" verilog-sk-state ?; \n
13567 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil)
13569 > "// Next State Logic for " verilog-sk-state \n
13570 > "always @ ( /*AUTOSENSE*/ ) begin\n"
13571 > "case (" '(verilog-sk-prompt-state-selector) ") " \n
13572 > ("case selector: " str ": begin" \n > "next_" verilog-sk-state " = " _ ";" \n > (- verilog-indent-level-behavioral) "end" \n )
13573 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil)
13574 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil))
13578 ;; Include file loading with mouse/return event
13580 ;; idea & first impl.: M. Rouat (eldo-mode.el)
13581 ;; second (emacs/xemacs) impl.: G. Van der Plas (spice-mode.el)
13583 (if (featurep 'xemacs)
13584 (require 'overlay))
13586 (defconst verilog-include-file-regexp
13587 "^`include\\s-+\"\\([^\n\"]*\\)\""
13588 "Regexp that matches the include file.")
13590 (defvar verilog-mode-mouse-map
13591 (let ((map (make-sparse-keymap))) ; as described in info pages, make a map
13592 (set-keymap-parent map verilog-mode-map)
13593 ;; mouse button bindings
13594 (define-key map "\r" 'verilog-load-file-at-point)
13595 (if (featurep 'xemacs)
13596 (define-key map 'button2 'verilog-load-file-at-mouse);ffap-at-mouse ?
13597 (define-key map [mouse-2] 'verilog-load-file-at-mouse))
13598 (if (featurep 'xemacs)
13599 (define-key map 'Sh-button2 'mouse-yank) ; you wanna paste don't you ?
13600 (define-key map [S-mouse-2] 'mouse-yank-at-click))
13602 "Map containing mouse bindings for `verilog-mode'.")
13605 (defun verilog-highlight-region (beg end old-len)
13606 "Colorize included files and modules in the (changed?) region.
13607 Clicking on the middle-mouse button loads them in a buffer (as in dired)."
13608 (when (or verilog-highlight-includes
13609 verilog-highlight-modules)
13611 (save-match-data ;; A query-replace may call this function - do not disturb
13612 (verilog-save-buffer-state
13613 (verilog-save-scan-cache
13616 (setq end-point (point-at-eol))
13618 (beginning-of-line) ; scan entire line
13619 ;; delete overlays existing on this line
13620 (let ((overlays (overlays-in (point) end-point)))
13623 (overlay-get (car overlays) 'detachable)
13624 (or (overlay-get (car overlays) 'verilog-include-file)
13625 (overlay-get (car overlays) 'verilog-inst-module)))
13626 (delete-overlay (car overlays)))
13627 (setq overlays (cdr overlays))))
13629 ;; make new include overlays
13630 (when verilog-highlight-includes
13631 (while (search-forward-regexp verilog-include-file-regexp end-point t)
13632 (goto-char (match-beginning 1))
13633 (let ((ov (make-overlay (match-beginning 1) (match-end 1))))
13634 (overlay-put ov 'start-closed 't)
13635 (overlay-put ov 'end-closed 't)
13636 (overlay-put ov 'evaporate 't)
13637 (overlay-put ov 'verilog-include-file 't)
13638 (overlay-put ov 'mouse-face 'highlight)
13639 (overlay-put ov 'local-map verilog-mode-mouse-map))))
13641 ;; make new module overlays
13643 ;; This scanner is syntax-fragile, so don't get bent
13644 (when verilog-highlight-modules
13645 (condition-case nil
13646 (while (verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-point t)
13648 (goto-char (match-beginning 0))
13649 (unless (verilog-inside-comment-or-string-p)
13650 (verilog-read-inst-module-matcher) ;; sets match 0
13651 (let* ((ov (make-overlay (match-beginning 0) (match-end 0))))
13652 (overlay-put ov 'start-closed 't)
13653 (overlay-put ov 'end-closed 't)
13654 (overlay-put ov 'evaporate 't)
13655 (overlay-put ov 'verilog-inst-module 't)
13656 (overlay-put ov 'mouse-face 'highlight)
13657 (overlay-put ov 'local-map verilog-mode-mouse-map)))))
13660 ;; Future highlights:
13661 ;; variables - make an Occur buffer of where referenced
13662 ;; pins - make an Occur buffer of the sig in the declaration module
13665 (defun verilog-highlight-buffer ()
13666 "Colorize included files and modules across the whole buffer."
13667 ;; Invoked via verilog-mode calling font-lock then `font-lock-mode-hook'
13669 ;; delete and remake overlays
13670 (verilog-highlight-region (point-min) (point-max) nil))
13672 ;; Deprecated, but was interactive, so we'll keep it around
13673 (defalias 'verilog-colorize-include-files-buffer 'verilog-highlight-buffer)
13675 ;; ffap-at-mouse isn't useful for Verilog mode. It uses library paths.
13676 ;; so define this function to do more or less the same as ffap-at-mouse
13677 ;; but first resolve filename...
13678 (defun verilog-load-file-at-mouse (event)
13679 "Load file under button 2 click's EVENT.
13680 Files are checked based on `verilog-library-flags'."
13682 (save-excursion ;; implement a Verilog specific ffap-at-mouse
13683 (mouse-set-point event)
13684 (verilog-load-file-at-point t)))
13686 ;; ffap isn't usable for Verilog mode. It uses library paths.
13687 ;; so define this function to do more or less the same as ffap
13688 ;; but first resolve filename...
13689 (defun verilog-load-file-at-point (&optional warn)
13690 "Load file under point.
13691 If WARN, throw warning if not found.
13692 Files are checked based on `verilog-library-flags'."
13694 (save-excursion ;; implement a Verilog specific ffap
13695 (let ((overlays (overlays-in (point) (point)))
13697 (while (and overlays (not hit))
13698 (when (overlay-get (car overlays) 'verilog-inst-module)
13699 (verilog-goto-defun-file (buffer-substring
13700 (overlay-start (car overlays))
13701 (overlay-end (car overlays))))
13703 (setq overlays (cdr overlays)))
13705 (beginning-of-line)
13706 (when (and (not hit)
13707 (looking-at verilog-include-file-regexp))
13708 (if (and (car (verilog-library-filenames
13709 (match-string 1) (buffer-file-name)))
13710 (file-readable-p (car (verilog-library-filenames
13711 (match-string 1) (buffer-file-name)))))
13712 (find-file (car (verilog-library-filenames
13713 (match-string 1) (buffer-file-name))))
13716 "File '%s' isn't readable, use shift-mouse2 to paste in this field"
13717 (match-string 1))))))))
13723 (defun verilog-faq ()
13724 "Tell the user their current version, and where to get the FAQ etc."
13726 (with-output-to-temp-buffer "*verilog-mode help*"
13727 (princ (format "You are using verilog-mode %s\n" verilog-mode-version))
13729 (princ "For new releases, see http://www.verilog.com\n")
13731 (princ "For frequently asked questions, see http://www.veripool.org/verilog-mode-faq.html\n")
13733 (princ "To submit a bug, use M-x verilog-submit-bug-report\n")
13736 (autoload 'reporter-submit-bug-report "reporter")
13737 (defvar reporter-prompt-for-summary-p)
13739 (defun verilog-submit-bug-report ()
13740 "Submit via mail a bug report on verilog-mode.el."
13742 (let ((reporter-prompt-for-summary-p t))
13743 (reporter-submit-bug-report
13744 "mac@verilog.com, wsnyder@wsnyder.org"
13745 (concat "verilog-mode v" verilog-mode-version)
13747 verilog-active-low-regexp
13748 verilog-after-save-font-hook
13749 verilog-align-ifelse
13750 verilog-assignment-delay
13751 verilog-auto-arg-sort
13752 verilog-auto-declare-nettype
13753 verilog-auto-delete-trailing-whitespace
13754 verilog-auto-endcomments
13756 verilog-auto-ignore-concat
13757 verilog-auto-indent-on-newline
13758 verilog-auto-inout-ignore-regexp
13759 verilog-auto-input-ignore-regexp
13760 verilog-auto-inst-column
13761 verilog-auto-inst-dot-name
13762 verilog-auto-inst-interfaced-ports
13763 verilog-auto-inst-param-value
13764 verilog-auto-inst-sort
13765 verilog-auto-inst-template-numbers
13766 verilog-auto-inst-vector
13767 verilog-auto-lineup
13768 verilog-auto-newline
13769 verilog-auto-output-ignore-regexp
13770 verilog-auto-read-includes
13771 verilog-auto-reset-blocking-in-non
13772 verilog-auto-reset-widths
13773 verilog-auto-save-policy
13774 verilog-auto-sense-defines-constant
13775 verilog-auto-sense-include-inputs
13776 verilog-auto-star-expand
13777 verilog-auto-star-save
13778 verilog-auto-template-warn-unused
13779 verilog-auto-tieoff-declaration
13780 verilog-auto-tieoff-ignore-regexp
13781 verilog-auto-unused-ignore-regexp
13782 verilog-auto-wire-type
13783 verilog-before-auto-hook
13784 verilog-before-delete-auto-hook
13785 verilog-before-getopt-flags-hook
13786 verilog-before-save-font-hook
13787 verilog-cache-enabled
13788 verilog-case-indent
13789 verilog-cexp-indent
13792 verilog-delete-auto-hook
13793 verilog-getopt-flags-hook
13794 verilog-highlight-grouping-keywords
13795 verilog-highlight-includes
13796 verilog-highlight-modules
13797 verilog-highlight-p1800-keywords
13798 verilog-highlight-translate-off
13799 verilog-indent-begin-after-if
13800 verilog-indent-declaration-macros
13801 verilog-indent-level
13802 verilog-indent-level-behavioral
13803 verilog-indent-level-declaration
13804 verilog-indent-level-directive
13805 verilog-indent-level-module
13806 verilog-indent-lists
13807 verilog-library-directories
13808 verilog-library-extensions
13809 verilog-library-files
13810 verilog-library-flags
13812 verilog-minimum-comment-distance
13814 verilog-mode-release-date
13815 verilog-mode-release-emacs
13816 verilog-mode-version
13817 verilog-preprocessor
13819 verilog-tab-always-indent
13820 verilog-tab-to-comment
13821 verilog-typedef-regexp
13827 I want to report a bug.
13829 Before I go further, I want to say that Verilog mode has changed my life.
13830 I save so much time, my files are colored nicely, my co workers respect
13831 my coding ability... until now. I'd really appreciate anything you
13832 could do to help me out with this minor deficiency in the product.
13834 I've taken a look at the Verilog-Mode FAQ at
13835 http://www.veripool.org/verilog-mode-faq.html.
13837 And, I've considered filing the bug on the issue tracker at
13838 http://www.veripool.org/verilog-mode-bugs
13839 since I realize that public bugs are easier for you to track,
13840 and for others to search, but would prefer to email.
13842 So, to reproduce the bug, start a fresh Emacs via " invocation-name "
13843 -no-init-file -no-site-file'. In a new buffer, in Verilog mode, type
13844 the code included below.
13846 Given those lines, I expected [[Fill in here]] to happen;
13847 but instead, [[Fill in here]] happens!.
13849 == The code: =="))))
13851 (provide 'verilog-mode)
13853 ;; Local Variables:
13854 ;; checkdoc-permit-comma-termination-flag:t
13855 ;; checkdoc-force-docstrings-flag:nil
13858 ;;; verilog-mode.el ends here