1 ;; verilog-mode.el --- major mode for editing verilog source in Emacs
3 ;; Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
4 ;; 2005, 2006, 2007 Free Software Foundation, Inc.
6 ;; Author: Michael McNamara (mac@verilog.com)
7 ;; http://www.verilog.com
9 ;; AUTO features, signal, modsig; by: Wilson Snyder
10 ;; (wsnyder@wsnyder.org)
11 ;; http://www.veripool.com
12 ;; Keywords: languages
14 ;; This file is part of GNU Emacs.
16 ;; GNU Emacs is free software; you can redistribute it and/or modify
17 ;; it under the terms of the GNU General Public License as published by
18 ;; the Free Software Foundation; either version 3, or (at your option)
21 ;; GNU Emacs is distributed in the hope that it will be useful,
22 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
23 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 ;; GNU General Public License for more details.
26 ;; You should have received a copy of the GNU General Public License
27 ;; along with GNU Emacs; see the file COPYING. If not, write to the
28 ;; Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
29 ;; Boston, MA 02110-1301, USA.
33 ;; This mode borrows heavily from the Pascal-mode and the cc-mode of emacs
38 ;; A major mode for editing Verilog HDL source code. When you have
39 ;; entered Verilog mode, you may get more info by pressing C-h m. You
40 ;; may also get online help describing various functions by: C-h f
41 ;; <Name of function you want described>
43 ;; KNOWN BUGS / BUG REPORTS
44 ;; =======================
46 ;; Verilog is a rapidly evolving language, and hence this mode is
47 ;; under continuous development. Hence this is beta code, and likely
48 ;; has bugs. Please report any and all bugs to me at mac@verilog.com.
49 ;; Please use verilog-submit-bug-report to submit a report; type C-c
50 ;; C-b to invoke this and as a result I will have a much easier time
51 ;; of reproducing the bug you find, and hence fixing it.
53 ;; INSTALLING THE MODE
54 ;; ===================
56 ;; An older version of this mode may be already installed as a part of
57 ;; your environment, and one method of updating would be to update
58 ;; your emacs environment. Sometimes this is difficult for local
59 ;; political/control reasons, and hence you can always install a
60 ;; private copy (or even a shared copy) which overrides the system
63 ;; You can get step by step help in installing this file by going to
64 ;; <http://www.verilog.com/emacs_install.html>
66 ;; The short list of installation instructions are: To set up
67 ;; automatic verilog mode, put this file in your load path, and put
68 ;; the following in code (please un comment it first!) in your
69 ;; .emacs, or in your site's site-load.el
71 ; (autoload 'verilog-mode "verilog-mode" "Verilog mode" t )
72 ; (setq auto-mode-alist (cons '("\\.v\\'" . verilog-mode) auto-mode-alist))
73 ; (setq auto-mode-alist (cons '("\\.dv\\'" . verilog-mode) auto-mode-alist))
75 ;; If you want to customize Verilog mode to fit your needs better,
76 ;; you may add these lines (the values of the variables presented
77 ;; here are the defaults). Note also that if you use an emacs that
78 ;; supports custom, it's probably better to use the custom menu to
81 ;; Be sure to examine at the help for verilog-auto, and the other
82 ;; verilog-auto-* functions for some major coding time savers.
84 ; ;; User customization for Verilog mode
85 ; (setq verilog-indent-level 3
86 ; verilog-indent-level-module 3
87 ; verilog-indent-level-declaration 3
88 ; verilog-indent-level-behavioral 3
89 ; verilog-indent-level-directive 1
90 ; verilog-case-indent 2
91 ; verilog-auto-newline t
92 ; verilog-auto-indent-on-newline t
93 ; verilog-tab-always-indent t
94 ; verilog-auto-endcomments t
95 ; verilog-minimum-comment-distance 40
96 ; verilog-indent-begin-after-if t
97 ; verilog-auto-lineup '(all)
98 ; verilog-highlight-p1800-keywords nil
99 ; verilog-linter "my_lint_shell_command"
109 ;; This variable will always hold the version number of the mode
110 (defconst verilog-mode-version "377"
111 "Version of this verilog mode.")
112 (defconst verilog-mode-release-date "2007-12-07"
113 "Version of this verilog mode.")
115 (defun verilog-version ()
116 "Inform caller of the version of this file."
118 (message "Using verilog-mode version %s" verilog-mode-version))
120 ;; Insure we have certain packages, and deal with it if we don't
122 (when (featurep 'xemacs)
127 (require 'regexp-opt)
129 ;; Bug in 19.28 through 19.30 skeleton.el, not provided.
136 (defmacro when (cond &rest body)
137 (list 'if cond (cons 'progn body))))
140 (if (fboundp 'unless)
142 (defmacro unless (cond &rest body)
143 (cons 'if (cons cond (cons nil body)))))
146 (if (fboundp 'store-match-data)
148 (defmacro store-match-data (&rest args) nil))
151 (if (boundp 'current-menubar)
154 (defmacro add-submenu (&rest args) nil))
158 (if (fboundp 'char-before)
160 (defmacro char-before (&rest body)
161 (char-after (1- (point)))))
167 (if (fboundp 'match-string-no-properties)
169 (defsubst match-string-no-properties (num &optional string)
170 "Return string of text matched by last search, without text properties.
171 NUM specifies which parenthesized expression in the last regexp.
172 Value is nil if NUMth pair didn't match, or there were less than NUM pairs.
173 Zero means the entire text matched by the whole regexp or whole string.
174 STRING should be given if the last search was by `string-match' on STRING."
175 (if (match-beginning num)
179 (match-beginning num) (match-end num))))
180 (set-text-properties 0 (length result) nil result)
182 (buffer-substring-no-properties (match-beginning num)
187 (if (and (featurep 'custom) (fboundp 'custom-declare-variable))
188 nil ;; We've got what we needed
189 ;; We have the old custom-library, hack around it!
190 (defmacro defgroup (&rest args) nil)
191 (defmacro customize (&rest args)
193 "Sorry, Customize is not available with this version of emacs"))
194 (defmacro defcustom (var value doc &rest args)
195 `(defvar ,var ,value ,doc))
197 (if (fboundp 'defface)
199 (defmacro defface (var values doc &rest args)
203 (if (and (featurep 'custom) (fboundp 'customize-group))
204 nil ;; We've got what we needed
205 ;; We have an intermediate custom-library, hack around it!
206 (defmacro customize-group (var &rest args)
210 ;; Provide a regular expression optimization routine, using regexp-opt
211 ;; if provided by the user's elisp libraries
213 (if (featurep 'xemacs)
214 (if (fboundp 'regexp-opt)
215 ;; regexp-opt is defined, does it take 3 or 2 arguments?
216 (if (fboundp 'function-max-args)
217 (let ((args (function-max-args `regexp-opt)))
219 ((eq args 3) ;; It takes 3
220 (condition-case nil ; Hide this defun from emacses
221 ;with just a two input regexp
222 (defun verilog-regexp-opt (a b)
223 "Deal with differing number of required arguments for `regexp-opt'.
224 Call 'regexp-opt' on A and B."
229 ((eq args 2) ;; It takes 2
230 (defun verilog-regexp-opt (a b)
231 "Call 'regexp-opt' on A and B."
235 ;; We can't tell; assume it takes 2
236 (defun verilog-regexp-opt (a b)
237 "Call 'regexp-opt' on A and B."
240 ;; There is no regexp-opt, provide our own
241 (defun verilog-regexp-opt (strings &optional paren shy)
242 (let ((open (if paren "\\(" "")) (close (if paren "\\)" "")))
243 (concat open (mapconcat 'regexp-quote strings "\\|") close)))
246 (defalias 'verilog-regexp-opt 'regexp-opt)))
249 (defun verilog-regexp-words (a)
250 "Call 'regexp-opt' with word delimiters for the words A."
251 (concat "\\<" (verilog-regexp-opt a t) "\\>")))
253 (defun verilog-customize ()
254 "Link to customize screen for Verilog."
256 (customize-group 'verilog-mode))
258 (defun verilog-font-customize ()
259 "Link to customize fonts used for Verilog."
261 (if (fboundp 'customize-apropos)
262 (customize-apropos "font-lock-*" 'faces)))
264 (defgroup verilog-mode nil
265 "Facilitates easy editing of Verilog source text"
268 ; (defgroup verilog-mode-fonts nil
269 ; "Facilitates easy customization fonts used in Verilog source text"
270 ; :link '(customize-apropos "font-lock-*" 'faces)
271 ; :group 'verilog-mode)
273 (defgroup verilog-mode-indent nil
274 "Customize indentation and highlighting of verilog source text"
275 :group 'verilog-mode)
277 (defgroup verilog-mode-actions nil
278 "Customize actions on verilog source text"
279 :group 'verilog-mode)
281 (defgroup verilog-mode-auto nil
282 "Customize AUTO actions when expanding verilog source text"
283 :group 'verilog-mode)
285 (defcustom verilog-linter
286 "echo 'No verilog-linter set, see \"M-x describe-variable verilog-linter\"'"
287 "*Unix program and arguments to call to run a lint checker on verilog source.
288 Depending on the `verilog-set-compile-command', this may be invoked when
289 you type \\[compile]. When the compile completes, \\[next-error] will take
290 you to the next lint error."
292 :group 'verilog-mode-actions)
294 (defcustom verilog-coverage
295 "echo 'No verilog-coverage set, see \"M-x describe-variable verilog-coverage\"'"
296 "*Program and arguments to use to annotate for coverage verilog source.
297 Depending on the `verilog-set-compile-command', this may be invoked when
298 you type \\[compile]. When the compile completes, \\[next-error] will take
299 you to the next lint error."
301 :group 'verilog-mode-actions)
303 (defcustom verilog-simulator
304 "echo 'No verilog-simulator set, see \"M-x describe-variable verilog-simulator\"'"
305 "*Program and arguments to use to interpret verilog source.
306 Depending on the `verilog-set-compile-command', this may be invoked when
307 you type \\[compile]. When the compile completes, \\[next-error] will take
308 you to the next lint error."
310 :group 'verilog-mode-actions)
312 (defcustom verilog-compiler
313 "echo 'No verilog-compiler set, see \"M-x describe-variable verilog-compiler\"'"
314 "*Program and arguments to use to compile verilog source.
315 Depending on the `verilog-set-compile-command', this may be invoked when
316 you type \\[compile]. When the compile completes, \\[next-error] will take
317 you to the next lint error."
319 :group 'verilog-mode-actions)
321 (defvar verilog-tool 'verilog-linter
322 "Which tool to use for building compiler-command.
323 Either nil, `verilog-linter, `verilog-coverage, `verilog-simulator, or
324 `verilog-compiler. Alternatively use the \"Choose Compilation Action\"
325 menu. See `verilog-set-compile-command' for more information.")
327 (defcustom verilog-highlight-translate-off nil
328 "*Non-nil means background-highlight code excluded from translation.
329 That is, all code between \"// synopsys translate_off\" and
330 \"// synopsys translate_on\" is highlighted using a different background color
331 \(face `verilog-font-lock-translate-off-face').
333 Note: This will slow down on-the-fly fontification (and thus editing).
335 Note: Activate the new setting in a Verilog buffer by re-fontifying it (menu
336 entry \"Fontify Buffer\"). XEmacs: turn off and on font locking."
338 :group 'verilog-mode-indent)
340 (defcustom verilog-indent-level 3
341 "*Indentation of Verilog statements with respect to containing block."
342 :group 'verilog-mode-indent
345 (defcustom verilog-indent-level-module 3
346 "*Indentation of Module level Verilog statements. (eg always, initial)
347 Set to 0 to get initial and always statements lined up on the left side of
349 :group 'verilog-mode-indent
352 (defcustom verilog-indent-level-declaration 3
353 "*Indentation of declarations with respect to containing block.
354 Set to 0 to get them list right under containing block."
355 :group 'verilog-mode-indent
358 (defcustom verilog-indent-declaration-macros nil
359 "*How to treat macro expansions in a declaration.
364 If non nil, treat as:
368 :group 'verilog-mode-indent
371 (defcustom verilog-indent-lists t
372 "*How to treat indenting items in a list.
373 If t (the default), indent as:
374 always @( posedge a or
378 always @( posedge a or
380 :group 'verilog-mode-indent
383 (defcustom verilog-indent-level-behavioral 3
384 "*Absolute indentation of first begin in a task or function block.
385 Set to 0 to get such code to start at the left side of the screen."
386 :group 'verilog-mode-indent
389 (defcustom verilog-indent-level-directive 1
390 "*Indentation to add to each level of `ifdef declarations.
391 Set to 0 to have all directives start at the left side of the screen."
392 :group 'verilog-mode-indent
395 (defcustom verilog-cexp-indent 2
396 "*Indentation of Verilog statements split across lines."
397 :group 'verilog-mode-indent
400 (defcustom verilog-case-indent 2
401 "*Indentation for case statements."
402 :group 'verilog-mode-indent
405 (defcustom verilog-auto-newline t
406 "*True means automatically newline after semicolons."
407 :group 'verilog-mode-indent
410 (defcustom verilog-auto-indent-on-newline t
411 "*True means automatically indent line after newline."
412 :group 'verilog-mode-indent
415 (defcustom verilog-tab-always-indent t
416 "*True means TAB should always re-indent the current line.
417 Nil means TAB will only reindent when at the beginning of the line."
418 :group 'verilog-mode-indent
421 (defcustom verilog-tab-to-comment nil
422 "*True means TAB moves to the right hand column in preparation for a comment."
423 :group 'verilog-mode-actions
426 (defcustom verilog-indent-begin-after-if t
427 "*If true, indent begin statements following if, else, while, for and repeat.
428 Otherwise, line them up."
429 :group 'verilog-mode-indent
433 (defcustom verilog-align-ifelse nil
434 "*If true, align `else' under matching `if'.
435 Otherwise else is lined up with first character on line holding matching if."
436 :group 'verilog-mode-indent
439 (defcustom verilog-minimum-comment-distance 10
440 "*Minimum distance (in lines) between begin and end required before a comment.
441 Setting this variable to zero results in every end acquiring a comment; the
442 default avoids too many redundant comments in tight quarters"
443 :group 'verilog-mode-indent
446 (defcustom verilog-auto-lineup '(declaration)
447 "*Algorithm for lining up statements on multiple lines.
449 If this list contains the symbol 'all', then all line ups described below
452 If this list contains the symbol 'declaration', then declarations are lined up
453 with any preceding declarations, taking into account widths and the like, so
454 for example the code:
461 If this list contains the symbol 'assignment', then assignments are lined up
462 with any preceding assignments, so for example the code
463 a_long_variable = b + c;
466 a_long_variable = b + c;
469 ;; The following is not implemented:
470 ;If this list contains the symbol 'case', then case items are lined up
471 ;with any preceding case items, so for example the code
473 ; a_long_state : a = 3;
478 ; a_long_state : a = 3;
483 :group 'verilog-mode-indent
486 (defcustom verilog-highlight-p1800-keywords nil
487 "*If true highlight words newly reserved by IEEE-1800 in
488 verilog-font-lock-p1800-face in order to gently suggest changing where
489 these words are used as variables to something else. Nil means highlight
490 these words as appropriate for the SystemVerilog IEEE-1800 standard. Note
491 that changing this will require restarting emacs to see the effect as font
492 color choices are cached by emacs"
493 :group 'verilog-mode-indent
496 (defcustom verilog-auto-endcomments t
497 "*True means insert a comment /* ... */ after 'end's.
498 The name of the function or case will be set between the braces."
499 :group 'verilog-mode-actions
502 (defcustom verilog-auto-read-includes nil
503 "*True means to automatically read includes before AUTOs.
504 This will do a `verilog-read-defines' and `verilog-read-includes' before
505 each AUTO expansion. This makes it easier to embed defines and includes,
506 but can result in very slow reading times if there are many or large
508 :group 'verilog-mode-actions
511 (defcustom verilog-auto-save-policy nil
512 "*Non-nil indicates action to take when saving a Verilog buffer with AUTOs.
513 A value of `force' will always do a \\[verilog-auto] automatically if
514 needed on every save. A value of `detect' will do \\[verilog-auto]
515 automatically when it thinks necessary. A value of `ask' will query the
516 user when it thinks updating is needed.
518 You should not rely on the 'ask or 'detect policies, they are safeguards
519 only. They do not detect when AUTOINSTs need to be updated because a
520 sub-module's port list has changed."
521 :group 'verilog-mode-actions
522 :type '(choice (const nil) (const ask) (const detect) (const force)))
524 (defcustom verilog-auto-star-expand t
525 "*Non-nil indicates to expand a SystemVerilog .* instance ports.
526 They will be expanded in the same way as if there was a AUTOINST in the
527 instantiation. See also `verilog-auto-star' and `verilog-auto-star-save'."
528 :group 'verilog-mode-actions
531 (defcustom verilog-auto-star-save nil
532 "*Non-nil indicates to save to disk SystemVerilog .* instance expansions.
533 Nil indicates direct connections will be removed before saving. Only
534 meaningful to those created due to `verilog-auto-star-expand' being set.
536 Instead of setting this, you may want to use /*AUTOINST*/, which will
538 :group 'verilog-mode-actions
541 (defvar verilog-auto-update-tick nil
542 "Modification tick at which autos were last performed.")
544 (defvar verilog-auto-last-file-locals nil
545 "Text from file-local-variables during last evaluation.")
547 (defvar verilog-error-regexp-add-didit nil)
548 (defvar verilog-error-regexp nil)
549 (setq verilog-error-regexp-add-didit nil
553 ;; ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 2)
554 ; Most SureFire tools
555 ("\\(WARNING\\|ERROR\\|INFO\\)[^:]*: \\([^,]+\\), \\(line \\|\\)\\([0-9]+\\):" 2 4 )
557 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
558 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 2 5)
560 ; Error! in file /homes/mac/Axis/Xsim/test.v at line 13 [OBJ_NOT_DECLARED]
561 ("\\(Error\\|Warning\\).*in file (\\([^ \t]+\\) at line *\\([0-9]+\\))" 2 3)
563 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 3)
564 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 2)
565 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 3)
566 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 2)
568 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4)
569 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4)
571 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 3)
572 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 1 2) ; vxl
573 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 1 2)
575 (".*\\*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 1 2)
577 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 1 2)
579 ; "*List of regexps for verilog compilers, like verilint. See compilation-error-regexp-alist for the formatting."
582 (defvar verilog-error-font-lock-keywords
584 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 bold t)
585 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 2 bold t)
587 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 2 bold t)
588 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 3 bold t)
591 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
592 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t)
594 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
595 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t)
597 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 bold t)
598 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 3 bold t)
600 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 bold t)
601 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 4 bold t)
603 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t)
604 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t)
606 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t)
607 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 3 bold t)
609 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 bold t)
610 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t)
612 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t)
613 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t)
615 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 1 bold t)
616 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 2 bold t)
618 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 1 bold t)
619 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 2 bold t)
621 (".*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 1 bold t)
622 (".*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 2 bold t)
624 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 1 bold t)
625 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 2 bold t)
627 "*Keywords to also highlight in Verilog *compilation* buffers."
630 (defcustom verilog-library-flags '("")
631 "*List of standard Verilog arguments to use for /*AUTOINST*/.
632 These arguments are used to find files for `verilog-auto', and match
633 the flags accepted by a standard Verilog-XL simulator.
635 -f filename Reads more `verilog-library-flags' from the filename.
636 +incdir+dir Adds the directory to `verilog-library-directories'.
637 -Idir Adds the directory to `verilog-library-directories'.
638 -y dir Adds the directory to `verilog-library-directories'.
639 +libext+.v Adds the extensions to `verilog-library-extensions'.
640 -v filename Adds the filename to `verilog-library-files'.
642 filename Adds the filename to `verilog-library-files'.
643 This is not recommended, -v is a better choice.
645 You might want these defined in each file; put at the *END* of your file
649 // verilog-library-flags:(\"-y dir -y otherdir\")
652 Verilog-mode attempts to detect changes to this local variable, but they
653 are only insured to be correct when the file is first visited. Thus if you
654 have problems, use \\[find-alternate-file] RET to have these take effect.
656 See also the variables mentioned above."
657 :group 'verilog-mode-auto
658 :type '(repeat string))
660 (defcustom verilog-library-directories '(".")
661 "*List of directories when looking for files for /*AUTOINST*/.
662 The directory may be relative to the current file, or absolute.
663 Environment variables are also expanded in the directory names.
664 Having at least the current directory is a good idea.
666 You might want these defined in each file; put at the *END* of your file
670 // verilog-library-directories:(\".\" \"subdir\" \"subdir2\")
673 Verilog-mode attempts to detect changes to this local variable, but they
674 are only insured to be correct when the file is first visited. Thus if you
675 have problems, use \\[find-alternate-file] RET to have these take effect.
677 See also `verilog-library-flags', `verilog-library-files'
678 and `verilog-library-extensions'."
679 :group 'verilog-mode-auto
680 :type '(repeat file))
682 (defcustom verilog-library-files '()
683 "*List of files to search for modules when looking for AUTOINST files.
684 This is a complete path, usually to a technology file with many standard
687 You might want these defined in each file; put at the *END* of your file
691 // verilog-library-files:(\"/some/path/technology.v\" \"/some/path/tech2.v\")
694 Verilog-mode attempts to detect changes to this local variable, but they
695 are only insured to be correct when the file is first visited. Thus if you
696 have problems, use \\[find-alternate-file] RET to have these take effect.
698 See also `verilog-library-flags', `verilog-library-directories'."
699 :group 'verilog-mode-auto
700 :type '(repeat directory))
702 (defcustom verilog-library-extensions '(".v")
703 "*List of extensions to use when looking for files for /*AUTOINST*/.
704 See also `verilog-library-flags', `verilog-library-directories'."
705 :type '(repeat string)
706 :group 'verilog-mode-auto)
708 (defcustom verilog-active-low-regexp nil
709 "*If set, treat signals matching this regexp as active low.
710 This is used for AUTORESET and AUTOTIEOFF. For proper behavior,
711 you will probably also need `verilog-auto-reset-widths' set."
712 :group 'verilog-mode-auto
715 (defcustom verilog-auto-sense-include-inputs nil
716 "*If true, AUTOSENSE should include all inputs.
717 If nil, only inputs that are NOT output signals in the same block are
720 :group 'verilog-mode-auto)
722 (defcustom verilog-auto-sense-defines-constant nil
723 "*If true, AUTOSENSE should assume all defines represent constants.
724 When true, the defines will not be included in sensitivity lists. To
725 maintain compatibility with other sites, this should be set at the bottom
726 of each verilog file that requires it, rather than being set globally."
728 :group 'verilog-mode-auto)
730 (defcustom verilog-auto-reset-widths t
731 "*If true, AUTORESET should determine the width of signals.
732 This is then used to set the width of the zero (32'h0 for example). This
733 is required by some lint tools that aren't smart enough to ignore widths of
734 the constant zero. This may result in ugly code when parameters determine
735 the MSB or LSB of a signal inside a AUTORESET."
737 :group 'verilog-mode-auto)
739 (defcustom verilog-assignment-delay ""
740 "*Text used for delays in delayed assignments. Add a trailing space if set."
742 :group 'verilog-mode-auto)
744 (defcustom verilog-auto-inst-vector t
745 "*If true, when creating default ports with AUTOINST, use bus subscripts.
746 If nil, skip the subscript when it matches the entire bus as declared in
747 the module (AUTOWIRE signals always are subscripted, you must manually
748 declare the wire to have the subscripts removed.) Nil may speed up some
749 simulators, but is less general and harder to read, so avoid."
750 :group 'verilog-mode-auto
753 (defcustom verilog-auto-inst-template-numbers nil
754 "*If true, when creating templated ports with AUTOINST, add a comment.
755 The comment will add the line number of the template that was used for that
756 port declaration. Setting this aids in debugging, but nil is suggested for
757 regular use to prevent large numbers of merge conflicts."
758 :group 'verilog-mode-auto
761 (defvar verilog-auto-inst-column 40
762 "Column number for first part of auto-inst.")
764 (defcustom verilog-auto-input-ignore-regexp nil
765 "*If set, when creating AUTOINPUT list, ignore signals matching this regexp.
766 See the \\[verilog-faq] for examples on using this."
767 :group 'verilog-mode-auto
770 (defcustom verilog-auto-inout-ignore-regexp nil
771 "*If set, when creating AUTOINOUT list, ignore signals matching this regexp.
772 See the \\[verilog-faq] for examples on using this."
773 :group 'verilog-mode-auto
776 (defcustom verilog-auto-output-ignore-regexp nil
777 "*If set, when creating AUTOOUTPUT list, ignore signals matching this regexp.
778 See the \\[verilog-faq] for examples on using this."
779 :group 'verilog-mode-auto
782 (defcustom verilog-auto-unused-ignore-regexp nil
783 "*If set, when creating AUTOUNUSED list, ignore signals matching this regexp.
784 See the \\[verilog-faq] for examples on using this."
785 :group 'verilog-mode-auto
788 (defcustom verilog-typedef-regexp nil
789 "*If non-nil, regular expression that matches Verilog-2001 typedef names.
790 For example, \"_t$\" matches typedefs named with _t, as in the C language."
791 :group 'verilog-mode-auto
794 (defcustom verilog-mode-hook 'verilog-set-compile-command
795 "*Hook (List of functions) run after verilog mode is loaded."
797 :group 'verilog-mode)
799 (defcustom verilog-auto-hook nil
800 "*Hook run after `verilog-mode' updates AUTOs."
802 :group 'verilog-mode-auto)
804 (defcustom verilog-before-auto-hook nil
805 "*Hook run before `verilog-mode' updates AUTOs."
807 :group 'verilog-mode-auto)
809 (defcustom verilog-delete-auto-hook nil
810 "*Hook run after `verilog-mode' deletes AUTOs."
812 :group 'verilog-mode-auto)
814 (defcustom verilog-before-delete-auto-hook nil
815 "*Hook run before `verilog-mode' deletes AUTOs."
817 :group 'verilog-mode-auto)
819 (defcustom verilog-getopt-flags-hook nil
820 "*Hook run after `verilog-getopt-flags' determines the Verilog option lists."
822 :group 'verilog-mode-auto)
824 (defcustom verilog-before-getopt-flags-hook nil
825 "*Hook run before `verilog-getopt-flags' determines the Verilog option lists."
827 :group 'verilog-mode-auto)
829 (defvar verilog-imenu-generic-expression
830 '((nil "^\\s-*\\(\\(m\\(odule\\|acromodule\\)\\)\\|primitive\\)\\s-+\\([a-zA-Z0-9_.:]+\\)" 4)
831 ("*Vars*" "^\\s-*\\(reg\\|wire\\)\\s-+\\(\\|\\[[^]]+\\]\\s-+\\)\\([A-Za-z0-9_]+\\)" 3))
832 "Imenu expression for Verilog-mode. See `imenu-generic-expression'.")
835 ;; provide a verilog-header function.
836 ;; Customization variables:
838 (defvar verilog-date-scientific-format nil
839 "*If non-nil, dates are written in scientific format (e.g. 1997/09/17).
840 If nil, in European format (e.g. 17.09.1997). The brain-dead American
841 format (e.g. 09/17/1997) is not supported.")
843 (defvar verilog-company nil
844 "*Default name of Company for verilog header.
845 If set will become buffer local.")
847 (make-variable-buffer-local 'verilog-company)
849 (defvar verilog-project nil
850 "*Default name of Project for verilog header.
851 If set will become buffer local.")
853 (make-variable-buffer-local 'verilog-project)
855 (defvar verilog-mode-map
856 (let ((map (make-sparse-keymap)))
857 (define-key map ";" 'electric-verilog-semi)
858 (define-key map [(control 59)] 'electric-verilog-semi-with-comment)
859 (define-key map ":" 'electric-verilog-colon)
860 ;;(define-key map "=" 'electric-verilog-equal)
861 (define-key map "\`" 'electric-verilog-tick)
862 (define-key map "\t" 'electric-verilog-tab)
863 (define-key map "\r" 'electric-verilog-terminate-line)
864 ;; backspace/delete key bindings
865 (define-key map [backspace] 'backward-delete-char-untabify)
866 (unless (boundp 'delete-key-deletes-forward) ; XEmacs variable
867 (define-key map [delete] 'delete-char)
868 (define-key map [(meta delete)] 'kill-word))
869 (define-key map "\M-\C-b" 'electric-verilog-backward-sexp)
870 (define-key map "\M-\C-f" 'electric-verilog-forward-sexp)
871 (define-key map "\M-\r" `electric-verilog-terminate-and-indent)
872 (define-key map "\M-\t" 'verilog-complete-word)
873 (define-key map "\M-?" 'verilog-show-completions)
874 (define-key map [(meta control h)] 'verilog-mark-defun)
875 (define-key map "\C-c\`" 'verilog-lint-off)
876 (define-key map "\C-c\*" 'verilog-delete-auto-star-implicit)
877 (define-key map "\C-c\C-r" 'verilog-label-be)
878 (define-key map "\C-c\C-i" 'verilog-pretty-declarations)
879 (define-key map "\C-c=" 'verilog-pretty-expr)
880 (define-key map "\C-c\C-b" 'verilog-submit-bug-report)
881 (define-key map "\M-*" 'verilog-star-comment)
882 (define-key map "\C-c\C-c" 'verilog-comment-region)
883 (define-key map "\C-c\C-u" 'verilog-uncomment-region)
884 (define-key map "\M-\C-a" 'verilog-beg-of-defun)
885 (define-key map "\M-\C-e" 'verilog-end-of-defun)
886 (define-key map "\C-c\C-d" 'verilog-goto-defun)
887 (define-key map "\C-c\C-k" 'verilog-delete-auto)
888 (define-key map "\C-c\C-a" 'verilog-auto)
889 (define-key map "\C-c\C-s" 'verilog-auto-save-compile)
890 (define-key map "\C-c\C-z" 'verilog-inject-auto)
891 (define-key map "\C-c\C-e" 'verilog-expand-vector)
892 (define-key map "\C-c\C-h" 'verilog-header)
894 "Keymap used in Verilog mode.")
897 (defvar verilog-xemacs-menu
899 ("Choose Compilation Action"
902 (setq verilog-tool nil)
903 (verilog-set-compile-command))
905 :selected (equal verilog-tool nil)]
908 (setq verilog-tool 'verilog-linter)
909 (verilog-set-compile-command))
911 :selected (equal verilog-tool `verilog-linter)]
914 (setq verilog-tool 'verilog-coverage)
915 (verilog-set-compile-command))
917 :selected (equal verilog-tool `verilog-coverage)]
920 (setq verilog-tool 'verilog-simulator)
921 (verilog-set-compile-command))
923 :selected (equal verilog-tool `verilog-simulator)]
926 (setq verilog-tool 'verilog-compiler)
927 (verilog-set-compile-command))
929 :selected (equal verilog-tool `verilog-compiler)]
932 ["Beginning of function" verilog-beg-of-defun t]
933 ["End of function" verilog-end-of-defun t]
934 ["Mark function" verilog-mark-defun t]
935 ["Goto function/module" verilog-goto-defun t]
936 ["Move to beginning of block" electric-verilog-backward-sexp t]
937 ["Move to end of block" electric-verilog-forward-sexp t]
940 ["Comment Region" verilog-comment-region t]
941 ["UnComment Region" verilog-uncomment-region t]
942 ["Multi-line comment insert" verilog-star-comment t]
943 ["Lint error to comment" verilog-lint-off t]
946 ["Compile" compile t]
947 ["AUTO, Save, Compile" verilog-auto-save-compile t]
948 ["Next Compile Error" next-error t]
949 ["Ignore Lint Warning at point" verilog-lint-off t]
951 ["Line up declarations around point" verilog-pretty-declarations t]
952 ["Line up equations around point" verilog-pretty-expr t]
953 ["Redo/insert comments on every end" verilog-label-be t]
954 ["Expand [x:y] vector line" verilog-expand-vector t]
955 ["Insert begin-end block" verilog-insert-block t]
956 ["Complete word" verilog-complete-word t]
958 ["Recompute AUTOs" verilog-auto t]
959 ["Kill AUTOs" verilog-delete-auto t]
960 ["Inject AUTOs" verilog-inject-auto t]
962 ["AUTO General" (describe-function 'verilog-auto) t]
963 ["AUTO Library Flags" (describe-variable 'verilog-library-flags) t]
964 ["AUTO Library Path" (describe-variable 'verilog-library-directories) t]
965 ["AUTO Library Files" (describe-variable 'verilog-library-files) t]
966 ["AUTO Library Extensions" (describe-variable 'verilog-library-extensions) t]
967 ["AUTO `define Reading" (describe-function 'verilog-read-defines) t]
968 ["AUTO `include Reading" (describe-function 'verilog-read-includes) t]
969 ["AUTOARG" (describe-function 'verilog-auto-arg) t]
970 ["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum) t]
971 ["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module) t]
972 ["AUTOINOUT" (describe-function 'verilog-auto-inout) t]
973 ["AUTOINPUT" (describe-function 'verilog-auto-input) t]
974 ["AUTOINST" (describe-function 'verilog-auto-inst) t]
975 ["AUTOINST (.*)" (describe-function 'verilog-auto-star) t]
976 ["AUTOINSTPARAM" (describe-function 'verilog-auto-inst-param) t]
977 ["AUTOOUTPUT" (describe-function 'verilog-auto-output) t]
978 ["AUTOOUTPUTEVERY" (describe-function 'verilog-auto-output-every) t]
979 ["AUTOREG" (describe-function 'verilog-auto-reg) t]
980 ["AUTOREGINPUT" (describe-function 'verilog-auto-reg-input) t]
981 ["AUTORESET" (describe-function 'verilog-auto-reset) t]
982 ["AUTOSENSE" (describe-function 'verilog-auto-sense) t]
983 ["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff) t]
984 ["AUTOUNUSED" (describe-function 'verilog-auto-unused) t]
985 ["AUTOWIRE" (describe-function 'verilog-auto-wire) t]
988 ["Submit bug report" verilog-submit-bug-report t]
989 ["Version and FAQ" verilog-faq t]
990 ["Customize Verilog Mode..." verilog-customize t]
991 ["Customize Verilog Fonts & Colors" verilog-font-customize t]
993 "Emacs menu for VERILOG mode."
995 (defvar verilog-statement-menu
997 ["Header" verilog-sk-header t]
998 ["Comment" verilog-sk-comment t]
1000 ["Module" verilog-sk-module t]
1001 ["Primitive" verilog-sk-primitive t]
1003 ["Input" verilog-sk-input t]
1004 ["Output" verilog-sk-output t]
1005 ["Inout" verilog-sk-inout t]
1006 ["Wire" verilog-sk-wire t]
1007 ["Reg" verilog-sk-reg t]
1008 ["Define thing under point as a register" verilog-sk-define-signal t]
1010 ["Initial" verilog-sk-initial t]
1011 ["Always" verilog-sk-always t]
1012 ["Function" verilog-sk-function t]
1013 ["Task" verilog-sk-task t]
1014 ["Specify" verilog-sk-specify t]
1015 ["Generate" verilog-sk-generate t]
1017 ["Begin" verilog-sk-begin t]
1018 ["If" verilog-sk-if t]
1019 ["(if) else" verilog-sk-else-if t]
1020 ["For" verilog-sk-for t]
1021 ["While" verilog-sk-while t]
1022 ["Fork" verilog-sk-fork t]
1023 ["Repeat" verilog-sk-repeat t]
1024 ["Case" verilog-sk-case t]
1025 ["Casex" verilog-sk-casex t]
1026 ["Casez" verilog-sk-casez t]
1028 "Menu for statement templates in Verilog."
1031 (easy-menu-define verilog-menu verilog-mode-map "Menu for Verilog mode"
1032 verilog-xemacs-menu)
1033 (easy-menu-define verilog-stmt-menu verilog-mode-map "Menu for statement templates in Verilog."
1034 verilog-statement-menu)
1036 (defvar verilog-mode-abbrev-table nil
1037 "Abbrev table in use in Verilog-mode buffers.")
1039 (define-abbrev-table 'verilog-mode-abbrev-table ())
1045 (defsubst verilog-string-replace-matches (from-string to-string fixedcase literal string)
1046 "Replace occurrences of FROM-STRING with TO-STRING.
1047 FIXEDCASE and LITERAL as in `replace-match`. STRING is what to replace.
1048 The case (verilog-string-replace-matches \"o\" \"oo\" nil nil \"foobar\")
1049 will break, as the o's continuously replace. xa -> x works ok though."
1050 ;; Hopefully soon to a emacs built-in
1052 (while (string-match from-string string start)
1053 (setq string (replace-match to-string fixedcase literal string)
1054 start (min (length string) (match-end 0))))
1057 (defsubst verilog-string-remove-spaces (string)
1058 "Remove spaces surrounding STRING."
1060 (setq string (verilog-string-replace-matches "^\\s-+" "" nil nil string))
1061 (setq string (verilog-string-replace-matches "\\s-+$" "" nil nil string))
1064 (defsubst verilog-re-search-forward (REGEXP BOUND NOERROR)
1065 ; checkdoc-params: (REGEXP BOUND NOERROR)
1066 "Like `re-search-forward', but skips over match in comments or strings."
1067 (store-match-data '(nil nil))
1069 (re-search-forward REGEXP BOUND NOERROR)
1070 (and (verilog-skip-forward-comment-or-string)
1072 (store-match-data '(nil nil))
1079 (defsubst verilog-re-search-backward (REGEXP BOUND NOERROR)
1080 ; checkdoc-params: (REGEXP BOUND NOERROR)
1081 "Like `re-search-backward', but skips over match in comments or strings."
1082 (store-match-data '(nil nil))
1084 (re-search-backward REGEXP BOUND NOERROR)
1085 (and (verilog-skip-backward-comment-or-string)
1087 (store-match-data '(nil nil))
1094 (defsubst verilog-re-search-forward-quick (regexp bound noerror)
1095 "Like `verilog-re-search-forward', including use of REGEXP BOUND and NOERROR,
1096 but trashes match data and is faster for REGEXP that doesn't match often.
1097 This may at some point use text properties to ignore comments,
1098 so there may be a large up front penalty for the first search."
1100 (while (and (not pt)
1101 (re-search-forward regexp bound noerror))
1102 (if (not (verilog-inside-comment-p))
1103 (setq pt (match-end 0))))
1106 (defsubst verilog-re-search-backward-quick (regexp bound noerror)
1107 ; checkdoc-params: (REGEXP BOUND NOERROR)
1108 "Like `verilog-re-search-backward', including use of REGEXP BOUND and NOERROR,
1109 but trashes match data and is faster for REGEXP that doesn't match often.
1110 This may at some point use text properties to ignore comments,
1111 so there may be a large up front penalty for the first search."
1113 (while (and (not pt)
1114 (re-search-backward regexp bound noerror))
1115 (if (not (verilog-inside-comment-p))
1116 (setq pt (match-end 0))))
1119 (defsubst verilog-get-beg-of-line (&optional arg)
1121 (beginning-of-line arg)
1124 (defsubst verilog-get-end-of-line (&optional arg)
1129 (defsubst verilog-within-string ()
1131 (nth 3 (parse-partial-sexp (verilog-get-beg-of-line) (point)))))
1133 ;; compilation program
1134 (defun verilog-set-compile-command ()
1135 "Function to compute shell command to compile verilog.
1137 This reads `verilog-tool' and sets `compile-command'. This specifies the
1138 program that executes when you type \\[compile] or
1139 \\[verilog-auto-save-compile].
1141 By default `verilog-tool' uses a Makefile if one exists in the current
1142 directory. If not, it is set to the `verilog-linter', `verilog-coverage',
1143 `verilog-simulator', or `verilog-compiler' variables, as selected with the
1144 Verilog -> \"Choose Compilation Action\" menu.
1146 You should set `verilog-tool' or the other variables to the path and
1147 arguments for your Verilog simulator. For example:
1150 \"(cd /tmp; surecov %s)\".
1152 In the former case, the path to the current buffer is concat'ed to the
1153 value of `verilog-tool'; in the later, the path to the current buffer is
1154 substituted for the %s.
1156 Where __FILE__ appears in the string, the buffer-file-name of the current
1157 buffer, without the directory portion, will be substituted."
1160 ((or (file-exists-p "makefile") ;If there is a makefile, use it
1161 (file-exists-p "Makefile"))
1162 (make-local-variable 'compile-command)
1163 (setq compile-command "make "))
1165 (make-local-variable 'compile-command)
1166 (setq compile-command
1168 (if (string-match "%s" (eval verilog-tool))
1169 (format (eval verilog-tool) (or buffer-file-name ""))
1170 (concat (eval verilog-tool) " " (or buffer-file-name "")))
1172 (verilog-modify-compile-command))
1174 (defun verilog-modify-compile-command ()
1175 "Replace meta-information in `compile-command'.
1176 Where __FILE__ appears in the string, the current buffer's file-name,
1177 without the directory portion, will be substituted."
1179 (stringp compile-command)
1180 (string-match "\\b__FILE__\\b" compile-command))
1181 (make-local-variable 'compile-command)
1182 (setq compile-command
1183 (verilog-string-replace-matches
1184 "\\b__FILE__\\b" (file-name-nondirectory (buffer-file-name))
1185 t t compile-command))))
1187 ;; Following code only gets called from compilation-mode-hook.
1188 (defvar compilation-error-regexp-alist)
1190 (defun verilog-error-regexp-add ()
1191 "Add the messages to the `compilation-error-regexp-alist'.
1192 Called by `compilation-mode-hook'. This allows \\[next-error] to
1194 (if (not verilog-error-regexp-add-didit)
1196 (setq verilog-error-regexp-add-didit t)
1197 (setq-default compilation-error-regexp-alist
1198 (append verilog-error-regexp
1199 (default-value 'compilation-error-regexp-alist)))
1200 ;; Could be buffer local at this point; maybe also in let; change all three
1201 (setq compilation-error-regexp-alist
1202 (default-value 'compilation-error-regexp-alist))
1203 (set (make-local-variable 'compilation-error-regexp-alist)
1204 (default-value 'compilation-error-regexp-alist))
1207 (add-hook 'compilation-mode-hook 'verilog-error-regexp-add)
1209 (defconst verilog-directive-re
1210 ;; "`case" "`default" "`define" "`define" "`else" "`endfor" "`endif"
1211 ;; "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
1212 ;; "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
1213 ;; "`time_scale" "`undef" "`while"
1214 "\\<`\\(case\\|def\\(ault\\|ine\\(\\)?\\)\\|e\\(lse\\|nd\\(for\\|if\\|protect\\|switch\\|while\\)\\)\\|for\\(mat\\)?\\|i\\(f\\(def\\|ndef\\)?\\|nclude\\)\\|let\\|protect\\|switch\\|time\\(_scale\\|scale\\)\\|undef\\|while\\)\\>")
1216 (defconst verilog-directive-begin
1217 "\\<`\\(for\\|i\\(f\\|fdef\\|fndef\\)\\|switch\\|while\\)\\>")
1219 (defconst verilog-directive-middle
1220 "\\<`\\(else\\|default\\|case\\)\\>")
1222 (defconst verilog-directive-end
1223 "`\\(endfor\\|endif\\|endswitch\\|endwhile\\)\\>")
1225 (defconst verilog-directive-re-1
1226 (concat "[ \t]*" verilog-directive-re))
1229 ;; Regular expressions used to calculate indent, etc.
1231 (defconst verilog-symbol-re "\\<[a-zA-Z_][a-zA-Z_0-9.]*\\>")
1232 (defconst verilog-case-re "\\(\\<case[xz]?\\>\\|\\<randcase\\>\\)")
1240 (defconst verilog-no-indent-begin-re
1241 "\\<\\(if\\|else\\|while\\|for\\|repeat\\|always\\|always_comb\\|always_ff\\|always_latch\\)\\>")
1243 (defconst verilog-ends-re
1244 ;; Parenthesis indicate type of keyword found
1246 "\\(\\<else\\>\\)\\|" ; 1
1247 "\\(\\<if\\>\\)\\|" ; 2
1248 "\\(\\<end\\>\\)\\|" ; 3
1249 "\\(\\<endcase\\>\\)\\|" ; 4
1250 "\\(\\<endfunction\\>\\)\\|" ; 5
1251 "\\(\\<endtask\\>\\)\\|" ; 6
1252 "\\(\\<endspecify\\>\\)\\|" ; 7
1253 "\\(\\<endtable\\>\\)\\|" ; 8
1254 "\\(\\<endgenerate\\>\\)\\|" ; 9
1255 "\\(\\<join\\(_any\\|_none\\)?\\>\\)\\|" ; 10
1256 "\\(\\<endclass\\>\\)\\|" ; 11
1257 "\\(\\<endgroup\\>\\)" ; 12
1260 (defconst verilog-auto-end-comment-lines-re
1261 ;; Matches to names in this list cause auto-end-commentation
1263 verilog-directive-re "\\)\\|\\("
1265 (verilog-regexp-words
1293 ;;; NOTE: verilog-leap-to-head expects that verilog-end-block-re and
1294 ;;; verilog-end-block-ordered-re matches exactly the same strings.
1295 (defconst verilog-end-block-ordered-re
1296 ;; Parenthesis indicate type of keyword found
1297 (concat "\\(\\<endcase\\>\\)\\|" ; 1
1298 "\\(\\<end\\>\\)\\|" ; 2
1299 "\\(\\<end" ; 3, but not used
1300 "\\(" ; 4, but not used
1301 "\\(function\\)\\|" ; 5
1303 "\\(module\\)\\|" ; 7
1304 "\\(primitive\\)\\|" ; 8
1305 "\\(interface\\)\\|" ; 9
1306 "\\(package\\)\\|" ; 10
1307 "\\(class\\)\\|" ; 11
1308 "\\(group\\)\\|" ; 12
1309 "\\(program\\)\\|" ; 13
1310 "\\(sequence\\)\\|" ; 14
1311 "\\(clocking\\)\\|" ; 15
1313 (defconst verilog-end-block-re
1315 (verilog-regexp-words
1317 `("end" ;; closes begin
1318 "endcase" ;; closes any of case, casex casez or randcase
1319 "join" "join_any" "join_none" ;; closes fork
1337 (defconst verilog-endcomment-reason-re
1338 ;; Parenthesis indicate type of keyword found
1340 "\\(\\<fork\\>\\)\\|"
1341 "\\(\\<begin\\>\\)\\|"
1343 "\\(\\<clocking\\>\\)\\|"
1344 "\\(\\<else\\>\\)\\|"
1345 "\\(\\<end\\>.*\\<else\\>\\)\\|"
1346 "\\(\\<task\\>\\)\\|"
1347 "\\(\\<function\\>\\)\\|"
1348 "\\(\\<initial\\>\\)\\|"
1349 "\\(\\<interface\\>\\)\\|"
1350 "\\(\\<package\\>\\)\\|"
1351 "\\(\\<final\\>\\)\\|"
1352 "\\(\\<always\\>\\(\[ \t\]*@\\)?\\)\\|"
1353 "\\(\\<always_comb\\>\\(\[ \t\]*@\\)?\\)\\|"
1354 "\\(\\<always_ff\\>\\(\[ \t\]*@\\)?\\)\\|"
1355 "\\(\\<always_latch\\>\\(\[ \t\]*@\\)?\\)\\|"
1357 "\\(\\<while\\>\\)\\|"
1358 "\\(\\<for\\(ever\\|each\\)?\\>\\)\\|"
1359 "\\(\\<repeat\\>\\)\\|\\(\\<wait\\>\\)\\|"
1362 (defconst verilog-named-block-re "begin[ \t]*:")
1364 ;; These words begin a block which can occur inside a module which should be indented,
1365 ;; and closed with the respective word from the end-block list
1367 (defconst verilog-beg-block-re
1369 (verilog-regexp-words
1371 "case" "casex" "casez" "randcase"
1381 ;; These are the same words, in a specific order in the regular
1382 ;; expression so that matching will work nicely for
1383 ;; verilog-forward-sexp and verilog-calc-indent
1385 (defconst verilog-beg-block-re-ordered
1388 "\\|\\(randcase\\|\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?\\)" ; 2
1389 ;; "\\|\\(randcase\\|case[xz]?\\)" ; 2
1393 "\\|\\(specify\\)" ;6
1394 "\\|\\(function\\)" ;7
1396 "\\|\\(generate\\)" ;9
1397 "\\|\\(covergroup\\)" ;10
1398 "\\|\\(property\\)" ;11
1399 "\\|\\(\\(rand\\)?sequence\\)" ;12
1400 "\\|\\(clocking\\)" ;13
1403 (defconst verilog-end-block-ordered-rry
1404 [ "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
1405 "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)"
1406 "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
1407 "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)"
1408 "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)"
1409 "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)"
1410 "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)"
1411 "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)"
1412 "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)"
1413 "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)"
1414 "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)"
1415 "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)"
1416 "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)"
1419 (defconst verilog-nameable-item-re
1421 (verilog-regexp-words
1424 "join" "join_any" "join_none"
1441 (defconst verilog-declaration-opener
1443 (verilog-regexp-words
1444 `("module" "begin" "task" "function"))))
1446 (defconst verilog-declaration-prefix-re
1448 (verilog-regexp-words
1451 "inout" "input" "output" "ref"
1453 "const" "static" "protected" "local"
1455 "localparam" "parameter" "var"
1459 (defconst verilog-declaration-core-re
1461 (verilog-regexp-words
1463 ;; integer_atom_type
1464 "byte" "shortint" "int" "longint" "integer" "time"
1465 ;; integer_vector_type
1468 "shortreal" "real" "realtime"
1470 "supply0" "supply1" "tri" "triand" "trior" "trireg" "tri0" "tri1" "uwire" "wire" "wand" "wor"
1472 "string" "event" "chandle" "virtual" "enum" "genvar"
1475 "mailbox" "semaphore"
1477 (defconst verilog-declaration-re
1478 (concat "\\(" verilog-declaration-prefix-re "\\s-*\\)?" verilog-declaration-core-re))
1479 (defconst verilog-range-re "\\(\\[[^]]*\\]\\s-*\\)+")
1480 (defconst verilog-optional-signed-re "\\s-*\\(signed\\)?")
1481 (defconst verilog-optional-signed-range-re
1483 "\\s-*\\(\\<\\(reg\\|wire\\)\\>\\s-*\\)?\\(\\<signed\\>\\s-*\\)?\\(" verilog-range-re "\\)?"))
1484 (defconst verilog-macroexp-re "`\\sw+")
1486 (defconst verilog-delay-re "#\\s-*\\(\\([0-9_]+\\('s?[hdxbo][0-9a-fA-F_xz]+\\)?\\)\\|\\(([^()]*)\\)\\|\\(\\sw+\\)\\)")
1487 (defconst verilog-declaration-re-2-no-macro
1488 (concat "\\s-*" verilog-declaration-re
1489 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
1491 (defconst verilog-declaration-re-2-macro
1492 (concat "\\s-*" verilog-declaration-re
1493 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
1494 "\\|\\(" verilog-macroexp-re "\\)"
1496 (defconst verilog-declaration-re-1-macro
1497 (concat "^" verilog-declaration-re-2-macro))
1499 (defconst verilog-declaration-re-1-no-macro (concat "^" verilog-declaration-re-2-no-macro))
1501 (defconst verilog-defun-re
1502 (eval-when-compile (verilog-regexp-words `("macromodule" "module" "class" "program" "interface" "package" "primitive" "config"))))
1503 (defconst verilog-end-defun-re
1504 (eval-when-compile (verilog-regexp-words `("endmodule" "endclass" "endprogram" "endinterface" "endpackage" "endprimitive" "endconfig"))))
1505 (defconst verilog-zero-indent-re
1506 (concat verilog-defun-re "\\|" verilog-end-defun-re))
1508 (defconst verilog-behavioral-block-beg-re
1509 (concat "\\(\\<initial\\>\\|\\<final\\>\\|\\<always\\>\\|\\<always_comb\\>\\|\\<always_ff\\>\\|"
1510 "\\<always_latch\\>\\|\\<function\\>\\|\\<task\\>\\)"))
1512 (defconst verilog-indent-re
1514 (verilog-regexp-words
1517 "always" "always_latch" "always_ff" "always_comb"
1519 ; "unique" "priority"
1520 "case" "casex" "casez" "randcase" "endcase"
1522 "clocking" "endclocking"
1523 "config" "endconfig"
1524 "covergroup" "endgroup"
1525 "fork" "join" "join_any" "join_none"
1526 "function" "endfunction"
1528 "generate" "endgenerate"
1530 "interface" "endinterface"
1531 "module" "macromodule" "endmodule"
1532 "package" "endpackage"
1533 "primitive" "endprimative"
1534 "program" "endprogram"
1535 "property" "endproperty"
1536 "sequence" "randsequence" "endsequence"
1537 "specify" "endspecify"
1543 "`if" "`ifdef" "`ifndef" "`else" "`endif"
1544 "`while" "`endwhile"
1549 "`protect" "`endprotect"
1550 "`switch" "`endswitch"
1555 (defconst verilog-defun-level-re
1557 (verilog-regexp-words
1559 "module" "macromodule" "primitive" "class" "program" "initial" "final" "always" "always_comb"
1560 "always_ff" "always_latch" "endtask" "endfunction" "interface" "package"
1563 (defconst verilog-defun-level-not-generate-re
1565 (verilog-regexp-words
1567 "module" "macromodule" "primitive" "class" "program" "interface" "package" "config"))))
1569 (defconst verilog-cpp-level-re
1571 (verilog-regexp-words
1573 "endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass"
1575 (defconst verilog-extended-case-re "\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?")
1576 (defconst verilog-extended-complete-re
1577 (concat "\\(\\<extern\\s-+\\|\\<virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)"
1578 "\\|\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)"
1579 "\\|" verilog-extended-case-re ))
1580 (defconst verilog-basic-complete-re
1582 (verilog-regexp-words
1584 "always" "assign" "always_latch" "always_ff" "always_comb" "constraint"
1585 "import" "initial" "final" "module" "macromodule" "repeat" "randcase" "while"
1586 "if" "for" "forever" "foreach" "else" "parameter" "do"
1588 (defconst verilog-complete-reg
1590 verilog-extended-complete-re
1592 verilog-basic-complete-re))
1594 (defconst verilog-end-statement-re
1595 (concat "\\(" verilog-beg-block-re "\\)\\|\\("
1596 verilog-end-block-re "\\)"))
1598 (defconst verilog-endcase-re
1599 (concat verilog-case-re "\\|"
1604 (defconst verilog-exclude-str-start "/* -----\\/----- EXCLUDED -----\\/-----"
1605 "String used to mark beginning of excluded text.")
1606 (defconst verilog-exclude-str-end " -----/\\----- EXCLUDED -----/\\----- */"
1607 "String used to mark end of excluded text.")
1608 (defconst verilog-preprocessor-re
1610 (verilog-regexp-words
1612 "`define" "`include" "`ifdef" "`ifndef" "`if" "`endif" "`else"
1615 (defconst verilog-keywords
1616 '( "`case" "`default" "`define" "`else" "`endfor" "`endif"
1617 "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
1618 "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
1619 "`time_scale" "`undef" "`while"
1621 "after" "alias" "always" "always_comb" "always_ff" "always_latch" "and"
1622 "assert" "assign" "assume" "automatic" "before" "begin" "bind"
1623 "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte"
1624 "case" "casex" "casez" "cell" "chandle" "class" "clocking" "cmos"
1625 "config" "const" "constraint" "context" "continue" "cover"
1626 "covergroup" "coverpoint" "cross" "deassign" "default" "defparam"
1627 "design" "disable" "dist" "do" "edge" "else" "end" "endcase"
1628 "endclass" "endclocking" "endconfig" "endfunction" "endgenerate"
1629 "endgroup" "endinterface" "endmodule" "endpackage" "endprimitive"
1630 "endprogram" "endproperty" "endspecify" "endsequence" "endtable"
1631 "endtask" "enum" "event" "expect" "export" "extends" "extern"
1632 "final" "first_match" "for" "force" "foreach" "forever" "fork"
1633 "forkjoin" "function" "generate" "genvar" "highz0" "highz1" "if"
1634 "iff" "ifnone" "ignore_bins" "illegal_bins" "import" "incdir"
1635 "include" "initial" "inout" "input" "inside" "instance" "int"
1636 "integer" "interface" "intersect" "join" "join_any" "join_none"
1637 "large" "liblist" "library" "local" "localparam" "logic"
1638 "longint" "macromodule" "mailbox" "matches" "medium" "modport" "module"
1639 "nand" "negedge" "new" "nmos" "nor" "noshowcancelled" "not"
1640 "notif0" "notif1" "null" "or" "output" "package" "packed"
1641 "parameter" "pmos" "posedge" "primitive" "priority" "program"
1642 "property" "protected" "pull0" "pull1" "pulldown" "pullup"
1643 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
1644 "randcase" "randsequence" "rcmos" "real" "realtime" "ref" "reg"
1645 "release" "repeat" "return" "rnmos" "rpmos" "rtran" "rtranif0"
1646 "rtranif1" "scalared" "semaphore" "sequence" "shortint" "shortreal"
1647 "showcancelled" "signed" "small" "solve" "specify" "specparam"
1648 "static" "string" "strong0" "strong1" "struct" "super" "supply0"
1649 "supply1" "table" "tagged" "task" "this" "throughout" "time"
1650 "timeprecision" "timeunit" "tran" "tranif0" "tranif1" "tri"
1651 "tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union"
1652 "unique" "unsigned" "use" "uwire" "var" "vectored" "virtual" "void"
1653 "wait" "wait_order" "wand" "weak0" "weak1" "while" "wildcard"
1654 "wire" "with" "within" "wor" "xnor" "xor"
1656 "List of Verilog keywords.")
1659 (defconst verilog-emacs-features
1660 ;; Documentation at the bottom
1661 (let ((major (and (boundp 'emacs-major-version)
1662 emacs-major-version))
1663 (minor (and (boundp 'emacs-minor-version)
1664 emacs-minor-version))
1665 flavor comments flock-syntax)
1666 ;; figure out version numbers if not already discovered
1667 (and (or (not major) (not minor))
1668 (string-match "\\([0-9]+\\).\\([0-9]+\\)" emacs-version)
1669 (setq major (string-to-number (substring emacs-version
1672 minor (string-to-number (substring emacs-version
1675 (if (not (and major minor))
1676 (error "Cannot figure out the major and minor version numbers"))
1677 ;; calculate the major version
1679 ((= major 4) (setq major 'v18)) ;Epoch 4
1680 ((= major 18) (setq major 'v18)) ;Emacs 18
1681 ((= major 19) (setq major 'v19 ;Emacs 19
1682 flavor (if (or (string-match "Lucid" emacs-version)
1683 (string-match "XEmacs" emacs-version))
1685 ((> major 19) (setq major 'v20
1686 flavor (if (or (string-match "Lucid" emacs-version)
1687 (string-match "XEmacs" emacs-version))
1690 (t (error "Cannot recognize major version number: %s" major)))
1691 ;; XEmacs 19 uses 8-bit modify-syntax-entry flags, as do all
1692 ;; patched Emacs 19, Emacs 18, Epoch 4's. Only Emacs 19 uses a
1693 ;; 1-bit flag. Let's be as smart as we can about figuring this
1695 (if (or (eq major 'v20) (eq major 'v19))
1696 (let ((table (copy-syntax-table)))
1697 (modify-syntax-entry ?a ". 12345678" table)
1699 ;; XEmacs pre 20 and Emacs pre 19.30 use vectors for syntax tables.
1701 (if (= (logand (lsh (aref table ?a) -16) 255) 255)
1702 (setq comments '8-bit)
1703 (setq comments '1-bit)))
1704 ;; XEmacs 20 is known to be 8-bit
1705 ((eq flavor 'XEmacs) (setq comments '8-bit))
1706 ;; Emacs 19.30 and beyond are known to be 1-bit
1707 ((eq flavor 'FSF) (setq comments '1-bit))
1708 ;; Don't know what this is
1709 (t (error "Couldn't figure out syntax table format"))
1711 ;; Emacs 18 has no support for dual comments
1712 (setq comments 'no-dual-comments))
1713 ;; determine whether to use old or new font lock syntax
1714 ;; We can assume 8-bit syntax table emacsen support new syntax, otherwise
1715 ;; look for version > 19.30
1717 (if (or (equal comments '8-bit)
1719 (and (equal major 'v19) (> minor 30)))
1720 'flock-syntax-after-1930
1721 'flock-syntax-before-1930))
1722 ;; lets do some minimal sanity checking.
1724 ;; Emacs before 19.6 had bugs
1725 (and (eq major 'v19) (eq flavor 'XEmacs) (< minor 6))
1726 ;; Emacs 19 before 19.21 has known bugs
1727 (and (eq major 'v19) (eq flavor 'FSF) (< minor 21))
1729 (with-output-to-temp-buffer "*verilog-mode warnings*"
1731 "The version of Emacs that you are running, %s,
1732 has known bugs in its syntax parsing routines which will affect the
1733 performance of verilog-mode. You should strongly consider upgrading to the
1734 latest available version. verilog-mode may continue to work, after a
1735 fashion, but strange indentation errors could be encountered."
1737 ;; Emacs 18, with no patch is not too good
1738 (if (and (eq major 'v18) (eq comments 'no-dual-comments))
1739 (with-output-to-temp-buffer "*verilog-mode warnings*"
1741 "The version of Emacs 18 you are running, %s,
1742 has known deficiencies in its ability to handle the dual verilog
1743 \(and C++) comments, (e.g. the // and /* */ comments). This will
1744 not be much of a problem for you if you only use the /* */ comments,
1745 but you really should strongly consider upgrading to one of the latest
1746 Emacs 19's. In Emacs 18, you may also experience performance degradations.
1747 Emacs 19 has some new built-in routines which will speed things up for you.
1748 Because of these inherent problems, verilog-mode is not supported
1751 ;; Emacs 18 with the syntax patches are no longer supported
1752 (if (and (eq major 'v18) (not (eq comments 'no-dual-comments)))
1753 (with-output-to-temp-buffer "*verilog-mode warnings*"
1755 "You are running a syntax patched Emacs 18 variant. While this should
1756 work for you, you may want to consider upgrading to Emacs 19.
1757 The syntax patches are no longer supported either for verilog-mode."))))
1758 (list major comments flock-syntax))
1759 "A list of features extant in the Emacs you are using.
1760 There are many flavors of Emacs out there, each with different
1761 features supporting those needed by `verilog-mode'. Here's the current
1762 supported list, along with the values for this variable:
1764 Vanilla Emacs 18/Epoch 4: (v18 no-dual-comments flock-syntax-before-1930)
1765 Emacs 18/Epoch 4 (patch2): (v18 8-bit flock-syntax-after-1930)
1766 XEmacs (formerly Lucid) 19: (v19 8-bit flock-syntax-after-1930)
1767 XEmacs 20: (v20 8-bit flock-syntax-after-1930)
1768 Emacs 19.1-19.30: (v19 8-bit flock-syntax-before-1930)
1769 Emacs 19.31-19.xx: (v19 8-bit flock-syntax-after-1930)
1770 Emacs20 : (v20 1-bit flock-syntax-after-1930).")
1772 (defconst verilog-comment-start-regexp "//\\|/\\*"
1773 "Dual comment value for `comment-start-regexp'.")
1775 (defun verilog-populate-syntax-table (table)
1776 "Populate the syntax TABLE."
1777 (modify-syntax-entry ?\\ "\\" table)
1778 (modify-syntax-entry ?+ "." table)
1779 (modify-syntax-entry ?- "." table)
1780 (modify-syntax-entry ?= "." table)
1781 (modify-syntax-entry ?% "." table)
1782 (modify-syntax-entry ?< "." table)
1783 (modify-syntax-entry ?> "." table)
1784 (modify-syntax-entry ?& "." table)
1785 (modify-syntax-entry ?| "." table)
1786 (modify-syntax-entry ?` "w" table)
1787 (modify-syntax-entry ?_ "w" table)
1788 (modify-syntax-entry ?\' "." table)
1791 (defun verilog-setup-dual-comments (table)
1792 "Set up TABLE to handle block and line style comments."
1794 ((memq '8-bit verilog-emacs-features)
1795 ;; XEmacs (formerly Lucid) has the best implementation
1796 (modify-syntax-entry ?/ ". 1456" table)
1797 (modify-syntax-entry ?* ". 23" table)
1798 (modify-syntax-entry ?\n "> b" table)
1800 ((memq '1-bit verilog-emacs-features)
1801 ;; Emacs 19 does things differently, but we can work with it
1802 (modify-syntax-entry ?/ ". 124b" table)
1803 (modify-syntax-entry ?* ". 23" table)
1804 (modify-syntax-entry ?\n "> b" table)
1808 (defvar verilog-mode-syntax-table nil
1809 "Syntax table used in `verilog-mode' buffers.")
1811 (defvar verilog-font-lock-keywords nil
1812 "Default highlighting for Verilog mode.")
1814 (defvar verilog-font-lock-keywords-1 nil
1815 "Subdued level highlighting for Verilog mode.")
1817 (defvar verilog-font-lock-keywords-2 nil
1818 "Medium level highlighting for Verilog mode.
1819 See also `verilog-font-lock-extra-types'.")
1821 (defvar verilog-font-lock-keywords-3 nil
1822 "Gaudy level highlighting for Verilog mode.
1823 See also `verilog-font-lock-extra-types'.")
1824 (defvar verilog-font-lock-translate-off-face
1825 'verilog-font-lock-translate-off-face
1826 "Font to use for translated off regions.")
1827 (defface verilog-font-lock-translate-off-face
1830 (:background "gray90" :italic t ))
1833 (:background "gray10" :italic t ))
1834 (((class grayscale) (background light))
1835 (:foreground "DimGray" :italic t))
1836 (((class grayscale) (background dark))
1837 (:foreground "LightGray" :italic t))
1839 "Font lock mode face used to background highlight translate-off regions."
1840 :group 'font-lock-highlighting-faces)
1842 (defvar verilog-font-lock-p1800-face
1843 'verilog-font-lock-p1800-face
1844 "Font to use for p1800 keywords.")
1845 (defface verilog-font-lock-p1800-face
1848 (:foreground "DarkOrange3" :bold t ))
1851 (:foreground "orange1" :bold t ))
1853 "Font lock mode face used to highlight P1800 keywords."
1854 :group 'font-lock-highlighting-faces)
1856 (defvar verilog-font-lock-ams-face
1857 'verilog-font-lock-ams-face
1858 "Font to use for Analog/Mixed Signal keywords.")
1859 (defface verilog-font-lock-ams-face
1862 (:foreground "Purple" :bold t ))
1865 (:foreground "orange1" :bold t ))
1867 "Font lock mode face used to highlight AMS keywords."
1868 :group 'font-lock-highlighting-faces)
1870 (let* ((verilog-type-font-keywords
1874 "and" "bit" "buf" "bufif0" "bufif1" "cmos" "defparam"
1875 "event" "genvar" "inout" "input" "integer" "localparam"
1876 "logic" "mailbox" "nand" "nmos" "not" "notif0" "notif1" "or"
1877 "output" "parameter" "pmos" "pull0" "pull1" "pullup"
1878 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran"
1879 "rtranif0" "rtranif1" "semaphore" "signed" "struct" "supply"
1880 "supply0" "supply1" "time" "tran" "tranif0" "tranif1"
1881 "tri" "tri0" "tri1" "triand" "trior" "trireg" "typedef"
1882 "uwire" "vectored" "wand" "wire" "wor" "xnor" "xor"
1885 (verilog-pragma-keywords
1888 '("surefire" "synopsys" "rtl_synthesis" "verilint" ) nil
1891 (verilog-p1800-keywords
1894 '("alias" "assert" "assume" "automatic" "before" "bind"
1895 "bins" "binsof" "break" "byte" "cell" "chandle" "class"
1896 "clocking" "config" "const" "constraint" "context" "continue"
1897 "cover" "covergroup" "coverpoint" "cross" "deassign" "design"
1898 "dist" "do" "edge" "endclass" "endclocking" "endconfig"
1899 "endgroup" "endprogram" "endproperty" "endsequence" "enum"
1900 "expect" "export" "extends" "extern" "first_match" "foreach"
1901 "forkjoin" "genvar" "highz0" "highz1" "ifnone" "ignore_bins"
1902 "illegal_bins" "import" "incdir" "include" "inside" "instance"
1903 "int" "intersect" "large" "liblist" "library" "local" "longint"
1904 "matches" "medium" "modport" "new" "noshowcancelled" "null"
1905 "packed" "program" "property" "protected" "pull0" "pull1"
1906 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
1907 "randcase" "randsequence" "ref" "release" "return" "scalared"
1908 "sequence" "shortint" "shortreal" "showcancelled" "small" "solve"
1909 "specparam" "static" "string" "strong0" "strong1" "struct"
1910 "super" "tagged" "this" "throughout" "timeprecision" "timeunit"
1911 "type" "union" "unsigned" "use" "var" "virtual" "void"
1912 "wait_order" "weak0" "weak1" "wildcard" "with" "within"
1915 (verilog-ams-keywords
1918 '("above" "abs" "absdelay" "acos" "acosh" "ac_stim"
1919 "aliasparam" "analog" "analysis" "asin" "asinh" "atan" "atan2" "atanh"
1920 "branch" "ceil" "connectmodule" "connectrules" "cos" "cosh" "ddt"
1921 "ddx" "discipline" "driver_update" "enddiscipline" "endconnectrules"
1922 "endnature" "endparamset" "exclude" "exp" "final_step" "flicker_noise"
1923 "floor" "flow" "from" "ground" "hypot" "idt" "idtmod" "inf"
1924 "initial_step" "laplace_nd" "laplace_np" "laplace_zd" "laplace_zp"
1925 "last_crossing" "limexp" "ln" "log" "max" "min" "nature"
1926 "net_resolution" "noise_table" "paramset" "potential" "pow" "sin"
1927 "sinh" "slew" "sqrt" "tan" "tanh" "timer" "transition" "white_noise"
1928 "wreal" "zi_nd" "zi_np" "zi_zd" ) nil )))
1930 (verilog-font-keywords
1934 "assign" "begin" "case" "casex" "casez" "randcase" "deassign"
1935 "default" "disable" "else" "end" "endcase" "endfunction"
1936 "endgenerate" "endinterface" "endmodule" "endprimitive"
1937 "endspecify" "endtable" "endtask" "final" "for" "force" "return" "break"
1938 "continue" "forever" "fork" "function" "generate" "if" "iff" "initial"
1939 "interface" "join" "join_any" "join_none" "macromodule" "module" "negedge"
1940 "package" "endpackage" "always" "always_comb" "always_ff"
1941 "always_latch" "posedge" "primitive" "priority" "release"
1942 "repeat" "specify" "table" "task" "unique" "wait" "while"
1943 "class" "program" "endclass" "endprogram"
1946 (setq verilog-font-lock-keywords
1948 ;; Fontify all builtin keywords
1949 (concat "\\<\\(" verilog-font-keywords "\\|"
1950 ;; And user/system tasks and functions
1951 "\\$[a-zA-Z][a-zA-Z0-9_\\$]*"
1953 ;; Fontify all types
1954 (cons (concat "\\<\\(" verilog-type-font-keywords "\\)\\>")
1955 'font-lock-type-face)
1956 ;; Fontify IEEE-P1800 keywords appropriately
1957 (if verilog-highlight-p1800-keywords
1958 (cons (concat "\\<\\(" verilog-p1800-keywords "\\)\\>")
1959 'verilog-font-lock-p1800-face)
1960 (cons (concat "\\<\\(" verilog-p1800-keywords "\\)\\>")
1961 'font-lock-type-face))
1962 ;; Fontify Verilog-AMS keywords
1963 (cons (concat "\\<\\(" verilog-ams-keywords "\\)\\>")
1964 'verilog-font-lock-ams-face)
1967 (setq verilog-font-lock-keywords-1
1968 (append verilog-font-lock-keywords
1970 ;; Fontify module definitions
1972 "\\<\\(\\(macro\\)?module\\|primitive\\|class\\|program\\|interface\\|package\\|task\\)\\>\\s-*\\(\\sw+\\)"
1973 '(1 font-lock-keyword-face)
1974 '(3 font-lock-function-name-face 'prepend))
1975 ;; Fontify function definitions
1977 (concat "\\<function\\>\\s-+\\(integer\\|real\\(time\\)?\\|time\\)\\s-+\\(\\sw+\\)" )
1978 '(1 font-lock-keyword-face)
1979 '(3 font-lock-reference-face prepend)
1981 '("\\<function\\>\\s-+\\(\\[[^]]+\\]\\)\\s-+\\(\\sw+\\)"
1982 (1 font-lock-keyword-face)
1983 (2 font-lock-reference-face append)
1985 '("\\<function\\>\\s-+\\(\\sw+\\)"
1986 1 'font-lock-reference-face append)
1989 (setq verilog-font-lock-keywords-2
1990 (append verilog-font-lock-keywords-1
1993 (concat "\\(//\\s-*" verilog-pragma-keywords "\\s-.*\\)")
1994 ;; Fontify escaped names
1995 '("\\(\\\\\\S-*\\s-\\)" 0 font-lock-function-name-face)
1996 ;; Fontify macro definitions/ uses
1997 '("`\\s-*[A-Za-z][A-Za-z0-9_]*" 0 (if (boundp 'font-lock-preprocessor-face)
1998 'font-lock-preprocessor-face
1999 'font-lock-type-face))
2000 ;; Fontify delays/numbers
2001 '("\\(@\\)\\|\\(#\\s-*\\(\\(\[0-9_.\]+\\('s?[hdxbo][0-9a-fA-F_xz]*\\)?\\)\\|\\(([^()]+)\\|\\sw+\\)\\)\\)"
2002 0 font-lock-type-face append)
2003 ;; Fontify instantiation names
2004 '("\\([A-Za-z][A-Za-z0-9_]+\\)\\s-*(" 1 font-lock-function-name-face)
2008 (setq verilog-font-lock-keywords-3
2009 (append verilog-font-lock-keywords-2
2010 (when verilog-highlight-translate-off
2012 ;; Fontify things in translate off regions
2013 '(verilog-match-translate-off
2014 (0 'verilog-font-lock-translate-off-face prepend))
2019 (defun verilog-inside-comment-p ()
2020 "Check if point inside a nested comment."
2022 (let ((st-point (point)) hitbeg)
2023 (or (search-backward "//" (verilog-get-beg-of-line) t)
2025 ;; This is for tricky case //*, we keep searching if /* is
2026 ;; proceeded by // on same line.
2028 (and (setq hitbeg (search-backward "/*" nil t))
2031 (search-backward "//" (verilog-get-beg-of-line) t))))
2033 (not (search-forward "*/" st-point t)))))))
2035 (defun verilog-declaration-end ()
2036 (search-forward ";"))
2038 (defun verilog-point-text (&optional pointnum)
2039 "Return text describing where POINTNUM or current point is (for errors).
2040 Use filename, if current buffer being edited shorten to just buffer name."
2041 (concat (or (and (equal (window-buffer (selected-window)) (current-buffer))
2045 ":" (int-to-string (count-lines (point-min) (or pointnum (point))))))
2047 (defun electric-verilog-backward-sexp ()
2048 "Move backward over a sexp."
2050 ;; before that see if we are in a comment
2051 (verilog-backward-sexp)
2053 (defun electric-verilog-forward-sexp ()
2054 "Move backward over a sexp."
2056 ;; before that see if we are in a comment
2057 (verilog-forward-sexp)
2059 ;;;used by hs-minor-mode
2060 (defun verilog-forward-sexp-function (arg)
2062 (verilog-backward-sexp)
2063 (verilog-forward-sexp)))
2066 (defun verilog-backward-sexp ()
2072 (if (not (looking-at "\\<"))
2075 ((verilog-skip-backward-comment-or-string)
2077 ((looking-at "\\<else\\>")
2079 verilog-end-block-re
2080 "\\|\\(\\<else\\>\\)"
2083 (while (and (not found)
2084 (verilog-re-search-backward reg nil 'move))
2086 ((match-end 1) ; matched verilog-end-block-re
2087 ; try to leap back to matching outward block by striding across
2088 ; indent level changing tokens then immediately
2089 ; previous line governs indentation.
2090 (verilog-leap-to-head))
2091 ((match-end 2) ; else, we're in deep
2092 (setq elsec (1+ elsec)))
2093 ((match-end 3) ; found it
2094 (setq elsec (1- elsec))
2096 ;; Now previous line describes syntax
2102 ((looking-at verilog-end-block-re)
2103 (verilog-leap-to-head))
2104 ((looking-at "\\(endmodule\\>\\)\\|\\(\\<endprimitive\\>\\)\\|\\(\\<endclass\\>\\)\\|\\(\\<endprogram\\>\\)\\|\\(\\<endinterface\\>\\)\\|\\(\\<endpackage\\>\\)")
2107 (verilog-re-search-backward "\\<\\(macro\\)?module\\>" nil 'move))
2109 (verilog-re-search-backward "\\<primitive\\>" nil 'move))
2111 (verilog-re-search-backward "\\<class\\>" nil 'move))
2113 (verilog-re-search-backward "\\<program\\>" nil 'move))
2115 (verilog-re-search-backward "\\<interface\\>" nil 'move))
2117 (verilog-re-search-backward "\\<package\\>" nil 'move))
2120 (backward-sexp 1))))
2127 (defun verilog-forward-sexp ()
2131 (if (not (looking-at "\\<"))
2134 ((verilog-skip-forward-comment-or-string)
2135 (verilog-forward-syntactic-ws)
2137 ((looking-at verilog-beg-block-re-ordered);; begin|case|fork|class|table|specify|function|task|generate|covergroup|property|sequence|clocking
2139 ((match-end 1) ; end
2140 ;; Search forward for matching begin
2141 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
2142 ((match-end 2) ; endcase
2143 ;; Search forward for matching case
2144 (setq reg "\\(\\<randcase\\>\\|\\(\\<unique\\>\\s-+\\|\\<priority\\>\\s-+\\)?\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )
2146 ((match-end 3) ; join
2147 ;; Search forward for matching fork
2148 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
2149 ((match-end 4) ; endclass
2150 ;; Search forward for matching class
2151 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
2152 ((match-end 5) ; endtable
2153 ;; Search forward for matching table
2154 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
2155 ((match-end 6) ; endspecify
2156 ;; Search forward for matching specify
2157 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
2158 ((match-end 7) ; endfunction
2159 ;; Search forward for matching function
2160 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
2161 ((match-end 8) ; endtask
2162 ;; Search forward for matching task
2163 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
2164 ((match-end 9) ; endgenerate
2165 ;; Search forward for matching generate
2166 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
2167 ((match-end 10) ; endgroup
2168 ;; Search forward for matching covergroup
2169 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
2170 ((match-end 11) ; endproperty
2171 ;; Search forward for matching property
2172 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
2173 ((match-end 12) ; endsequence
2174 ;; Search forward for matching sequence
2175 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" )
2176 (setq md 3) ; 3 to get to endsequence in the reg above
2178 ((match-end 13) ; endclocking
2179 ;; Search forward for matching clocking
2180 (setq reg "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)" ))
2182 (if (forward-word 1)
2185 (while (verilog-re-search-forward reg nil 'move)
2187 ((match-end md) ; the closer in reg, so we are climbing out
2188 (setq nest (1- nest))
2189 (if (= 0 nest) ; we are out!
2191 ((match-end 1) ; the opener in reg, so we are deeper now
2192 (setq nest (1+ nest)))))
2195 ((looking-at (concat
2196 "\\(\\<\\(macro\\)?module\\>\\)\\|"
2197 "\\(\\<primitive\\>\\)\\|"
2198 "\\(\\<class\\>\\)\\|"
2199 "\\(\\<program\\>\\)\\|"
2200 "\\(\\<interface\\>\\)\\|"
2201 "\\(\\<package\\>\\)"))
2204 (verilog-re-search-forward "\\<endmodule\\>" nil 'move))
2206 (verilog-re-search-forward "\\<endprimitive\\>" nil 'move))
2208 (verilog-re-search-forward "\\<endclass\\>" nil 'move))
2210 (verilog-re-search-forward "\\<endprogram\\>" nil 'move))
2212 (verilog-re-search-forward "\\<endinterface\\>" nil 'move))
2214 (verilog-re-search-forward "\\<endpackage\\>" nil 'move))
2217 (if (= (following-char) ?\) )
2219 (forward-sexp 1)))))
2222 (if (= (following-char) ?\) )
2228 (defun verilog-declaration-beg ()
2229 (verilog-re-search-backward verilog-declaration-re (bobp) t))
2231 (defun verilog-font-lock-init ()
2232 "Initialize fontification."
2233 ;; highlight keywords and standardized types, attributes, enumeration
2234 ;; values, and subprograms
2235 (setq verilog-font-lock-keywords-3
2236 (append verilog-font-lock-keywords-2
2237 (when verilog-highlight-translate-off
2239 ;; Fontify things in translate off regions
2240 '(verilog-match-translate-off
2241 (0 'verilog-font-lock-translate-off-face prepend))
2243 (put 'verilog-mode 'font-lock-defaults
2244 '((verilog-font-lock-keywords
2245 verilog-font-lock-keywords-1
2246 verilog-font-lock-keywords-2
2247 verilog-font-lock-keywords-3)
2248 nil ; nil means highlight strings & comments as well as keywords
2249 nil ; nil means keywords must match case
2250 nil ; syntax table handled elsewhere
2251 ;; Function to move to beginning of reasonable region to highlight
2252 verilog-beg-of-defun)))
2254 ;; initialize fontification for Verilog Mode
2255 (verilog-font-lock-init)
2257 (defconst verilog-startup-message-lines
2258 '("Please use \\[verilog-submit-bug-report] to report bugs."
2259 "Visit http://www.verilog.com to check for updates"
2261 (defvar verilog-startup-message-displayed t)
2262 (defun verilog-display-startup-message ()
2263 (if (not verilog-startup-message-displayed)
2265 (let ((lines verilog-startup-message-lines))
2266 (message "verilog-mode version %s, released %s; type \\[describe-mode] for help"
2267 verilog-mode-version verilog-mode-release-date)
2268 (setq verilog-startup-message-displayed t)
2269 (while (and (sit-for 4) lines)
2270 (message (substitute-command-keys (car lines)))
2271 (setq lines (cdr lines)))))
2277 (defvar verilog-which-tool 1)
2279 (defun verilog-mode ()
2280 "Major mode for editing Verilog code.
2281 \\<verilog-mode-map>
2282 See \\[describe-function] verilog-auto (\\[verilog-auto]) for details on how
2283 AUTOs can improve coding efficiency.
2285 Use \\[verilog-faq] for a pointer to frequently asked questions.
2287 NEWLINE, TAB indents for Verilog code.
2288 Delete converts tabs to spaces as it moves back.
2290 Supports highlighting.
2292 Turning on Verilog mode calls the value of the variable `verilog-mode-hook'
2293 with no args, if that value is non-nil.
2295 Variables controlling indentation/edit style:
2297 variable `verilog-indent-level' (default 3)
2298 Indentation of Verilog statements with respect to containing block.
2299 `verilog-indent-level-module' (default 3)
2300 Absolute indentation of Module level Verilog statements.
2301 Set to 0 to get initial and always statements lined up
2302 on the left side of your screen.
2303 `verilog-indent-level-declaration' (default 3)
2304 Indentation of declarations with respect to containing block.
2305 Set to 0 to get them list right under containing block.
2306 `verilog-indent-level-behavioral' (default 3)
2307 Indentation of first begin in a task or function block
2308 Set to 0 to get such code to lined up underneath the task or function keyword
2309 `verilog-indent-level-directive' (default 1)
2310 Indentation of `ifdef/`endif blocks
2311 `verilog-cexp-indent' (default 1)
2312 Indentation of Verilog statements broken across lines i.e.:
2315 `verilog-case-indent' (default 2)
2316 Indentation for case statements.
2317 `verilog-auto-newline' (default nil)
2318 Non-nil means automatically newline after semicolons and the punctuation
2320 `verilog-auto-indent-on-newline' (default t)
2321 Non-nil means automatically indent line after newline
2322 `verilog-tab-always-indent' (default t)
2323 Non-nil means TAB in Verilog mode should always reindent the current line,
2324 regardless of where in the line point is when the TAB command is used.
2325 `verilog-indent-begin-after-if' (default t)
2326 Non-nil means to indent begin statements following a preceding
2327 if, else, while, for and repeat statements, if any. otherwise,
2328 the begin is lined up with the preceding token. If t, you get:
2330 begin // amount of indent based on `verilog-cexp-indent'
2334 `verilog-auto-endcomments' (default t)
2335 Non-nil means a comment /* ... */ is set after the ends which ends
2336 cases, tasks, functions and modules.
2337 The type and name of the object will be set between the braces.
2338 `verilog-minimum-comment-distance' (default 10)
2339 Minimum distance (in lines) between begin and end required before a comment
2340 will be inserted. Setting this variable to zero results in every
2341 end acquiring a comment; the default avoids too many redundant
2342 comments in tight quarters.
2343 `verilog-auto-lineup' (default `(all))
2344 List of contexts where auto lineup of code should be done.
2346 Variables controlling other actions:
2348 `verilog-linter' (default surelint)
2349 Unix program to call to run the lint checker. This is the default
2350 command for \\[compile-command] and \\[verilog-auto-save-compile].
2352 See \\[customize] for the complete list of variables.
2354 AUTO expansion functions are, in part:
2356 \\[verilog-auto] Expand AUTO statements.
2357 \\[verilog-delete-auto] Remove the AUTOs.
2358 \\[verilog-inject-auto] Insert AUTOs for the first time.
2360 Some other functions are:
2362 \\[verilog-complete-word] Complete word with appropriate possibilities.
2363 \\[verilog-mark-defun] Mark function.
2364 \\[verilog-beg-of-defun] Move to beginning of current function.
2365 \\[verilog-end-of-defun] Move to end of current function.
2366 \\[verilog-label-be] Label matching begin ... end, fork ... join, etc statements.
2368 \\[verilog-comment-region] Put marked area in a comment.
2369 \\[verilog-uncomment-region] Uncomment an area commented with \\[verilog-comment-region].
2370 \\[verilog-insert-block] Insert begin ... end;.
2371 \\[verilog-star-comment] Insert /* ... */.
2373 \\[verilog-sk-always] Insert a always @(AS) begin .. end block.
2374 \\[verilog-sk-begin] Insert a begin .. end block.
2375 \\[verilog-sk-case] Insert a case block, prompting for details.
2376 \\[verilog-sk-for] Insert a for (...) begin .. end block, prompting for details.
2377 \\[verilog-sk-generate] Insert a generate .. endgenerate block.
2378 \\[verilog-sk-header] Insert a nice header block at the top of file.
2379 \\[verilog-sk-initial] Insert an initial begin .. end block.
2380 \\[verilog-sk-fork] Insert a fork begin .. end .. join block.
2381 \\[verilog-sk-module] Insert a module .. (/*AUTOARG*/);.. endmodule block.
2382 \\[verilog-sk-primitive] Insert a primitive .. (.. );.. endprimitive block.
2383 \\[verilog-sk-repeat] Insert a repeat (..) begin .. end block.
2384 \\[verilog-sk-specify] Insert a specify .. endspecify block.
2385 \\[verilog-sk-task] Insert a task .. begin .. end endtask block.
2386 \\[verilog-sk-while] Insert a while (...) begin .. end block, prompting for details.
2387 \\[verilog-sk-casex] Insert a casex (...) item: begin.. end endcase block, prompting for details.
2388 \\[verilog-sk-casez] Insert a casez (...) item: begin.. end endcase block, prompting for details.
2389 \\[verilog-sk-if] Insert an if (..) begin .. end block.
2390 \\[verilog-sk-else-if] Insert an else if (..) begin .. end block.
2391 \\[verilog-sk-comment] Insert a comment block.
2392 \\[verilog-sk-assign] Insert an assign .. = ..; statement.
2393 \\[verilog-sk-function] Insert a function .. begin .. end endfunction block.
2394 \\[verilog-sk-input] Insert an input declaration, prompting for details.
2395 \\[verilog-sk-output] Insert an output declaration, prompting for details.
2396 \\[verilog-sk-state-machine] Insert a state machine definition, prompting for details.
2397 \\[verilog-sk-inout] Insert an inout declaration, prompting for details.
2398 \\[verilog-sk-wire] Insert a wire declaration, prompting for details.
2399 \\[verilog-sk-reg] Insert a register declaration, prompting for details.
2400 \\[verilog-sk-define-signal] Define signal under point as a register at the top of the module.
2402 All key bindings can be seen in a Verilog-buffer with \\[describe-bindings].
2403 Key bindings specific to `verilog-mode-map' are:
2405 \\{verilog-mode-map}"
2407 (kill-all-local-variables)
2408 (use-local-map verilog-mode-map)
2409 (setq major-mode 'verilog-mode)
2410 (setq mode-name "Verilog")
2411 (setq local-abbrev-table verilog-mode-abbrev-table)
2412 (setq verilog-mode-syntax-table (make-syntax-table))
2413 (verilog-populate-syntax-table verilog-mode-syntax-table)
2414 (set (make-local-variable 'beginning-of-defun-function)
2415 'verilog-beg-of-defun)
2416 (set (make-local-variable 'end-of-defun-function)
2417 'verilog-end-of-defun)
2418 ;; add extra comment syntax
2419 (verilog-setup-dual-comments verilog-mode-syntax-table)
2420 (set-syntax-table verilog-mode-syntax-table)
2421 (make-local-variable 'indent-line-function)
2422 (setq indent-line-function 'verilog-indent-line-relative)
2423 (setq comment-indent-function 'verilog-comment-indent)
2424 (make-local-variable 'parse-sexp-ignore-comments)
2425 (setq parse-sexp-ignore-comments nil)
2426 (make-local-variable 'comment-start)
2427 (make-local-variable 'comment-end)
2428 (make-local-variable 'comment-multi-line)
2429 (make-local-variable 'comment-start-skip)
2430 (setq comment-start "// "
2432 comment-start-skip "/\\*+ *\\|// *"
2433 comment-multi-line nil)
2434 ;; Set up for compilation
2435 (setq verilog-which-tool 1)
2436 (setq verilog-tool 'verilog-linter)
2437 (verilog-set-compile-command)
2438 (when (boundp 'hack-local-variables-hook) ;; Also modify any file-local-variables
2439 (add-hook 'hack-local-variables-hook 'verilog-modify-compile-command t))
2442 (when (featurep 'xemacs)
2443 (when (and current-menubar
2444 (not (assoc "Verilog" current-menubar)))
2445 ;; (set-buffer-menubar (copy-sequence current-menubar))
2446 (add-submenu nil verilog-xemacs-menu)
2447 (add-submenu nil verilog-stmt-menu)
2449 ;; Stuff for GNU emacs
2450 (set (make-local-variable 'font-lock-defaults)
2451 '((verilog-font-lock-keywords verilog-font-lock-keywords-1
2452 verilog-font-lock-keywords-2
2453 verilog-font-lock-keywords-3)
2454 nil nil nil verilog-beg-of-defun))
2455 ;;------------------------------------------------------------
2456 ;; now hook in 'verilog-colorize-include-files (eldo-mode.el&spice-mode.el)
2457 ;; all buffer local:
2458 (when (featurep 'xemacs)
2459 (make-local-hook 'font-lock-mode-hook)
2460 (make-local-hook 'font-lock-after-fontify-buffer-hook); doesn't exist in emacs 20
2461 (make-local-hook 'after-change-functions))
2462 (add-hook 'font-lock-mode-hook 'verilog-colorize-include-files-buffer t t)
2463 (add-hook 'font-lock-after-fontify-buffer-hook 'verilog-colorize-include-files-buffer t t) ; not in emacs 20
2464 (add-hook 'after-change-functions 'verilog-colorize-include-files t t)
2466 ;; Tell imenu how to handle verilog.
2467 (make-local-variable 'imenu-generic-expression)
2468 (setq imenu-generic-expression verilog-imenu-generic-expression)
2470 (unless (assq 'verilog-mode hs-special-modes-alist)
2471 (setq hs-special-modes-alist
2472 (cons '(verilog-mode-mode "\\<begin\\>" "\\<end\\>" nil
2473 verilog-forward-sexp-function)
2474 hs-special-modes-alist)))
2475 ;; Display version splash information.
2476 (verilog-display-startup-message)
2479 (add-hook 'write-contents-hooks 'verilog-auto-save-check) ; already local
2480 ;; (verilog-auto-reeval-locals t) ; Save locals in case user changes them
2481 ;; (verilog-getopt-flags)
2482 (run-hooks 'verilog-mode-hook))
2486 ;; Electric functions
2488 (defun electric-verilog-terminate-line (&optional arg)
2489 "Terminate line and indent next line.
2490 With optional ARG, remove existing end of line comments."
2492 ;; before that see if we are in a comment
2495 (parse-partial-sexp (point-min) (point)))))
2497 ((nth 7 state) ; Inside // comment
2500 (delete-horizontal-space)
2505 (beginning-of-line)))
2506 (verilog-indent-line))
2507 ((nth 4 state) ; Inside any comment (hence /**/)
2509 (verilog-more-comment))
2511 ;; First, check if current line should be indented
2513 (delete-horizontal-space)
2515 (skip-chars-forward " \t")
2516 (if (looking-at verilog-auto-end-comment-lines-re)
2517 (let ((indent-str (verilog-indent-line)))
2518 ;; Maybe we should set some endcomments
2519 (if verilog-auto-endcomments
2520 (verilog-set-auto-endcomments indent-str arg))
2522 (delete-horizontal-space)
2529 (delete-horizontal-space)
2534 ;; see if we should line up assignments
2536 (if (or (memq 'all verilog-auto-lineup)
2537 (memq 'assignments verilog-auto-lineup))
2538 (verilog-pretty-expr)
2545 (if verilog-auto-indent-on-newline
2546 (verilog-indent-line))
2552 (defun electric-verilog-terminate-and-indent ()
2553 "Insert a newline and indent for the next statement."
2555 (electric-verilog-terminate-line 1))
2557 (defun electric-verilog-semi ()
2558 "Insert `;' character and reindent the line."
2560 (insert last-command-char)
2562 (if (or (verilog-in-comment-or-string-p)
2563 (verilog-in-escaped-name-p))
2567 (verilog-forward-ws&directives)
2568 (verilog-indent-line)
2570 (if (and verilog-auto-newline
2571 (not (verilog-parenthesis-depth)))
2572 (electric-verilog-terminate-line))))
2574 (defun electric-verilog-semi-with-comment ()
2575 "Insert `;' character, reindent the line and indent for comment."
2580 (verilog-indent-line))
2581 (indent-for-comment))
2583 (defun electric-verilog-colon ()
2584 "Insert `:' and do all indentations except line indent on this line."
2586 (insert last-command-char)
2587 ;; Do nothing if within string.
2589 (verilog-within-string)
2590 (not (verilog-in-case-region-p)))
2594 (lim (progn (verilog-beg-of-statement) (point))))
2596 (verilog-backward-case-item lim)
2597 (verilog-indent-line)))
2598 ;; (let ((verilog-tab-always-indent nil))
2599 ;; (verilog-indent-line))
2602 ;;(defun electric-verilog-equal ()
2603 ;; "Insert `=', and do indentation if within block."
2605 ;; (insert last-command-char)
2606 ;; Could auto line up expressions, but not yet
2607 ;; (if (eq (car (verilog-calculate-indent)) 'block)
2608 ;; (let ((verilog-tab-always-indent nil))
2609 ;; (verilog-indent-command)))
2612 (defun electric-verilog-tick ()
2613 "Insert back-tick, and indent to column 0 if this is a CPP directive."
2615 (insert last-command-char)
2619 (looking-at verilog-directive-re-1))
2620 (verilog-indent-line))))
2622 (defun electric-verilog-tab ()
2623 "Function called when TAB is pressed in Verilog mode."
2625 ;; If verilog-tab-always-indent, indent the beginning of the line.
2626 (if (or verilog-tab-always-indent
2628 (skip-chars-backward " \t")
2630 (let* ((oldpnt (point))
2634 (skip-chars-forward " \t")
2635 (verilog-indent-line)
2636 (back-to-indentation)
2638 (if (< (point) boi-point)
2639 (back-to-indentation)
2640 (cond ((not verilog-tab-to-comment))
2644 (indent-for-comment)
2645 (when (and (eolp) (= oldpnt (point)))
2646 ; kill existing comment
2648 (re-search-forward comment-start-skip oldpnt 'move)
2649 (goto-char (match-beginning 0))
2650 (skip-chars-backward " \t")
2651 (kill-region (point) oldpnt)
2654 (progn (insert "\t"))))
2659 ;; Interactive functions
2662 (defun verilog-indent-buffer ()
2663 "Indent-region the entire buffer as Verilog code.
2664 To call this from the command line, see \\[verilog-batch-indent]."
2667 (indent-region (point-min) (point-max) nil))
2669 (defun verilog-insert-block ()
2670 "Insert Verilog begin ... end; block in the code with right indentation."
2672 (verilog-indent-line)
2674 (electric-verilog-terminate-line)
2676 (electric-verilog-terminate-line)
2679 (verilog-indent-line)))
2681 (defun verilog-star-comment ()
2682 "Insert Verilog star comment at point."
2684 (verilog-indent-line)
2692 (defun verilog-insert-1 (fmt max)
2693 "Insert integers 0 to MAX-1 according to format string FMT.
2694 Inserts one integer per line, at the current column. Stops early
2695 if it reaches the end of the buffer."
2696 (let ((col (current-column))
2700 (insert (format fmt n))
2702 ;; Note that this function does not bother to check for lines
2703 ;; shorter than col.
2707 (move-to-column col))))))
2709 (defun verilog-insert-indices (max)
2710 "Insert a set of indices into a rectangle.
2711 The upper left corner is defined by point. Indices begin with 0
2712 and extend to the MAX - 1. If no prefix arg is given, the user
2713 is prompted for a value. The indices are surrounded by square
2714 brackets \[]. For example, the following code with the point
2715 located after the first 'a' gives:
2721 a = b ==> insert-indices ==> a[ 4] = b
2727 (interactive "NMAX? ")
2728 (verilog-insert-1 "[%3d]" max))
2730 (defun verilog-generate-numbers (max)
2731 "Insert a set of generated numbers into a rectangle.
2732 The upper left corner is defined by point. The numbers are padded to three
2733 digits, starting with 000 and extending to (MAX - 1). If no prefix argument
2734 is supplied, then the user is prompted for the MAX number. Consider the
2735 following code fragment:
2741 buf buf ==> generate-numbers ==> buf buf004
2747 (interactive "NMAX? ")
2748 (verilog-insert-1 "%3.3d" max))
2750 (defun verilog-mark-defun ()
2751 "Mark the current verilog function (or procedure).
2752 This puts the mark at the end, and point at the beginning."
2755 (verilog-end-of-defun)
2757 (verilog-beg-of-defun)
2758 (if (fboundp 'zmacs-activate-region)
2759 (zmacs-activate-region)))
2761 (defun verilog-comment-region (start end)
2762 ; checkdoc-params: (start end)
2763 "Put the region into a Verilog comment.
2764 The comments that are in this area are \"deformed\":
2765 `*)' becomes `!(*' and `}' becomes `!{'.
2766 These deformed comments are returned to normal if you use
2767 \\[verilog-uncomment-region] to undo the commenting.
2769 The commented area starts with `verilog-exclude-str-start', and ends with
2770 `verilog-exclude-str-end'. But if you change these variables,
2771 \\[verilog-uncomment-region] won't recognize the comments."
2774 ;; Insert start and endcomments
2776 (if (and (save-excursion (skip-chars-forward " \t") (eolp))
2777 (not (save-excursion (skip-chars-backward " \t") (bolp))))
2779 (beginning-of-line))
2780 (insert verilog-exclude-str-end)
2785 (insert verilog-exclude-str-start)
2787 ;; Replace end-comments within commented area
2790 (while (re-search-backward "\\*/" start t)
2791 (replace-match "*-/" t t)))
2793 (let ((s+1 (1+ start)))
2794 (while (re-search-backward "/\\*" s+1 t)
2795 (replace-match "/-*" t t))))
2798 (defun verilog-uncomment-region ()
2799 "Uncomment a commented area; change deformed comments back to normal.
2800 This command does nothing if the pointer is not in a commented
2801 area. See also `verilog-comment-region'."
2804 (let ((start (point))
2806 ;; Find the boundaries of the comment
2808 (setq start (progn (search-backward verilog-exclude-str-start nil t)
2810 (setq end (progn (search-forward verilog-exclude-str-end nil t)
2812 ;; Check if we're really inside a comment
2813 (if (or (equal start (point)) (<= end (point)))
2814 (message "Not standing within commented area.")
2816 ;; Remove endcomment
2819 (let ((pos (point)))
2821 (delete-region pos (1+ (point))))
2822 ;; Change comments back to normal
2824 (while (re-search-backward "\\*-/" start t)
2825 (replace-match "*/" t t)))
2827 (while (re-search-backward "/-\\*" start t)
2828 (replace-match "/*" t t)))
2829 ;; Remove start comment
2832 (let ((pos (point)))
2834 (delete-region pos (1+ (point)))))))))
2836 (defun verilog-beg-of-defun ()
2837 "Move backward to the beginning of the current function or procedure."
2839 (verilog-re-search-backward verilog-defun-re nil 'move))
2841 (defun verilog-end-of-defun ()
2842 "Move forward to the end of the current function or procedure."
2844 (verilog-re-search-forward verilog-end-defun-re nil 'move))
2846 (defun verilog-get-beg-of-defun (&optional warn)
2848 (cond ((verilog-re-search-forward-quick verilog-defun-re nil t)
2851 (error "%s: Can't find module beginning" (verilog-point-text))
2853 (defun verilog-get-end-of-defun (&optional warn)
2855 (cond ((verilog-re-search-forward-quick verilog-end-defun-re nil t)
2858 (error "%s: Can't find endmodule" (verilog-point-text))
2861 (defun verilog-label-be (&optional arg)
2862 "Label matching begin ... end, fork ... join and case ... endcase statements.
2863 With ARG, first kill any existing labels."
2868 (verilog-beg-of-defun)
2871 (verilog-end-of-defun)
2874 (goto-char (marker-position b))
2876 (message "Relabeling module..."))
2878 (> (marker-position e) (point))
2879 (verilog-re-search-forward
2881 "\\<end\\(\\(function\\)\\|\\(task\\)\\|\\(module\\)\\|\\(primitive\\)\\|\\(interface\\)\\|\\(package\\)\\|\\(case\\)\\)?\\>"
2882 "\\|\\(`endif\\)\\|\\(`else\\)")
2884 (goto-char (match-beginning 0))
2885 (let ((indent-str (verilog-indent-line)))
2886 (verilog-set-auto-endcomments indent-str 't)
2888 (delete-horizontal-space)
2891 (if (= 9 (% cnt 10))
2892 (message "%d..." cnt))
2898 (message "%d lines auto commented" cnt))
2901 (defun verilog-beg-of-statement ()
2902 "Move backward to beginning of statement."
2904 ;; Move back token by token until we see the end
2905 ;; of some ealier line.
2907 ;; If the current point does not begin a new
2908 ;; statement, as in the character ahead of us is a ';', or SOF
2909 ;; or the string after us unambiguosly starts a statement,
2910 ;; or the token before us unambiguously ends a statement,
2911 ;; then move back a token and test again.
2914 (= (preceding-char) ?\;)
2919 (looking-at verilog-extended-complete-re)
2920 (not (save-excursion
2921 (verilog-backward-token)
2922 (looking-at verilog-extended-complete-re)))
2924 (looking-at verilog-basic-complete-re)
2926 (verilog-backward-token)
2928 (looking-at verilog-end-block-re)
2929 (looking-at verilog-preprocessor-re)))
2931 (verilog-backward-syntactic-ws)
2932 (verilog-backward-token))
2933 ;; Now point is where the previous line ended.
2934 (verilog-forward-syntactic-ws))
2936 (defun verilog-beg-of-statement-1 ()
2937 "Move backward to beginning of statement."
2941 (while (and (not (looking-at verilog-complete-reg))
2943 (verilog-backward-token)
2944 (not (looking-at verilog-complete-reg))
2945 (verilog-backward-syntactic-ws)
2948 (not (= (preceding-char) ?\;))))
2950 (verilog-forward-ws&directives)))
2952 (defun verilog-end-of-statement ()
2953 "Move forward to end of current statement."
2956 (or (looking-at verilog-beg-block-re)
2957 ;; Skip to end of statement
2958 (setq pos (catch 'found
2961 (verilog-skip-forward-comment-or-string)
2962 (cond ((looking-at "[ \t]*;")
2963 (skip-chars-forward "^;")
2965 (throw 'found (point)))
2968 (looking-at verilog-beg-block-re))
2969 (goto-char (match-beginning 0))
2971 ((looking-at "[ \t]*)")
2972 (throw 'found (point)))
2974 (throw 'found (point))))))))
2976 ;; Skip a whole block
2979 (verilog-re-search-forward verilog-end-statement-re nil 'move)
2980 (setq nest (if (match-end 1)
2984 (throw 'found (point)))
2986 (throw 'found (verilog-end-of-statement))))))
2989 (defun verilog-in-case-region-p ()
2990 "Return TRUE if in a case region;
2991 more specifically, point @ in the line foo : @ begin"
2995 (progn (verilog-forward-syntactic-ws)
2996 (looking-at "\\<begin\\>"))
2997 (progn (verilog-backward-syntactic-ws)
2998 (= (preceding-char) ?\:)))
3002 (verilog-re-search-backward
3003 (concat "\\(\\<module\\>\\)\\|\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|"
3004 "\\(\\<endcase\\>\\)\\>")
3008 (setq nest (1+ nest)))
3012 (setq nest (1- nest)))
3014 (throw 'found (= nest 0)))
3017 (defun verilog-in-struct-region-p ()
3018 "Return TRUE if in a struct region;
3019 more specifically, in a list after a struct|union keyword"
3022 (let* ((state (parse-partial-sexp (point-min) (point)))
3023 (depth (nth 0 state)))
3025 (progn (backward-up-list depth)
3026 (verilog-beg-of-statement)
3027 (looking-at "\\<typedef\\>?\\s-*\\<struct\\|union\\>")
3034 (defun verilog-in-generate-region-p ()
3035 "Return TRUE if in a generate region;
3036 more specifically, after a generate and before an endgenerate"
3038 (let ((lim (save-excursion (verilog-beg-of-defun) (point)))
3044 (verilog-re-search-backward "\\<\\(generate\\)\\|\\(endgenerate\\)\\>" lim 'move)
3046 ((match-end 1) ; generate
3047 (setq nest (1- nest)))
3048 ((match-end 2) ; endgenerate
3049 (setq nest (1+ nest)))
3052 (= nest 0) )) ; return nest
3054 (defun verilog-in-fork-region-p ()
3055 "Return true if between a fork and join."
3057 (let ((lim (save-excursion (verilog-beg-of-defun) (point)))
3063 (verilog-re-search-backward "\\<\\(fork\\)\\|\\(join\\(_any\\|_none\\)?\\)\\>" lim 'move)
3065 ((match-end 1) ; fork
3066 (setq nest (1- nest)))
3067 ((match-end 2) ; join
3068 (setq nest (1+ nest)))
3071 (= nest 0) )) ; return nest
3073 (defun verilog-backward-case-item (lim)
3074 "Skip backward to nearest enclosing case item.
3075 Limit search to point LIM."
3081 (verilog-re-search-backward verilog-endcomment-reason-re
3084 ;; Try to find the real :
3085 (if (save-excursion (search-backward ":" lim1 t))
3091 (verilog-re-search-backward "\\(\\[\\)\\|\\(\\]\\)\\|\\(:\\)"
3095 (setq colon (1+ colon))
3097 (error "%s: unbalanced [" (verilog-point-text))))
3099 (setq colon (1- colon)))
3102 (setq colon (1+ colon)))
3104 ;; Skip back to beginning of case item
3105 (skip-chars-backward "\t ")
3106 (verilog-skip-backward-comment-or-string)
3111 (verilog-re-search-backward
3112 "\\<\\(case[zx]?\\)\\>\\|;\\|\\<end\\>" nil 'move)
3116 (goto-char (match-end 1))
3117 (verilog-forward-ws&directives)
3118 (if (looking-at "(")
3121 (verilog-forward-ws&directives)))
3124 (goto-char (match-end 0))
3125 (verilog-forward-ws&directives)
3128 (error "Malformed case item")
3130 (setq str (buffer-substring b e))
3134 "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
3135 (setq str (concat (substring str 0 e) "...")))
3144 (defun verilog-kill-existing-comment ()
3145 "Kill auto comment on this line."
3153 (search-forward "//" e t))))
3155 (delete-region (- b 2) e)))))
3157 (defconst verilog-directive-nest-re
3158 (concat "\\(`else\\>\\)\\|"
3159 "\\(`endif\\>\\)\\|"
3161 "\\(`ifdef\\>\\)\\|"
3162 "\\(`ifndef\\>\\)"))
3163 (defun verilog-set-auto-endcomments (indent-str kill-existing-comment)
3164 "Add ending comment with given INDENT-STR.
3165 With KILL-EXISTING-COMMENT, remove what was there before.
3166 Insert `// case: 7 ' or `// NAME ' on this line if appropriate.
3167 Insert `// case expr ' if this line ends a case block.
3168 Insert `// ifdef FOO ' if this line ends code conditional on FOO.
3169 Insert `// NAME ' if this line ends a function, task, module, primitive or interface named NAME."
3172 (; Comment close preprocessor directives
3174 (looking-at "\\(`endif\\)\\|\\(`else\\)")
3175 (or kill-existing-comment
3176 (not (save-excursion
3178 (search-backward "//" (verilog-get-beg-of-line) t)))))
3181 (else (if (match-end 2) "!" " "))
3184 (if kill-existing-comment
3185 (verilog-kill-existing-comment))
3186 (delete-horizontal-space)
3189 (while (and (/= nest 0)
3190 (verilog-re-search-backward verilog-directive-nest-re nil 'move))
3192 ((match-end 1) ; `else
3195 ((match-end 2) ; `endif
3196 (setq nest (1+ nest)))
3197 ((match-end 3) ; `if
3198 (setq nest (1- nest)))
3199 ((match-end 4) ; `ifdef
3200 (setq nest (1- nest)))
3201 ((match-end 5) ; `ifndef
3202 (setq nest (1- nest)))
3210 (skip-chars-forward "^ \t")
3211 (verilog-forward-syntactic-ws)
3214 (skip-chars-forward "a-zA-Z0-9_")
3218 (if (> (count-lines (point) b) verilog-minimum-comment-distance)
3219 (insert (concat " // " else m " " (buffer-substring b e))))
3221 (insert " // unmatched `else or `endif")
3225 (; Comment close case/class/function/task/module and named block
3226 (and (looking-at "\\<end")
3227 (or kill-existing-comment
3228 (not (save-excursion
3230 (search-backward "//" (verilog-get-beg-of-line) t)))))
3231 (let ((type (car indent-str)))
3232 (unless (eq type 'declaration)
3233 (unless (looking-at (concat "\\(" verilog-end-block-ordered-re "\\)[ \t]*:")) ;; ignore named ends
3234 (if (looking-at verilog-end-block-ordered-re)
3236 (;- This is a case block; search back for the start of this case
3237 (match-end 1) ;; of verilog-end-block-ordered-re
3240 (str "UNMATCHED!!"))
3242 (verilog-leap-to-head)
3244 ((looking-at "\\<randcase\\>")
3245 (setq str "randcase")
3248 (goto-char (match-end 1))
3251 (setq s (match-beginning 1))
3252 (setq f (progn (end-of-line)
3254 (setq str (buffer-substring s f)))
3256 (setq str (concat (buffer-substring (match-beginning 1) (match-end 1))
3258 (verilog-get-expr))))))
3260 (if kill-existing-comment
3261 (verilog-kill-existing-comment))
3262 (delete-horizontal-space)
3263 (insert (concat " // " str ))
3264 (if err (ding 't))))
3266 (;- This is a begin..end block
3267 (match-end 2) ;; of verilog-end-block-ordered-re
3268 (let ((str " // UNMATCHED !!")
3275 (verilog-leap-to-head)
3276 (setq there (point))
3277 (if (not (match-end 0))
3281 (if kill-existing-comment
3282 (verilog-kill-existing-comment))
3283 (delete-horizontal-space)
3288 (save-excursion (verilog-beg-of-defun) (point)))
3292 (;-- handle named block differently
3293 (looking-at verilog-named-block-re)
3294 (search-forward ":")
3295 (setq there (point))
3296 (setq str (verilog-get-expr))
3298 (setq str (concat " // block: " str )))
3300 ((verilog-in-case-region-p) ;-- handle case item differently
3302 (setq str (verilog-backward-case-item lim))
3303 (setq there (point))
3305 (setq str (concat " // case: " str )))
3307 (;- try to find "reason" for this begin
3311 (verilog-backward-token)
3312 (verilog-beg-of-statement-1)
3316 ((looking-at verilog-endcomment-reason-re)
3317 (setq there (match-end 0))
3319 (buffer-substring (match-beginning 0) (match-end 0)) " "))
3325 (if (and (verilog-continued-line)
3326 (looking-at "\\<repeat\\>\\|\\<wait\\>\\|\\<always\\>"))
3328 (goto-char (match-end 0))
3329 (setq there (point))
3332 (buffer-substring (match-beginning 0) (match-end 0)) " "
3333 (verilog-get-expr))))
3339 ( reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)")
3342 (while (verilog-re-search-backward reg nil 'move)
3344 ((match-end 1) ; begin
3345 (setq nest (1- nest)))
3346 ((match-end 2) ; end
3347 (setq nest (1+ nest)))
3351 (goto-char (match-end 0))
3352 (setq there (point))
3354 (setq str (verilog-get-expr))
3355 (setq str (concat " // else: !if" str ))
3364 ( reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)")
3367 (while (verilog-re-search-backward reg nil 'move)
3369 ((match-end 1) ; begin
3370 (setq nest (1- nest)))
3371 ((match-end 2) ; end
3372 (setq nest (1+ nest)))
3376 (goto-char (match-end 0))
3377 (setq there (point))
3379 (setq str (verilog-get-expr))
3380 (setq str (concat " // else: !if" str ))
3385 (;- task/function/initial et cetera
3388 (goto-char (match-end 0))
3389 (setq there (point))
3391 (setq str (verilog-get-expr))
3392 (setq str (concat " // " cntx str )))
3395 (setq str " // auto-endcomment confused "))
3399 (verilog-in-case-region-p) ;-- handle case item differently
3401 (setq there (point))
3403 (setq str (verilog-backward-case-item lim))))
3405 (setq str (concat " // case: " str )))
3407 ((verilog-in-fork-region-p)
3409 (setq str " // fork branch" ))
3411 ((looking-at "\\<end\\>")
3414 (verilog-forward-syntactic-ws)
3416 (setq str (verilog-get-expr))
3417 (setq str (concat " // " cntx str )))
3422 (if kill-existing-comment
3423 (verilog-kill-existing-comment))
3424 (delete-horizontal-space)
3426 (> (count-lines here there) verilog-minimum-comment-distance))
3430 (;- this is endclass, which can be nested
3431 (match-end 11) ;; of verilog-end-block-ordered-re
3434 ( reg "\\<\\(class\\)\\|\\(endclass\\)\\|\\(package\\|primitive\\|\\(macro\\)?module\\)\\>")
3439 (while (verilog-re-search-backward reg nil 'move)
3441 ((match-end 3) ; endclass
3443 (setq string "unmatched endclass")
3446 ((match-end 2) ; endclass
3447 (setq nest (1+ nest)))
3449 ((match-end 1) ; class
3450 (setq nest (1- nest))
3453 (goto-char (match-end 0))
3456 (skip-chars-forward "^ \t")
3457 (verilog-forward-ws&directives)
3460 (skip-chars-forward "a-zA-Z0-9_")
3462 (setq string (buffer-substring b e)))
3466 (insert (concat " // " string )))
3469 (;- this is end{function,generate,task,module,primitive,table,generate}
3470 ;- which can not be nested.
3472 (let (string reg (width nil))
3474 (if kill-existing-comment
3476 (verilog-kill-existing-comment)))
3477 (delete-horizontal-space)
3480 ((match-end 5) ;; of verilog-end-block-ordered-re
3481 (setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
3482 (setq width "\\(\\s-*\\(\\[[^]]*\\]\\)\\|\\(real\\(time\\)?\\)\\|\\(integer\\)\\|\\(time\\)\\)?")
3484 ((match-end 6) ;; of verilog-end-block-ordered-re
3485 (setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)"))
3486 ((match-end 7) ;; of verilog-end-block-ordered-re
3487 (setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\<endmodule\\>"))
3488 ((match-end 8) ;; of verilog-end-block-ordered-re
3489 (setq reg "\\(\\<primitive\\>\\)\\|\\(\\<\\(endprimitive\\|package\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3490 ((match-end 9) ;; of verilog-end-block-ordered-re
3491 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<\\(endinterface\\|package\\|primitive\\|\\(macro\\)?module\\)\\>\\)"))
3492 ((match-end 10) ;; of verilog-end-block-ordered-re
3493 (setq reg "\\(\\<package\\>\\)\\|\\(\\<\\(endpackage\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3494 ((match-end 11) ;; of verilog-end-block-ordered-re
3495 (setq reg "\\(\\<class\\>\\)\\|\\(\\<\\(endclass\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3496 ((match-end 12) ;; of verilog-end-block-ordered-re
3497 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<\\(endcovergroup\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3498 ((match-end 13) ;; of verilog-end-block-ordered-re
3499 (setq reg "\\(\\<program\\>\\)\\|\\(\\<\\(endprogram\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3500 ((match-end 14) ;; of verilog-end-block-ordered-re
3501 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<\\(endsequence\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3502 ((match-end 15) ;; of verilog-end-block-ordered-re
3503 (setq reg "\\(\\<clocking\\>\\)\\|\\<endclocking\\>"))
3505 (t (error "Problem in verilog-set-auto-endcomments"))
3509 (verilog-re-search-backward reg nil 'move)
3513 (skip-chars-forward "^ \t")
3514 (verilog-forward-ws&directives)
3515 (if (and width (looking-at width))
3517 (goto-char (match-end 0))
3518 (verilog-forward-ws&directives)
3522 (skip-chars-forward "a-zA-Z0-9_")
3524 (setq string (buffer-substring b e)))
3527 (setq string "unmatched end(function|task|module|primitive|interface|package|class|clocking)")))))
3529 (insert (concat " // " string )))
3532 (defun verilog-get-expr()
3533 "Grab expression at point, e.g, case ( a | b & (c ^d))"
3535 (verilog-forward-syntactic-ws)
3536 (skip-chars-forward " \t")
3542 (verilog-forward-syntactic-ws)
3543 (if (looking-at "(")
3546 (while (and (/= par 0)
3547 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
3550 (setq par (1+ par)))
3552 (setq par (1- par)))))))
3556 (while (and (/= par 0)
3557 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
3560 (setq par (1+ par)))
3562 (setq par (1- par)))))
3566 (while (and (/= par 0)
3567 (verilog-re-search-forward "\\(\\[\\)\\|\\(\\]\\)" nil 'move))
3570 (setq par (1+ par)))
3572 (setq par (1- par)))))
3573 (verilog-forward-syntactic-ws)
3574 (skip-chars-forward "^ \t\n\f")
3576 ((looking-at "/[/\\*]")
3579 (skip-chars-forward "^: \t\n\f")
3582 (str (buffer-substring b e)))
3583 (if (setq e (string-match "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
3584 (setq str (concat (substring str 0 e) "...")))
3587 (defun verilog-expand-vector ()
3588 "Take a signal vector on the current line and expand it to multiple lines.
3589 Useful for creating tri's and other expanded fields."
3591 (verilog-expand-vector-internal "[" "]"))
3593 (defun verilog-expand-vector-internal (bra ket)
3594 "Given BRA, the start brace and KET, the end brace, expand one line into many lines."
3597 (let ((signal-string (buffer-substring (point)
3599 (end-of-line) (point)))))
3603 "\\([0-9]*\\)\\(:[0-9]*\\|\\)\\(::[0-9---]*\\|\\)"
3605 "\\(.*\\)$") signal-string)
3606 (let* ((sig-head (match-string 1 signal-string))
3607 (vec-start (string-to-number (match-string 2 signal-string)))
3608 (vec-end (if (= (match-beginning 3) (match-end 3))
3611 (substring signal-string (1+ (match-beginning 3))
3614 (if (= (match-beginning 4) (match-end 4))
3617 (substring signal-string (+ 2 (match-beginning 4))
3619 (sig-tail (match-string 5 signal-string))
3624 (let ((tmp vec-start))
3625 (setq vec-start vec-end
3627 vec-range (- vec-range))))
3628 (if (< vec-end vec-start)
3629 (while (<= vec-end vec-start)
3630 (setq vec (append vec (list vec-start)))
3631 (setq vec-start (- vec-start vec-range)))
3632 (while (<= vec-start vec-end)
3633 (setq vec (append vec (list vec-start)))
3634 (setq vec-start (+ vec-start vec-range))))
3636 ;; Delete current line
3637 (delete-region (point) (progn (forward-line 0) (point)))
3641 (insert (concat sig-head bra
3642 (int-to-string (car vec)) ket sig-tail "\n"))
3643 (setq vec (cdr vec)))
3648 (defun verilog-strip-comments ()
3649 "Strip all comments from the verilog code."
3651 (goto-char (point-min))
3652 (while (re-search-forward "//" nil t)
3653 (if (verilog-within-string)
3654 (re-search-forward "\"" nil t)
3655 (if (verilog-in-star-comment-p)
3656 (re-search-forward "\*/" nil t)
3657 (let ((bpt (- (point) 2)))
3659 (delete-region bpt (point))))))
3661 (goto-char (point-min))
3662 (while (re-search-forward "/\\*" nil t)
3663 (if (verilog-within-string)
3664 (re-search-forward "\"" nil t)
3665 (let ((bpt (- (point) 2)))
3666 (re-search-forward "\\*/")
3667 (delete-region bpt (point))))))
3669 (defun verilog-one-line ()
3670 "Convert structural verilog instances to occupy one line."
3672 (goto-char (point-min))
3673 (while (re-search-forward "\\([^;]\\)[ \t]*\n[ \t]*" nil t)
3674 (replace-match "\\1 " nil nil)))
3676 (defun verilog-linter-name ()
3677 "Return name of linter, either surelint or verilint."
3678 (let ((compile-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
3680 (lint-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
3682 (cond ((equal compile-word1 "surelint") `surelint)
3683 ((equal compile-word1 "verilint") `verilint)
3684 ((equal lint-word1 "surelint") `surelint)
3685 ((equal lint-word1 "verilint") `verilint)
3686 (t `surelint)))) ;; back compatibility
3688 (defun verilog-lint-off ()
3689 "Convert a Verilog linter warning line into a disable statement.
3691 pci_bfm_null.v, line 46: Unused input: pci_rst_
3692 becomes a comment for the appropriate tool.
3694 The first word of the `compile-command' or `verilog-linter'
3695 variables are used to determine which product is being used.
3697 See \\[verilog-surelint-off] and \\[verilog-verilint-off]."
3699 (let ((linter (verilog-linter-name)))
3700 (cond ((equal linter `surelint)
3701 (verilog-surelint-off))
3702 ((equal linter `verilint)
3703 (verilog-verilint-off))
3704 (t (error "Linter name not set")))))
3706 (defvar compilation-last-buffer)
3708 (defun verilog-surelint-off ()
3709 "Convert a SureLint warning line into a disable statement.
3710 Run from Verilog source window; assumes there is a *compile* buffer
3711 with point set appropriately.
3714 WARNING [STD-UDDONX]: xx.v, line 8: output out is never assigned.
3716 // surefire lint_line_off UDDONX"
3718 (let ((buff (if (boundp 'next-error-last-buffer)
3719 next-error-last-buffer
3720 compilation-last-buffer)))
3721 (when (buffer-live-p buff)
3722 ;; FIXME with-current-buffer?
3724 (switch-to-buffer buff)
3727 (looking-at "\\(INFO\\|WARNING\\|ERROR\\) \\[[^-]+-\\([^]]+\\)\\]: \\([^,]+\\), line \\([0-9]+\\): \\(.*\\)$")
3728 (let* ((code (match-string 2))
3729 (file (match-string 3))
3730 (line (match-string 4))
3731 (buffer (get-file-buffer file))
3736 (and (file-exists-p file)
3737 (find-file-noselect file)))
3739 (let* ((pop-up-windows t))
3740 (let ((name (expand-file-name
3742 (format "Find this error in: (default %s) "
3745 (if (file-directory-p name)
3746 (setq name (expand-file-name filename name)))
3748 (and (file-exists-p name)
3749 (find-file-noselect name))))))))
3750 (switch-to-buffer buffer)
3751 (goto-line (string-to-number line))
3755 ((verilog-in-slash-comment-p)
3756 (re-search-backward "//")
3758 ((looking-at "// surefire lint_off_line ")
3759 (goto-char (match-end 0))
3760 (let ((lim (save-excursion (end-of-line) (point))))
3761 (if (re-search-forward code lim 'move)
3763 (insert (concat " " code)))))
3766 ((verilog-in-star-comment-p)
3767 (re-search-backward "/\*")
3768 (insert (format " // surefire lint_off_line %6s" code ))
3771 (insert (format " // surefire lint_off_line %6s" code ))
3774 (defun verilog-verilint-off ()
3775 "Convert a Verilint warning line into a disable statement.
3778 (W240) pci_bfm_null.v, line 46: Unused input: pci_rst_
3780 //Verilint 240 off // WARNING: Unused input"
3784 (when (looking-at "\\(.*\\)([WE]\\([0-9A-Z]+\\)).*,\\s +line\\s +[0-9]+:\\s +\\([^:\n]+\\):?.*$")
3785 (replace-match (format
3786 ;; %3s makes numbers 1-999 line up nicely
3787 "\\1//Verilint %3s off // WARNING: \\3"
3790 (verilog-indent-line))))
3792 (defun verilog-auto-save-compile ()
3793 "Update automatics with \\[verilog-auto], save the buffer, and compile."
3795 (verilog-auto) ; Always do it for safety
3797 (compile compile-command))
3805 (defmacro verilog-batch-error-wrapper (&rest body)
3806 "Execute BODY and add error prefix to any errors found.
3807 This lets programs calling batch mode to easily extract error messages."
3808 `(condition-case err
3811 (error "%%Error: %s%s" (error-message-string err)
3812 (if (featurep 'xemacs) "\n" ""))))) ;; xemacs forgets to add a newline
3814 (defun verilog-batch-execute-func (funref)
3815 "Internal processing of a batch command, running FUNREF on all command arguments."
3816 (verilog-batch-error-wrapper
3817 ;; General globals needed
3818 (setq make-backup-files nil)
3819 (setq-default make-backup-files nil)
3820 (setq enable-local-variables t)
3821 (setq enable-local-eval t)
3822 ;; Make sure any sub-files we read get proper mode
3823 (setq default-major-mode `verilog-mode)
3824 ;; Ditto files already read in
3826 (when (buffer-file-name buf)
3831 ;; Process the files
3832 (mapcar '(lambda (buf)
3833 (when (buffer-file-name buf)
3835 (if (not (file-exists-p (buffer-file-name buf)))
3837 (concat "File not found: " (buffer-file-name buf))))
3838 (message (concat "Processing " (buffer-file-name buf)))
3844 (defun verilog-batch-auto ()
3845 "For use with --batch, perform automatic expansions as a stand-alone tool.
3846 This sets up the appropriate Verilog-Mode environment, updates automatics
3847 with \\[verilog-auto] on all command-line files, and saves the buffers.
3848 For proper results, multiple filenames need to be passed on the command
3849 line in bottom-up order."
3850 (unless noninteractive
3851 (error "Use verilog-batch-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
3852 (verilog-batch-execute-func `verilog-auto))
3854 (defun verilog-batch-delete-auto ()
3855 "For use with --batch, perform automatic deletion as a stand-alone tool.
3856 This sets up the appropriate Verilog-Mode environment, deletes automatics
3857 with \\[verilog-delete-auto] on all command-line files, and saves the buffers."
3858 (unless noninteractive
3859 (error "Use verilog-batch-delete-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
3860 (verilog-batch-execute-func `verilog-delete-auto))
3862 (defun verilog-batch-inject-auto ()
3863 "For use with --batch, perform automatic injection as a stand-alone tool.
3864 This sets up the appropriate Verilog-Mode environment, injects new automatics
3865 with \\[verilog-inject-auto] on all command-line files, and saves the buffers.
3866 For proper results, multiple filenames need to be passed on the command
3867 line in bottom-up order."
3868 (unless noninteractive
3869 (error "Use verilog-batch-inject-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
3870 (verilog-batch-execute-func `verilog-inject-auto))
3872 (defun verilog-batch-indent ()
3873 "For use with --batch, reindent an a entire file as a stand-alone tool.
3874 This sets up the appropriate Verilog-Mode environment, calls
3875 \\[verilog-indent-buffer] on all command-line files, and saves the buffers."
3876 (unless noninteractive
3877 (error "Use verilog-batch-indent only with --batch")) ;; Otherwise we'd mess up buffer modes
3878 (verilog-batch-execute-func `verilog-indent-buffer))
3884 (defconst verilog-indent-alist
3885 '((block . (+ ind verilog-indent-level))
3886 (case . (+ ind verilog-case-indent))
3887 (cparenexp . (+ ind verilog-indent-level))
3888 (cexp . (+ ind verilog-cexp-indent))
3889 (defun . verilog-indent-level-module)
3890 (declaration . verilog-indent-level-declaration)
3891 (directive . (verilog-calculate-indent-directive))
3892 (tf . verilog-indent-level)
3893 (behavioral . (+ verilog-indent-level-behavioral verilog-indent-level-module))
3896 (comment . (verilog-comment-indent))
3900 (defun verilog-continued-line-1 (lim)
3901 "Return true if this is a continued line.
3902 Set point to where line starts. Limit search to point LIM."
3903 (let ((continued 't))
3904 (if (eq 0 (forward-line -1))
3907 (verilog-backward-ws&directives lim)
3909 (setq continued nil)
3910 (setq continued (verilog-backward-token))))
3911 (setq continued nil))
3914 (defun verilog-calculate-indent ()
3915 "Calculate the indent of the current Verilog line.
3916 Examine previous lines. Once a line is found that is definitive as to the
3917 type of the current line, return that lines' indent level and its
3918 type. Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
3920 (let* ((starting_position (point))
3922 (begin (looking-at "[ \t]*begin\\>"))
3923 (lim (save-excursion (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)" nil t)))
3924 (type (catch 'nesting
3925 ;; Keep working backwards until we can figure out
3926 ;; what type of statement this is.
3927 ;; Basically we need to figure out
3928 ;; 1) if this is a continuation of the previous line;
3929 ;; 2) are we in a block scope (begin..end)
3931 ;; if we are in a comment, done.
3932 (if (verilog-in-star-comment-p)
3933 (throw 'nesting 'comment))
3935 ;; if we have a directive, done.
3936 (if (save-excursion (beginning-of-line) (looking-at verilog-directive-re-1))
3937 (throw 'nesting 'directive))
3939 ;; unless we are in the newfangled coverpoint or constraint blocks
3940 ;; if we are in a parenthesized list, and the user likes to indent these, return.
3942 verilog-indent-lists
3943 (not (verilog-in-coverage))
3946 (throw 'nesting 'block))
3949 ;; See if we are continuing a previous line
3951 ;; trap out if we crawl off the top of the buffer
3952 (if (bobp) (throw 'nesting 'cpp))
3954 (if (verilog-continued-line-1 lim)
3957 (not (looking-at verilog-complete-reg))
3958 (verilog-continued-line-1 lim))
3959 (progn (goto-char sp)
3960 (throw 'nesting 'cexp))
3965 (not verilog-indent-begin-after-if)
3966 (looking-at verilog-no-indent-begin-re))
3969 (skip-chars-forward " \t")
3970 (throw 'nesting 'statement))
3972 (throw 'nesting 'cexp))))
3973 ;; not a continued line
3974 (goto-char starting_position))
3976 (if (looking-at "\\<else\\>")
3977 ;; search back for governing if, striding across begin..end pairs
3980 (while (verilog-re-search-backward verilog-ends-re nil 'move)
3982 ((match-end 1) ; else, we're in deep
3983 (setq elsec (1+ elsec)))
3985 (setq elsec (1- elsec))
3987 (if verilog-align-ifelse
3988 (throw 'nesting 'statement)
3989 (progn ;; back up to first word on this line
3991 (verilog-forward-syntactic-ws)
3992 (throw 'nesting 'statement)))))
3994 ; try to leap back to matching outward block by striding across
3995 ; indent level changing tokens then immediately
3996 ; previous line governs indentation.
3997 (let (( reg) (nest 1))
3998 ;; verilog-ends => else|if|end|join(_any|_none|)|endcase|endclass|endtable|endspecify|endfunction|endtask|endgenerate|endgroup
4000 ((match-end 3) ; end
4001 ;; Search back for matching begin
4002 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
4003 ((match-end 4) ; endcase
4004 ;; Search back for matching case
4005 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
4006 ((match-end 5) ; endfunction
4007 ;; Search back for matching function
4008 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
4009 ((match-end 6) ; endtask
4010 ;; Search back for matching task
4011 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
4012 ((match-end 7) ; endspecify
4013 ;; Search back for matching specify
4014 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
4015 ((match-end 8) ; endtable
4016 ;; Search back for matching table
4017 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
4018 ((match-end 9) ; endgenerate
4019 ;; Search back for matching generate
4020 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
4021 ((match-end 10) ; joins
4022 ;; Search back for matching fork
4023 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|none\\)?\\>\\)" ))
4024 ((match-end 11) ; class
4025 ;; Search back for matching class
4026 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
4027 ((match-end 12) ; covergroup
4028 ;; Search back for matching covergroup
4029 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
4032 (while (verilog-re-search-backward reg nil 'move)
4034 ((match-end 1) ; begin
4035 (setq nest (1- nest))
4038 ((match-end 2) ; end
4039 (setq nest (1+ nest)))))
4043 (throw 'nesting (verilog-calc-1))
4048 ;; Return type of block and indent level.
4051 (if (> par 0) ; Unclosed Parenthesis
4052 (list 'cparenexp par)
4055 (list type (verilog-case-indent-level)))
4056 ((eq type 'statement)
4057 (list type (current-column)))
4061 (list type (verilog-current-indent-level)))))
4063 (defun verilog-wai ()
4064 "Show matching nesting block for debugging."
4067 (let ((nesting (verilog-calc-1)))
4068 (message "You are at nesting %s" nesting))))
4070 (defun verilog-calc-1 ()
4072 (while (verilog-re-search-backward (concat "\\({\\|}\\|" verilog-indent-re "\\)") nil 'move)
4074 ((equal (char-after) ?\{)
4075 (if (verilog-at-constraint-p)
4076 (throw 'nesting 'block)
4078 ((equal (char-after) ?\})
4080 (let ((there (verilog-at-close-constraint-p)))
4081 (if there (goto-char there))))
4083 ((looking-at verilog-beg-block-re-ordered)
4085 ((match-end 2) ; *sigh* could be "unique case" or "priority casex"
4086 (let ((here (point)))
4087 (verilog-beg-of-statement)
4088 (if (looking-at verilog-extended-case-re)
4089 (throw 'nesting 'case)
4091 (throw 'nesting 'case))
4093 ;; need to consider typedef struct here...
4094 ((looking-at "\\<class\\|struct\\|function\\|task\\|property\\>")
4095 ; *sigh* These words have an optional prefix:
4096 ; extern {virtual|protected}? function a();
4097 ; assert property (p_1);
4098 ; typedef class foo;
4099 ; and we don't want to confuse this with
4104 (let ((here (point)))
4106 (verilog-beg-of-statement)
4107 (if (= (point) here)
4108 (throw 'nesting 'block)))))
4109 (t (throw 'nesting 'block))))
4111 ((looking-at verilog-end-block-re)
4112 (verilog-leap-to-head)
4113 (if (verilog-in-case-region-p)
4115 (verilog-leap-to-case-head)
4116 (if (looking-at verilog-case-re)
4117 (throw 'nesting 'case)))))
4119 ((looking-at (if (verilog-in-generate-region-p)
4120 verilog-defun-level-not-generate-re
4121 verilog-defun-level-re))
4122 (throw 'nesting 'defun))
4124 ((looking-at verilog-cpp-level-re)
4125 (throw 'nesting 'cpp))
4128 (throw 'nesting 'cpp))))
4129 (throw 'nesting 'cpp)))
4131 (defun verilog-calculate-indent-directive ()
4132 "Return indentation level for directive.
4133 For speed, the searcher looks at the last directive, not the indent
4134 of the appropriate enclosing block."
4135 (let ((base -1) ;; Indent of the line that determines our indentation
4136 (ind 0) ;; Relative offset caused by other directives (like `endif on same line as `else)
4138 ;; Start at current location, scan back for another directive
4142 (while (and (< base 0)
4143 (verilog-re-search-backward verilog-directive-re nil t))
4144 (cond ((save-excursion (skip-chars-backward " \t") (bolp))
4145 (setq base (current-indentation))
4147 (cond ((and (looking-at verilog-directive-end) (< base 0)) ;; Only matters when not at BOL
4148 (setq ind (- ind verilog-indent-level-directive)))
4149 ((and (looking-at verilog-directive-middle) (>= base 0)) ;; Only matters when at BOL
4150 (setq ind (+ ind verilog-indent-level-directive)))
4151 ((looking-at verilog-directive-begin)
4152 (setq ind (+ ind verilog-indent-level-directive)))))
4153 ;; Adjust indent to starting indent of critical line
4154 (setq ind (max 0 (+ ind base))))
4158 (skip-chars-forward " \t")
4159 (cond ((or (looking-at verilog-directive-middle)
4160 (looking-at verilog-directive-end))
4161 (setq ind (max 0 (- ind verilog-indent-level-directive))))))
4164 (defun verilog-leap-to-case-head ()
4167 (verilog-re-search-backward "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" nil 'move)
4170 (setq nest (1- nest)))
4172 (setq nest (1+ nest)))
4177 (defun verilog-leap-to-head ()
4178 "Move point to the head of this block; jump from end to matching begin,
4179 from endcase to matching case, and so on."
4184 ((looking-at "\\<end\\>")
4185 ;; 1: Search back for matching begin
4186 (setq reg (concat "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|"
4187 "\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))
4188 ((looking-at "\\<endcase\\>")
4189 ;; 2: Search back for matching case
4190 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)" ))
4191 ((looking-at "\\<join\\(_any\\|_none\\)?\\>")
4192 ;; 3: Search back for matching fork
4193 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
4194 ((looking-at "\\<endclass\\>")
4195 ;; 4: Search back for matching class
4196 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
4197 ((looking-at "\\<endtable\\>")
4198 ;; 5: Search back for matching table
4199 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
4200 ((looking-at "\\<endspecify\\>")
4201 ;; 6: Search back for matching specify
4202 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
4203 ((looking-at "\\<endfunction\\>")
4204 ;; 7: Search back for matching function
4205 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
4206 ((looking-at "\\<endgenerate\\>")
4207 ;; 8: Search back for matching generate
4208 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
4209 ((looking-at "\\<endtask\\>")
4210 ;; 9: Search back for matching task
4211 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
4212 ((looking-at "\\<endgroup\\>")
4213 ;; 10: Search back for matching covergroup
4214 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
4215 ((looking-at "\\<endproperty\\>")
4216 ;; 11: Search back for matching property
4217 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
4218 ((looking-at "\\<endinterface\\>")
4219 ;; 12: Search back for matching interface
4220 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<endinterface\\>\\)" ))
4221 ((looking-at "\\<endsequence\\>")
4222 ;; 12: Search back for matching sequence
4223 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" ))
4224 ((looking-at "\\<endclocking\\>")
4225 ;; 12: Search back for matching clocking
4226 (setq reg "\\(\\<clocking\\)\\|\\(\\<endclocking\\>\\)" ))
4231 (while (verilog-re-search-backward reg nil 'move)
4233 ((match-end 1) ; begin
4234 (setq nest (1- nest))
4236 ;; Now previous line describes syntax
4241 ((match-end 2) ; end
4242 (setq nest (1+ nest)))
4244 ;; endcase, jump to case
4246 (setq nest (1+ nest))
4248 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
4250 ;; join, jump to fork
4252 (setq nest (1+ nest))
4254 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
4257 (defun verilog-continued-line ()
4258 "Return true if this is a continued line.
4259 Set point to where line starts"
4260 (let ((continued 't))
4261 (if (eq 0 (forward-line -1))
4264 (verilog-backward-ws&directives)
4266 (setq continued nil)
4267 (while (and continued
4269 (skip-chars-backward " \t")
4271 (setq continued (verilog-backward-token))
4274 (setq continued nil))
4277 (defun verilog-backward-token ()
4278 "Step backward token, returning true if we are now at an end of line token."
4280 (verilog-backward-syntactic-ws)
4284 (;-- Anything ending in a ; is complete
4285 (= (preceding-char) ?\;)
4287 (; If a "}" is prefixed by a ";", then this is a complete statement
4288 ; i.e.: constraint foo { a = b; }
4289 (= (preceding-char) ?\})
4292 (verilog-at-close-constraint-p))
4294 (;-- constraint foo { a = b }
4295 ; is a complete statement. *sigh*
4296 (= (preceding-char) ?\{)
4299 (not (verilog-at-constraint-p)))
4301 (;-- Could be 'case (foo)' or 'always @(bar)' which is complete
4302 ; also could be simply '@(foo)'
4304 ; (b, ... which ISN'T complete
4305 ;;;; Do we need this???
4306 (= (preceding-char) ?\))
4309 (backward-up-list 1)
4310 (verilog-backward-syntactic-ws)
4311 (let ((back (point)))
4314 ((looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|case\\(\\|[xz]\\)\\|for\\(\\|each\\|ever\\)\\|i\\(f\\|nitial\\)\\|repeat\\|while\\)\\>")
4315 (not (looking-at "\\<randcase\\>\\|\\<case[xz]?\\>[^:]")))
4319 ((= (preceding-char) ?\@)
4322 (verilog-backward-token)
4323 (not (looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|initial\\|while\\)\\>"))))
4324 ((= (preceding-char) ?\#)
4330 (;-- any of begin|initial|while are complete statements; 'begin : foo' is also complete
4334 ((looking-at "\\<else\\>")
4336 ((looking-at verilog-indent-re)
4341 (verilog-backward-syntactic-ws)
4343 ((= (preceding-char) ?\:)
4345 (verilog-backward-syntactic-ws)
4347 (if (looking-at verilog-nameable-item-re )
4351 ((= (preceding-char) ?\#)
4354 ((= (preceding-char) ?\`)
4363 (defun verilog-backward-syntactic-ws (&optional bound)
4364 "Backward skip over syntactic whitespace for Emacs 19.
4365 Optional BOUND limits search."
4367 (let* ((bound (or bound (point-min))) (here bound) )
4368 (if (< bound (point))
4370 (narrow-to-region bound (point))
4371 (while (/= here (point))
4373 (verilog-skip-backward-comments)
4378 (defun verilog-forward-syntactic-ws (&optional bound)
4379 "Forward skip over syntactic whitespace for Emacs 19.
4380 Optional BOUND limits search."
4382 (let* ((bound (or bound (point-max)))
4385 (if (> bound (point))
4387 (narrow-to-region (point) bound)
4388 (while (/= here (point))
4390 (forward-comment (buffer-size))
4394 (defun verilog-backward-ws&directives (&optional bound)
4395 "Backward skip over syntactic whitespace and compiler directives for Emacs 19.
4396 Optional BOUND limits search."
4398 (let* ((bound (or bound (point-min)))
4401 (if (< bound (point))
4405 (parse-partial-sexp (point-min) (point)))))
4407 ((nth 7 state) ;; in // comment
4408 (verilog-re-search-backward "//" nil 'move)
4409 (skip-chars-backward "/"))
4410 ((nth 4 state) ;; in /* */ comment
4411 (verilog-re-search-backward "/\*" nil 'move))))
4412 (narrow-to-region bound (point))
4413 (while (/= here (point))
4415 (verilog-skip-backward-comments)
4420 ((verilog-within-translate-off)
4421 (verilog-back-to-start-translate-off (point-min)))
4422 ((looking-at verilog-directive-re-1)
4426 (if p (goto-char p))
4430 (defun verilog-forward-ws&directives (&optional bound)
4431 "Forward skip over syntactic whitespace and compiler directives for Emacs 19.
4432 Optional BOUND limits search."
4434 (let* ((bound (or bound (point-max)))
4438 (if (> bound (point))
4442 (parse-partial-sexp (point-min) (point)))))
4444 ((nth 7 state) ;; in // comment
4445 (verilog-re-search-forward "//" nil 'move))
4446 ((nth 4 state) ;; in /* */ comment
4447 (verilog-re-search-forward "/\*" nil 'move))))
4448 (narrow-to-region (point) bound)
4449 (while (/= here (point))
4452 (forward-comment (buffer-size))
4455 (if (looking-at verilog-directive-re-1)
4458 (beginning-of-line 2))
4462 (defun verilog-in-comment-p ()
4463 "Return true if in a star or // comment."
4466 (parse-partial-sexp (point-min) (point)))))
4467 (or (nth 4 state) (nth 7 state))))
4469 (defun verilog-in-star-comment-p ()
4470 "Return true if in a star comment."
4473 (parse-partial-sexp (point-min) (point)))))
4475 (nth 4 state) ; t if in a comment of style a // or b /**/
4477 (nth 7 state) ; t if in a comment of style b /**/
4480 (defun verilog-in-slash-comment-p ()
4481 "Return true if in a slash comment."
4484 (parse-partial-sexp (point-min) (point)))))
4487 (defun verilog-in-comment-or-string-p ()
4488 "Return true if in a string or comment."
4491 (parse-partial-sexp (point-min) (point)))))
4492 (or (nth 3 state) (nth 4 state) (nth 7 state)))) ; Inside string or comment)
4494 (defun verilog-in-escaped-name-p ()
4495 "Return true if in an escaped name."
4498 (skip-chars-backward "^ \t\n\f")
4499 (if (equal (char-after (point) ) ?\\ )
4503 (defun verilog-in-paren ()
4504 "Return true if in a parenthetical expression."
4507 (parse-partial-sexp (point-min) (point)))))
4508 (> (nth 0 state) 0 )))
4510 (defun verilog-in-coverage ()
4511 "Return true if in a constraint or coverpoint expression."
4514 (if (verilog-in-paren)
4516 (backward-up-list 1)
4517 (verilog-at-constraint-p)
4520 (defun verilog-at-close-constraint-p ()
4521 "If at the } that closes a constraint or covergroup, return true."
4523 (equal (char-after) ?\})
4527 (verilog-backward-ws&directives)
4528 (if (equal (char-before) ?\;)
4532 (defun verilog-at-constraint-p ()
4533 "If at the { of a constraint or coverpoint definition, return true, moving point to constraint."
4536 (equal (char-after) ?\{)
4538 (progn (backward-char 1)
4539 (verilog-backward-ws&directives)
4540 (equal (char-before) ?\;))
4543 (verilog-re-search-backward "\\<constraint\\|coverpoint\\|cross\\>" nil 'move)
4549 (defun verilog-parenthesis-depth ()
4550 "Return non zero if in parenthetical-expression."
4552 (nth 1 (parse-partial-sexp (point-min) (point)))))
4555 (defun verilog-skip-forward-comment-or-string ()
4556 "Return true if in a string or comment."
4559 (parse-partial-sexp (point-min) (point)))))
4561 ((nth 3 state) ;Inside string
4562 (goto-char (nth 3 state))
4564 ((nth 7 state) ;Inside // comment
4567 ((nth 4 state) ;Inside any comment (hence /**/)
4568 (search-forward "*/"))
4572 (defun verilog-skip-backward-comment-or-string ()
4573 "Return true if in a string or comment."
4576 (parse-partial-sexp (point-min) (point)))))
4578 ((nth 3 state) ;Inside string
4579 (search-backward "\"")
4581 ((nth 7 state) ;Inside // comment
4582 (search-backward "//")
4583 (skip-chars-backward "/")
4585 ((nth 4 state) ;Inside /* */ comment
4586 (search-backward "/*")
4591 (defun verilog-skip-backward-comments ()
4592 "Return true if a comment was skipped."
4598 (parse-partial-sexp (point-min) (point)))))
4600 ((nth 7 state) ;Inside // comment
4601 (search-backward "//")
4602 (skip-chars-backward "/")
4603 (skip-chars-backward " \t\n\f")
4605 ((nth 4 state) ;Inside /* */ comment
4606 (search-backward "/*")
4607 (skip-chars-backward " \t\n\f")
4610 (= (char-before) ?\/)
4611 (= (char-before (1- (point))) ?\*)
4613 (goto-char (- (point) 2))
4616 (skip-chars-backward " \t\n\f")
4619 (defun verilog-skip-forward-comment-p ()
4620 "If in comment, move to end and return true."
4625 (parse-partial-sexp (point-min) (point))))
4629 ((nth 7 state) ;Inside // comment
4633 ((nth 4 state) ;Inside any comment
4638 (defun verilog-indent-line-relative ()
4639 "Cheap version of indent line.
4640 Only look at a few lines to determine indent level."
4644 (if (looking-at "^[ \t]*$")
4645 (cond ;- A blank line; No need to be too smart.
4647 (setq indent-str (list 'cpp 0)))
4648 ((verilog-continued-line)
4649 (let ((sp1 (point)))
4650 (if (verilog-continued-line)
4654 indent-str (list 'statement (verilog-current-indent-level))))
4656 (setq indent-str (list 'block (verilog-current-indent-level)))))
4659 (setq indent-str (verilog-calculate-indent))))
4660 (progn (skip-chars-forward " \t")
4661 (setq indent-str (verilog-calculate-indent))))
4662 (verilog-do-indent indent-str)))
4664 (defun verilog-indent-line ()
4665 "Indent for special part of code."
4666 (verilog-do-indent (verilog-calculate-indent)))
4668 (defun verilog-do-indent (indent-str)
4669 (let ((type (car indent-str))
4670 (ind (car (cdr indent-str))))
4672 (; handle continued exp
4674 (let ((here (point)))
4675 (verilog-backward-syntactic-ws)
4678 (= (preceding-char) ?\,)
4679 (= (preceding-char) ?\])
4681 (verilog-beg-of-statement-1)
4682 (looking-at verilog-declaration-re)))
4687 (verilog-beg-of-statement-1)
4689 (if (looking-at verilog-declaration-re)
4690 (progn ;; we have multiple words
4691 (goto-char (match-end 0))
4692 (skip-chars-forward " \t")
4694 ((and verilog-indent-declaration-macros
4695 (= (following-char) ?\`))
4699 (skip-chars-forward " \t")))
4700 ((= (following-char) ?\[)
4703 (backward-up-list -1)
4704 (skip-chars-forward " \t")))
4709 (+ (current-column) verilog-cexp-indent))
4712 (indent-line-to val))
4714 ((= (preceding-char) ?\) )
4716 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
4717 (indent-line-to val)))
4721 (verilog-beg-of-statement-1)
4722 (if (and (< (point) here)
4723 (verilog-re-search-forward "=[ \\t]*" here 'move))
4724 (setq val (current-column))
4725 (setq val (eval (cdr (assoc type verilog-indent-alist)))))
4727 (indent-line-to val)))
4730 (; handle inside parenthetical expressions
4731 (eq type 'cparenexp)
4732 (let ((val (save-excursion
4733 (backward-up-list 1)
4735 (skip-chars-forward " \t")
4737 (indent-line-to val)
4738 (if (and (not (verilog-in-struct-region-p))
4739 (looking-at verilog-declaration-re))
4740 (verilog-indent-declaration ind))
4743 (;-- Handle the ends
4745 (looking-at verilog-end-block-re )
4746 (verilog-at-close-constraint-p))
4747 (let ((val (if (eq type 'statement)
4748 (- ind verilog-indent-level)
4750 (indent-line-to val)))
4752 (;-- Case -- maybe line 'em up
4753 (and (eq type 'case) (not (looking-at "^[ \t]*$")))
4756 ((looking-at "\\<endcase\\>")
4757 (indent-line-to ind))
4759 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
4760 (indent-line-to val))))))
4763 (and (eq type 'defun)
4764 (looking-at verilog-zero-indent-re))
4771 (looking-at verilog-declaration-re))
4772 (verilog-indent-declaration ind))
4774 (;-- Everything else
4776 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
4777 (indent-line-to val)))
4779 (if (looking-at "[ \t]+$")
4780 (skip-chars-forward " \t"))
4781 indent-str ; Return indent data
4784 (defun verilog-current-indent-level ()
4785 "Return the indent-level the current statement has."
4789 (setq par-pos (verilog-parenthesis-depth))
4793 (setq par-pos (verilog-parenthesis-depth)))
4794 (skip-chars-forward " \t")
4797 (defun verilog-case-indent-level ()
4798 "Return the indent-level the current statement has.
4799 Do not count named blocks or case-statements."
4801 (skip-chars-forward " \t")
4803 ((looking-at verilog-named-block-re)
4805 ((and (not (looking-at verilog-case-re))
4806 (looking-at "^[^:;]+[ \t]*:"))
4807 (verilog-re-search-forward ":" nil t)
4808 (skip-chars-forward " \t")
4811 (current-column)))))
4813 (defun verilog-indent-comment ()
4814 "Indent current line as comment."
4817 ((verilog-in-star-comment-p)
4819 (re-search-backward "/\\*" nil t)
4820 (1+(current-column))))
4825 (re-search-backward "//" nil t)
4828 (indent-line-to stcol)
4831 (defun verilog-more-comment ()
4832 "Make more comment lines like the previous."
4836 ((verilog-in-star-comment-p)
4839 (re-search-backward "/\\*" nil t)
4840 (1+(current-column))))
4845 (re-search-backward "//" nil t)
4853 (skip-chars-forward " \t")
4857 (defun verilog-comment-indent (&optional arg)
4858 "Return the column number the line should be indented to.
4859 ARG is ignored, for `comment-indent-function' compatibility."
4861 ((verilog-in-star-comment-p)
4863 (re-search-backward "/\\*" nil t)
4864 (1+(current-column))))
4869 (re-search-backward "//" nil t)
4870 (current-column)))))
4874 (defun verilog-pretty-declarations ()
4875 "Line up declarations around point."
4879 (verilog-beg-of-statement-1)
4880 (looking-at verilog-declaration-re))
4881 (let* ((m1 (make-marker))
4884 ;; Start of declaration range
4887 (verilog-beg-of-statement-1)
4888 (while (looking-at verilog-declaration-re)
4891 (verilog-backward-syntactic-ws)
4893 (verilog-beg-of-statement-1)) ;Ack, need to grok `define
4895 ;; End of declaration range
4899 (verilog-end-of-statement)
4900 (setq e (point)) ;Might be on last line
4901 (verilog-forward-syntactic-ws)
4902 (while (looking-at verilog-declaration-re)
4904 (verilog-end-of-statement)
4906 (verilog-forward-syntactic-ws))
4908 (edpos (set-marker (make-marker) end))
4913 (verilog-do-indent (verilog-calculate-indent))
4914 (verilog-forward-ws&directives)
4919 (if (> (- end start) 100)
4920 (message "Lining up declarations..(please stand by)"))
4921 ;; Get the beginning of line indent first
4922 (while (progn (setq e (marker-position edpos))
4925 ( (save-excursion (skip-chars-backward " \t")
4927 (verilog-forward-ws&directives)
4928 (indent-line-to base-ind)
4929 (verilog-forward-ws&directives)
4930 (verilog-re-search-forward "[ \t\n\f]" e 'move)
4934 (verilog-re-search-forward "[ \t\n\f]" e 'move)
4939 ;; Now find biggest prefix
4940 (setq ind (verilog-get-lineup-indent start edpos))
4941 ;; Now indent each line.
4943 (while (progn (setq e (marker-position edpos))
4944 (setq r (- e (point)))
4949 ((or (and verilog-indent-declaration-macros
4950 (looking-at verilog-declaration-re-1-macro))
4951 (looking-at verilog-declaration-re-1-no-macro))
4952 (let ((p (match-end 0)))
4954 (if (verilog-re-search-forward "[[#`]" p 'move)
4958 (goto-char (marker-position m1))
4965 ((verilog-continued-line-1 start)
4967 (indent-line-to ind))
4968 (t ; Must be comment or white space
4970 (verilog-forward-ws&directives)
4976 (defun verilog-pretty-expr (&optional myre)
4977 "Line up expressions around point."
4978 (interactive "sRegular Expression: ((<|:)?=) ")
4980 (if (or (eq myre nil)
4981 (string-equal myre ""))
4982 (setq myre "\\(<\\|:\\)?="))
4983 ; (setq myre (concat "\\(^[^;" myre "]*\\)\\([" myre "]\\)"))
4984 (setq myre (concat "\\(^[^;#:?=]*\\)\\([" myre "]\\)"))
4986 (if (and (not (looking-at (concat "^\\s-*" verilog-complete-reg)))
4988 (let* ((here (point))
4994 (verilog-backward-syntactic-ws)
4996 (while (and (not (looking-at (concat "^\\s-*" verilog-complete-reg)))
5001 (verilog-backward-syntactic-ws)
5003 ) ;Ack, need to grok `define
5009 (setq e (point)) ;Might be on last line
5010 (verilog-forward-syntactic-ws)
5012 (while (and (not (looking-at
5013 (concat "^\\s-*" verilog-complete-reg)))
5017 (verilog-forward-syntactic-ws)
5021 (edpos (set-marker (make-marker) end))
5025 (verilog-do-indent (verilog-calculate-indent))
5026 (if (> (- end start) 100)
5027 (message "Lining up expressions..(please stand by)"))
5029 ;; Set indent to minimum throughout region
5030 (while (< (point) (marker-position edpos))
5032 (verilog-just-one-space myre)
5034 (verilog-forward-syntactic-ws)
5037 ;; Now find biggest prefix
5038 (setq ind (verilog-get-lineup-indent-2 myre start edpos))
5040 ;; Now indent each line.
5042 (while (progn (setq e (marker-position edpos))
5043 (setq r (- e (point)))
5049 (goto-char (match-end 1))
5050 (if (eq (char-after) ?=)
5051 (indent-to (1+ ind)) ; line up the = of the <= with surrounding =
5055 ((verilog-continued-line-1 start)
5057 (indent-line-to ind))
5058 (t ; Must be comment or white space
5060 (verilog-forward-ws&directives)
5067 (defun verilog-just-one-space (myre)
5068 "Remove extra spaces around regular expression MYRE."
5070 (if (and (not(looking-at verilog-complete-reg))
5072 (let ((p1 (match-end 1))
5076 (if (looking-at "\\s-") (just-one-space) )
5079 (if (looking-at "\\s-") (just-one-space))
5084 (defun verilog-indent-declaration (baseind)
5085 "Indent current lines as declaration.
5086 Line up the variable names based on previous declaration's indentation.
5087 BASEIND is the base indent to offset everything."
5089 (let ((pos (point-marker))
5090 (lim (save-excursion
5091 ;; (verilog-re-search-backward verilog-declaration-opener nil 'move)
5092 (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)\\|\\(\\<task\\>\\)" nil 'move)
5099 (+ baseind (eval (cdr (assoc 'declaration verilog-indent-alist)))))
5100 (indent-line-to val)
5102 ;; Use previous declaration (in this module) as template.
5103 (if (or (memq 'all verilog-auto-lineup)
5104 (memq 'declaration verilog-auto-lineup))
5105 (if (verilog-re-search-backward
5106 (or (and verilog-indent-declaration-macros
5107 verilog-declaration-re-1-macro)
5108 verilog-declaration-re-1-no-macro) lim t)
5110 (goto-char (match-end 0))
5111 (skip-chars-forward " \t")
5112 (setq ind (current-column))
5116 (eval (cdr (assoc 'declaration verilog-indent-alist)))))
5117 (indent-line-to val)
5118 (if (and verilog-indent-declaration-macros
5119 (looking-at verilog-declaration-re-2-macro))
5120 (let ((p (match-end 0)))
5122 (if (verilog-re-search-forward "[[#`]" p 'move)
5126 (goto-char (marker-position m1))
5130 (if (/= (current-column) ind)
5135 (if (looking-at verilog-declaration-re-2-no-macro)
5136 (let ((p (match-end 0)))
5138 (if (verilog-re-search-forward "[[`#]" p 'move)
5142 (goto-char (marker-position m1))
5145 (if (/= (current-column) ind)
5148 (indent-to ind))))))))))
5151 (defun verilog-get-lineup-indent (b edpos)
5152 "Return the indent level that will line up several lines within the region.
5153 Region is defined by B and EDPOS."
5157 ;; Get rightmost position
5158 (while (progn (setq e (marker-position edpos))
5160 (if (verilog-re-search-forward
5161 (or (and verilog-indent-declaration-macros
5162 verilog-declaration-re-1-macro)
5163 verilog-declaration-re-1-no-macro) e 'move)
5165 (goto-char (match-end 0))
5166 (verilog-backward-syntactic-ws)
5167 (if (> (current-column) ind)
5168 (setq ind (current-column)))
5169 (goto-char (match-end 0)))))
5172 ;; No lineup-string found
5175 (skip-chars-backward " \t")
5176 (1+ (current-column))))))
5178 (defun verilog-get-lineup-indent-2 (myre b edpos)
5179 "Return the indent level that will line up several lines within the region."
5183 ;; Get rightmost position
5184 (while (progn (setq e (marker-position edpos))
5186 (if (verilog-re-search-forward myre e 'move)
5188 (goto-char (match-end 0))
5189 (verilog-backward-syntactic-ws)
5190 (if (> (current-column) ind)
5191 (setq ind (current-column)))
5192 (goto-char (match-end 0)))))
5195 ;; No lineup-string found
5198 (skip-chars-backward " \t")
5199 (1+ (current-column))))))
5201 (defun verilog-comment-depth (type val)
5202 "A useful mode debugging aide. TYPE and VAL are comments for insertion."
5210 (if (re-search-backward " /\\* \[#-\]# \[a-zA-Z\]+ \[0-9\]+ ## \\*/" b t)
5212 (replace-match " /* -# ## */")
5216 (insert " /* ## ## */"))))
5219 (format "%s %d" type val))))
5225 (defvar verilog-str nil)
5226 (defvar verilog-all nil)
5227 (defvar verilog-pred nil)
5228 (defvar verilog-buffer-to-use nil)
5229 (defvar verilog-flag nil)
5230 (defvar verilog-toggle-completions nil
5231 "*True means \\<verilog-mode-map>\\[verilog-complete-word] should try all possible completions one by one.
5232 Repeated use of \\[verilog-complete-word] will show you all of them.
5233 Normally, when there is more than one possible completion,
5234 it displays a list of all possible completions.")
5237 (defvar verilog-type-keywords
5239 "and" "buf" "bufif0" "bufif1" "cmos" "defparam" "inout" "input"
5240 "integer" "localparam" "logic" "mailbox" "nand" "nmos" "nor" "not" "notif0"
5241 "notif1" "or" "output" "parameter" "pmos" "pull0" "pull1" "pullup"
5242 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran" "rtranif0"
5243 "rtranif1" "semaphore" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1"
5244 "triand" "trior" "trireg" "wand" "wire" "wor" "xnor" "xor"
5246 "*Keywords for types used when completing a word in a declaration or parmlist.
5247 \(eg. integer, real, reg...)")
5249 (defvar verilog-cpp-keywords
5250 '("module" "macromodule" "primitive" "timescale" "define" "ifdef" "ifndef" "else"
5252 "*Keywords to complete when at first word of a line in declarative scope.
5253 \(eg. initial, always, begin, assign.)
5254 The procedures and variables defined within the Verilog program
5255 will be completed runtime and should not be added to this list.")
5257 (defvar verilog-defun-keywords
5260 "always" "always_comb" "always_ff" "always_latch" "assign"
5261 "begin" "end" "generate" "endgenerate" "module" "endmodule"
5262 "specify" "endspecify" "function" "endfunction" "initial" "final"
5263 "task" "endtask" "primitive" "endprimitive"
5265 verilog-type-keywords)
5266 "*Keywords to complete when at first word of a line in declarative scope.
5267 \(eg. initial, always, begin, assign.)
5268 The procedures and variables defined within the Verilog program
5269 will be completed runtime and should not be added to this list.")
5271 (defvar verilog-block-keywords
5273 "begin" "break" "case" "continue" "else" "end" "endfunction"
5274 "endgenerate" "endinterface" "endpackage" "endspecify" "endtask"
5275 "for" "fork" "if" "join" "join_any" "join_none" "repeat" "return"
5277 "*Keywords to complete when at first word of a line in behavioral scope.
5278 \(eg. begin, if, then, else, for, fork.)
5279 The procedures and variables defined within the Verilog program
5280 will be completed runtime and should not be added to this list.")
5282 (defvar verilog-tf-keywords
5283 '("begin" "break" "fork" "join" "join_any" "join_none" "case" "end" "endtask" "endfunction" "if" "else" "for" "while" "repeat")
5284 "*Keywords to complete when at first word of a line in a task or function.
5285 \(eg. begin, if, then, else, for, fork.)
5286 The procedures and variables defined within the Verilog program
5287 will be completed runtime and should not be added to this list.")
5289 (defvar verilog-case-keywords
5290 '("begin" "fork" "join" "join_any" "join_none" "case" "end" "endcase" "if" "else" "for" "repeat")
5291 "*Keywords to complete when at first word of a line in case scope.
5292 \(eg. begin, if, then, else, for, fork.)
5293 The procedures and variables defined within the Verilog program
5294 will be completed runtime and should not be added to this list.")
5296 (defvar verilog-separator-keywords
5297 '("else" "then" "begin")
5298 "*Keywords to complete when NOT standing at the first word of a statement.
5300 Variables and function names defined within the
5301 Verilog program are completed runtime and should not be added to this list.")
5303 (defun verilog-string-diff (str1 str2)
5304 "Return index of first letter where STR1 and STR2 differs."
5308 (if (or (> (1+ diff) (length str1))
5309 (> (1+ diff) (length str2)))
5311 (or (equal (aref str1 diff) (aref str2 diff))
5313 (setq diff (1+ diff))))))
5315 ;; Calculate all possible completions for functions if argument is `function',
5316 ;; completions for procedures if argument is `procedure' or both functions and
5317 ;; procedures otherwise.
5319 (defun verilog-func-completion (type)
5320 "Build regular expression for module/task/function names.
5321 TYPE is 'module, 'tf for task or function, or t if unknown."
5322 (if (string= verilog-str "")
5323 (setq verilog-str "[a-zA-Z_]"))
5324 (let ((verilog-str (concat (cond
5325 ((eq type 'module) "\\<\\(module\\)\\s +")
5326 ((eq type 'tf) "\\<\\(task\\|function\\)\\s +")
5327 (t "\\<\\(task\\|function\\|module\\)\\s +"))
5328 "\\<\\(" verilog-str "[a-zA-Z0-9_.]*\\)\\>"))
5331 (if (not (looking-at verilog-defun-re))
5332 (verilog-re-search-backward verilog-defun-re nil t))
5335 ;; Search through all reachable functions
5336 (goto-char (point-min))
5337 (while (verilog-re-search-forward verilog-str (point-max) t)
5338 (progn (setq match (buffer-substring (match-beginning 2)
5340 (if (or (null verilog-pred)
5341 (funcall verilog-pred match))
5342 (setq verilog-all (cons match verilog-all)))))
5343 (if (match-beginning 0)
5344 (goto-char (match-beginning 0)))))
5346 (defun verilog-get-completion-decl (end)
5347 "Macro for searching through current declaration (var, type or const)
5348 for matches of `str' and adding the occurrence tp `all' through point END."
5349 (let ((re (or (and verilog-indent-declaration-macros
5350 verilog-declaration-re-2-macro)
5351 verilog-declaration-re-2-no-macro))
5354 (while (and (< (point) end)
5355 (verilog-re-search-forward re end t))
5356 ;; Traverse current line
5357 (setq decl-end (save-excursion (verilog-declaration-end)))
5358 (while (and (verilog-re-search-forward verilog-symbol-re decl-end t)
5359 (not (match-end 1)))
5360 (setq match (buffer-substring (match-beginning 0) (match-end 0)))
5361 (if (string-match (concat "\\<" verilog-str) match)
5362 (if (or (null verilog-pred)
5363 (funcall verilog-pred match))
5364 (setq verilog-all (cons match verilog-all)))))
5371 (defun verilog-type-completion ()
5372 "Calculate all possible completions for types."
5373 (let ((start (point))
5375 ;; Search for all reachable type declarations
5376 (while (or (verilog-beg-of-defun)
5377 (setq goon (not goon)))
5379 (if (and (< start (prog1 (save-excursion (verilog-end-of-defun)
5382 (verilog-re-search-forward
5383 "\\<type\\>\\|\\<\\(begin\\|function\\|procedure\\)\\>"
5385 (not (match-end 1)))
5386 ;; Check current type declaration
5387 (verilog-get-completion-decl start))))))
5389 (defun verilog-var-completion ()
5390 "Calculate all possible completions for variables (or constants)."
5391 (let ((start (point)))
5392 ;; Search for all reachable var declarations
5393 (verilog-beg-of-defun)
5395 ;; Check var declarations
5396 (verilog-get-completion-decl start))))
5398 (defun verilog-keyword-completion (keyword-list)
5399 "Give list of all possible completions of keywords in KEYWORD-LIST."
5400 (mapcar '(lambda (s)
5401 (if (string-match (concat "\\<" verilog-str) s)
5402 (if (or (null verilog-pred)
5403 (funcall verilog-pred s))
5404 (setq verilog-all (cons s verilog-all)))))
5408 (defun verilog-completion (verilog-str verilog-pred verilog-flag)
5409 "Function passed to `completing-read', `try-completion' or `all-completions'.
5410 Called to get completion on VERILOG-STR. If VERILOG-PRED is non-nil, it
5411 must be a function to be called for every match to check if this should
5412 really be a match. If VERILOG-FLAG is t, the function returns a list of all
5413 possible completions. If VERILOG-FLAG is nil it returns a string, the
5414 longest possible completion, or t if STR is an exact match. If VERILOG-FLAG
5415 is 'lambda, the function returns t if STR is an exact match, nil
5418 (let ((verilog-all nil))
5419 ;; Set buffer to use for searching labels. This should be set
5420 ;; within functions which use verilog-completions
5421 (set-buffer verilog-buffer-to-use)
5423 ;; Determine what should be completed
5424 (let ((state (car (verilog-calculate-indent))))
5425 (cond ((eq state 'defun)
5426 (save-excursion (verilog-var-completion))
5427 (verilog-func-completion 'module)
5428 (verilog-keyword-completion verilog-defun-keywords))
5430 ((eq state 'behavioral)
5431 (save-excursion (verilog-var-completion))
5432 (verilog-func-completion 'module)
5433 (verilog-keyword-completion verilog-defun-keywords))
5436 (save-excursion (verilog-var-completion))
5437 (verilog-func-completion 'tf)
5438 (verilog-keyword-completion verilog-block-keywords))
5441 (save-excursion (verilog-var-completion))
5442 (verilog-func-completion 'tf)
5443 (verilog-keyword-completion verilog-case-keywords))
5446 (save-excursion (verilog-var-completion))
5447 (verilog-func-completion 'tf)
5448 (verilog-keyword-completion verilog-tf-keywords))
5451 (save-excursion (verilog-var-completion))
5452 (verilog-keyword-completion verilog-cpp-keywords))
5454 ((eq state 'cparenexp)
5455 (save-excursion (verilog-var-completion)))
5458 (save-excursion (verilog-var-completion))
5459 (verilog-func-completion 'both)
5460 (verilog-keyword-completion verilog-separator-keywords))))
5462 ;; Now we have built a list of all matches. Give response to caller
5463 (verilog-completion-response))))
5465 (defun verilog-completion-response ()
5466 (cond ((or (equal verilog-flag 'lambda) (null verilog-flag))
5467 ;; This was not called by all-completions
5468 (if (null verilog-all)
5469 ;; Return nil if there was no matching label
5471 ;; Get longest string common in the labels
5472 (let* ((elm (cdr verilog-all))
5473 (match (car verilog-all))
5474 (min (length match))
5476 (if (string= match verilog-str)
5477 ;; Return t if first match was an exact match
5479 (while (not (null elm))
5480 ;; Find longest common string
5481 (if (< (setq tmp (verilog-string-diff match (car elm))) min)
5484 (setq match (substring match 0 min))))
5485 ;; Terminate with match=t if this is an exact match
5486 (if (string= (car elm) verilog-str)
5490 (setq elm (cdr elm)))))
5491 ;; If this is a test just for exact match, return nil ot t
5492 (if (and (equal verilog-flag 'lambda) (not (equal match 't)))
5495 ;; If flag is t, this was called by all-completions. Return
5496 ;; list of all possible completions
5500 (defvar verilog-last-word-numb 0)
5501 (defvar verilog-last-word-shown nil)
5502 (defvar verilog-last-completions nil)
5504 (defun verilog-complete-word ()
5505 "Complete word at current point.
5506 \(See also `verilog-toggle-completions', `verilog-type-keywords',
5507 and `verilog-separator-keywords'.)"
5509 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
5510 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
5511 (verilog-str (buffer-substring b e))
5512 ;; The following variable is used in verilog-completion
5513 (verilog-buffer-to-use (current-buffer))
5514 (allcomp (if (and verilog-toggle-completions
5515 (string= verilog-last-word-shown verilog-str))
5516 verilog-last-completions
5517 (all-completions verilog-str 'verilog-completion)))
5518 (match (if verilog-toggle-completions
5520 verilog-str (mapcar '(lambda (elm)
5521 (cons elm 0)) allcomp)))))
5522 ;; Delete old string
5525 ;; Toggle-completions inserts whole labels
5526 (if verilog-toggle-completions
5528 ;; Update entry number in list
5529 (setq verilog-last-completions allcomp
5530 verilog-last-word-numb
5531 (if (>= verilog-last-word-numb (1- (length allcomp)))
5533 (1+ verilog-last-word-numb)))
5534 (setq verilog-last-word-shown (elt allcomp verilog-last-word-numb))
5535 ;; Display next match or same string if no match was found
5536 (if (not (null allcomp))
5537 (insert "" verilog-last-word-shown)
5538 (insert "" verilog-str)
5539 (message "(No match)")))
5540 ;; The other form of completion does not necessarily do that.
5542 ;; Insert match if found, or the original string if no match
5543 (if (or (null match) (equal match 't))
5544 (progn (insert "" verilog-str)
5545 (message "(No match)"))
5547 ;; Give message about current status of completion
5548 (cond ((equal match 't)
5549 (if (not (null (cdr allcomp)))
5550 (message "(Complete but not unique)")
5551 (message "(Sole completion)")))
5552 ;; Display buffer if the current completion didn't help
5553 ;; on completing the label.
5554 ((and (not (null (cdr allcomp))) (= (length verilog-str)
5556 (with-output-to-temp-buffer "*Completions*"
5557 (display-completion-list allcomp))
5558 ;; Wait for a key press. Then delete *Completion* window
5559 (momentary-string-display "" (point))
5560 (delete-window (get-buffer-window (get-buffer "*Completions*")))
5563 (defun verilog-show-completions ()
5564 "Show all possible completions at current point."
5566 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
5567 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
5568 (verilog-str (buffer-substring b e))
5569 ;; The following variable is used in verilog-completion
5570 (verilog-buffer-to-use (current-buffer))
5571 (allcomp (if (and verilog-toggle-completions
5572 (string= verilog-last-word-shown verilog-str))
5573 verilog-last-completions
5574 (all-completions verilog-str 'verilog-completion))))
5575 ;; Show possible completions in a temporary buffer.
5576 (with-output-to-temp-buffer "*Completions*"
5577 (display-completion-list allcomp))
5578 ;; Wait for a key press. Then delete *Completion* window
5579 (momentary-string-display "" (point))
5580 (delete-window (get-buffer-window (get-buffer "*Completions*")))))
5583 (defun verilog-get-default-symbol ()
5584 "Return symbol around current point as a string."
5586 (buffer-substring (progn
5587 (skip-chars-backward " \t")
5588 (skip-chars-backward "a-zA-Z0-9_")
5591 (skip-chars-forward "a-zA-Z0-9_")
5594 (defun verilog-build-defun-re (str &optional arg)
5595 "Return function/task/module starting with STR as regular expression.
5596 With optional second ARG non-nil, STR is the complete name of the instruction."
5598 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "\\)\\>")
5599 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "[a-zA-Z0-9_]*\\)\\>")))
5601 (defun verilog-comp-defun (verilog-str verilog-pred verilog-flag)
5602 "Function passed to `completing-read', `try-completion' or `all-completions'.
5603 Returns a completion on any function name based on VERILOG-STR prefix. If
5604 VERILOG-PRED is non-nil, it must be a function to be called for every match
5605 to check if this should really be a match. If VERILOG-FLAG is t, the
5606 function returns a list of all possible completions. If it is nil it
5607 returns a string, the longest possible completion, or t if VERILOG-STR is
5608 an exact match. If VERILOG-FLAG is 'lambda, the function returns t if
5609 VERILOG-STR is an exact match, nil otherwise."
5611 (let ((verilog-all nil)
5614 ;; Set buffer to use for searching labels. This should be set
5615 ;; within functions which use verilog-completions
5616 (set-buffer verilog-buffer-to-use)
5618 (let ((verilog-str verilog-str))
5619 ;; Build regular expression for functions
5620 (if (string= verilog-str "")
5621 (setq verilog-str (verilog-build-defun-re "[a-zA-Z_]"))
5622 (setq verilog-str (verilog-build-defun-re verilog-str)))
5623 (goto-char (point-min))
5625 ;; Build a list of all possible completions
5626 (while (verilog-re-search-forward verilog-str nil t)
5627 (setq match (buffer-substring (match-beginning 2) (match-end 2)))
5628 (if (or (null verilog-pred)
5629 (funcall verilog-pred match))
5630 (setq verilog-all (cons match verilog-all)))))
5632 ;; Now we have built a list of all matches. Give response to caller
5633 (verilog-completion-response))))
5635 (defun verilog-goto-defun ()
5636 "Move to specified Verilog module/task/function.
5637 The default is a name found in the buffer around point.
5638 If search fails, other files are checked based on
5639 `verilog-library-flags'."
5641 (let* ((default (verilog-get-default-symbol))
5642 ;; The following variable is used in verilog-comp-function
5643 (verilog-buffer-to-use (current-buffer))
5644 (label (if (not (string= default ""))
5645 ;; Do completion with default
5646 (completing-read (concat "Label: (default " default ") ")
5647 'verilog-comp-defun nil nil "")
5648 ;; There is no default value. Complete without it
5649 (completing-read "Label: "
5650 'verilog-comp-defun nil nil "")))
5652 ;; If there was no response on prompt, use default value
5653 (if (string= label "")
5654 (setq label default))
5655 ;; Goto right place in buffer if label is not an empty string
5656 (or (string= label "")
5659 (goto-char (point-min))
5661 (re-search-forward (verilog-build-defun-re label t) nil t)))
5664 (beginning-of-line))
5666 (verilog-goto-defun-file label)
5669 ;; Eliminate compile warning
5671 (if (not (boundp 'occur-pos-list))
5672 (defvar occur-pos-list nil "Backward compatibility occur positions.")))
5674 (defun verilog-showscopes ()
5675 "List all scopes in this module."
5677 (let ((buffer (current-buffer))
5681 (prevpos (point-min))
5682 (final-context-start (make-marker))
5683 (regexp "\\(module\\s-+\\w+\\s-*(\\)\\|\\(\\w+\\s-+\\w+\\s-*(\\)")
5685 (with-output-to-temp-buffer "*Occur*"
5687 (message (format "Searching for %s ..." regexp))
5688 ;; Find next match, but give up if prev match was at end of buffer.
5689 (while (and (not (= prevpos (point-max)))
5690 (verilog-re-search-forward regexp nil t))
5691 (goto-char (match-beginning 0))
5694 (setq linenum (+ linenum (count-lines prevpos (point)))))
5695 (setq prevpos (point))
5696 (goto-char (match-end 0))
5697 (let* ((start (save-excursion
5698 (goto-char (match-beginning 0))
5699 (forward-line (if (< nlines 0) nlines (- nlines)))
5701 (end (save-excursion
5702 (goto-char (match-end 0))
5704 (forward-line (1+ nlines))
5707 (tag (format "%3d" linenum))
5708 (empty (make-string (length tag) ?\ ))
5711 (setq tem (make-marker))
5712 (set-marker tem (point))
5713 (set-buffer standard-output)
5714 (setq occur-pos-list (cons tem occur-pos-list))
5715 (or first (zerop nlines)
5716 (insert "--------\n"))
5718 (insert-buffer-substring buffer start end)
5719 (backward-char (- end start))
5720 (setq tem (if (< nlines 0) (- nlines) nlines))
5724 (setq tem (1- tem)))
5725 (let ((this-linenum linenum))
5726 (set-marker final-context-start
5727 (+ (point) (- (match-end 0) (match-beginning 0))))
5728 (while (< (point) final-context-start)
5730 (setq tag (format "%3d" this-linenum)))
5731 (insert tag ?:)))))))
5732 (set-buffer-modified-p nil))))
5735 ;; Highlight helper functions
5736 (defconst verilog-directive-regexp "\\(translate\\|coverage\\|lint\\)_")
5737 (defun verilog-within-translate-off ()
5738 "Return point if within translate-off region, else nil."
5739 (and (save-excursion
5741 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "\\(on\\|off\\)\\>")
5743 (equal "off" (match-string 2))
5746 (defun verilog-start-translate-off (limit)
5747 "Return point before translate-off directive if before LIMIT, else nil."
5748 (when (re-search-forward
5749 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
5751 (match-beginning 0)))
5753 (defun verilog-back-to-start-translate-off (limit)
5754 "Return point before translate-off directive if before LIMIT, else nil."
5755 (when (re-search-backward
5756 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
5758 (match-beginning 0)))
5760 (defun verilog-end-translate-off (limit)
5761 "Return point after translate-on directive if before LIMIT, else nil."
5763 (re-search-forward (concat
5764 "//\\s-*.*\\s-*" verilog-directive-regexp "on\\>") limit t))
5766 (defun verilog-match-translate-off (limit)
5767 "Match a translate-off block, setting `match-data' and returning t, else nil.
5768 Bound search by LIMIT."
5769 (when (< (point) limit)
5770 (let ((start (or (verilog-within-translate-off)
5771 (verilog-start-translate-off limit)))
5772 (case-fold-search t))
5774 (let ((end (or (verilog-end-translate-off limit) limit)))
5775 (set-match-data (list start end))
5776 (goto-char end))))))
5778 (defun verilog-font-lock-match-item (limit)
5779 "Match, and move over, any declaration item after point.
5780 Bound search by LIMIT. Adapted from
5781 `font-lock-match-c-style-declaration-item-and-skip-to-next'."
5784 (narrow-to-region (point-min) limit)
5786 (when (looking-at "\\s-*\\([a-zA-Z]\\w*\\)")
5788 (goto-char (match-end 1))
5789 ;; move to next item
5790 (if (looking-at "\\(\\s-*,\\)")
5791 (goto-char (match-end 1))
5796 ;; Added by Subbu Meiyappan for Header
5798 (defun verilog-header ()
5799 "Insert a standard Verilog file header."
5801 (let ((start (point)))
5803 //-----------------------------------------------------------------------------
5805 // Project : <project>
5806 //-----------------------------------------------------------------------------
5807 // File : <filename>
5808 // Author : <author>
5809 // Created : <credate>
5810 // Last modified : <moddate>
5811 //-----------------------------------------------------------------------------
5814 //-----------------------------------------------------------------------------
5815 // Copyright (c) <copydate> by <company> This model is the confidential and
5816 // proprietary property of <company> and the possession or use of this
5817 // file requires a written license from <company>.
5818 //------------------------------------------------------------------------------
5819 // Modification history :
5821 //-----------------------------------------------------------------------------
5825 (search-forward "<filename>")
5826 (replace-match (buffer-name) t t)
5827 (search-forward "<author>") (replace-match "" t t)
5828 (insert (user-full-name))
5829 (insert " <" (user-login-name) "@" (system-name) ">")
5830 (search-forward "<credate>") (replace-match "" t t)
5831 (verilog-insert-date)
5832 (search-forward "<moddate>") (replace-match "" t t)
5833 (verilog-insert-date)
5834 (search-forward "<copydate>") (replace-match "" t t)
5835 (verilog-insert-year)
5836 (search-forward "<modhist>") (replace-match "" t t)
5837 (verilog-insert-date)
5838 (insert " : created")
5841 (setq string (read-string "title: "))
5842 (search-forward "<title>")
5843 (replace-match string t t)
5844 (setq string (read-string "project: " verilog-project))
5845 (setq verilog-project string)
5846 (search-forward "<project>")
5847 (replace-match string t t)
5848 (setq string (read-string "Company: " verilog-company))
5849 (setq verilog-company string)
5850 (search-forward "<company>")
5851 (replace-match string t t)
5852 (search-forward "<company>")
5853 (replace-match string t t)
5854 (search-forward "<company>")
5855 (replace-match string t t)
5856 (search-backward "<description>")
5857 (replace-match "" t t)
5860 ;; verilog-header Uses the verilog-insert-date function
5862 (defun verilog-insert-date ()
5863 "Insert date from the system."
5866 (setq timpos (point))
5867 (if verilog-date-scientific-format
5868 (shell-command "date \"+@%Y/%m/%d\"" t)
5869 (shell-command "date \"+@%d.%m.%Y\"" t))
5870 (search-forward "@")
5871 (delete-region timpos (point))
5875 (defun verilog-insert-year ()
5876 "Insert year from the system."
5879 (setq timpos (point))
5880 (shell-command "date \"+@%Y\"" t)
5881 (search-forward "@")
5882 (delete-region timpos (point))
5888 ;; Signal list parsing
5891 ;; Elements of a signal list
5892 (defsubst verilog-sig-name (sig)
5894 (defsubst verilog-sig-bits (sig)
5896 (defsubst verilog-sig-comment (sig)
5898 (defsubst verilog-sig-memory (sig)
5900 (defsubst verilog-sig-enum (sig)
5902 (defsubst verilog-sig-signed (sig)
5904 (defsubst verilog-sig-type (sig)
5906 (defsubst verilog-sig-multidim (sig)
5908 (defsubst verilog-sig-multidim-string (sig)
5909 (if (verilog-sig-multidim sig)
5910 (let ((str "") (args (verilog-sig-multidim sig)))
5912 (setq str (concat str (car args)))
5913 (setq args (cdr args)))
5915 (defsubst verilog-sig-width (sig)
5916 (verilog-make-width-expression (verilog-sig-bits sig)))
5918 (defsubst verilog-alw-get-inputs (sigs)
5920 (defsubst verilog-alw-get-outputs (sigs)
5922 (defsubst verilog-alw-get-uses-delayed (sigs)
5925 (defun verilog-signals-not-in (in-list not-list)
5926 "Return list of signals in IN-LIST that aren't also in NOT-LIST,
5927 and also remove any duplicates in IN-LIST.
5928 Signals must be in standard (base vector) form."
5931 (if (not (or (assoc (car (car in-list)) not-list)
5932 (assoc (car (car in-list)) out-list)))
5933 (setq out-list (cons (car in-list) out-list)))
5934 (setq in-list (cdr in-list)))
5935 (nreverse out-list)))
5936 ;;(verilog-signals-not-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" "")))
5938 (defun verilog-signals-in (in-list other-list)
5939 "Return list of signals in IN-LIST that are also in OTHER-LIST.
5940 Signals must be in standard (base vector) form."
5943 (if (assoc (car (car in-list)) other-list)
5944 (setq out-list (cons (car in-list) out-list)))
5945 (setq in-list (cdr in-list)))
5946 (nreverse out-list)))
5947 ;;(verilog-signals-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" "")))
5949 (defun verilog-signals-memory (in-list)
5950 "Return list of signals in IN-LIST that are memoried (multidimensional)."
5953 (if (nth 3 (car in-list))
5954 (setq out-list (cons (car in-list) out-list)))
5955 (setq in-list (cdr in-list)))
5957 ;;(verilog-signals-memory '(("A" nil nil "[3:0]")) '(("B" nil nil nil)))
5959 (defun verilog-signals-sort-compare (a b)
5960 "Compare signal A and B for sorting."
5961 (string< (car a) (car b)))
5963 (defun verilog-signals-not-params (in-list)
5964 "Return list of signals in IN-LIST that aren't parameters or numeric constants."
5967 (unless (boundp (intern (concat "vh-" (car (car in-list)))))
5968 (setq out-list (cons (car in-list) out-list)))
5969 (setq in-list (cdr in-list)))
5970 (nreverse out-list)))
5972 (defun verilog-signals-combine-bus (in-list)
5973 "Return a list of signals in IN-LIST, with busses combined.
5974 Duplicate signals are also removed. For example A[2] and A[1] become A[2:1]."
5977 sig highbit lowbit ; Temp information about current signal
5978 sv-name sv-highbit sv-lowbit ; Details about signal we are forming
5979 sv-comment sv-memory sv-enum sv-signed sv-type sv-multidim sv-busstring
5981 ;; Shove signals so duplicated signals will be adjacent
5982 (setq in-list (sort in-list `verilog-signals-sort-compare))
5984 (setq sig (car in-list))
5985 ;; No current signal; form from existing details
5987 (setq sv-name (verilog-sig-name sig)
5990 sv-comment (verilog-sig-comment sig)
5991 sv-memory (verilog-sig-memory sig)
5992 sv-enum (verilog-sig-enum sig)
5993 sv-signed (verilog-sig-signed sig)
5994 sv-type (verilog-sig-type sig)
5995 sv-multidim (verilog-sig-multidim sig)
5999 ;; Extract bus details
6000 (setq bus (verilog-sig-bits sig))
6002 (or (and (string-match "\\[\\([0-9]+\\):\\([0-9]+\\)\\]" bus)
6003 (setq highbit (string-to-number (match-string 1 bus))
6004 lowbit (string-to-number
6005 (match-string 2 bus))))
6006 (and (string-match "\\[\\([0-9]+\\)\\]" bus)
6007 (setq highbit (string-to-number (match-string 1 bus))
6009 ;; Combine bits in bus
6011 (setq sv-highbit (max highbit sv-highbit)
6012 sv-lowbit (min lowbit sv-lowbit))
6013 (setq sv-highbit highbit
6016 ;; String, probably something like `preproc:0
6017 (setq sv-busstring bus)))
6018 ;; Peek ahead to next signal
6019 (setq in-list (cdr in-list))
6020 (setq sig (car in-list))
6021 (cond ((and sig (equal sv-name (verilog-sig-name sig)))
6022 ;; Combine with this signal
6023 (when (and sv-busstring
6024 (not (equal sv-busstring (verilog-sig-bits sig))))
6025 (when nil ;; Debugging
6026 (message (concat "Warning, can't merge into single bus "
6028 ", the AUTOs may be wrong")))
6029 (setq buswarn ", Couldn't Merge"))
6030 (if (verilog-sig-comment sig) (setq combo ", ..."))
6031 (setq sv-memory (or sv-memory (verilog-sig-memory sig))
6032 sv-enum (or sv-enum (verilog-sig-enum sig))
6033 sv-signed (or sv-signed (verilog-sig-signed sig))
6034 sv-type (or sv-type (verilog-sig-type sig))
6035 sv-multidim (or sv-multidim (verilog-sig-multidim sig))))
6036 ;; Doesn't match next signal, add to queue, zero in prep for next
6037 ;; Note sig may also be nil for the last signal in the list
6044 (concat "[" (int-to-string sv-highbit) ":"
6045 (int-to-string sv-lowbit) "]")))
6046 (concat sv-comment combo buswarn)
6047 sv-memory sv-enum sv-signed sv-type sv-multidim)
6054 (defun verilog-sig-tieoff (sig &optional no-width)
6055 "Return tieoff expression for given SIGNAL, with appropriate width.
6056 Ignore width if optional NO-WIDTH is set."
6057 (let* ((width (if no-width nil (verilog-sig-width sig))))
6059 (if (and verilog-active-low-regexp
6060 (string-match verilog-active-low-regexp (verilog-sig-name sig)))
6064 ((string-match "^[0-9]+$" width)
6065 (concat width (if (verilog-sig-signed sig) "'sh0" "'h0")))
6067 (concat "{" width "{1'b0}}"))))))
6070 ;; Port/Wire/Etc Reading
6073 (defun verilog-read-inst-backward-name ()
6074 "Internal. Move point back to beginning of inst-name."
6075 (verilog-backward-open-paren)
6078 (verilog-re-search-backward-quick "\\()\\|\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil) ; ] isn't word boundary
6079 (cond ((looking-at ")")
6080 (verilog-backward-open-paren))
6081 (t (setq done t)))))
6082 (while (looking-at "\\]")
6083 (verilog-backward-open-bracket)
6084 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil))
6085 (skip-chars-backward "a-zA-Z0-9`_$"))
6087 (defun verilog-read-inst-module ()
6088 "Return module_name when point is inside instantiation."
6090 (verilog-read-inst-backward-name)
6091 ;; Skip over instantiation name
6092 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary
6093 ;; Check for parameterized instantiations
6094 (when (looking-at ")")
6095 (verilog-backward-open-paren)
6096 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil))
6097 (skip-chars-backward "a-zA-Z0-9'_$")
6098 (looking-at "[a-zA-Z0-9`_\$]+")
6099 ;; Important: don't use match string, this must work with emacs 19 font-lock on
6100 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
6102 (defun verilog-read-inst-name ()
6103 "Return instance_name when point is inside instantiation."
6105 (verilog-read-inst-backward-name)
6106 (looking-at "[a-zA-Z0-9`_\$]+")
6107 ;; Important: don't use match string, this must work with emacs 19 font-lock on
6108 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
6110 (defun verilog-read-module-name ()
6111 "Return module name when after its ( or ;."
6113 (re-search-backward "[(;]")
6114 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil)
6115 (skip-chars-backward "a-zA-Z0-9`_$")
6116 (looking-at "[a-zA-Z0-9`_\$]+")
6117 ;; Important: don't use match string, this must work with emacs 19 font-lock on
6118 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
6120 (defun verilog-read-auto-params (num-param &optional max-param)
6121 "Return parameter list inside auto.
6122 Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters."
6125 ;; /*AUTOPUNT("parameter", "parameter")*/
6126 (search-backward "(")
6127 (while (looking-at "(?\\s *\"\\([^\"]*\\)\"\\s *,?")
6128 (setq olist (cons (match-string 1) olist))
6129 (goto-char (match-end 0))))
6130 (or (eq nil num-param)
6131 (<= num-param (length olist))
6132 (error "%s: Expected %d parameters" (verilog-point-text) num-param))
6133 (if (eq max-param nil) (setq max-param num-param))
6134 (or (eq nil max-param)
6135 (>= max-param (length olist))
6136 (error "%s: Expected <= %d parameters" (verilog-point-text) max-param))
6139 (defun verilog-read-decls ()
6140 "Compute signal declaration information for the current module at point.
6141 Return a array of [outputs inouts inputs wire reg assign const]."
6142 (let ((end-mod-point (or (verilog-get-end-of-defun t) (point-max)))
6143 (functask 0) (paren 0) (sig-paren 0)
6144 sigs-in sigs-out sigs-inout sigs-wire sigs-reg sigs-assign sigs-const sigs-gparam
6145 vec expect-signal keywd newsig rvalue enum io signed typedefed multidim)
6147 (verilog-beg-of-defun)
6148 (setq sigs-const (verilog-read-auto-constants (point) end-mod-point))
6149 (while (< (point) end-mod-point)
6150 ;;(if dbg (setq dbg (cons (format "Pt %s Vec %s Kwd'%s'\n" (point) vec keywd) dbg)))
6153 (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
6154 (setq enum (match-string 1)))
6155 (search-forward "\n"))
6156 ((looking-at "/\\*")
6158 (if (looking-at "[^*]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
6159 (setq enum (match-string 1)))
6160 (or (search-forward "*/")
6161 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
6162 ((looking-at "(\\*")
6164 (or (looking-at "\\s-*)") ; It's a "always @ (*)"
6165 (search-forward "*)")
6166 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
6167 ((eq ?\" (following-char))
6168 (or (re-search-forward "[^\\]\"" nil t) ;; don't forward-char first, since we look for a non backslash first
6169 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
6170 ((eq ?\; (following-char))
6171 (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil)
6173 ((eq ?= (following-char))
6174 (setq rvalue t newsig nil)
6176 ((and (or rvalue sig-paren)
6177 (cond ((and (eq ?, (following-char))
6178 (eq paren sig-paren))
6182 ;; ,'s can occur inside {} & funcs
6183 ((looking-at "[{(]")
6184 (setq paren (1+ paren))
6187 ((looking-at "[})]")
6188 (setq paren (1- paren))
6190 (when (< paren sig-paren)
6191 (setq expect-signal nil)) ; ) that ends variables inside v2k arg list
6194 ((looking-at "\\s-*\\(\\[[^]]+\\]\\)")
6195 (goto-char (match-end 0))
6196 (cond (newsig ; Memory, not just width. Patch last signal added's memory (nth 3)
6197 (setcar (cdr (cdr (cdr newsig))) (match-string 1)))
6198 (vec ;; Multidimensional
6199 (setq multidim (cons vec multidim))
6200 (setq vec (verilog-string-replace-matches
6201 "\\s-+" "" nil nil (match-string 1))))
6203 (setq vec (verilog-string-replace-matches
6204 "\\s-+" "" nil nil (match-string 1))))))
6205 ;; Normal or escaped identifier -- note we remember the \ if escaped
6206 ((looking-at "\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
6207 (goto-char (match-end 0))
6208 (setq keywd (match-string 1))
6209 (when (string-match "^\\\\" keywd)
6210 (setq keywd (concat keywd " "))) ;; Escaped ID needs space at end
6211 (cond ((equal keywd "input")
6212 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
6213 expect-signal 'sigs-in io t))
6214 ((equal keywd "output")
6215 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
6216 expect-signal 'sigs-out io t))
6217 ((equal keywd "inout")
6218 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
6219 expect-signal 'sigs-inout io t))
6220 ((or (equal keywd "wire")
6222 (equal keywd "tri0")
6223 (equal keywd "tri1"))
6224 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6225 expect-signal 'sigs-wire)))
6226 ((or (equal keywd "reg")
6227 (equal keywd "trireg"))
6228 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6229 expect-signal 'sigs-reg)))
6230 ((equal keywd "assign")
6231 (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6232 expect-signal 'sigs-assign))
6233 ((or (equal keywd "supply0")
6234 (equal keywd "supply1")
6235 (equal keywd "supply")
6236 (equal keywd "localparam"))
6237 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6238 expect-signal 'sigs-const)))
6239 ((or (equal keywd "parameter"))
6240 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6241 expect-signal 'sigs-gparam)))
6242 ((equal keywd "signed")
6243 (setq signed "signed"))
6244 ((or (equal keywd "function")
6245 (equal keywd "task"))
6246 (setq functask (1+ functask)))
6247 ((or (equal keywd "endfunction")
6248 (equal keywd "endtask"))
6249 (setq functask (1- functask)))
6250 ((or (equal keywd "`ifdef")
6251 (equal keywd "`ifndef"))
6253 ((verilog-typedef-name-p keywd)
6254 (setq typedefed keywd))
6258 (eq paren sig-paren)
6259 (not (member keywd verilog-keywords)))
6260 ;; Add new signal to expect-signal's variable
6261 (setq newsig (list keywd vec nil nil enum signed typedefed multidim))
6262 (set expect-signal (cons newsig
6263 (symbol-value expect-signal))))))
6266 (skip-syntax-forward " "))
6268 (vector (nreverse sigs-out)
6269 (nreverse sigs-inout)
6271 (nreverse sigs-wire)
6273 (nreverse sigs-assign)
6274 (nreverse sigs-const)
6275 (nreverse sigs-gparam)
6278 (defvar sigs-in) ; Prevent compile warning
6279 (defvar sigs-inout) ; Prevent compile warning
6280 (defvar sigs-out) ; Prevent compile warning
6283 (defsubst verilog-modi-get-decls (modi)
6284 (verilog-modi-cache-results modi 'verilog-read-decls))
6286 (defsubst verilog-modi-get-sub-decls (modi)
6287 (verilog-modi-cache-results modi 'verilog-read-sub-decls))
6290 ;; Signal reading for given module
6291 ;; Note these all take modi's - as returned from the
6292 ;; verilog-modi-current function.
6293 (defsubst verilog-modi-get-outputs (modi)
6294 (aref (verilog-modi-get-decls modi) 0))
6295 (defsubst verilog-modi-get-inouts (modi)
6296 (aref (verilog-modi-get-decls modi) 1))
6297 (defsubst verilog-modi-get-inputs (modi)
6298 (aref (verilog-modi-get-decls modi) 2))
6299 (defsubst verilog-modi-get-wires (modi)
6300 (aref (verilog-modi-get-decls modi) 3))
6301 (defsubst verilog-modi-get-regs (modi)
6302 (aref (verilog-modi-get-decls modi) 4))
6303 (defsubst verilog-modi-get-assigns (modi)
6304 (aref (verilog-modi-get-decls modi) 5))
6305 (defsubst verilog-modi-get-consts (modi)
6306 (aref (verilog-modi-get-decls modi) 6))
6307 (defsubst verilog-modi-get-gparams (modi)
6308 (aref (verilog-modi-get-decls modi) 7))
6309 (defsubst verilog-modi-get-sub-outputs (modi)
6310 (aref (verilog-modi-get-sub-decls modi) 0))
6311 (defsubst verilog-modi-get-sub-inouts (modi)
6312 (aref (verilog-modi-get-sub-decls modi) 1))
6313 (defsubst verilog-modi-get-sub-inputs (modi)
6314 (aref (verilog-modi-get-sub-decls modi) 2))
6317 (defun verilog-read-sub-decls-sig (submodi comment port sig vec multidim)
6318 "For verilog-read-sub-decls-line, add a signal."
6321 (setq port (verilog-symbol-detick-denumber port))
6322 (setq sig (verilog-symbol-detick-denumber sig))
6323 (if sig (setq sig (verilog-string-replace-matches "^[---+~!|&]+" "" nil nil sig)))
6324 (if vec (setq vec (verilog-symbol-detick-denumber vec)))
6325 (if multidim (setq multidim (mapcar `verilog-symbol-detick-denumber multidim)))
6326 (unless (or (not sig)
6327 (equal sig "")) ;; Ignore .foo(1'b1) assignments
6328 (cond ((setq portdata (assoc port (verilog-modi-get-inouts submodi)))
6329 (setq sigs-inout (cons (list sig vec (concat "To/From " comment) nil nil
6330 (verilog-sig-signed portdata)
6331 (verilog-sig-type portdata)
6334 ((setq portdata (assoc port (verilog-modi-get-outputs submodi)))
6335 (setq sigs-out (cons (list sig vec (concat "From " comment) nil nil
6336 (verilog-sig-signed portdata)
6337 (verilog-sig-type portdata)
6340 ((setq portdata (assoc port (verilog-modi-get-inputs submodi)))
6341 (setq sigs-in (cons (list sig vec (concat "To " comment) nil nil
6342 (verilog-sig-signed portdata)
6343 (verilog-sig-type portdata)
6346 ;; (t -- warning pin isn't defined.) ; Leave for lint tool
6349 (defun verilog-read-sub-decls-line (submodi comment)
6350 "For read-sub-decls, read lines of port defs until none match anymore.
6351 Return the list of signals found, using submodi to look up each port."
6352 (let (done port sig vec multidim)
6357 (cond ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*(\\s-*")
6358 (setq port (match-string 1))
6359 (goto-char (match-end 0)))
6360 ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*(\\s-*")
6361 (setq port (concat (match-string 1) " ")) ;; escaped id's need trailing space
6362 (goto-char (match-end 0)))
6363 ((looking-at "\\s-*\\.[^(]*(")
6364 (setq port nil) ;; skip this line
6365 (goto-char (match-end 0)))
6367 (setq port nil done t))) ;; Unknown, ignore rest of line
6371 (cond ((looking-at "\\(\\\\[^ \t\n\f]*\\)\\s-*)")
6372 (setq sig (concat (match-string 1) " ") ;; escaped id's need trailing space
6374 ; We intentionally ignore (non-escaped) signals with .s in them
6375 ; this prevents AUTOWIRE etc from noticing hierarchical sigs.
6376 ((looking-at "\\([^[({).]*\\)\\s-*)")
6377 (setq sig (verilog-string-remove-spaces (match-string 1))
6379 ((looking-at "\\([^[({).]*\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*)")
6380 (setq sig (verilog-string-remove-spaces (match-string 1))
6381 vec (match-string 2)))
6382 ((looking-at "\\([^[({).]*\\)\\s-*/\\*\\(\\[[^*]+\\]\\)\\*/\\s-*)")
6383 (setq sig (verilog-string-remove-spaces (match-string 1))
6385 (let ((parse (match-string 2)))
6386 (while (string-match "^\\(\\[[^]]+\\]\\)\\(.*\\)$" parse)
6387 (when vec (setq multidim (cons vec multidim)))
6388 (setq vec (match-string 1 parse))
6389 (setq parse (match-string 2 parse)))))
6390 ((looking-at "{\\(.*\\)}.*\\s-*)")
6391 (let ((mlst (split-string (match-string 1) ","))
6393 (while (setq mstr (pop mlst))
6394 ;;(unless noninteractive (message "sig: %s " mstr))
6396 ((string-match "\\(['`a-zA-Z0-9_$]+\\)\\s-*$" mstr)
6397 (setq sig (verilog-string-remove-spaces (match-string 1 mstr))
6399 ;;(unless noninteractive (message "concat sig1: %s %s" mstr (match-string 1 mstr)))
6401 ((string-match "\\([^[({).]+\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*" mstr)
6402 (setq sig (verilog-string-remove-spaces (match-string 1 mstr))
6403 vec (match-string 2 mstr))
6404 ;;(unless noninteractive (message "concat sig2: '%s' '%s' '%s'" mstr (match-string 1 mstr) (match-string 2 mstr)))
6409 (verilog-read-sub-decls-sig submodi comment port sig vec multidim))))
6413 (verilog-read-sub-decls-sig submodi comment port sig vec multidim))
6415 (forward-line 1)))))
6417 (defun verilog-read-sub-decls ()
6418 "Internally parse signals going to modules under this module.
6419 Return a array of [ outputs inouts inputs ] signals for modules that are
6420 instantiated in this module. For example if declare A A (.B(SIG)) and SIG
6421 is a output, then SIG will be included in the list.
6423 This only works on instantiations created with /*AUTOINST*/ converted by
6424 \\[verilog-auto-inst]. Otherwise, it would have to read in the whole
6425 component library to determine connectivity of the design.
6427 One work around for this problem is to manually create // Inputs and //
6428 Outputs comments above subcell signals, for example:
6430 module1 instance1x (
6436 (let ((end-mod-point (verilog-get-end-of-defun t))
6437 st-point end-inst-point
6438 ;; below 3 modified by verilog-read-sub-decls-line
6439 sigs-out sigs-inout sigs-in)
6440 (verilog-beg-of-defun)
6441 (while (re-search-forward "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-mod-point t)
6443 (goto-char (match-beginning 0))
6444 (unless (verilog-inside-comment-p)
6445 ;; Attempt to snarf a comment
6446 (let* ((submod (verilog-read-inst-module))
6447 (inst (verilog-read-inst-name))
6448 (comment (concat inst " of " submod ".v")) submodi)
6449 (when (setq submodi (verilog-modi-lookup submod t))
6450 ;; This could have used a list created by verilog-auto-inst
6451 ;; However I want it to be runnable even on user's manually added signals
6452 (verilog-backward-open-paren)
6453 (setq end-inst-point (save-excursion (forward-sexp 1) (point))
6455 (while (re-search-forward "\\s *(?\\s *// Outputs" end-inst-point t)
6456 (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-out
6457 (goto-char st-point)
6458 (while (re-search-forward "\\s *// Inouts" end-inst-point t)
6459 (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-inout
6460 (goto-char st-point)
6461 (while (re-search-forward "\\s *// Inputs" end-inst-point t)
6462 (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-in
6464 ;; Combine duplicate bits
6465 ;;(setq rr (vector sigs-out sigs-inout sigs-in))
6466 (vector (verilog-signals-combine-bus (nreverse sigs-out))
6467 (verilog-signals-combine-bus (nreverse sigs-inout))
6468 (verilog-signals-combine-bus (nreverse sigs-in))))))
6470 (defun verilog-read-inst-pins ()
6471 "Return a array of [ pins ] for the current instantiation at point.
6472 For example if declare A A (.B(SIG)) then B will be included in the list."
6474 (let ((end-mod-point (point)) ;; presume at /*AUTOINST*/ point
6476 (verilog-backward-open-paren)
6477 (while (re-search-forward "\\.\\([^(,) \t\n\f]*\\)\\s-*" end-mod-point t)
6478 (setq pin (match-string 1))
6479 (unless (verilog-inside-comment-p)
6480 (setq pins (cons (list pin) pins))
6481 (when (looking-at "(")
6485 (defun verilog-read-arg-pins ()
6486 "Return a array of [ pins ] for the current argument declaration at point."
6488 (let ((end-mod-point (point)) ;; presume at /*AUTOARG*/ point
6490 (verilog-backward-open-paren)
6491 (while (re-search-forward "\\([a-zA-Z0-9$_.%`]+\\)" end-mod-point t)
6492 (setq pin (match-string 1))
6493 (unless (verilog-inside-comment-p)
6494 (setq pins (cons (list pin) pins))))
6497 (defun verilog-read-auto-constants (beg end-mod-point)
6498 "Return a list of AUTO_CONSTANTs used in the region from BEG to END-MOD-POINT."
6501 (let (sig-list tpl-end-pt)
6503 (while (re-search-forward "\\<AUTO_CONSTANT" end-mod-point t)
6504 (if (not (looking-at "\\s *("))
6505 (error "%s: Missing () after AUTO_CONSTANT" (verilog-point-text)))
6506 (search-forward "(" end-mod-point)
6507 (setq tpl-end-pt (save-excursion
6509 (forward-sexp 1) ;; Moves to paren that closes argdecl's
6512 (while (re-search-forward "\\s-*\\([\"a-zA-Z0-9$_.%`]+\\)\\s-*,*" tpl-end-pt t)
6513 (setq sig-list (cons (list (match-string 1) nil nil) sig-list))))
6516 (defun verilog-read-auto-lisp (start end)
6517 "Look for and evaluate a AUTO_LISP between START and END."
6520 (while (re-search-forward "\\<AUTO_LISP(" end t)
6522 (let* ((beg-pt (prog1 (point)
6523 (forward-sexp 1))) ;; Closing paren
6525 (eval-region beg-pt end-pt nil)))))
6527 ;; These are passed in a let, not global
6530 (defvar uses-delayed)
6532 (defun verilog-read-always-signals-recurse
6533 (exit-keywd rvalue ignore-next)
6534 "Recursive routine for parentheses/bracket matching.
6535 EXIT-KEYWD is expression to stop at, nil if top level.
6536 RVALUE is true if at right hand side of equal.
6537 IGNORE-NEXT is true to ignore next token, fake from inside case statement."
6538 (let* ((semi-rvalue (equal "endcase" exit-keywd)) ;; true if after a ; we are looking for rvalue
6539 keywd last-keywd sig-tolk sig-last-tolk gotend got-sig got-rvalue end-else-check)
6540 ;;(if dbg (setq dbg (concat dbg (format "Recursion %S %S %S\n" exit-keywd rvalue ignore-next))))
6541 (while (not (or (eobp) gotend))
6544 (search-forward "\n"))
6545 ((looking-at "/\\*")
6546 (or (search-forward "*/")
6547 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
6548 ((looking-at "(\\*")
6549 (or (looking-at "(\\*\\s-*)") ; It's a "always @ (*)"
6550 (search-forward "*)")
6551 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
6552 (t (setq keywd (buffer-substring-no-properties
6554 (save-excursion (when (eq 0 (skip-chars-forward "a-zA-Z0-9$_.%`"))
6557 sig-last-tolk sig-tolk
6559 ;;(if dbg (setq dbg (concat dbg (format "\tPt=%S %S\trv=%S in=%S ee=%S\n" (point) keywd rvalue ignore-next end-else-check))))
6562 (or (re-search-forward "[^\\]\"" nil t)
6563 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
6564 ;; else at top level loop, keep parsing
6565 ((and end-else-check (equal keywd "else"))
6566 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else %s\n" keywd))))
6567 ;; no forward movement, want to see else in lower loop
6568 (setq end-else-check nil))
6569 ;; End at top level loop
6570 ((and end-else-check (looking-at "[^ \t\n\f]"))
6571 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else-other %s\n" keywd))))
6574 ((and exit-keywd (equal keywd exit-keywd))
6576 (forward-char (length keywd)))
6577 ;; Standard tokens...
6579 (setq ignore-next nil rvalue semi-rvalue)
6580 ;; Final statement at top level loop?
6581 (when (not exit-keywd)
6582 ;;(if dbg (setq dbg (concat dbg (format "\ttop-end-check %s\n" keywd))))
6583 (setq end-else-check t))
6586 (if (looking-at "'s?[hdxbo][0-9a-fA-F_xz? \t]*")
6587 (goto-char (match-end 0))
6589 ((equal keywd ":") ;; Case statement, begin/end label, x?y:z
6590 (cond ((equal "endcase" exit-keywd) ;; case x: y=z; statement next
6591 (setq ignore-next nil rvalue nil))
6592 ((equal "?" exit-keywd) ;; x?y:z rvalue
6594 (got-sig ;; label: statement
6595 (setq ignore-next nil rvalue semi-rvalue got-sig nil))
6596 ((not rvalue) ;; begin label
6597 (setq ignore-next t rvalue nil)))
6600 (if (eq (char-before) ?< )
6601 (setq uses-delayed 1))
6602 (setq ignore-next nil rvalue t)
6606 (verilog-read-always-signals-recurse ":" rvalue nil))
6609 (verilog-read-always-signals-recurse "]" t nil))
6612 (cond (sig-last-tolk ;; Function call; zap last signal
6613 (setq got-sig nil)))
6614 (cond ((equal last-keywd "for")
6615 (verilog-read-always-signals-recurse ";" nil nil)
6616 (verilog-read-always-signals-recurse ";" t nil)
6617 (verilog-read-always-signals-recurse ")" nil nil))
6618 (t (verilog-read-always-signals-recurse ")" t nil))))
6619 ((equal keywd "begin")
6620 (skip-syntax-forward "w_")
6621 (verilog-read-always-signals-recurse "end" nil nil)
6622 ;;(if dbg (setq dbg (concat dbg (format "\tgot-end %s\n" exit-keywd))))
6623 (setq ignore-next nil rvalue semi-rvalue)
6624 (if (not exit-keywd) (setq end-else-check t)))
6625 ((or (equal keywd "case")
6626 (equal keywd "casex")
6627 (equal keywd "casez"))
6628 (skip-syntax-forward "w_")
6629 (verilog-read-always-signals-recurse "endcase" t nil)
6630 (setq ignore-next nil rvalue semi-rvalue)
6631 (if (not exit-keywd) (setq gotend t))) ;; top level begin/end
6632 ((string-match "^[$`a-zA-Z_]" keywd) ;; not exactly word constituent
6633 (cond ((or (equal keywd "`ifdef")
6634 (equal keywd "`ifndef"))
6635 (setq ignore-next t))
6637 (member keywd verilog-keywords)
6638 (string-match "^\\$" keywd)) ;; PLI task
6639 (setq ignore-next nil))
6641 (setq keywd (verilog-symbol-detick-denumber keywd))
6643 (if got-rvalue (setq sigs-in (cons got-sig sigs-in))
6644 (setq sigs-out (cons got-sig sigs-out)))
6645 ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S rv=%S\n" got-sig got-rvalue))))
6647 (setq got-rvalue rvalue
6648 got-sig (if (or (not keywd)
6649 (assoc keywd (if got-rvalue sigs-in sigs-out)))
6650 nil (list keywd nil nil))
6652 (skip-chars-forward "a-zA-Z0-9$_.%`"))
6655 ;; End of non-comment token
6656 (setq last-keywd keywd)
6658 (skip-syntax-forward " "))
6659 ;; Append the final pending signal
6661 (if got-rvalue (setq sigs-in (cons got-sig sigs-in))
6662 (setq sigs-out (cons got-sig sigs-out)))
6663 ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S rv=%S\n" got-sig got-rvalue))))
6665 ;;(if dbg (setq dbg (concat dbg (format "ENDRecursion %s\n" exit-keywd))))
6668 (defun verilog-read-always-signals ()
6669 "Parse always block at point and return list of (outputs inout inputs)."
6674 uses-delayed) ;; Found signal/rvalue; push if not function
6675 (search-forward ")")
6676 (verilog-read-always-signals-recurse nil nil nil)
6677 ;;(if dbg (save-excursion (set-buffer (get-buffer-create "*vl-dbg*")) (delete-region (point-min) (point-max)) (insert dbg) (setq dbg "")))
6678 ;; Return what was found
6679 (list sigs-out nil sigs-in uses-delayed))))
6681 (defun verilog-read-instants ()
6682 "Parse module at point and return list of ( ( file instance ) ... )."
6683 (verilog-beg-of-defun)
6684 (let* ((end-mod-point (verilog-get-end-of-defun t))
6686 (instants-list nil))
6688 (while (< (point) end-mod-point)
6689 ;; Stay at level 0, no comments
6691 (setq state (parse-partial-sexp (point) end-mod-point 0 t nil))
6692 (or (> (car state) 0) ; in parens
6693 (nth 5 state) ; comment
6697 (if (looking-at "^\\s-*\\([a-zA-Z0-9`_$]+\\)\\s-+\\([a-zA-Z0-9`_$]+\\)\\s-*(")
6698 ;;(if (looking-at "^\\(.+\\)$")
6699 (let ((module (match-string 1))
6700 (instant (match-string 2)))
6701 (if (not (member module verilog-keywords))
6702 (setq instants-list (cons (list module instant) instants-list)))))
6708 (defun verilog-read-auto-template (module)
6709 "Look for a auto_template for the instantiation of the given MODULE.
6710 If found returns the signal name connections. Return REGEXP and
6711 list of ( (signal_name connection_name)... )"
6714 (let ((tpl-regexp "\\([0-9]+\\)")
6717 tpl-sig-list tpl-wild-list tpl-end-pt rep)
6719 (re-search-backward (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)
6721 (goto-char (point-min))
6722 (re-search-forward (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)))
6723 (goto-char (match-end 0))
6725 ;; We reserve @"..." for future lisp expressions that evaluate once-per-AUTOINST
6726 (when (looking-at "\\s-*\"\\([^\"]*)\\)\"")
6727 (setq tpl-regexp (match-string 1))
6728 (goto-char (match-end 0)))
6729 (search-forward "(")
6730 ;; Parse lines in the template
6731 (when verilog-auto-inst-template-numbers
6733 (goto-char (point-min))
6734 (while (search-forward "AUTO_TEMPLATE" nil t)
6735 (setq templateno (1+ templateno)))))
6736 (setq tpl-end-pt (save-excursion
6738 (forward-sexp 1) ;; Moves to paren that closes argdecl's
6742 (while (< (point) tpl-end-pt)
6743 (cond ((looking-at "\\s-*\\.\\([a-zA-Z0-9`_$]+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
6744 (setq tpl-sig-list (cons (list
6745 (match-string-no-properties 1)
6746 (match-string-no-properties 2)
6749 (goto-char (match-end 0)))
6752 ;; Regexp bug in xemacs disallows ][ inside [], and wants + last
6753 "\\s-*\\.\\(\\([a-zA-Z0-9`_$+@^.*?|---]+\\|[][]\\|\\\\[()|]\\)+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
6754 (setq rep (match-string-no-properties 3))
6755 (goto-char (match-end 0))
6759 (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil
6765 ((looking-at "[ \t\f]+")
6766 (goto-char (match-end 0)))
6768 (setq lineno (1+ lineno))
6769 (goto-char (match-end 0)))
6771 (search-forward "\n"))
6772 ((looking-at "/\\*")
6774 (or (search-forward "*/")
6775 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
6777 (error "%s: AUTO_TEMPLATE parsing error: %s"
6778 (verilog-point-text)
6779 (progn (looking-at ".*$") (match-string 0))))
6783 (list tpl-sig-list tpl-wild-list)))
6784 ;; If no template found
6785 (t (vector tpl-regexp nil))))))
6786 ;;(progn (find-file "auto-template.v") (verilog-read-auto-template "ptl_entry"))
6788 (defun verilog-set-define (defname defvalue &optional buffer enumname)
6789 "Set the definition DEFNAME to the DEFVALUE in the given BUFFER.
6790 Optionally associate it with the specified enumeration ENUMNAME."
6792 (set-buffer (or buffer (current-buffer)))
6793 (let ((mac (intern (concat "vh-" defname))))
6794 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
6795 ;; Need to define to a constant if no value given
6796 (set (make-variable-buffer-local mac)
6797 (if (equal defvalue "") "1" defvalue)))
6799 (let ((enumvar (intern (concat "venum-" enumname))))
6800 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
6801 (make-variable-buffer-local enumvar)
6802 (add-to-list enumvar defname)))
6805 (defun verilog-read-defines (&optional filename recurse subcall)
6806 "Read `defines and parameters for the current file, or optional FILENAME.
6807 If the filename is provided, `verilog-library-flags' will be used to
6808 resolve it. If optional RECURSE is non-nil, recurse through `includes.
6810 Parameters must be simple assignments to constants, or have their own
6811 \"parameter\" label rather than a list of parameters. Thus:
6813 parameter X = 5, Y = 10; // Ok
6814 parameter X = {1'b1, 2'h2}; // Ok
6815 parameter X = {1'b1, 2'h2}, Y = 10; // Bad, make into 2 parameter lines
6817 Defines must be simple text substitutions, one on a line, starting
6818 at the beginning of the line. Any ifdefs or multiline comments around the
6821 Defines are stored inside Emacs variables using the name vh-{definename}.
6823 This function is useful for setting vh-* variables. The file variables
6824 feature can be used to set defines that `verilog-mode' can see; put at the
6825 *END* of your file something like:
6828 // vh-macro:\"macro_definition\"
6831 If macros are defined earlier in the same file and you want their values,
6832 you can read them automatically (provided `enable-local-eval' is on):
6835 // eval:(verilog-read-defines)
6836 // eval:(verilog-read-defines \"group_standard_includes.v\")
6839 Note these are only read when the file is first visited, you must use
6840 \\[find-alternate-file] RET to have these take effect after editing them!
6842 If you want to disable the \"Process `eval' or hook local variables\"
6843 warning message, you need to add to your .emacs file:
6845 (setq enable-local-eval t)"
6846 (let ((origbuf (current-buffer)))
6848 (unless subcall (verilog-getopt-flags))
6850 (let ((fns (verilog-library-filenames filename (buffer-file-name))))
6852 (set-buffer (find-file-noselect (car fns)))
6853 (error (concat (verilog-point-text)
6854 ": Can't find verilog-read-defines file: " filename)))))
6856 (goto-char (point-min))
6857 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
6858 (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string-no-properties 1))))
6859 (unless (verilog-inside-comment-p)
6860 (verilog-read-defines inc recurse t)))))
6862 ;; note we don't use verilog-re... it's faster this way, and that
6863 ;; function has problems when comments are at the end of the define
6864 (goto-char (point-min))
6865 (while (re-search-forward "^\\s-*`define\\s-+\\([a-zA-Z0-9_$]+\\)\\s-+\\(.*\\)$" nil t)
6866 (let ((defname (match-string-no-properties 1))
6867 (defvalue (match-string-no-properties 2)))
6868 (setq defvalue (verilog-string-replace-matches "\\s-*/[/*].*$" "" nil nil defvalue))
6869 (verilog-set-define defname defvalue origbuf)))
6870 ;; Hack: Read parameters
6871 (goto-char (point-min))
6872 (while (re-search-forward
6873 "^\\s-*\\(parameter\\|localparam\\)\\(\\(\\s-*\\[[^]]*\\]\\|\\)\\s-+\\([a-zA-Z0-9_$]+\\)\\s-*=\\s-*\\([^;,]*\\),?\\|\\)\\s-*" nil t)
6874 (let ((var (match-string-no-properties 4))
6875 (val (match-string-no-properties 5))
6877 ;; The primary way of getting defines is verilog-read-decls
6878 ;; However, that isn't called yet for included files, so we'll add another scheme
6879 (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
6880 (setq enumname (match-string-no-properties 1)))
6882 (verilog-set-define var val origbuf enumname))
6883 (forward-comment 999)
6884 (while (looking-at "\\s-*,?\\s-*\\([a-zA-Z0-9_$]+\\)\\s-*=\\s-*\\([^;,]*\\),?\\s-*")
6885 (verilog-set-define (match-string-no-properties 1) (match-string-no-properties 2) origbuf enumname)
6886 (goto-char (match-end 0))
6887 (forward-comment 999))))
6890 (defun verilog-read-includes ()
6891 "Read `includes for the current file.
6892 This will find all of the `includes which are at the beginning of lines,
6893 ignoring any ifdefs or multiline comments around them.
6894 `verilog-read-defines' is then performed on the current and each included
6897 It is often useful put at the *END* of your file something like:
6900 // eval:(verilog-read-defines)
6901 // eval:(verilog-read-includes)
6904 Note includes are only read when the file is first visited, you must use
6905 \\[find-alternate-file] RET to have these take effect after editing them!
6907 It is good to get in the habit of including all needed files in each .v
6908 file that needs it, rather than waiting for compile time. This will aid
6909 this process, Verilint, and readability. To prevent defining the same
6910 variable over and over when many modules are compiled together, put a test
6911 around the inside each include file:
6914 `ifdef _FOO_V // include if not already included
6917 ... contents of file
6919 ;;slow: (verilog-read-defines nil t))
6921 (verilog-getopt-flags)
6922 (goto-char (point-min))
6923 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
6924 (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string 1))))
6925 (verilog-read-defines inc nil t)))))
6927 (defun verilog-read-signals (&optional start end)
6928 "Return a simple list of all possible signals in the file.
6929 Bounded by optional region from START to END. Overly aggressive but fast.
6930 Some macros and such are also found and included. For dinotrace.el"
6931 (let (sigs-all keywd)
6932 (progn;save-excursion
6933 (goto-char (or start (point-min)))
6934 (setq end (or end (point-max)))
6935 (while (re-search-forward "[\"/a-zA-Z_.%`]" end t)
6939 (search-forward "\n"))
6940 ((looking-at "/\\*")
6941 (search-forward "*/"))
6942 ((looking-at "(\\*")
6943 (or (looking-at "(\\*\\s-*)") ; It's a "always @ (*)"
6944 (search-forward "*)")))
6945 ((eq ?\" (following-char))
6946 (re-search-forward "[^\\]\"")) ;; don't forward-char first, since we look for a non backslash first
6947 ((looking-at "\\s-*\\([a-zA-Z0-9$_.%`]+\\)")
6948 (goto-char (match-end 0))
6949 (setq keywd (match-string-no-properties 1))
6950 (or (member keywd verilog-keywords)
6951 (member keywd sigs-all)
6952 (setq sigs-all (cons keywd sigs-all))))
6953 (t (forward-char 1)))
6959 ;; Argument file parsing
6962 (defun verilog-getopt (arglist)
6963 "Parse -f, -v etc arguments in ARGLIST list or string."
6964 (unless (listp arglist) (setq arglist (list arglist)))
6965 (let ((space-args '())
6967 ;; Split on spaces, so users can pass whole command lines
6969 (setq arg (car arglist)
6970 arglist (cdr arglist))
6971 (while (string-match "^\\([^ \t\n\f]+\\)[ \t\n\f]*\\(.*$\\)" arg)
6972 (setq space-args (append space-args
6973 (list (match-string-no-properties 1 arg))))
6974 (setq arg (match-string 2 arg))))
6977 (setq arg (car space-args)
6978 space-args (cdr space-args))
6982 (setq next-param arg))
6984 (setq next-param arg))
6986 (setq next-param arg))
6987 ;; +libext+(ext1)+(ext2)...
6988 ((string-match "^\\+libext\\+\\(.*\\)" arg)
6989 (setq arg (match-string 1 arg))
6990 (while (string-match "\\([^+]+\\)\\+?\\(.*\\)" arg)
6991 (verilog-add-list-unique `verilog-library-extensions
6992 (match-string 1 arg))
6993 (setq arg (match-string 2 arg))))
6995 ((or (string-match "^-D\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; -Ddefine=val
6996 (string-match "^-D\\([^+=]*\\)\\(\\)" arg) ;; -Ddefine
6997 (string-match "^\\+define\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; +define+val
6998 (string-match "^\\+define\\([^+=]*\\)\\(\\)" arg)) ;; +define+define
6999 (verilog-set-define (match-string 1 arg) (match-string 2 arg)))
7001 ((or (string-match "^\\+incdir\\+\\(.*\\)" arg) ;; +incdir+dir
7002 (string-match "^-I\\(.*\\)" arg)) ;; -Idir
7003 (verilog-add-list-unique `verilog-library-directories
7004 (match-string 1 arg)))
7006 ((equal "+librescan" arg))
7007 ((string-match "^-U\\(.*\\)" arg)) ;; -Udefine
7008 ;; Second parameters
7009 ((equal next-param "-f")
7010 (setq next-param nil)
7011 (verilog-getopt-file arg))
7012 ((equal next-param "-v")
7013 (setq next-param nil)
7014 (verilog-add-list-unique `verilog-library-files arg))
7015 ((equal next-param "-y")
7016 (setq next-param nil)
7017 (verilog-add-list-unique `verilog-library-directories arg))
7019 ((string-match "^[^-+]" arg)
7020 (verilog-add-list-unique `verilog-library-files arg))
7021 ;; Default - ignore; no warning
7026 ;;(verilog-getopt (list "+libext+.a+.b" "+incdir+foodir" "+define+a+aval" "-f" "otherf" "-v" "library" "-y" "dir"))
7028 (defun verilog-getopt-file (filename)
7029 "Read verilog options from the specified FILENAME."
7031 (let ((fns (verilog-library-filenames filename (buffer-file-name)))
7032 (orig-buffer (current-buffer))
7035 (set-buffer (find-file-noselect (car fns)))
7036 (error (concat (verilog-point-text)
7037 "Can't find verilog-getopt-file -f file: " filename)))
7038 (goto-char (point-min))
7040 (setq line (buffer-substring (point)
7041 (save-excursion (end-of-line) (point))))
7043 (when (string-match "//" line)
7044 (setq line (substring line 0 (match-beginning 0))))
7046 (set-buffer orig-buffer) ; Variables are buffer-local, so need right context.
7047 (verilog-getopt line))))))
7049 (defun verilog-getopt-flags ()
7050 "Convert `verilog-library-flags' into standard library variables."
7051 ;; If the flags are local, then all the outputs should be local also
7052 (when (local-variable-p `verilog-library-flags (current-buffer))
7053 (mapc 'make-local-variable '(verilog-library-extensions
7054 verilog-library-directories
7055 verilog-library-files
7056 verilog-library-flags)))
7057 ;; Allow user to customize
7058 (run-hooks 'verilog-before-getopt-flags-hook)
7059 ;; Process arguments
7060 (verilog-getopt verilog-library-flags)
7061 ;; Allow user to customize
7062 (run-hooks 'verilog-getopt-flags-hook))
7064 (defun verilog-add-list-unique (varref object)
7065 "Append to VARREF list the given OBJECT,
7066 unless it is already a member of the variable's list"
7067 (unless (member object (symbol-value varref))
7068 (set varref (append (symbol-value varref) (list object))))
7070 ;;(progn (setq l '()) (verilog-add-list-unique `l "a") (verilog-add-list-unique `l "a") l)
7074 ;; Module name lookup
7077 (defun verilog-module-inside-filename-p (module filename)
7078 "Return point if MODULE is specified inside FILENAME, else nil.
7079 Allows version control to check out the file if need be."
7080 (and (or (file-exists-p filename)
7081 (and (fboundp 'vc-backend)
7082 (vc-backend filename)))
7085 (set-buffer (find-file-noselect filename))
7086 (goto-char (point-min))
7088 ;; It may be tempting to look for verilog-defun-re, don't, it slows things down a lot!
7089 (verilog-re-search-forward-quick "\\<module\\>" nil t)
7090 (verilog-re-search-forward-quick "[(;]" nil t))
7091 (if (equal module (verilog-read-module-name))
7095 (defun verilog-is-number (symbol)
7096 "Return true if SYMBOL is number-like."
7097 (or (string-match "^[0-9 \t:]+$" symbol)
7098 (string-match "^[---]*[0-9]+$" symbol)
7099 (string-match "^[0-9 \t]+'s?[hdxbo][0-9a-fA-F_xz? \t]*$" symbol)
7102 (defun verilog-symbol-detick (symbol wing-it)
7103 "Return a expanded SYMBOL name without any defines.
7104 If the variable vh-{symbol} is defined, return that value.
7105 If undefined, and WING-IT, return just SYMBOL without the tick, else nil."
7106 (while (and symbol (string-match "^`" symbol))
7107 (setq symbol (substring symbol 1))
7109 (if (boundp (intern (concat "vh-" symbol)))
7110 ;; Emacs has a bug where boundp on a buffer-local
7111 ;; variable in only one buffer returns t in another.
7112 ;; This can confuse, so check for nil.
7113 (let ((val (eval (intern (concat "vh-" symbol)))))
7115 (if wing-it symbol nil)
7117 (if wing-it symbol nil))))
7119 ;;(verilog-symbol-detick "`mod" nil)
7121 (defun verilog-symbol-detick-denumber (symbol)
7122 "Return SYMBOL with defines converted and any numbers dropped to nil."
7123 (when (string-match "^`" symbol)
7124 ;; This only will work if the define is a simple signal, not
7125 ;; something like a[b]. Sorry, it should be substituted into the parser
7127 (verilog-string-replace-matches
7128 "\[[^0-9: \t]+\]" "" nil nil
7129 (or (verilog-symbol-detick symbol nil)
7130 (if verilog-auto-sense-defines-constant
7133 (if (verilog-is-number symbol)
7137 (defun verilog-symbol-detick-text (text)
7138 "Return TEXT with any without any known defines.
7139 If the variable vh-{symbol} is defined, substitute that value."
7140 (let ((ok t) symbol val)
7141 (while (and ok (string-match "`\\([a-zA-Z0-9_]+\\)" text))
7142 (setq symbol (match-string 1 text))
7145 (boundp (intern (concat "vh-" symbol)))
7146 ;; Emacs has a bug where boundp on a buffer-local
7147 ;; variable in only one buffer returns t in another.
7148 ;; This can confuse, so check for nil.
7149 (setq val (eval (intern (concat "vh-" symbol)))))
7150 (setq text (replace-match val nil nil text)))
7151 (t (setq ok nil)))))
7153 ;;(progn (setq vh-mod "`foo" vh-foo "bar") (verilog-symbol-detick-text "bar `mod `undefed"))
7155 (defun verilog-expand-dirnames (&optional dirnames)
7156 "Return a list of existing directories given a list of wildcarded DIRNAMES.
7157 Or, just the existing dirnames themselves if there are no wildcards."
7159 (unless dirnames (error "`verilog-library-directories' should include at least '.'"))
7160 (setq dirnames (reverse dirnames)) ; not nreverse
7162 pattern dirfile dirfiles dirname root filename rest)
7164 (setq dirname (substitute-in-file-name (car dirnames))
7165 dirnames (cdr dirnames))
7166 (cond ((string-match (concat "^\\(\\|[/\\]*[^*?]*[/\\]\\)" ;; root
7167 "\\([^/\\]*[*?][^/\\]*\\)" ;; filename with *?
7170 (setq root (match-string 1 dirname)
7171 filename (match-string 2 dirname)
7172 rest (match-string 3 dirname)
7174 ;; now replace those * and ? with .+ and .
7175 ;; use ^ and /> to get only whole file names
7176 ;;verilog-string-replace-matches
7177 (setq pattern (verilog-string-replace-matches "[*]" ".+" nil nil pattern)
7178 pattern (verilog-string-replace-matches "[?]" "." nil nil pattern)
7180 ;; Unfortunately allows abc/*/rtl to match abc/rtl
7181 ;; because abc/.. shows up in dirfiles. Solutions welcome.
7182 dirfiles (if (file-directory-p root) ; Ignore version control external
7183 (directory-files root t pattern nil)))
7185 (setq dirfile (expand-file-name (concat (car dirfiles) rest))
7186 dirfiles (cdr dirfiles))
7187 (if (file-directory-p dirfile)
7188 (setq dirlist (cons dirfile dirlist))))
7192 (if (file-directory-p dirname)
7193 (setq dirlist (cons dirname dirlist))))
7196 ;;(verilog-expand-dirnames (list "." ".." "nonexist" "../*" "/home/wsnyder/*/v"))
7198 (defun verilog-library-filenames (filename current &optional check-ext)
7199 "Return a search path to find the given FILENAME name.
7200 Uses the CURRENT filename, `verilog-library-directories' and
7201 `verilog-library-extensions' variables to build the path.
7202 With optional CHECK-EXT also check `verilog-library-extensions'."
7203 (let ((ckdir (verilog-expand-dirnames verilog-library-directories))
7206 (let ((ckext (if check-ext verilog-library-extensions `(""))))
7208 (setq fn (expand-file-name
7209 (concat filename (car ckext))
7210 (expand-file-name (car ckdir) (file-name-directory current))))
7211 (if (file-exists-p fn)
7212 (setq outlist (cons fn outlist)))
7213 (setq ckext (cdr ckext))))
7214 (setq ckdir (cdr ckdir)))
7215 (nreverse outlist)))
7217 (defun verilog-module-filenames (module current)
7218 "Return a search path to find the given MODULE name.
7219 Uses the CURRENT filename, `verilog-library-extensions',
7220 `verilog-library-directories' and `verilog-library-files'
7221 variables to build the path."
7222 ;; Return search locations for it
7223 (append (list current) ; first, current buffer
7224 (verilog-library-filenames module current t)
7225 verilog-library-files)) ; finally, any libraries
7228 ;; Module Information
7230 ;; Many of these functions work on "modi" a module information structure
7231 ;; A modi is: [module-name-string file-name begin-point]
7233 (defvar verilog-cache-enabled t
7234 "If true, enable caching of signals, etc. Set to nil for debugging to make things SLOW!")
7236 (defvar verilog-modi-cache-list nil
7237 "Cache of ((Module Function) Buf-Tick Buf-Modtime Func-Returns)...
7238 For speeding up verilog-modi-get-* commands.
7241 (make-variable-buffer-local 'verilog-modi-cache-list)
7243 (defvar verilog-modi-cache-preserve-tick nil
7244 "Modification tick after which the cache is still considered valid.
7245 Use verilog-preserve-cache's to set")
7246 (defvar verilog-modi-cache-preserve-buffer nil
7247 "Modification tick after which the cache is still considered valid.
7248 Use verilog-preserve-cache's to set")
7250 (defun verilog-modi-current ()
7251 "Return the modi structure for the module currently at point."
7253 ;; read current module's name
7255 (verilog-re-search-backward-quick verilog-defun-re nil nil)
7256 (verilog-re-search-forward-quick "(" nil nil)
7257 (setq name (verilog-read-module-name))
7260 (vector name (or (buffer-file-name) (current-buffer)) pt)))
7262 (defvar verilog-modi-lookup-last-mod nil "Cache of last module looked up.")
7263 (defvar verilog-modi-lookup-last-modi nil "Cache of last modi returned.")
7264 (defvar verilog-modi-lookup-last-current nil "Cache of last `current-buffer' looked up.")
7265 (defvar verilog-modi-lookup-last-tick nil "Cache of last `buffer-modified-tick' looked up.")
7267 (defun verilog-modi-lookup (module allow-cache &optional ignore-error)
7268 "Find the file and point at which MODULE is defined.
7269 If ALLOW-CACHE is set, check and remember cache of previous lookups.
7270 Return modi if successful, else print message unless IGNORE-ERROR is true."
7271 (let* ((current (or (buffer-file-name) (current-buffer))))
7272 (cond ((and verilog-modi-lookup-last-modi
7273 verilog-cache-enabled
7275 (equal verilog-modi-lookup-last-mod module)
7276 (equal verilog-modi-lookup-last-current current)
7277 (equal verilog-modi-lookup-last-tick (buffer-modified-tick)))
7280 (t (let* ((realmod (verilog-symbol-detick module t))
7281 (orig-filenames (verilog-module-filenames realmod current))
7282 (filenames orig-filenames)
7284 (while (and filenames (not pt))
7285 (if (not (setq pt (verilog-module-inside-filename-p realmod (car filenames))))
7286 (setq filenames (cdr filenames))))
7287 (cond (pt (setq verilog-modi-lookup-last-modi
7288 (vector realmod (car filenames) pt)))
7289 (t (setq verilog-modi-lookup-last-modi nil)
7291 (error (concat (verilog-point-text)
7292 ": Can't locate " module " module definition"
7293 (if (not (equal module realmod))
7294 (concat " (Expanded macro to " realmod ")")
7296 "\n Check the verilog-library-directories variable."
7297 "\n I looked in (if not listed, doesn't exist):\n\t"
7298 (mapconcat 'concat orig-filenames "\n\t")))))
7300 (setq verilog-modi-lookup-last-mod module
7301 verilog-modi-lookup-last-current current
7302 verilog-modi-lookup-last-tick (buffer-modified-tick)))))
7303 verilog-modi-lookup-last-modi
7306 (defsubst verilog-modi-name (modi)
7308 (defsubst verilog-modi-file-or-buffer (modi)
7310 (defsubst verilog-modi-point (modi)
7313 (defun verilog-modi-filename (modi)
7314 "Filename of MODI, or name of buffer if its never been saved."
7315 (if (bufferp (verilog-modi-file-or-buffer modi))
7316 (or (buffer-file-name (verilog-modi-file-or-buffer modi))
7317 (buffer-name (verilog-modi-file-or-buffer modi)))
7318 (verilog-modi-file-or-buffer modi)))
7320 (defun verilog-modi-goto (modi)
7321 "Move point/buffer to specified MODI."
7322 (or modi (error "Passed unfound modi to goto, check earlier"))
7323 (set-buffer (if (bufferp (verilog-modi-file-or-buffer modi))
7324 (verilog-modi-file-or-buffer modi)
7325 (find-file-noselect (verilog-modi-file-or-buffer modi))))
7326 (or (equal major-mode `verilog-mode) ;; Put into verilog mode to get syntax
7328 (goto-char (verilog-modi-point modi)))
7330 (defun verilog-goto-defun-file (module)
7331 "Move point to the file at which a given MODULE is defined."
7332 (interactive "sGoto File for Module: ")
7333 (let* ((modi (verilog-modi-lookup module nil)))
7335 (verilog-modi-goto modi)
7336 (switch-to-buffer (current-buffer)))))
7338 (defun verilog-modi-cache-results (modi function)
7339 "Run on MODI the given FUNCTION. Locate the module in a file.
7340 Cache the output of function so next call may have faster access."
7341 (let (func-returns fass)
7343 (verilog-modi-goto modi)
7344 (if (and (setq fass (assoc (list (verilog-modi-name modi) function)
7345 verilog-modi-cache-list))
7346 ;; Destroy caching when incorrect; Modified or file changed
7347 (not (and verilog-cache-enabled
7348 (or (equal (buffer-modified-tick) (nth 1 fass))
7349 (and verilog-modi-cache-preserve-tick
7350 (<= verilog-modi-cache-preserve-tick (nth 1 fass))
7351 (equal verilog-modi-cache-preserve-buffer (current-buffer))))
7352 (equal (visited-file-modtime) (nth 2 fass)))))
7353 (setq verilog-modi-cache-list nil
7357 (setq func-returns (nth 3 fass)))
7360 ;; Clear then restore any hilighting to make emacs19 happy
7361 (let ((fontlocked (when (and (boundp 'font-lock-mode)
7363 (font-lock-mode nil)
7365 (setq func-returns (funcall function))
7366 (when fontlocked (font-lock-mode t)))
7367 ;; Cache for next time
7368 (setq verilog-modi-cache-list
7369 (cons (list (list (verilog-modi-name modi) function)
7370 (buffer-modified-tick)
7371 (visited-file-modtime)
7373 verilog-modi-cache-list)))
7378 (defun verilog-modi-cache-add (modi function element sig-list)
7379 "Add function return results to the module cache.
7380 Update MODI's cache for given FUNCTION so that the return ELEMENT of that
7381 function now contains the additional SIG-LIST parameters."
7384 (verilog-modi-goto modi)
7385 (if (setq fass (assoc (list (verilog-modi-name modi) function)
7386 verilog-modi-cache-list))
7387 (let ((func-returns (nth 3 fass)))
7388 (aset func-returns element
7389 (append sig-list (aref func-returns element))))))))
7391 (defmacro verilog-preserve-cache (&rest body)
7392 "Execute the BODY forms, allowing cache preservation within BODY.
7393 This means that changes to the buffer will not result in the cache being
7394 flushed. If the changes affect the modsig state, they must call the
7395 modsig-cache-add-* function, else the results of later calls may be
7396 incorrect. Without this, changes are assumed to be adding/removing signals
7397 and invalidating the cache."
7398 `(let ((verilog-modi-cache-preserve-tick (buffer-modified-tick))
7399 (verilog-modi-cache-preserve-buffer (current-buffer)))
7403 (defun verilog-signals-matching-enum (in-list enum)
7404 "Return all signals in IN-LIST matching the given ENUM."
7407 (if (equal (verilog-sig-enum (car in-list)) enum)
7408 (setq out-list (cons (car in-list) out-list)))
7409 (setq in-list (cdr in-list)))
7411 (let* ((enumvar (intern (concat "venum-" enum)))
7412 (enumlist (and (boundp enumvar) (eval enumvar))))
7414 (add-to-list 'out-list (list (car enumlist)))
7415 (setq enumlist (cdr enumlist))))
7416 (nreverse out-list)))
7418 (defun verilog-signals-not-matching-regexp (in-list regexp)
7419 "Return all signals in IN-LIST not matching the given REGEXP, if non-nil."
7424 (if (not (string-match regexp (verilog-sig-name (car in-list))))
7425 (setq out-list (cons (car in-list) out-list)))
7426 (setq in-list (cdr in-list)))
7427 (nreverse out-list))))
7430 (defun verilog-modi-get-signals (modi)
7432 (verilog-modi-get-outputs modi)
7433 (verilog-modi-get-inouts modi)
7434 (verilog-modi-get-inputs modi)
7435 (verilog-modi-get-wires modi)
7436 (verilog-modi-get-regs modi)
7437 (verilog-modi-get-assigns modi)
7438 (verilog-modi-get-consts modi)
7439 (verilog-modi-get-gparams modi)))
7441 (defun verilog-modi-get-ports (modi)
7443 (verilog-modi-get-outputs modi)
7444 (verilog-modi-get-inouts modi)
7445 (verilog-modi-get-inputs modi)))
7447 (defsubst verilog-modi-cache-add-outputs (modi sig-list)
7448 (verilog-modi-cache-add modi 'verilog-read-decls 0 sig-list))
7449 (defsubst verilog-modi-cache-add-inouts (modi sig-list)
7450 (verilog-modi-cache-add modi 'verilog-read-decls 1 sig-list))
7451 (defsubst verilog-modi-cache-add-inputs (modi sig-list)
7452 (verilog-modi-cache-add modi 'verilog-read-decls 2 sig-list))
7453 (defsubst verilog-modi-cache-add-wires (modi sig-list)
7454 (verilog-modi-cache-add modi 'verilog-read-decls 3 sig-list))
7455 (defsubst verilog-modi-cache-add-regs (modi sig-list)
7456 (verilog-modi-cache-add modi 'verilog-read-decls 4 sig-list))
7458 (defun verilog-signals-from-signame (signame-list)
7459 "Return signals in standard form from SIGNAME-LIST, a simple list of signal names."
7460 (mapcar (function (lambda (name) (list name nil nil)))
7464 ;; Auto creation utilities
7467 (defun verilog-auto-search-do (search-for func)
7468 "Search for the given auto text SEARCH-FOR, and perform FUNC where it occurs."
7469 (goto-char (point-min))
7470 (while (search-forward search-for nil t)
7471 (if (not (save-excursion
7472 (goto-char (match-beginning 0))
7473 (verilog-inside-comment-p)))
7476 (defun verilog-auto-re-search-do (search-for func)
7477 "Search for the given auto text SEARCH-FOR, and perform FUNC where it occurs."
7478 (goto-char (point-min))
7479 (while (re-search-forward search-for nil t)
7480 (if (not (save-excursion
7481 (goto-char (match-beginning 0))
7482 (verilog-inside-comment-p)))
7485 (defun verilog-insert-one-definition (sig type indent-pt)
7486 "Print out a definition for SIGNAL of the given TYPE,
7487 with appropriate INDENT-PT indentation."
7488 (indent-to indent-pt)
7490 (when (verilog-sig-signed sig)
7491 (insert " " (verilog-sig-signed sig)))
7492 (when (verilog-sig-multidim sig)
7493 (insert " " (verilog-sig-multidim-string sig)))
7494 (when (verilog-sig-bits sig)
7495 (insert " " (verilog-sig-bits sig)))
7496 (indent-to (max 24 (+ indent-pt 16)))
7497 (unless (= (char-syntax (preceding-char)) ?\ )
7498 (insert " ")) ; Need space between "]name" if indent-to did nothing
7499 (insert (verilog-sig-name sig)))
7501 (defun verilog-insert-definition (sigs direction indent-pt v2k &optional dont-sort)
7502 "Print out a definition for a list of SIGS of the given DIRECTION,
7503 with appropriate INDENT-PT indentation. If V2K, use Verilog 2001 I/O
7504 format. Sort unless DONT-SORT. DIRECTION is normally wire/reg/output."
7506 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
7508 (let ((sig (car sigs)))
7509 (verilog-insert-one-definition
7511 ;; Want "type x" or "output type x", not "wire type x"
7512 (cond ((verilog-sig-type sig)
7514 (if (not (equal direction "wire"))
7515 (concat direction " "))
7516 (verilog-sig-type sig)))
7519 (insert (if v2k "," ";"))
7520 (if (or (not (verilog-sig-comment sig))
7521 (equal "" (verilog-sig-comment sig)))
7523 (indent-to (max 48 (+ indent-pt 40)))
7524 (insert (concat "// " (verilog-sig-comment sig) "\n")))
7525 (setq sigs (cdr sigs)))))
7528 (if (not (boundp 'indent-pt))
7529 (defvar indent-pt nil "Local used by insert-indent")))
7531 (defun verilog-insert-indent (&rest stuff)
7532 "Indent to position stored in local `indent-pt' variable, then insert STUFF.
7533 Presumes that any newlines end a list element."
7534 (let ((need-indent t))
7536 (if need-indent (indent-to indent-pt))
7537 (setq need-indent nil)
7538 (insert (car stuff))
7539 (setq need-indent (string-match "\n$" (car stuff))
7540 stuff (cdr stuff)))))
7541 ;;(let ((indent-pt 10)) (verilog-insert-indent "hello\n" "addon" "there\n"))
7543 (defun verilog-repair-open-comma ()
7544 "If backwards-from-point is other than a open parenthesis insert comma."
7546 (verilog-backward-syntactic-ws)
7547 (when (save-excursion
7549 (and (not (looking-at "[(,]"))
7551 (verilog-re-search-backward "[(`]" nil t)
7555 (defun verilog-repair-close-comma ()
7556 "If point is at a comma followed by a close parenthesis, fix it.
7557 This repairs those mis-inserted by a AUTOARG."
7558 ;; It would be much nicer if Verilog allowed extra commas like Perl does!
7560 (verilog-forward-close-paren)
7562 (verilog-backward-syntactic-ws)
7564 (when (looking-at ",")
7567 (defun verilog-get-list (start end)
7568 "Return the elements of a comma separated list between START and END."
7570 (let ((my-list (list))
7573 (while (< (point) end)
7574 (when (re-search-forward "\\([^,{]+\\)" end t)
7575 (setq my-string (verilog-string-remove-spaces (match-string 1)))
7576 (setq my-list (nconc my-list (list my-string) ))
7577 (goto-char (match-end 0))))
7580 (defun verilog-make-width-expression (range-exp)
7581 "Return an expression calculating the length of a range [x:y] in RANGE-EXP."
7583 (cond ((not range-exp)
7586 (if (string-match "^\\[\\(.*\\)\\]$" range-exp)
7587 (setq range-exp (match-string 1 range-exp)))
7588 (cond ((not range-exp)
7590 ((string-match "^\\s *\\([0-9]+\\)\\s *:\\s *\\([0-9]+\\)\\s *$"
7593 (1+ (abs (- (string-to-number (match-string 1 range-exp))
7594 (string-to-number (match-string 2 range-exp)))))))
7595 ((string-match "^\\(.*\\)\\s *:\\s *\\(.*\\)\\s *$" range-exp)
7596 (concat "(1+(" (match-string 1 range-exp) ")"
7597 (if (equal "0" (match-string 2 range-exp))
7598 ;; Don't bother with -(0)
7600 (concat "-(" (match-string 2 range-exp) ")"))
7603 ;;(verilog-make-width-expression "`A:`B")
7605 (defun verilog-typedef-name-p (variable-name)
7606 "Return true if the VARIABLE-NAME is a type definition."
7607 (when verilog-typedef-regexp
7608 (string-match verilog-typedef-regexp variable-name)))
7614 (defun verilog-delete-autos-lined ()
7615 "Delete autos that occupy multiple lines, between begin and end comments."
7619 (looking-at "\\s-*// Beginning")
7620 (search-forward "// End of automatic" nil t))
7623 (delete-region pt (point))
7627 (defun verilog-forward-close-paren ()
7628 "Find the close parenthesis that match the current point,
7629 ignore other close parenthesis with matching open parens"
7632 (unless (verilog-re-search-forward-quick "[()]" nil t)
7633 (error "%s: Mismatching ()" (verilog-point-text)))
7634 (cond ((= (preceding-char) ?\( )
7635 (setq parens (1+ parens)))
7636 ((= (preceding-char) ?\) )
7637 (setq parens (1- parens)))))))
7639 (defun verilog-backward-open-paren ()
7640 "Find the open parenthesis that match the current point,
7641 ignore other open parenthesis with matching close parens"
7644 (unless (verilog-re-search-backward-quick "[()]" nil t)
7645 (error "%s: Mismatching ()" (verilog-point-text)))
7646 (cond ((= (following-char) ?\) )
7647 (setq parens (1+ parens)))
7648 ((= (following-char) ?\( )
7649 (setq parens (1- parens)))))))
7651 (defun verilog-backward-open-bracket ()
7652 "Find the open bracket that match the current point,
7653 ignore other open bracket with matching close bracket"
7656 (unless (verilog-re-search-backward-quick "[][]" nil t)
7657 (error "%s: Mismatching []" (verilog-point-text)))
7658 (cond ((= (following-char) ?\] )
7659 (setq parens (1+ parens)))
7660 ((= (following-char) ?\[ )
7661 (setq parens (1- parens)))))))
7663 (defun verilog-delete-to-paren ()
7664 "Delete the automatic inst/sense/arg created by autos.
7665 Deletion stops at the matching end parenthesis."
7666 (delete-region (point)
7668 (verilog-backward-open-paren)
7669 (forward-sexp 1) ;; Moves to paren that closes argdecl's
7673 (defun verilog-auto-star-safe ()
7674 "Return if a .* AUTOINST is safe to delete or expand.
7675 It was created by the AUTOS themselves, or by the user."
7676 (and verilog-auto-star-expand
7677 (looking-at "[ \t\n\f,]*\\([)]\\|// \\(Outputs\\|Inouts\\|Inputs\\)\\)")))
7679 (defun verilog-delete-auto-star-all ()
7680 "Delete a .* AUTOINST, if it is safe."
7681 (when (verilog-auto-star-safe)
7682 (verilog-delete-to-paren)))
7684 (defun verilog-delete-auto-star-implicit ()
7685 "Delete all .* implicit connections created by `verilog-auto-star'.
7686 This function will be called automatically at save unless
7687 `verilog-auto-star-save' is set, any non-templated expanded pins will be
7690 (let (paren-pt indent have-close-paren)
7692 (goto-char (point-min))
7693 ;; We need to match these even outside of comments.
7694 ;; For reasonable performance, we don't check if inside comments, sorry.
7695 (while (re-search-forward "// Implicit \\.\\*" nil t)
7696 (setq paren-pt (point))
7698 (setq have-close-paren
7700 (when (search-forward ");" paren-pt t)
7701 (setq indent (current-indentation))
7703 (delete-region (point) (+ 1 paren-pt)) ; Nuke line incl CR
7704 (when have-close-paren
7705 ;; Delete extra commentary
7709 (looking-at "\\s *//\\s *\\(Outputs\\|Inouts\\|Inputs\\)\n"))
7710 (delete-region (match-beginning 0) (match-end 0))))
7711 ;; If it is simple, we can put the ); on the same line as the last text
7712 (let ((rtn-pt (point)))
7714 (while (progn (backward-char 1)
7715 (looking-at "[ \t\n\f]")))
7716 (when (looking-at ",")
7717 (delete-region (+ 1 (point)) rtn-pt))))
7721 ;; Still need to kill final comma - always is one as we put one after the .*
7722 (re-search-backward ",")
7723 (delete-char 1))))))
7725 (defun verilog-delete-auto ()
7726 "Delete the automatic outputs, regs, and wires created by \\[verilog-auto].
7727 Use \\[verilog-auto] to re-insert the updated AUTOs.
7729 The hooks `verilog-before-delete-auto-hook' and `verilog-delete-auto-hook' are
7730 called before and after this function, respectively."
7733 (if (buffer-file-name)
7734 (find-file-noselect (buffer-file-name))) ;; To check we have latest version
7735 ;; Allow user to customize
7736 (run-hooks 'verilog-before-delete-auto-hook)
7738 ;; Remove those that have multi-line insertions
7739 (verilog-auto-re-search-do "/\\*AUTO\\(OUTPUTEVERY\\|CONCATCOMMENT\\|WIRE\\|REG\\|DEFINEVALUE\\|REGINPUT\\|INPUT\\|OUTPUT\\|INOUT\\|RESET\\|TIEOFF\\|UNUSED\\)\\*/"
7740 'verilog-delete-autos-lined)
7741 ;; Remove those that have multi-line insertions with parameters
7742 (verilog-auto-re-search-do "/\\*AUTO\\(INOUTMODULE\\|ASCIIENUM\\)([^)]*)\\*/"
7743 'verilog-delete-autos-lined)
7744 ;; Remove those that are in parenthesis
7745 (verilog-auto-re-search-do "/\\*\\(AS\\|AUTO\\(ARG\\|CONCATWIDTH\\|INST\\|INSTPARAM\\|SENSE\\)\\)\\*/"
7746 'verilog-delete-to-paren)
7747 ;; Do .* instantiations, but avoid removing any user pins by looking for our magic comments
7748 (verilog-auto-re-search-do "\\.\\*"
7749 'verilog-delete-auto-star-all)
7750 ;; Remove template comments ... anywhere in case was pasted after AUTOINST removed
7751 (goto-char (point-min))
7752 (while (re-search-forward "\\s-*// \\(Templated\\|Implicit \\.\\*\\)[ \tLT0-9]*$" nil t)
7756 (run-hooks 'verilog-delete-auto-hook)))
7762 (defun verilog-inject-auto ()
7763 "Examine legacy non-AUTO code and insert AUTOs in appropriate places.
7765 Any always @ blocks with sensitivity lists that match computed lists will
7766 be replaced with /*AS*/ comments.
7768 Any cells will get /*AUTOINST*/ added to the end of the pin list. Pins with
7769 have identical names will be deleted.
7771 Argument lists will not be deleted, /*AUTOARG*/ will only be inserted to
7772 support adding new ports. You may wish to delete older ports yourself.
7776 module ex_inject (i, o);
7782 cell cell (.foobar(baz),
7786 Typing \\[verilog-inject-auto] will make this into:
7788 module ex_inject (i, o/*AUTOARG*/
7793 always @ (/*AS*/i or j)
7795 cell cell (.foobar(baz),
7803 (defun verilog-inject-arg ()
7804 "Inject AUTOARG into new code. See `verilog-inject-auto'."
7805 ;; Presume one module per file.
7807 (goto-char (point-min))
7808 (while (verilog-re-search-forward-quick "\\<module\\>" nil t)
7809 (let ((endmodp (save-excursion
7810 (verilog-re-search-forward-quick "\\<endmodule\\>" nil t)
7812 ;; See if there's already a comment .. inside a comment so not verilog-re-search
7813 (when (not (re-search-forward "/\\*AUTOARG\\*/" endmodp t))
7814 (verilog-re-search-forward-quick ";" nil t)
7816 (verilog-backward-syntactic-ws)
7817 (backward-char 1) ; Moves to paren that closes argdecl's
7818 (when (looking-at ")")
7819 (insert "/*AUTOARG*/")))))))
7821 (defun verilog-inject-sense ()
7822 "Inject AUTOSENSE into new code. See `verilog-inject-auto'."
7824 (goto-char (point-min))
7825 (while (verilog-re-search-forward-quick "\\<always\\s *@\\s *(" nil t)
7826 (let ((start-pt (point))
7827 (modi (verilog-modi-current))
7832 (backward-char 1) ;; End )
7833 (when (not (verilog-re-search-backward "/\\*\\(AUTOSENSE\\|AS\\)\\*/" start-pt t))
7834 (setq pre-sigs (verilog-signals-from-signame
7835 (verilog-read-signals start-pt (point)))
7836 got-sigs (verilog-auto-sense-sigs modi nil))
7837 (when (not (or (verilog-signals-not-in pre-sigs got-sigs) ; Both are equal?
7838 (verilog-signals-not-in got-sigs pre-sigs)))
7839 (delete-region start-pt (point))
7840 (insert "/*AS*/")))))))
7842 (defun verilog-inject-inst ()
7843 "Inject AUTOINST into new code. See `verilog-inject-auto'."
7845 (goto-char (point-min))
7846 ;; It's hard to distinguish modules; we'll instead search for pins.
7847 (while (verilog-re-search-forward-quick "\\.\\s *[a-zA-Z0-9`_\$]+\\s *(\\s *[a-zA-Z0-9`_\$]+\\s *)" nil t)
7848 (verilog-backward-open-paren) ;; Inst start
7850 ((= (preceding-char) ?\#) ;; #(...) parameter section, not pin. Skip.
7852 (verilog-forward-close-paren)) ;; Parameters done
7855 (let ((indent-pt (+ (current-column)))
7856 (end-pt (save-excursion (verilog-forward-close-paren) (point))))
7857 (cond ((verilog-re-search-forward "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-pt t)
7858 (goto-char end-pt)) ;; Already there, continue search with next instance
7860 ;; Delete identical interconnect
7861 (let ((case-fold-search nil)) ;; So we don't convert upper-to-lower, etc
7862 (while (verilog-re-search-forward "\\.\\s *\\([a-zA-Z0-9`_\$]+\\)*\\s *(\\s *\\1\\s *)\\s *" end-pt t)
7863 (delete-region (match-beginning 0) (match-end 0))
7864 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))) ;; Keep it correct
7865 (while (or (looking-at "[ \t\n\f,]+")
7866 (looking-at "//[^\n]*"))
7867 (delete-region (match-beginning 0) (match-end 0))
7868 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))))))
7869 (verilog-forward-close-paren)
7871 ;; Not verilog-re-search, as we don't want to strip comments
7872 (while (re-search-backward "[ \t\n\f]+" (- (point) 1) t)
7873 (delete-region (match-beginning 0) (match-end 0)))
7875 (indent-to indent-pt)
7876 (insert "/*AUTOINST*/")))))))))
7882 (defun verilog-auto-save-check ()
7883 "On saving see if we need auto update."
7884 (cond ((not verilog-auto-save-policy)) ; disabled
7885 ((not (save-excursion
7887 (let ((case-fold-search nil))
7888 (goto-char (point-min))
7889 (re-search-forward "AUTO" nil t))))))
7890 ((eq verilog-auto-save-policy 'force)
7892 ((not (buffer-modified-p)))
7893 ((eq verilog-auto-update-tick (buffer-modified-tick))) ; up-to-date
7894 ((eq verilog-auto-save-policy 'detect)
7897 (when (yes-or-no-p "AUTO statements not recomputed, do it now? ")
7899 ;; Don't ask again if didn't update
7900 (set (make-local-variable 'verilog-auto-update-tick) (buffer-modified-tick))
7902 (when (not verilog-auto-star-save)
7903 (verilog-delete-auto-star-implicit))
7904 nil) ;; Always return nil -- we don't write the file ourselves
7906 (defun verilog-auto-read-locals ()
7907 "Return file local variable segment at bottom of file."
7909 (goto-char (point-max))
7910 (if (re-search-backward "Local Variables:" nil t)
7911 (buffer-substring-no-properties (point) (point-max))
7914 (defun verilog-auto-reeval-locals (&optional force)
7915 "Read file local variable segment at bottom of file if it has changed.
7916 If FORCE, always reread it."
7917 (make-local-variable 'verilog-auto-last-file-locals)
7918 (let ((curlocal (verilog-auto-read-locals)))
7919 (when (or force (not (equal verilog-auto-last-file-locals curlocal)))
7920 (setq verilog-auto-last-file-locals curlocal)
7921 ;; Note this may cause this function to be recursively invoked.
7922 ;; The above when statement will prevent it from recursing forever.
7923 (hack-local-variables)
7930 (defun verilog-auto-arg-ports (sigs message indent-pt)
7931 "Print a list of ports for a AUTOINST.
7932 Takes SIGS list, adds MESSAGE to front and inserts each at INDENT-PT."
7935 (indent-to indent-pt)
7939 (indent-to indent-pt)
7941 (cond ((> (+ 2 (current-column) (length (verilog-sig-name (car sigs)))) fill-column)
7943 (indent-to indent-pt))
7945 (insert (verilog-sig-name (car sigs)) ",")
7946 (setq sigs (cdr sigs)
7949 (defun verilog-auto-arg ()
7950 "Expand AUTOARG statements.
7951 Replace the argument declarations at the beginning of the
7952 module with ones automatically derived from input and output
7953 statements. This can be dangerous if the module is instantiated
7954 using position-based connections, so use only name-based when
7955 instantiating the resulting module. Long lines are split based
7956 on the `fill-column', see \\[set-fill-column].
7959 Concatenation and outputting partial busses is not supported.
7961 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
7965 module ex_arg (/*AUTOARG*/);
7970 Typing \\[verilog-auto] will make this into:
7972 module ex_arg (/*AUTOARG*/
7982 Any ports declared between the ( and /*AUTOARG*/ are presumed to be
7983 predeclared and are not redeclared by AUTOARG. AUTOARG will make a
7984 conservative guess on adding a comma for the first signal, if you have any
7985 ifdefs or complicated expressions before the AUTOARG you will need to
7986 choose the comma yourself.
7988 Avoid declaring ports manually, as it makes code harder to maintain."
7990 (let ((modi (verilog-modi-current))
7991 (skip-pins (aref (verilog-read-arg-pins) 0)))
7992 (verilog-repair-open-comma)
7993 (verilog-auto-arg-ports (verilog-signals-not-in
7994 (verilog-modi-get-outputs modi)
7997 verilog-indent-level-declaration)
7998 (verilog-auto-arg-ports (verilog-signals-not-in
7999 (verilog-modi-get-inouts modi)
8002 verilog-indent-level-declaration)
8003 (verilog-auto-arg-ports (verilog-signals-not-in
8004 (verilog-modi-get-inputs modi)
8007 verilog-indent-level-declaration)
8008 (verilog-repair-close-comma)
8009 (unless (eq (char-before) ?/ )
8011 (indent-to verilog-indent-level-declaration)
8014 (defun verilog-auto-inst-port-map (port-st)
8017 (defvar vector-skip-list nil) ; Prevent compile warning
8018 (defvar vl-cell-type nil "See `verilog-auto-inst'.") ; Prevent compile warning
8019 (defvar vl-cell-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
8020 (defvar vl-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
8021 (defvar vl-width nil "See `verilog-auto-inst'.") ; Prevent compile warning
8022 (defvar vl-dir nil "See `verilog-auto-inst'.") ; Prevent compile warning
8024 (defun verilog-auto-inst-port (port-st indent-pt tpl-list tpl-num for-star)
8025 "Print out a instantiation connection for this PORT-ST.
8026 Insert to INDENT-PT, use template TPL-LIST.
8027 @ are instantiation numbers, replaced with TPL-NUM.
8028 @\"(expression @)\" are evaluated, with @ as a variable."
8029 (let* ((port (verilog-sig-name port-st))
8030 (tpl-ass (or (assoc port (car tpl-list))
8031 (verilog-auto-inst-port-map port-st)))
8032 ;; vl-* are documented for user use
8033 (vl-name (verilog-sig-name port-st))
8034 (vl-width (verilog-sig-width port-st))
8035 (vl-bits (if (or verilog-auto-inst-vector
8036 (not (assoc port vector-skip-list))
8037 (not (equal (verilog-sig-bits port-st)
8038 (verilog-sig-bits (assoc port vector-skip-list)))))
8039 (or (verilog-sig-bits port-st) "")
8041 ;; Default if not found
8042 (tpl-net (if (verilog-sig-multidim port-st)
8043 (concat port "/*" (verilog-sig-multidim-string port-st)
8045 (concat port vl-bits)))
8046 (case-fold-search nil))
8048 (cond (tpl-ass ; Template of exact port name
8049 (setq tpl-net (nth 1 tpl-ass)))
8050 ((nth 1 tpl-list) ; Wildcards in template, search them
8051 (let ((wildcards (nth 1 tpl-list)))
8053 (when (string-match (nth 0 (car wildcards)) port)
8054 (setq tpl-ass (car wildcards) ; so allow @ parsing
8055 tpl-net (replace-match (nth 1 (car wildcards))
8057 (setq wildcards (cdr wildcards))))))
8058 ;; Parse Templated variable
8060 ;; Evaluate @"(lispcode)"
8061 (when (string-match "@\".*[^\\]\"" tpl-net)
8062 (while (string-match "@\"\\(\\([^\\\"]*\\(\\\\.\\)*\\)*\\)\"" tpl-net)
8065 (substring tpl-net 0 (match-beginning 0))
8067 (let* ((expr (match-string 1 tpl-net))
8070 (setq expr (verilog-string-replace-matches "\\\\\"" "\"" nil nil expr))
8071 (setq expr (verilog-string-replace-matches "@" tpl-num nil nil expr))
8072 (prin1 (eval (car (read-from-string expr)))
8073 (lambda (ch) ())))))
8074 (if (numberp value) (setq value (number-to-string value)))
8077 (substring tpl-net (match-end 0))))))
8078 ;; Replace @ and [] magic variables in final output
8079 (setq tpl-net (verilog-string-replace-matches "@" tpl-num nil nil tpl-net))
8080 (setq tpl-net (verilog-string-replace-matches "\\[\\]" vl-bits nil nil tpl-net))
8082 (indent-to indent-pt)
8084 (indent-to verilog-auto-inst-column)
8085 (insert "(" tpl-net "),")
8087 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
8088 verilog-auto-inst-column))
8089 (insert " // Templated")
8090 (when verilog-auto-inst-template-numbers
8091 (insert " T" (int-to-string (nth 2 tpl-ass))
8092 " L" (int-to-string (nth 3 tpl-ass)))))
8094 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
8095 verilog-auto-inst-column))
8096 (insert " // Implicit .\*"))) ;For some reason the . or * must be escaped...
8098 ;;(verilog-auto-inst-port (list "foo" "[5:0]") 10 (list (list "foo" "a@\"(% (+ @ 1) 4)\"a")) "3")
8099 ;;(x "incom[@\"(+ (* 8 @) 7)\":@\"(* 8 @)\"]")
8100 ;;(x ".out (outgo[@\"(concat (+ (* 8 @) 7) \\\":\\\" ( * 8 @))\"]));")
8102 (defun verilog-auto-inst-first ()
8103 "Insert , etc before first ever port in this instant, as part of \\[verilog-auto-inst]."
8104 ;; Do we need a trailing comma?
8105 ;; There maybe a ifdef or something similar before us. What a mess. Thus
8106 ;; to avoid trouble we only insert on preceeding ) or *.
8107 ;; Insert first port on new line
8108 (insert "\n") ;; Must insert before search, so point will move forward if insert comma
8110 (verilog-re-search-backward "[^ \t\n\f]" nil nil)
8111 (when (looking-at ")\\|\\*") ;; Generally don't insert, unless we are fairly sure
8115 (defun verilog-auto-star ()
8116 "Expand SystemVerilog .* pins, as part of \\[verilog-auto].
8118 If `verilog-auto-star-expand' is set, .* pins are treated if they were
8119 AUTOINST statements, otherwise they are ignored. For safety, Verilog-Mode
8120 will also ignore any .* that are not last in your pin list (this prevents
8121 it from deleting pins following the .* when it expands the AUTOINST.)
8123 On writing your file, unless `verilog-auto-star-save' is set, any
8124 non-templated expanded pins will be removed. You may do this at any time
8125 with \\[verilog-delete-auto-star-implicit].
8127 If you are converting a module to use .* for the first time, you may wish
8128 to use \\[verilog-inject-auto] and then replace the created AUTOINST with .*.
8130 See `verilog-auto-inst' for examples, templates, and more information."
8131 (when (verilog-auto-star-safe)
8132 (verilog-auto-inst)))
8134 (defun verilog-auto-inst ()
8135 "Expand AUTOINST statements, as part of \\[verilog-auto].
8136 Replace the pin connections to an instantiation with ones
8137 automatically derived from the module header of the instantiated netlist.
8139 If `verilog-auto-star-expand' is set, also expand SystemVerilog .* ports,
8140 and delete them before saving unless `verilog-auto-star-save' is set.
8141 See `verilog-auto-star' for more information.
8144 Module names must be resolvable to filenames by adding a
8145 `verilog-library-extensions', and being found in the same directory, or
8146 by changing the variable `verilog-library-flags' or
8147 `verilog-library-directories'. Macros `modname are translated through the
8148 vh-{name} Emacs variable, if that is not found, it just ignores the `.
8150 In templates you must have one signal per line, ending in a ), or ));,
8151 and have proper () nesting, including a final ); to end the template.
8153 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
8155 SystemVerilog multidimmensional input/output has only experimental support.
8157 For example, first take the submodule inst.v:
8162 wire [31:0] o = {32{i}};
8165 This is then used in a upper level module:
8167 module ex_inst (o,i)
8170 inst inst (/*AUTOINST*/);
8173 Typing \\[verilog-auto] will make this into:
8175 module ex_inst (o,i)
8178 inst inst (/*AUTOINST*/
8185 Where the list of inputs and outputs came from the inst module.
8189 Unless you are instantiating a module multiple times, or the module is
8190 something trivial like a adder, DO NOT CHANGE SIGNAL NAMES ACROSS HIERARCHY.
8191 It just makes for unmaintainable code. To sanitize signal names, try
8192 vrename from http://www.veripool.com
8194 When you need to violate this suggestion there are two ways to list
8195 exceptions, placing them before the AUTOINST, or using templates.
8197 Any ports defined before the /*AUTOINST*/ are not included in the list of
8198 automatics. This is similar to making a template as described below, but
8199 is restricted to simple connections just like you normally make. Also note
8200 that any signals before the AUTOINST will only be picked up by AUTOWIRE if
8201 you have the appropriate // Input or // Output comment, and exactly the
8202 same line formatting as AUTOINST itself uses.
8204 inst inst (// Inputs
8205 .i (my_i_dont_mess_with_it),
8213 For multiple instantiations based upon a single template, create a
8214 commented out template:
8216 /* instantiating_module_name AUTO_TEMPLATE (
8221 Templates go ABOVE the instantiation(s). When a instantiation is
8222 expanded `verilog-mode' simply searches up for the closest template.
8223 Thus you can have multiple templates for the same module, just alternate
8224 between the template for a instantiation and the instantiation itself.
8226 The module name must be the same as the name of the module in the
8227 instantiation name, and the code \"AUTO_TEMPLATE\" must be in these exact
8228 words and capitalized. Only signals that must be different for each
8229 instantiation need to be listed.
8231 Inside a template, a [] in a connection name (with nothing else inside
8232 the brackets) will be replaced by the same bus subscript as it is being
8233 connected to, or the [] will be removed if it is a single bit signal.
8234 Generally it is a good idea to do this for all connections in a template,
8235 as then they will work for any width signal, and with AUTOWIRE. See
8236 PTL_BUS becoming PTL_BUSNEW below.
8238 If you have a complicated template, set `verilog-auto-inst-template-numbers'
8239 to see which regexps are matching. Don't leave that mode set after
8240 debugging is completed though, it will result in lots of extra differences
8241 and merge conflicts.
8245 /* psm_mas AUTO_TEMPLATE (
8246 .ptl_bus (ptl_busnew[]),
8249 psm_mas ms2m (/*AUTOINST*/);
8251 Typing \\[verilog-auto] will make this into:
8253 psm_mas ms2m (/*AUTOINST*/
8255 .NotInTemplate (NotInTemplate),
8256 .ptl_bus (ptl_busnew[3:0]), // Templated
8261 It is common to instantiate a cell multiple times, so templates make it
8262 trivial to substitute part of the cell name into the connection name.
8264 /* cell_type AUTO_TEMPLATE <optional \"REGEXP\"> (
8266 .sig2 (sigy[@\"(% (+ 1 @) 4)\"]),
8270 If no regular expression is provided immediately after the AUTO_TEMPLATE
8271 keyword, then the @ character in any connection names will be replaced
8272 with the instantiation number; the first digits found in the cell's
8275 If a regular expression is provided, the @ character will be replaced
8276 with the first \(\) grouping that matches against the cell name. Using a
8277 regexp of \"\\([0-9]+\\)\" provides identical values for @ as when no
8278 regexp is provided. If you use multiple layers of parenthesis,
8279 \"test\\([^0-9]+\\)_\\([0-9]+\\)\" would replace @ with non-number
8280 characters after test and before _, whereas
8281 \"\\(test\\([a-z]+\\)_\\([0-9]+\\)\\)\" would replace @ with the entire
8286 /* psm_mas AUTO_TEMPLATE (
8287 .ptl_mapvalidx (ptl_mapvalid[@]),
8288 .ptl_mapvalidp1x (ptl_mapvalid[@\"(% (+ 1 @) 4)\"]),
8291 psm_mas ms2m (/*AUTOINST*/);
8293 Typing \\[verilog-auto] will make this into:
8295 psm_mas ms2m (/*AUTOINST*/
8297 .ptl_mapvalidx (ptl_mapvalid[2]),
8298 .ptl_mapvalidp1x (ptl_mapvalid[3]));
8300 Note the @ character was replaced with the 2 from \"ms2m\".
8302 Alternatively, using a regular expression for @:
8304 /* psm_mas AUTO_TEMPLATE \"_\\([a-z]+\\)\" (
8305 .ptl_mapvalidx (@_ptl_mapvalid),
8306 .ptl_mapvalidp1x (ptl_mapvalid_@),
8309 psm_mas ms2_FOO (/*AUTOINST*/);
8310 psm_mas ms2_BAR (/*AUTOINST*/);
8312 Typing \\[verilog-auto] will make this into:
8314 psm_mas ms2_FOO (/*AUTOINST*/
8316 .ptl_mapvalidx (FOO_ptl_mapvalid),
8317 .ptl_mapvalidp1x (ptl_mapvalid_FOO));
8318 psm_mas ms2_BAR (/*AUTOINST*/
8320 .ptl_mapvalidx (BAR_ptl_mapvalid),
8321 .ptl_mapvalidp1x (ptl_mapvalid_BAR));
8326 A template entry of the form
8328 .pci_req\\([0-9]+\\)_l (pci_req_jtag_[\\1]),
8330 will apply a Emacs style regular expression search for any port beginning
8331 in pci_req followed by numbers and ending in _l and connecting that to
8332 the pci_req_jtag_[] net, with the bus subscript coming from what matches
8333 inside the first set of \\( \\). Thus pci_req2_l becomes pci_req_jtag_[2].
8335 Since \\([0-9]+\\) is so common and ugly to read, a @ in the port name
8336 does the same thing. (Note a @ in the connection/replacement text is
8337 completely different -- still use \\1 there!) Thus this is the same as
8340 .pci_req@_l (pci_req_jtag_[\\1]),
8342 Here's another example to remove the _l, useful when naming conventions
8343 specify _ alone to mean active low. Note the use of [] to keep the bus
8346 .\\(.*\\)_l (\\1_[]),
8350 First any regular expression template is expanded.
8352 If the syntax @\"( ... )\" is found in a connection, the expression in
8353 quotes will be evaluated as a Lisp expression, with @ replaced by the
8354 instantiation number. The MAPVALIDP1X example above would put @+1 modulo
8355 4 into the brackets. Quote all double-quotes inside the expression with
8356 a leading backslash (\\\"). There are special variables defined that are
8357 useful in these Lisp functions:
8359 vl-name Name portion of the input/output port
8360 vl-bits Bus bits portion of the input/output port ('[2:0]')
8361 vl-width Width of the input/output port ('3' for [2:0])
8362 May be a (...) expression if bits isn't a constant.
8363 vl-dir Direction of the pin input/output/inout.
8364 vl-cell-type Module name/type of the cell ('psm_mas')
8365 vl-cell-name Instance name of the cell ('ms2m')
8367 Normal Lisp variables may be used in expressions. See
8368 `verilog-read-defines' which can set vh-{definename} variables for use
8369 here. Also, any comments of the form:
8371 /*AUTO_LISP(setq foo 1)*/
8373 will evaluate any Lisp expression inside the parenthesis between the
8374 beginning of the buffer and the point of the AUTOINST. This allows
8375 functions to be defined or variables to be changed between instantiations.
8377 Note that when using lisp expressions errors may occur when @ is not a
8378 number, you may need to use the standard Emacs Lisp functions
8379 `number-to-string' and `string-to-number'.
8381 After the evaluation is completed, @ substitution and [] substitution
8386 (for-star (save-excursion (backward-char 2) (looking-at "\\.\\*")))
8387 (indent-pt (save-excursion (verilog-backward-open-paren)
8388 (1+ (current-column))))
8389 (verilog-auto-inst-column (max verilog-auto-inst-column
8390 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
8391 (modi (verilog-modi-current))
8392 (vector-skip-list (unless verilog-auto-inst-vector
8393 (verilog-modi-get-signals modi)))
8394 submod submodi inst skip-pins tpl-list tpl-num did-first)
8395 ;; Find module name that is instantiated
8396 (setq submod (verilog-read-inst-module)
8397 inst (verilog-read-inst-name)
8400 skip-pins (aref (verilog-read-inst-pins) 0))
8402 ;; Parse any AUTO_LISP() before here
8403 (verilog-read-auto-lisp (point-min) pt)
8405 ;; Lookup position, etc of submodule
8406 ;; Note this may raise an error
8407 (when (setq submodi (verilog-modi-lookup submod t))
8408 ;; If there's a number in the instantiation, it may be a argument to the
8409 ;; automatic variable instantiation program.
8410 (let* ((tpl-info (verilog-read-auto-template submod))
8411 (tpl-regexp (aref tpl-info 0)))
8412 (setq tpl-num (if (string-match tpl-regexp inst)
8413 (match-string 1 inst)
8415 tpl-list (aref tpl-info 1)))
8416 ;; Find submodule's signals and dump
8417 (let ((sig-list (verilog-signals-not-in
8418 (verilog-modi-get-outputs submodi)
8422 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
8423 (indent-to indent-pt)
8424 ;; Note these are searched for in verilog-read-sub-decls.
8425 (insert "// Outputs\n")
8426 (mapc (lambda (port)
8427 (verilog-auto-inst-port port indent-pt
8428 tpl-list tpl-num for-star))
8430 (let ((sig-list (verilog-signals-not-in
8431 (verilog-modi-get-inouts submodi)
8435 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
8436 (indent-to indent-pt)
8437 (insert "// Inouts\n")
8438 (mapc (lambda (port)
8439 (verilog-auto-inst-port port indent-pt
8440 tpl-list tpl-num for-star))
8442 (let ((sig-list (verilog-signals-not-in
8443 (verilog-modi-get-inputs submodi)
8447 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
8448 (indent-to indent-pt)
8449 (insert "// Inputs\n")
8450 (mapc (lambda (port)
8451 (verilog-auto-inst-port port indent-pt
8452 tpl-list tpl-num for-star))
8457 (re-search-backward "," pt t)
8460 (search-forward "\n") ;; Added by inst-port
8461 (delete-backward-char 1)
8462 (if (search-forward ")" nil t) ;; From user, moved up a line
8463 (delete-backward-char 1))
8464 (if (search-forward ";" nil t) ;; Don't error if user had syntax error and forgot it
8465 (delete-backward-char 1))
8469 (defun verilog-auto-inst-param ()
8470 "Expand AUTOINSTPARAM statements, as part of \\[verilog-auto].
8471 Replace the parameter connections to an instantiation with ones
8472 automatically derived from the module header of the instantiated netlist.
8474 See \\[verilog-auto-inst] for limitations, and templates to customize the
8477 For example, first take the submodule inst.v:
8483 This is then used in a upper level module:
8485 module ex_inst (o,i)
8487 inst #(/*AUTOINSTPARAM*/)
8488 inst (/*AUTOINST*/);
8491 Typing \\[verilog-auto] will make this into:
8493 module ex_inst (o,i)
8496 inst (/*AUTOINSTPARAM*/
8499 inst (/*AUTOINST*/);
8502 Where the list of parameter connections come from the inst module.
8506 You can customize the parameter connections using AUTO_TEMPLATEs,
8507 just as you would with \\[verilog-auto-inst]."
8511 (indent-pt (save-excursion (verilog-backward-open-paren)
8512 (1+ (current-column))))
8513 (verilog-auto-inst-column (max verilog-auto-inst-column
8514 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
8515 (modi (verilog-modi-current))
8516 (vector-skip-list (unless verilog-auto-inst-vector
8517 (verilog-modi-get-signals modi)))
8518 submod submodi inst skip-pins tpl-list tpl-num did-first)
8519 ;; Find module name that is instantiated
8520 (setq submod (save-excursion
8521 ;; Get to the point where AUTOINST normally is to read the module
8522 (verilog-re-search-forward-quick "[(;]" nil nil)
8523 (verilog-read-inst-module))
8524 inst (save-excursion
8525 ;; Get to the point where AUTOINST normally is to read the module
8526 (verilog-re-search-forward-quick "[(;]" nil nil)
8527 (verilog-read-inst-name))
8530 skip-pins (aref (verilog-read-inst-pins) 0))
8532 ;; Parse any AUTO_LISP() before here
8533 (verilog-read-auto-lisp (point-min) pt)
8535 ;; Lookup position, etc of submodule
8536 ;; Note this may raise an error
8537 (when (setq submodi (verilog-modi-lookup submod t))
8538 ;; If there's a number in the instantiation, it may be a argument to the
8539 ;; automatic variable instantiation program.
8540 (let* ((tpl-info (verilog-read-auto-template submod))
8541 (tpl-regexp (aref tpl-info 0)))
8542 (setq tpl-num (if (string-match tpl-regexp inst)
8543 (match-string 1 inst)
8545 tpl-list (aref tpl-info 1)))
8546 ;; Find submodule's signals and dump
8547 (let ((sig-list (verilog-signals-not-in
8548 (verilog-modi-get-gparams submodi)
8550 (vl-dir "parameter"))
8552 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
8553 (indent-to indent-pt)
8554 ;; Note these are searched for in verilog-read-sub-decls.
8555 (insert "// Parameters\n")
8556 (mapc (lambda (port)
8557 (verilog-auto-inst-port port indent-pt
8558 tpl-list tpl-num nil))
8563 (re-search-backward "," pt t)
8566 (search-forward "\n") ;; Added by inst-port
8567 (delete-backward-char 1)
8568 (if (search-forward ")" nil t) ;; From user, moved up a line
8569 (delete-backward-char 1))
8573 (defun verilog-auto-reg ()
8574 "Expand AUTOREG statements, as part of \\[verilog-auto].
8575 Make reg statements for any output that isn't already declared,
8576 and isn't a wire output from a block.
8579 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
8581 This does NOT work on memories, declare those yourself.
8592 Typing \\[verilog-auto] will make this into:
8598 // Beginning of automatic regs (for this module's undeclared outputs)
8600 // End of automatics
8604 ;; Point must be at insertion point.
8605 (let* ((indent-pt (current-indentation))
8606 (modi (verilog-modi-current))
8607 (sig-list (verilog-signals-not-in
8608 (verilog-modi-get-outputs modi)
8609 (append (verilog-modi-get-wires modi)
8610 (verilog-modi-get-regs modi)
8611 (verilog-modi-get-assigns modi)
8612 (verilog-modi-get-consts modi)
8613 (verilog-modi-get-gparams modi)
8614 (verilog-modi-get-sub-outputs modi)
8615 (verilog-modi-get-sub-inouts modi)
8619 (verilog-insert-indent "// Beginning of automatic regs (for this module's undeclared outputs)\n")
8620 (verilog-insert-definition sig-list "reg" indent-pt nil)
8621 (verilog-modi-cache-add-regs modi sig-list)
8622 (verilog-insert-indent "// End of automatics\n"))
8625 (defun verilog-auto-reg-input ()
8626 "Expand AUTOREGINPUT statements, as part of \\[verilog-auto].
8627 Make reg statements instantiation inputs that aren't already declared.
8628 This is useful for making a top level shell for testing the module that is
8632 This ONLY detects inputs of AUTOINSTants (see `verilog-read-sub-decls').
8634 This does NOT work on memories, declare those yourself.
8636 An example (see `verilog-auto-inst' for what else is going on here):
8638 module ex_reg_input (o,i)
8642 inst inst (/*AUTOINST*/);
8645 Typing \\[verilog-auto] will make this into:
8647 module ex_reg_input (o,i)
8651 // Beginning of automatic reg inputs (for undeclared ...
8652 reg [31:0] iv; // From inst of inst.v
8653 // End of automatics
8654 inst inst (/*AUTOINST*/
8661 ;; Point must be at insertion point.
8662 (let* ((indent-pt (current-indentation))
8663 (modi (verilog-modi-current))
8664 (sig-list (verilog-signals-combine-bus
8665 (verilog-signals-not-in
8666 (append (verilog-modi-get-sub-inputs modi)
8667 (verilog-modi-get-sub-inouts modi))
8668 (verilog-modi-get-signals modi)
8672 (verilog-insert-indent "// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)\n")
8673 (verilog-insert-definition sig-list "reg" indent-pt nil)
8674 (verilog-modi-cache-add-regs modi sig-list)
8675 (verilog-insert-indent "// End of automatics\n"))
8678 (defun verilog-auto-wire ()
8679 "Expand AUTOWIRE statements, as part of \\[verilog-auto].
8680 Make wire statements for instantiations outputs that aren't
8684 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'),
8685 and all busses must have widths, such as those from AUTOINST, or using []
8688 This does NOT work on memories or SystemVerilog .name connections,
8689 declare those yourself.
8691 Verilog-mode will add \"Couldn't Merge\" comments to signals it cannot
8692 determine how to bus together. This occurs when you have ports with
8693 non-numeric or non-sequential bus subscripts. If Verilog-Mode
8694 mis-guessed, you'll have to declare them yourself.
8696 An example (see `verilog-auto-inst' for what else is going on here):
8698 module ex_wire (o,i)
8702 inst inst (/*AUTOINST*/);
8705 Typing \\[verilog-auto] will make this into:
8707 module ex_wire (o,i)
8711 // Beginning of automatic wires
8712 wire [31:0] ov; // From inst of inst.v
8713 // End of automatics
8714 inst inst (/*AUTOINST*/
8722 ;; Point must be at insertion point.
8723 (let* ((indent-pt (current-indentation))
8724 (modi (verilog-modi-current))
8725 (sig-list (verilog-signals-combine-bus
8726 (verilog-signals-not-in
8727 (append (verilog-modi-get-sub-outputs modi)
8728 (verilog-modi-get-sub-inouts modi))
8729 (verilog-modi-get-signals modi)
8733 (verilog-insert-indent "// Beginning of automatic wires (for undeclared instantiated-module outputs)\n")
8734 (verilog-insert-definition sig-list "wire" indent-pt nil)
8735 (verilog-modi-cache-add-wires modi sig-list)
8736 (verilog-insert-indent "// End of automatics\n")
8737 (when nil ;; Too slow on huge modules, plus makes everyone's module change
8740 (verilog-pretty-declarations)
8742 (verilog-pretty-expr "//")))
8745 (defun verilog-auto-output ()
8746 "Expand AUTOOUTPUT statements, as part of \\[verilog-auto].
8747 Make output statements for any output signal from an /*AUTOINST*/ that
8748 isn't a input to another AUTOINST. This is useful for modules which
8749 only instantiate other modules.
8752 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
8754 If placed inside the parenthesis of a module declaration, it creates
8755 Verilog 2001 style, else uses Verilog 1995 style.
8757 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
8758 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
8760 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
8762 Signals matching `verilog-auto-output-ignore-regexp' are not included.
8764 An example (see `verilog-auto-inst' for what else is going on here):
8766 module ex_output (ov,i)
8769 inst inst (/*AUTOINST*/);
8772 Typing \\[verilog-auto] will make this into:
8774 module ex_output (ov,i)
8777 // Beginning of automatic outputs (from unused autoinst outputs)
8778 output [31:0] ov; // From inst of inst.v
8779 // End of automatics
8780 inst inst (/*AUTOINST*/
8787 ;; Point must be at insertion point.
8788 (let* ((indent-pt (current-indentation))
8789 (v2k (verilog-in-paren))
8790 (modi (verilog-modi-current))
8791 (sig-list (verilog-signals-not-in
8792 (verilog-modi-get-sub-outputs modi)
8793 (append (verilog-modi-get-outputs modi)
8794 (verilog-modi-get-inouts modi)
8795 (verilog-modi-get-sub-inputs modi)
8796 (verilog-modi-get-sub-inouts modi)
8798 (setq sig-list (verilog-signals-not-matching-regexp
8799 sig-list verilog-auto-output-ignore-regexp))
8801 (when v2k (verilog-repair-open-comma))
8803 (verilog-insert-indent "// Beginning of automatic outputs (from unused autoinst outputs)\n")
8804 (verilog-insert-definition sig-list "output" indent-pt v2k)
8805 (verilog-modi-cache-add-outputs modi sig-list)
8806 (verilog-insert-indent "// End of automatics\n"))
8807 (when v2k (verilog-repair-close-comma))
8810 (defun verilog-auto-output-every ()
8811 "Expand AUTOOUTPUTEVERY statements, as part of \\[verilog-auto].
8812 Make output statements for any signals that aren't primary inputs or
8813 outputs already. This makes every signal in the design a output. This is
8814 useful to get Synopsys to preserve every signal in the design, since it
8815 won't optimize away the outputs.
8819 module ex_output_every (o,i,tempa,tempb)
8828 Typing \\[verilog-auto] will make this into:
8830 module ex_output_every (o,i,tempa,tempb)
8834 // Beginning of automatic outputs (every signal)
8837 // End of automatics
8843 ;;Point must be at insertion point
8844 (let* ((indent-pt (current-indentation))
8845 (v2k (verilog-in-paren))
8846 (modi (verilog-modi-current))
8847 (sig-list (verilog-signals-combine-bus
8848 (verilog-signals-not-in
8849 (verilog-modi-get-signals modi)
8850 (verilog-modi-get-ports modi)
8853 (when v2k (verilog-repair-open-comma))
8855 (verilog-insert-indent "// Beginning of automatic outputs (every signal)\n")
8856 (verilog-insert-definition sig-list "output" indent-pt v2k)
8857 (verilog-modi-cache-add-outputs modi sig-list)
8858 (verilog-insert-indent "// End of automatics\n"))
8859 (when v2k (verilog-repair-close-comma))
8862 (defun verilog-auto-input ()
8863 "Expand AUTOINPUT statements, as part of \\[verilog-auto].
8864 Make input statements for any input signal into an /*AUTOINST*/ that
8865 isn't declared elsewhere inside the module. This is useful for modules which
8866 only instantiate other modules.
8869 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
8871 If placed inside the parenthesis of a module declaration, it creates
8872 Verilog 2001 style, else uses Verilog 1995 style.
8874 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
8875 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
8877 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
8879 Signals matching `verilog-auto-input-ignore-regexp' are not included.
8881 An example (see `verilog-auto-inst' for what else is going on here):
8883 module ex_input (ov,i)
8886 inst inst (/*AUTOINST*/);
8889 Typing \\[verilog-auto] will make this into:
8891 module ex_input (ov,i)
8894 // Beginning of automatic inputs (from unused autoinst inputs)
8895 input i; // From inst of inst.v
8896 // End of automatics
8897 inst inst (/*AUTOINST*/
8904 (let* ((indent-pt (current-indentation))
8905 (v2k (verilog-in-paren))
8906 (modi (verilog-modi-current))
8907 (sig-list (verilog-signals-not-in
8908 (verilog-modi-get-sub-inputs modi)
8909 (append (verilog-modi-get-inputs modi)
8910 (verilog-modi-get-inouts modi)
8911 (verilog-modi-get-wires modi)
8912 (verilog-modi-get-regs modi)
8913 (verilog-modi-get-consts modi)
8914 (verilog-modi-get-gparams modi)
8915 (verilog-modi-get-sub-outputs modi)
8916 (verilog-modi-get-sub-inouts modi)
8918 (setq sig-list (verilog-signals-not-matching-regexp
8919 sig-list verilog-auto-input-ignore-regexp))
8921 (when v2k (verilog-repair-open-comma))
8923 (verilog-insert-indent "// Beginning of automatic inputs (from unused autoinst inputs)\n")
8924 (verilog-insert-definition sig-list "input" indent-pt v2k)
8925 (verilog-modi-cache-add-inputs modi sig-list)
8926 (verilog-insert-indent "// End of automatics\n"))
8927 (when v2k (verilog-repair-close-comma))
8930 (defun verilog-auto-inout ()
8931 "Expand AUTOINOUT statements, as part of \\[verilog-auto].
8932 Make inout statements for any inout signal in an /*AUTOINST*/ that
8933 isn't declared elsewhere inside the module.
8936 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
8938 If placed inside the parenthesis of a module declaration, it creates
8939 Verilog 2001 style, else uses Verilog 1995 style.
8941 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
8942 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
8944 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
8946 Signals matching `verilog-auto-inout-ignore-regexp' are not included.
8948 An example (see `verilog-auto-inst' for what else is going on here):
8950 module ex_inout (ov,i)
8953 inst inst (/*AUTOINST*/);
8956 Typing \\[verilog-auto] will make this into:
8958 module ex_inout (ov,i)
8961 // Beginning of automatic inouts (from unused autoinst inouts)
8962 inout [31:0] ov; // From inst of inst.v
8963 // End of automatics
8964 inst inst (/*AUTOINST*/
8971 ;; Point must be at insertion point.
8972 (let* ((indent-pt (current-indentation))
8973 (v2k (verilog-in-paren))
8974 (modi (verilog-modi-current))
8975 (sig-list (verilog-signals-not-in
8976 (verilog-modi-get-sub-inouts modi)
8977 (append (verilog-modi-get-outputs modi)
8978 (verilog-modi-get-inouts modi)
8979 (verilog-modi-get-inputs modi)
8980 (verilog-modi-get-sub-inputs modi)
8981 (verilog-modi-get-sub-outputs modi)
8983 (setq sig-list (verilog-signals-not-matching-regexp
8984 sig-list verilog-auto-inout-ignore-regexp))
8986 (when v2k (verilog-repair-open-comma))
8988 (verilog-insert-indent "// Beginning of automatic inouts (from unused autoinst inouts)\n")
8989 (verilog-insert-definition sig-list "inout" indent-pt v2k)
8990 (verilog-modi-cache-add-inouts modi sig-list)
8991 (verilog-insert-indent "// End of automatics\n"))
8992 (when v2k (verilog-repair-close-comma))
8995 (defun verilog-auto-inout-module ()
8996 "Expand AUTOINOUTMODULE statements, as part of \\[verilog-auto].
8997 Take input/output/inout statements from the specified module and insert
8998 into the current module. This is useful for making null templates and
8999 shell modules which need to have identical I/O with another module. Any
9000 I/O which are already defined in this module will not be redefined.
9003 If placed inside the parenthesis of a module declaration, it creates
9004 Verilog 2001 style, else uses Verilog 1995 style.
9006 Concatenation and outputting partial busses is not supported.
9008 Module names must be resolvable to filenames. See `verilog-auto-inst'.
9010 Signals are not inserted in the same order as in the original module,
9011 though they will appear to be in the same order to a AUTOINST
9012 instantiating either module.
9016 module ex_shell (/*AUTOARG*/)
9017 /*AUTOINOUTMODULE(\"ex_main\")*/
9020 module ex_main (i,o,io)
9026 Typing \\[verilog-auto] will make this into:
9028 module ex_shell (/*AUTOARG*/i,o,io)
9029 /*AUTOINOUTMODULE(\"ex_main\")*/
9030 // Beginning of automatic in/out/inouts (from specific module)
9034 // End of automatics
9037 (let* ((submod (car (verilog-read-auto-params 1))) submodi)
9038 ;; Lookup position, etc of co-module
9039 ;; Note this may raise an error
9040 (when (setq submodi (verilog-modi-lookup submod t))
9041 (let* ((indent-pt (current-indentation))
9042 (v2k (verilog-in-paren))
9043 (modi (verilog-modi-current))
9044 (sig-list-i (verilog-signals-not-in
9045 (verilog-modi-get-inputs submodi)
9046 (append (verilog-modi-get-inputs modi))))
9047 (sig-list-o (verilog-signals-not-in
9048 (verilog-modi-get-outputs submodi)
9049 (append (verilog-modi-get-outputs modi))))
9050 (sig-list-io (verilog-signals-not-in
9051 (verilog-modi-get-inouts submodi)
9052 (append (verilog-modi-get-inouts modi)))))
9054 (when v2k (verilog-repair-open-comma))
9055 (when (or sig-list-i sig-list-o sig-list-io)
9056 (verilog-insert-indent "// Beginning of automatic in/out/inouts (from specific module)\n")
9057 ;; Don't sort them so a upper AUTOINST will match the main module
9058 (verilog-insert-definition sig-list-o "output" indent-pt v2k t)
9059 (verilog-insert-definition sig-list-io "inout" indent-pt v2k t)
9060 (verilog-insert-definition sig-list-i "input" indent-pt v2k t)
9061 (verilog-modi-cache-add-inputs modi sig-list-i)
9062 (verilog-modi-cache-add-outputs modi sig-list-o)
9063 (verilog-modi-cache-add-inouts modi sig-list-io)
9064 (verilog-insert-indent "// End of automatics\n"))
9065 (when v2k (verilog-repair-close-comma))
9068 (defun verilog-auto-sense-sigs (modi presense-sigs)
9069 "Return list of signals for current AUTOSENSE block."
9070 (let* ((sigss (verilog-read-always-signals))
9071 (sig-list (verilog-signals-not-params
9072 (verilog-signals-not-in (verilog-alw-get-inputs sigss)
9073 (append (and (not verilog-auto-sense-include-inputs)
9074 (verilog-alw-get-outputs sigss))
9075 (verilog-modi-get-consts modi)
9076 (verilog-modi-get-gparams modi)
9080 (defun verilog-auto-sense ()
9081 "Expand AUTOSENSE statements, as part of \\[verilog-auto].
9082 Replace the always (/*AUTOSENSE*/) sensitivity list (/*AS*/ for short)
9083 with one automatically derived from all inputs declared in the always
9084 statement. Signals that are generated within the same always block are NOT
9085 placed into the sensitivity list (see `verilog-auto-sense-include-inputs').
9086 Long lines are split based on the `fill-column', see \\[set-fill-column].
9089 Verilog does not allow memories (multidimensional arrays) in sensitivity
9090 lists. AUTOSENSE will thus exclude them, and add a /*memory or*/ comment.
9093 AUTOSENSE cannot always determine if a `define is a constant or a signal
9094 (it could be in a include file for example). If a `define or other signal
9095 is put into the AUTOSENSE list and is not desired, use the AUTO_CONSTANT
9096 declaration anywhere in the module (parenthesis are required):
9098 /* AUTO_CONSTANT ( `this_is_really_constant_dont_autosense_it ) */
9100 Better yet, use a parameter, which will be understood to be constant
9104 If AUTOSENSE makes a mistake, please report it. (First try putting
9105 a begin/end after your always!) As a workaround, if a signal that
9106 shouldn't be in the sensitivity list was, use the AUTO_CONSTANT above.
9107 If a signal should be in the sensitivity list wasn't, placing it before
9108 the /*AUTOSENSE*/ comment will prevent it from being deleted when the
9109 autos are updated (or added if it occurs there already).
9113 always @ (/*AUTOSENSE*/) begin
9114 /* AUTO_CONSTANT (`constant) */
9115 outin = ina | inb | `constant;
9119 Typing \\[verilog-auto] will make this into:
9121 always @ (/*AUTOSENSE*/ina or inb) begin
9122 /* AUTO_CONSTANT (`constant) */
9123 outin = ina | inb | `constant;
9128 (let* ((start-pt (save-excursion
9129 (verilog-re-search-backward "(" nil t)
9131 (indent-pt (save-excursion
9132 (or (and (goto-char start-pt) (1+ (current-column)))
9133 (current-indentation))))
9134 (modi (verilog-modi-current))
9135 (sig-memories (verilog-signals-memory
9137 (verilog-modi-get-regs modi)
9138 (verilog-modi-get-wires modi))))
9139 sig-list not-first presense-sigs)
9140 ;; Read signals in always, eliminate outputs from sense list
9141 (setq presense-sigs (verilog-signals-from-signame
9143 (verilog-read-signals start-pt (point)))))
9144 (setq sig-list (verilog-auto-sense-sigs modi presense-sigs))
9146 (let ((tlen (length sig-list)))
9147 (setq sig-list (verilog-signals-not-in sig-list sig-memories))
9148 (if (not (eq tlen (length sig-list))) (insert " /*memory or*/ "))))
9149 (if (and presense-sigs ;; Add a "or" if not "(.... or /*AUTOSENSE*/"
9150 (save-excursion (goto-char (point))
9151 (verilog-re-search-backward "[a-zA-Z0-9$_.%`]+" start-pt t)
9152 (verilog-re-search-backward "\\s-" start-pt t)
9153 (while (looking-at "\\s-`endif")
9154 (verilog-re-search-backward "[a-zA-Z0-9$_.%`]+" start-pt t)
9155 (verilog-re-search-backward "\\s-" start-pt t))
9156 (not (looking-at "\\s-or\\b"))))
9158 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
9160 (cond ((> (+ 4 (current-column) (length (verilog-sig-name (car sig-list)))) fill-column) ;+4 for width of or
9162 (indent-to indent-pt)
9163 (if not-first (insert "or ")))
9164 (not-first (insert " or ")))
9165 (insert (verilog-sig-name (car sig-list)))
9166 (setq sig-list (cdr sig-list)
9170 (defun verilog-auto-reset ()
9171 "Expand AUTORESET statements, as part of \\[verilog-auto].
9172 Replace the /*AUTORESET*/ comment with code to initialize all
9173 registers set elsewhere in the always block.
9176 AUTORESET will not clear memories.
9178 AUTORESET uses <= if there are any <= in the block, else it uses =.
9180 /*AUTORESET*/ presumes that any signals mentioned between the previous
9181 begin/case/if statement and the AUTORESET comment are being reset manually
9182 and should not be automatically reset. This includes omitting any signals
9183 used on the right hand side of assignments.
9185 By default, AUTORESET will include the width of the signal in the autos,
9186 this is a recent change. To control this behavior, see
9187 `verilog-auto-reset-widths'.
9189 AUTORESET ties signals to deasserted, which is presumed to be zero.
9190 Signals that match `verilog-active-low-regexp' will be deasserted by tieing
9195 always @(posedge clk or negedge reset_l) begin
9207 Typing \\[verilog-auto] will make this into:
9209 always @(posedge core_clk or negedge reset_l) begin
9213 // Beginning of autoreset for uninitialized flops
9216 // End of automatics
9228 (let* ((indent-pt (current-indentation))
9229 (modi (verilog-modi-current))
9230 (all-list (verilog-modi-get-signals modi))
9231 sigss sig-list prereset-sigs assignment-str)
9232 ;; Read signals in always, eliminate outputs from reset list
9233 (setq prereset-sigs (verilog-signals-from-signame
9235 (verilog-read-signals
9237 (verilog-re-search-backward "\\(@\\|\\<begin\\>\\|\\<if\\>\\|\\<case\\>\\)" nil t)
9241 (verilog-re-search-backward "@" nil t)
9242 (setq sigss (verilog-read-always-signals)))
9243 (setq assignment-str (if (verilog-alw-get-uses-delayed sigss)
9244 (concat " <= " verilog-assignment-delay)
9246 (setq sig-list (verilog-signals-not-in (verilog-alw-get-outputs sigss)
9248 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
9251 (indent-to indent-pt)
9252 (insert "// Beginning of autoreset for uninitialized flops\n");
9253 (indent-to indent-pt)
9255 (let ((sig (or (assoc (verilog-sig-name (car sig-list)) all-list) ;; As sig-list has no widths
9257 (insert (verilog-sig-name sig)
9259 (verilog-sig-tieoff sig (not verilog-auto-reset-widths))
9261 (indent-to indent-pt)
9262 (setq sig-list (cdr sig-list))))
9263 (insert "// End of automatics"))
9266 (defun verilog-auto-tieoff ()
9267 "Expand AUTOTIEOFF statements, as part of \\[verilog-auto].
9268 Replace the /*AUTOTIEOFF*/ comment with code to wire-tie all unused output
9269 signals to deasserted.
9271 /*AUTOTIEOFF*/ is used to make stub modules; modules that have the same
9272 input/output list as another module, but no internals. Specifically, it
9273 finds all outputs in the module, and if that input is not otherwise declared
9274 as a register or wire, creates a tieoff.
9276 AUTORESET ties signals to deasserted, which is presumed to be zero.
9277 Signals that match `verilog-active-low-regexp' will be deasserted by tieing
9280 An example of making a stub for another module:
9282 module FooStub (/*AUTOINST*/);
9283 /*AUTOINOUTMODULE(\"Foo\")*/
9285 // verilator lint_off UNUSED
9286 wire _unused_ok = &{1'b0,
9289 // verilator lint_on UNUSED
9292 Typing \\[verilog-auto] will make this into:
9294 module FooStub (/*AUTOINST*/...);
9295 /*AUTOINOUTMODULE(\"Foo\")*/
9296 // Beginning of autotieoff
9298 // End of automatics
9301 // Beginning of autotieoff
9302 wire [2:0] foo = 3'b0;
9303 // End of automatics
9309 (let* ((indent-pt (current-indentation))
9310 (modi (verilog-modi-current))
9311 (sig-list (verilog-signals-not-in
9312 (verilog-modi-get-outputs modi)
9313 (append (verilog-modi-get-wires modi)
9314 (verilog-modi-get-regs modi)
9315 (verilog-modi-get-assigns modi)
9316 (verilog-modi-get-consts modi)
9317 (verilog-modi-get-gparams modi)
9318 (verilog-modi-get-sub-outputs modi)
9319 (verilog-modi-get-sub-inouts modi)
9323 (verilog-insert-indent "// Beginning of automatic tieoffs (for this module's unterminated outputs)\n")
9324 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
9325 (verilog-modi-cache-add-wires modi sig-list) ; Before we trash list
9327 (let ((sig (car sig-list)))
9328 (verilog-insert-one-definition sig "wire" indent-pt)
9329 (indent-to (max 48 (+ indent-pt 40)))
9330 (insert "= " (verilog-sig-tieoff sig)
9332 (setq sig-list (cdr sig-list))))
9333 (verilog-insert-indent "// End of automatics\n")
9336 (defun verilog-auto-unused ()
9337 "Expand AUTOUNUSED statements, as part of \\[verilog-auto].
9338 Replace the /*AUTOUNUSED*/ comment with a comma separated list of all unused
9339 input and inout signals.
9341 /*AUTOUNUSED*/ is used to make stub modules; modules that have the same
9342 input/output list as another module, but no internals. Specifically, it
9343 finds all inputs and inouts in the module, and if that input is not otherwise
9344 used, adds it to a comma separated list.
9346 The comma separated list is intended to be used to create a _unused_ok
9347 signal. Using the exact name \"_unused_ok\" for name of the temporary
9348 signal is recommended as it will insure maximum forward compatibility, it
9349 also makes lint warnings easy to understand; ignore any unused warnings
9350 with \"unused\" in the signal name.
9352 To reduce simulation time, the _unused_ok signal should be forced to a
9353 constant to prevent wiggling. The easiest thing to do is use a
9354 reduction-and with 1'b0 as shown.
9356 This way all unused signals are in one place, making it convenient to add
9357 your tool's specific pragmas around the assignment to disable any unused
9360 You can add signals you do not want included in AUTOUNUSED with
9361 `verilog-auto-unused-ignore-regexp'.
9363 An example of making a stub for another module:
9365 module FooStub (/*AUTOINST*/);
9366 /*AUTOINOUTMODULE(\"Foo\")*/
9368 // verilator lint_off UNUSED
9369 wire _unused_ok = &{1'b0,
9372 // verilator lint_on UNUSED
9375 Typing \\[verilog-auto] will make this into:
9378 // verilator lint_off UNUSED
9379 wire _unused_ok = &{1'b0,
9381 // Beginning of automatics
9385 // End of automatics
9387 // verilator lint_on UNUSED
9392 (let* ((indent-pt (progn (search-backward "/*") (current-column)))
9393 (modi (verilog-modi-current))
9394 (sig-list (verilog-signals-not-in
9395 (append (verilog-modi-get-inputs modi)
9396 (verilog-modi-get-inouts modi))
9397 (append (verilog-modi-get-sub-inputs modi)
9398 (verilog-modi-get-sub-inouts modi)
9400 (setq sig-list (verilog-signals-not-matching-regexp
9401 sig-list verilog-auto-unused-ignore-regexp))
9404 (verilog-insert-indent "// Beginning of automatic unused inputs\n")
9405 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
9407 (let ((sig (car sig-list)))
9408 (indent-to indent-pt)
9409 (insert (verilog-sig-name sig) ",\n")
9410 (setq sig-list (cdr sig-list))))
9411 (verilog-insert-indent "// End of automatics\n")
9414 (defun verilog-enum-ascii (signm elim-regexp)
9415 "Convert a enum name SIGNM to a ascii string for insertion.
9416 Remove user provided prefix ELIM-REGEXP."
9417 (or elim-regexp (setq elim-regexp "_ DONT MATCH IT_"))
9418 (let ((case-fold-search t))
9419 ;; All upper becomes all lower for readability
9420 (downcase (verilog-string-replace-matches elim-regexp "" nil nil signm))))
9422 (defun verilog-auto-ascii-enum ()
9423 "Expand AUTOASCIIENUM statements, as part of \\[verilog-auto].
9424 Create a register to contain the ASCII decode of a enumerated signal type.
9425 This will allow trace viewers to show the ASCII name of states.
9427 First, parameters are built into a enumeration using the synopsys enum
9428 comment. The comment must be between the keyword and the symbol.
9429 \(Annoying, but that's what Synopsys's dc_shell FSM reader requires.)
9431 Next, registers which that enum applies to are also tagged with the same
9432 enum. Synopsys also suggests labeling state vectors, but `verilog-mode'
9435 Finally, a AUTOASCIIENUM command is used.
9437 The first parameter is the name of the signal to be decoded.
9439 The second parameter is the name to store the ASCII code into. For the
9440 signal foo, I suggest the name _foo__ascii, where the leading _ indicates
9441 a signal that is just for simulation, and the magic characters _ascii
9442 tell viewers like Dinotrace to display in ASCII format.
9444 The final optional parameter is a string which will be removed from the
9449 //== State enumeration
9450 parameter [2:0] // synopsys enum state_info
9454 //== State variables
9455 reg [2:0] /* synopsys enum state_info */
9456 state_r; /* synopsys state_vector state_r */
9457 reg [2:0] /* synopsys enum state_info */
9460 //== ASCII state decoding
9462 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
9464 Typing \\[verilog-auto] will make this into:
9466 ... same front matter ...
9468 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
9469 // Beginning of automatic ASCII enum decoding
9470 reg [39:0] state_ascii_r; // Decode of state_r
9471 always @(state_r) begin
9473 SM_IDLE: state_ascii_r = \"idle \";
9474 SM_SEND: state_ascii_r = \"send \";
9475 SM_WAIT1: state_ascii_r = \"wait1\";
9476 default: state_ascii_r = \"%Erro\";
9479 // End of automatics"
9481 (let* ((params (verilog-read-auto-params 2 3))
9482 (undecode-name (nth 0 params))
9483 (ascii-name (nth 1 params))
9484 (elim-regexp (nth 2 params))
9486 (indent-pt (current-indentation))
9487 (modi (verilog-modi-current))
9489 (sig-list-consts (append (verilog-modi-get-consts modi)
9490 (verilog-modi-get-gparams modi)))
9491 (sig-list-all (append (verilog-modi-get-regs modi)
9492 (verilog-modi-get-outputs modi)
9493 (verilog-modi-get-inouts modi)
9494 (verilog-modi-get-inputs modi)
9495 (verilog-modi-get-wires modi)))
9497 (undecode-sig (or (assoc undecode-name sig-list-all)
9498 (error "%s: Signal %s not found in design" (verilog-point-text) undecode-name)))
9499 (undecode-enum (or (verilog-sig-enum undecode-sig)
9500 (error "%s: Signal %s does not have a enum tag" (verilog-point-text) undecode-name)))
9502 (enum-sigs (or (verilog-signals-matching-enum sig-list-consts undecode-enum)
9503 (error "%s: No state definitions for %s" (verilog-point-text) undecode-enum)))
9508 ;; Find number of ascii chars needed
9509 (let ((tmp-sigs enum-sigs))
9511 (setq enum-chars (max enum-chars (length (verilog-sig-name (car tmp-sigs))))
9512 ascii-chars (max ascii-chars (length (verilog-enum-ascii
9513 (verilog-sig-name (car tmp-sigs))
9515 tmp-sigs (cdr tmp-sigs))))
9518 (verilog-insert-indent "// Beginning of automatic ASCII enum decoding\n")
9519 (let ((decode-sig-list (list (list ascii-name (format "[%d:0]" (- (* ascii-chars 8) 1))
9520 (concat "Decode of " undecode-name) nil nil))))
9521 (verilog-insert-definition decode-sig-list "reg" indent-pt nil)
9522 (verilog-modi-cache-add-regs modi decode-sig-list))
9524 (verilog-insert-indent "always @(" undecode-name ") begin\n")
9525 (setq indent-pt (+ indent-pt verilog-indent-level))
9526 (indent-to indent-pt)
9527 (insert "case ({" undecode-name "})\n")
9528 (setq indent-pt (+ indent-pt verilog-case-indent))
9530 (let ((tmp-sigs enum-sigs)
9531 (chrfmt (format "%%-%ds %s = \"%%-%ds\";\n" (1+ (max 8 enum-chars))
9532 ascii-name ascii-chars))
9533 (errname (substring "%Error" 0 (min 6 ascii-chars))))
9535 (verilog-insert-indent
9536 (format chrfmt (concat (verilog-sig-name (car tmp-sigs)) ":")
9537 (verilog-enum-ascii (verilog-sig-name (car tmp-sigs))
9539 (setq tmp-sigs (cdr tmp-sigs)))
9540 (verilog-insert-indent (format chrfmt "default:" errname)))
9542 (setq indent-pt (- indent-pt verilog-case-indent))
9543 (verilog-insert-indent "endcase\n")
9544 (setq indent-pt (- indent-pt verilog-indent-level))
9545 (verilog-insert-indent "end\n"
9546 "// End of automatics\n")
9549 (defun verilog-auto-templated-rel ()
9550 "Replace Templated relative line numbers with absolute line numbers.
9551 Internal use only. This hacks around the line numbers in AUTOINST Templates
9552 being different from the final output's line numbering."
9553 (let ((templateno 0) (template-line (list 0)))
9554 ;; Find line number each template is on
9555 (goto-char (point-min))
9556 (while (search-forward "AUTO_TEMPLATE" nil t)
9557 (setq templateno (1+ templateno))
9559 (cons (count-lines (point-min) (point)) template-line)))
9560 (setq template-line (nreverse template-line))
9561 ;; Replace T# L# with absolute line number
9562 (goto-char (point-min))
9563 (while (re-search-forward " Templated T\\([0-9]+\\) L\\([0-9]+\\)" nil t)
9565 (concat " Templated "
9566 (int-to-string (+ (nth (string-to-number (match-string 1))
9568 (string-to-number (match-string 2)))))
9576 (defun verilog-auto (&optional inject) ; Use verilog-inject-auto instead of passing a arg
9577 "Expand AUTO statements.
9578 Look for any /*AUTO...*/ commands in the code, as used in
9579 instantiations or argument headers. Update the list of signals
9580 following the /*AUTO...*/ command.
9582 Use \\[verilog-delete-auto] to remove the AUTOs.
9584 Use \\[verilog-inject-auto] to insert AUTOs for the first time.
9586 Use \\[verilog-faq] for a pointer to frequently asked questions.
9588 The hooks `verilog-before-auto-hook' and `verilog-auto-hook' are
9589 called before and after this function, respectively.
9592 module (/*AUTOARG*/)
9597 somesub sub #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);
9599 You can also update the AUTOs from the shell using:
9600 emacs --batch <filenames.v> -f verilog-batch-auto
9601 Or fix indentation with:
9602 emacs --batch <filenames.v> -f verilog-batch-indent
9603 Likewise, you can delete or inject AUTOs with:
9604 emacs --batch <filenames.v> -f verilog-batch-delete-auto
9605 emacs --batch <filenames.v> -f verilog-batch-inject-auto
9607 Using \\[describe-function], see also:
9608 `verilog-auto-arg' for AUTOARG module instantiations
9609 `verilog-auto-ascii-enum' for AUTOASCIIENUM enumeration decoding
9610 `verilog-auto-inout-module' for AUTOINOUTMODULE copying i/o from elsewhere
9611 `verilog-auto-inout' for AUTOINOUT making hierarchy inouts
9612 `verilog-auto-input' for AUTOINPUT making hierarchy inputs
9613 `verilog-auto-inst' for AUTOINST instantiation pins
9614 `verilog-auto-star' for AUTOINST .* SystemVerilog pins
9615 `verilog-auto-inst-param' for AUTOINSTPARAM instantiation params
9616 `verilog-auto-output' for AUTOOUTPUT making hierarchy outputs
9617 `verilog-auto-output-every' for AUTOOUTPUTEVERY making all outputs
9618 `verilog-auto-reg' for AUTOREG registers
9619 `verilog-auto-reg-input' for AUTOREGINPUT instantiation registers
9620 `verilog-auto-reset' for AUTORESET flop resets
9621 `verilog-auto-sense' for AUTOSENSE always sensitivity lists
9622 `verilog-auto-tieoff' for AUTOTIEOFF output tieoffs
9623 `verilog-auto-unused' for AUTOUNUSED unused inputs/inouts
9624 `verilog-auto-wire' for AUTOWIRE instantiation wires
9626 `verilog-read-defines' for reading `define values
9627 `verilog-read-includes' for reading `includes
9629 If you have bugs with these autos, try contacting the AUTOAUTHOR
9630 Wilson Snyder (wsnyder@wsnyder.org), and/or see http://www.veripool.com."
9632 (unless noninteractive (message "Updating AUTOs..."))
9633 (if (fboundp 'dinotrace-unannotate-all)
9634 (dinotrace-unannotate-all))
9635 (let ((oldbuf (if (not (buffer-modified-p))
9637 ;; Before version 20, match-string with font-lock returns a
9638 ;; vector that is not equal to the string. IE if on "input"
9639 ;; nil==(equal "input" (progn (looking-at "input") (match-string 0)))
9640 (fontlocked (when (and (boundp 'font-lock-mode)
9642 (font-lock-mode nil)
9646 ;; If we're not in verilog-mode, change syntax table so parsing works right
9647 (unless (eq major-mode `verilog-mode) (verilog-mode))
9648 ;; Allow user to customize
9649 (run-hooks 'verilog-before-auto-hook)
9650 ;; Try to save the user from needing to revert-file to reread file local-variables
9651 (verilog-auto-reeval-locals)
9652 (verilog-read-auto-lisp (point-min) (point-max))
9653 (verilog-getopt-flags)
9654 ;; These two may seem obvious to do always, but on large includes it can be way too slow
9655 (when verilog-auto-read-includes
9656 (verilog-read-includes)
9657 (verilog-read-defines nil nil t))
9658 ;; This particular ordering is important
9659 ;; INST: Lower modules correct, no internal dependencies, FIRST
9660 (verilog-preserve-cache
9661 ;; Clear existing autos else we'll be screwed by existing ones
9662 (verilog-delete-auto)
9663 ;; Injection if appropriate
9665 (verilog-inject-inst)
9666 (verilog-inject-sense)
9667 (verilog-inject-arg))
9669 (verilog-auto-search-do "/*AUTOINSTPARAM*/" 'verilog-auto-inst-param)
9670 (verilog-auto-search-do "/*AUTOINST*/" 'verilog-auto-inst)
9671 (verilog-auto-search-do ".*" 'verilog-auto-star)
9672 ;; Doesn't matter when done, but combine it with a common changer
9673 (verilog-auto-re-search-do "/\\*\\(AUTOSENSE\\|AS\\)\\*/" 'verilog-auto-sense)
9674 (verilog-auto-re-search-do "/\\*AUTORESET\\*/" 'verilog-auto-reset)
9675 ;; Must be done before autoin/out as creates a reg
9676 (verilog-auto-re-search-do "/\\*AUTOASCIIENUM([^)]*)\\*/" 'verilog-auto-ascii-enum)
9678 ;; first in/outs from other files
9679 (verilog-auto-re-search-do "/\\*AUTOINOUTMODULE([^)]*)\\*/" 'verilog-auto-inout-module)
9680 ;; next in/outs which need previous sucked inputs first
9681 (verilog-auto-search-do "/*AUTOOUTPUT*/" 'verilog-auto-output)
9682 (verilog-auto-search-do "/*AUTOINPUT*/" 'verilog-auto-input)
9683 (verilog-auto-search-do "/*AUTOINOUT*/" 'verilog-auto-inout)
9684 ;; Then tie off those in/outs
9685 (verilog-auto-search-do "/*AUTOTIEOFF*/" 'verilog-auto-tieoff)
9686 ;; Wires/regs must be after inputs/outputs
9687 (verilog-auto-search-do "/*AUTOWIRE*/" 'verilog-auto-wire)
9688 (verilog-auto-search-do "/*AUTOREG*/" 'verilog-auto-reg)
9689 (verilog-auto-search-do "/*AUTOREGINPUT*/" 'verilog-auto-reg-input)
9690 ;; outputevery needs AUTOOUTPUTs done first
9691 (verilog-auto-search-do "/*AUTOOUTPUTEVERY*/" 'verilog-auto-output-every)
9692 ;; After we've created all new variables
9693 (verilog-auto-search-do "/*AUTOUNUSED*/" 'verilog-auto-unused)
9694 ;; Must be after all inputs outputs are generated
9695 (verilog-auto-search-do "/*AUTOARG*/" 'verilog-auto-arg)
9696 ;; Fix line numbers (comments only)
9697 (verilog-auto-templated-rel)
9700 (run-hooks 'verilog-auto-hook)
9702 (set (make-local-variable 'verilog-auto-update-tick) (buffer-modified-tick))
9704 ;; If end result is same as when started, clear modified flag
9705 (cond ((and oldbuf (equal oldbuf (buffer-string)))
9706 (set-buffer-modified-p nil)
9707 (unless noninteractive (message "Updating AUTOs...done (no changes)")))
9708 (t (unless noninteractive (message "Updating AUTOs...done")))))
9711 ;; Restore font-lock
9712 (when fontlocked (font-lock-mode t)))
9717 ;; Skeleton based code insertion
9719 (defvar verilog-template-map
9720 (let ((map (make-sparse-keymap)))
9721 (define-key map "a" 'verilog-sk-always)
9722 (define-key map "b" 'verilog-sk-begin)
9723 (define-key map "c" 'verilog-sk-case)
9724 (define-key map "f" 'verilog-sk-for)
9725 (define-key map "g" 'verilog-sk-generate)
9726 (define-key map "h" 'verilog-sk-header)
9727 (define-key map "i" 'verilog-sk-initial)
9728 (define-key map "j" 'verilog-sk-fork)
9729 (define-key map "m" 'verilog-sk-module)
9730 (define-key map "p" 'verilog-sk-primitive)
9731 (define-key map "r" 'verilog-sk-repeat)
9732 (define-key map "s" 'verilog-sk-specify)
9733 (define-key map "t" 'verilog-sk-task)
9734 (define-key map "w" 'verilog-sk-while)
9735 (define-key map "x" 'verilog-sk-casex)
9736 (define-key map "z" 'verilog-sk-casez)
9737 (define-key map "?" 'verilog-sk-if)
9738 (define-key map ":" 'verilog-sk-else-if)
9739 (define-key map "/" 'verilog-sk-comment)
9740 (define-key map "A" 'verilog-sk-assign)
9741 (define-key map "F" 'verilog-sk-function)
9742 (define-key map "I" 'verilog-sk-input)
9743 (define-key map "O" 'verilog-sk-output)
9744 (define-key map "S" 'verilog-sk-state-machine)
9745 (define-key map "=" 'verilog-sk-inout)
9746 (define-key map "W" 'verilog-sk-wire)
9747 (define-key map "R" 'verilog-sk-reg)
9748 (define-key map "D" 'verilog-sk-define-signal)
9750 "Keymap used in Verilog mode for smart template operations.")
9754 ;; Place the templates into Verilog Mode. They may be inserted under any key.
9755 ;; C-c C-t will be the default. If you use templates a lot, you
9756 ;; may want to consider moving the binding to another key in your .emacs
9759 ;(define-key verilog-mode-map "\C-ct" verilog-template-map)
9760 (define-key verilog-mode-map "\C-c\C-t" verilog-template-map)
9762 ;;; ---- statement skeletons ------------------------------------------
9764 (define-skeleton verilog-sk-prompt-condition
9765 "Prompt for the loop condition."
9766 "[condition]: " str )
9768 (define-skeleton verilog-sk-prompt-init
9769 "Prompt for the loop init statement."
9770 "[initial statement]: " str )
9772 (define-skeleton verilog-sk-prompt-inc
9773 "Prompt for the loop increment statement."
9774 "[increment statement]: " str )
9776 (define-skeleton verilog-sk-prompt-name
9777 "Prompt for the name of something."
9780 (define-skeleton verilog-sk-prompt-clock
9781 "Prompt for the name of something."
9782 "name and edge of clock(s): " str)
9784 (defvar verilog-sk-reset nil)
9785 (defun verilog-sk-prompt-reset ()
9786 "Prompt for the name of a state machine reset."
9787 (setq verilog-sk-reset (read-string "name of reset: " "rst")))
9790 (define-skeleton verilog-sk-prompt-state-selector
9791 "Prompt for the name of a state machine selector."
9792 "name of selector (eg {a,b,c,d}): " str )
9794 (define-skeleton verilog-sk-prompt-output
9795 "Prompt for the name of something."
9798 (define-skeleton verilog-sk-prompt-msb
9799 "Prompt for least significant bit specification."
9800 "msb:" str & ?: & (verilog-sk-prompt-lsb) | -1 )
9802 (define-skeleton verilog-sk-prompt-lsb
9803 "Prompt for least significant bit specification."
9806 (defvar verilog-sk-p nil)
9807 (define-skeleton verilog-sk-prompt-width
9808 "Prompt for a width specification."
9811 (setq verilog-sk-p (point))
9812 (verilog-sk-prompt-msb)
9813 (if (> (point) verilog-sk-p) "] " " ")))
9815 (defun verilog-sk-header ()
9816 "Insert a descriptive header at the top of the file."
9819 (goto-char (point-min))
9820 (verilog-sk-header-tmpl)))
9822 (define-skeleton verilog-sk-header-tmpl
9823 "Insert a comment block containing the module title, author, etc."
9825 "// -*- Mode: Verilog -*-"
9826 "\n// Filename : " (buffer-name)
9827 "\n// Description : " str
9828 "\n// Author : " (user-full-name)
9829 "\n// Created On : " (current-time-string)
9830 "\n// Last Modified By: ."
9831 "\n// Last Modified On: ."
9832 "\n// Update Count : 0"
9833 "\n// Status : Unknown, Use with caution!"
9836 (define-skeleton verilog-sk-module
9837 "Insert a module definition."
9839 > "module " (verilog-sk-prompt-name) " (/*AUTOARG*/ ) ;" \n
9841 > (- verilog-indent-level-behavioral) "endmodule" (progn (electric-verilog-terminate-line) nil))
9843 (define-skeleton verilog-sk-primitive
9844 "Insert a task definition."
9846 > "primitive " (verilog-sk-prompt-name) " ( " (verilog-sk-prompt-output) ("input:" ", " str ) " );"\n
9848 > (- verilog-indent-level-behavioral) "endprimitive" (progn (electric-verilog-terminate-line) nil))
9850 (define-skeleton verilog-sk-task
9851 "Insert a task definition."
9853 > "task " (verilog-sk-prompt-name) & ?; \n
9857 > (- verilog-indent-level-behavioral) "end" \n
9858 > (- verilog-indent-level-behavioral) "endtask" (progn (electric-verilog-terminate-line) nil))
9860 (define-skeleton verilog-sk-function
9861 "Insert a function definition."
9863 > "function [" (verilog-sk-prompt-width) | -1 (verilog-sk-prompt-name) ?; \n
9867 > (- verilog-indent-level-behavioral) "end" \n
9868 > (- verilog-indent-level-behavioral) "endfunction" (progn (electric-verilog-terminate-line) nil))
9870 (define-skeleton verilog-sk-always
9871 "Insert always block. Uses the minibuffer to prompt
9872 for sensitivity list."
9874 > "always @ ( /*AUTOSENSE*/ ) begin\n"
9876 > (- verilog-indent-level-behavioral) "end" \n >
9879 (define-skeleton verilog-sk-initial
9880 "Insert an initial block."
9884 > (- verilog-indent-level-behavioral) "end" \n > )
9886 (define-skeleton verilog-sk-specify
9887 "Insert specify block. "
9891 > (- verilog-indent-level-behavioral) "endspecify" \n > )
9893 (define-skeleton verilog-sk-generate
9894 "Insert generate block. "
9898 > (- verilog-indent-level-behavioral) "endgenerate" \n > )
9900 (define-skeleton verilog-sk-begin
9901 "Insert begin end block. Uses the minibuffer to prompt for name"
9903 > "begin" (verilog-sk-prompt-name) \n
9905 > (- verilog-indent-level-behavioral) "end"
9908 (define-skeleton verilog-sk-fork
9909 "Insert an fork join block."
9914 > (- verilog-indent-level-behavioral) "end" \n
9917 > (- verilog-indent-level-behavioral) "end" \n
9918 > (- verilog-indent-level-behavioral) "join" \n
9922 (define-skeleton verilog-sk-case
9923 "Build skeleton case statement, prompting for the selector expression,
9924 and the case items."
9925 "[selector expression]: "
9926 > "case (" str ") " \n
9927 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n )
9928 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
9930 (define-skeleton verilog-sk-casex
9931 "Build skeleton casex statement, prompting for the selector expression,
9932 and the case items."
9933 "[selector expression]: "
9934 > "casex (" str ") " \n
9935 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n )
9936 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
9938 (define-skeleton verilog-sk-casez
9939 "Build skeleton casez statement, prompting for the selector expression,
9940 and the case items."
9941 "[selector expression]: "
9942 > "casez (" str ") " \n
9943 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n )
9944 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
9946 (define-skeleton verilog-sk-if
9947 "Insert a skeleton if statement."
9948 > "if (" (verilog-sk-prompt-condition) & ")" " begin" \n
9950 > (- verilog-indent-level-behavioral) "end " \n )
9952 (define-skeleton verilog-sk-else-if
9953 "Insert a skeleton else if statement."
9954 > (verilog-indent-line) "else if ("
9955 (progn (setq verilog-sk-p (point)) nil) (verilog-sk-prompt-condition) (if (> (point) verilog-sk-p) ") " -1 ) & " begin" \n
9957 > "end" (progn (electric-verilog-terminate-line) nil))
9959 (define-skeleton verilog-sk-datadef
9960 "Common routine to get data definition"
9962 (verilog-sk-prompt-width) | -1 ("name (RET to end):" str ", ") -2 ";" \n)
9964 (define-skeleton verilog-sk-input
9965 "Insert an input definition."
9967 > "input [" (verilog-sk-datadef))
9969 (define-skeleton verilog-sk-output
9970 "Insert an output definition."
9972 > "output [" (verilog-sk-datadef))
9974 (define-skeleton verilog-sk-inout
9975 "Insert an inout definition."
9977 > "inout [" (verilog-sk-datadef))
9979 (defvar verilog-sk-signal nil)
9980 (define-skeleton verilog-sk-def-reg
9981 "Insert a reg definition."
9983 > "reg [" (verilog-sk-prompt-width) | -1 verilog-sk-signal ";" \n (verilog-pretty-declarations) )
9985 (defun verilog-sk-define-signal ()
9986 "Insert a definition of signal under point at top of module."
9989 (sig-re "[a-zA-Z0-9_]*")
9990 (v1 (buffer-substring
9992 (skip-chars-backward sig-re)
9995 (skip-chars-forward sig-re)
9998 (if (not (member v1 verilog-keywords))
10000 (setq verilog-sk-signal v1)
10001 (verilog-beg-of-defun)
10002 (verilog-end-of-statement)
10003 (verilog-forward-syntactic-ws)
10004 (verilog-sk-def-reg)
10005 (message "signal at point is %s" v1))
10006 (message "object at point (%s) is a keyword" v1))
10011 (define-skeleton verilog-sk-wire
10012 "Insert a wire definition."
10014 > "wire [" (verilog-sk-datadef))
10016 (define-skeleton verilog-sk-reg
10017 "Insert a reg definition."
10019 > "reg [" (verilog-sk-datadef))
10021 (define-skeleton verilog-sk-assign
10022 "Insert a skeleton assign statement."
10024 > "assign " (verilog-sk-prompt-name) " = " _ ";" \n)
10026 (define-skeleton verilog-sk-while
10027 "Insert a skeleton while loop statement."
10029 > "while (" (verilog-sk-prompt-condition) ") begin" \n
10031 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
10033 (define-skeleton verilog-sk-repeat
10034 "Insert a skeleton repeat loop statement."
10036 > "repeat (" (verilog-sk-prompt-condition) ") begin" \n
10038 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
10040 (define-skeleton verilog-sk-for
10041 "Insert a skeleton while loop statement."
10044 (verilog-sk-prompt-init) "; "
10045 (verilog-sk-prompt-condition) "; "
10046 (verilog-sk-prompt-inc)
10049 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
10051 (define-skeleton verilog-sk-comment
10052 "Inserts three comment lines, making a display comment."
10058 (define-skeleton verilog-sk-state-machine
10059 "Insert a state machine definition."
10060 "Name of state variable: "
10061 '(setq input "state")
10062 > "// State registers for " str | -23 \n
10063 '(setq verilog-sk-state str)
10064 > "reg [" (verilog-sk-prompt-width) | -1 verilog-sk-state ", next_" verilog-sk-state ?; \n
10067 > "// State FF for " verilog-sk-state \n
10068 > "always @ ( " (read-string "clock:" "posedge clk") " or " (verilog-sk-prompt-reset) " ) begin" \n
10069 > "if ( " verilog-sk-reset " ) " verilog-sk-state " = 0; else" \n
10070 > verilog-sk-state " = next_" verilog-sk-state ?; \n
10071 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil)
10073 > "// Next State Logic for " verilog-sk-state \n
10074 > "always @ ( /*AUTOSENSE*/ ) begin\n"
10075 > "case (" (verilog-sk-prompt-state-selector) ") " \n
10076 > ("case selector: " str ": begin" \n > "next_" verilog-sk-state " = " _ ";" \n > (- verilog-indent-level-behavioral) "end" \n )
10077 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil)
10078 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil))
10080 ;; Eliminate compile warning
10082 (if (not (boundp 'mode-popup-menu))
10083 (defvar mode-popup-menu nil "Compatibility with XEmacs.")))
10085 ;; ---- add menu 'Statements' in Verilog mode (MH)
10086 (defun verilog-add-statement-menu ()
10087 "Add the menu 'Statements' to the menu bar in Verilog mode."
10088 (if (featurep 'xemacs)
10090 (easy-menu-add verilog-stmt-menu)
10091 (easy-menu-add verilog-menu)
10092 (setq mode-popup-menu (cons "Verilog Mode" verilog-stmt-menu)))))
10094 (add-hook 'verilog-mode-hook 'verilog-add-statement-menu)
10099 ;; Include file loading with mouse/return event
10101 ;; idea & first impl.: M. Rouat (eldo-mode.el)
10102 ;; second (emacs/xemacs) impl.: G. Van der Plas (spice-mode.el)
10104 (if (featurep 'xemacs)
10106 (require 'lucid)) ;; what else can we do ??
10108 (defconst verilog-include-file-regexp
10109 "^`include\\s-+\"\\([^\n\"]*\\)\""
10110 "Regexp that matches the include file.")
10112 (defvar verilog-mode-mouse-map
10113 (let ((map (make-sparse-keymap))) ; as described in info pages, make a map
10114 (set-keymap-parent map verilog-mode-map)
10115 ;; mouse button bindings
10116 (define-key map "\r" 'verilog-load-file-at-point)
10117 (if (featurep 'xemacs)
10118 (define-key map 'button2 'verilog-load-file-at-mouse);ffap-at-mouse ?
10119 (define-key map [mouse-2] 'verilog-load-file-at-mouse))
10120 (if (featurep 'xemacs)
10121 (define-key map 'Sh-button2 'mouse-yank) ; you wanna paste don't you ?
10122 (define-key map [S-mouse-2] 'mouse-yank-at-click))
10124 "Map containing mouse bindings for `verilog-mode'.")
10127 (defun verilog-colorize-include-files (beg end old-len)
10128 "This function colorizes included files when the mouse passes over them.
10129 Clicking on the middle-mouse button loads them in a buffer (as in dired)."
10134 (setq end-point (verilog-get-end-of-line))
10136 (beginning-of-line) ; scan entire line !
10137 ;; delete overlays existing on this line
10138 (let ((overlays (overlays-in (point) end-point)))
10141 (overlay-get (car overlays) 'detachable)
10142 (overlay-get (car overlays) 'verilog-include-file))
10143 (delete-overlay (car overlays)))
10144 (setq overlays (cdr overlays)))) ; let
10145 ;; make new ones, could reuse deleted one ?
10146 (while (search-forward-regexp verilog-include-file-regexp end-point t)
10148 (goto-char (match-beginning 1))
10149 (setq ov (make-overlay (match-beginning 1) (match-end 1)))
10150 (overlay-put ov 'start-closed 't)
10151 (overlay-put ov 'end-closed 't)
10152 (overlay-put ov 'evaporate 't)
10153 (overlay-put ov 'verilog-include-file 't)
10154 (overlay-put ov 'mouse-face 'highlight)
10155 (overlay-put ov 'local-map verilog-mode-mouse-map)))))))
10158 (defun verilog-colorize-include-files-buffer ()
10159 "Colorize a include file."
10162 (let ((overlays (overlays-in (point-min) (point-max))))
10165 (overlay-get (car overlays) 'detachable)
10166 (overlay-get (car overlays) 'verilog-include-file))
10167 (delete-overlay (car overlays)))
10168 (setq overlays (cdr overlays)))) ; let
10170 (verilog-colorize-include-files (point-min) (point-max) nil))
10172 ;; ffap-at-mouse isn't useful for verilog mode. It uses library paths.
10173 ;; so define this function to do more or less the same as ffap-at-mouse
10174 ;; but first resolve filename...
10175 (defun verilog-load-file-at-mouse (event)
10176 "Load file under button 2 click's EVENT.
10177 Files are checked based on `verilog-library-directories'."
10179 (save-excursion ;; implement a verilog specific ffap-at-mouse
10180 (mouse-set-point event)
10181 (beginning-of-line)
10182 (if (looking-at verilog-include-file-regexp)
10183 (if (and (car (verilog-library-filenames
10184 (match-string 1) (buffer-file-name)))
10185 (file-readable-p (car (verilog-library-filenames
10186 (match-string 1) (buffer-file-name)))))
10187 (find-file (car (verilog-library-filenames
10188 (match-string 1) (buffer-file-name))))
10191 "File '%s' isn't readable, use shift-mouse2 to paste in this field"
10192 (match-string 1))))
10195 ;; ffap isn't useable for verilog mode. It uses library paths.
10196 ;; so define this function to do more or less the same as ffap
10197 ;; but first resolve filename...
10198 (defun verilog-load-file-at-point ()
10199 "Load file under point.
10200 Files are checked based on `verilog-library-directories'."
10202 (save-excursion ;; implement a verilog specific ffap
10203 (beginning-of-line)
10204 (if (looking-at verilog-include-file-regexp)
10206 (car (verilog-library-filenames
10207 (match-string 1) (buffer-file-name)))
10208 (file-readable-p (car (verilog-library-filenames
10209 (match-string 1) (buffer-file-name)))))
10210 (find-file (car (verilog-library-filenames
10211 (match-string 1) (buffer-file-name))))))
10219 (defun verilog-faq ()
10220 "Tell the user their current version, and where to get the FAQ etc."
10222 (with-output-to-temp-buffer "*verilog-mode help*"
10223 (princ (format "You are using verilog-mode %s\n" verilog-mode-version))
10225 (princ "For new releases, see http://www.verilog.com\n")
10227 (princ "For frequently asked questions, see http://www.veripool.com/verilog-mode-faq.html\n")
10229 (princ "To submit a bug, use M-x verilog-submit-bug-report\n")
10232 (autoload 'reporter-submit-bug-report "reporter")
10234 (defun verilog-submit-bug-report ()
10235 "Submit via mail a bug report on verilog-mode.el."
10237 (let ((reporter-prompt-for-summary-p t))
10238 (reporter-submit-bug-report
10240 (concat "verilog-mode v" verilog-mode-version)
10242 verilog-align-ifelse
10243 verilog-auto-endcomments
10245 verilog-auto-indent-on-newline
10246 verilog-auto-inst-vector
10247 verilog-auto-inst-template-numbers
10248 verilog-auto-lineup
10249 verilog-auto-newline
10250 verilog-auto-save-policy
10251 verilog-auto-sense-defines-constant
10252 verilog-auto-sense-include-inputs
10253 verilog-before-auto-hook
10254 verilog-case-indent
10255 verilog-cexp-indent
10258 verilog-highlight-translate-off
10259 verilog-indent-begin-after-if
10260 verilog-indent-declaration-macros
10261 verilog-indent-level
10262 verilog-indent-level-behavioral
10263 verilog-indent-level-declaration
10264 verilog-indent-level-directive
10265 verilog-indent-level-module
10266 verilog-indent-lists
10267 verilog-library-flags
10268 verilog-library-directories
10269 verilog-library-extensions
10270 verilog-library-files
10272 verilog-minimum-comment-distance
10275 verilog-tab-always-indent
10276 verilog-tab-to-comment
10281 I want to report a bug. I've read the `Bugs' section of `Info' on
10282 Emacs, so I know how to make a clear and unambiguous report. To get
10283 to that Info section, I typed
10285 M-x info RET m " invocation-name " RET m bugs RET
10287 Before I go further, I want to say that Verilog mode has changed my life.
10288 I save so much time, my files are colored nicely, my co workers respect
10289 my coding ability... until now. I'd really appreciate anything you
10290 could do to help me out with this minor deficiency in the product.
10292 If you have bugs with the AUTO functions, please CC the AUTOAUTHOR Wilson
10293 Snyder (wsnyder@wsnyder.org) and/or see http://www.veripool.com.
10294 You may also want to look at the Verilog-Mode FAQ, see
10295 http://www.veripool.com/verilog-mode-faq.html.
10297 To reproduce the bug, start a fresh Emacs via " invocation-name "
10298 -no-init-file -no-site-file'. In a new buffer, in verilog mode, type
10299 the code included below.
10301 Given those lines, I expected [[Fill in here]] to happen;
10302 but instead, [[Fill in here]] happens!.
10304 == The code: =="))))
10306 (provide 'verilog-mode)
10308 ;; Local Variables:
10309 ;; checkdoc-permit-comma-termination-flag:t
10310 ;; checkdoc-force-docstrings-flag:nil
10313 ;; arch-tag: 87923725-57b3-41b5-9494-be21118c6a6f
10314 ;;; verilog-mode.el ends here