1 ;;; verilog-mode.el --- major mode for editing verilog source in Emacs
3 ;; Copyright (C) 1996-2014 Free Software Foundation, Inc.
5 ;; Author: Michael McNamara <mac@verilog.com>
6 ;; Wilson Snyder <wsnyder@wsnyder.org>
7 ;; http://www.verilog.com
8 ;; http://www.veripool.org
10 ;; Keywords: languages
12 ;; Yoni Rabkin <yoni@rabkins.net> contacted the maintainer of this
13 ;; file on 19/3/2008, and the maintainer agreed that when a bug is
14 ;; filed in the Emacs bug reporting system against this file, a copy
15 ;; of the bug report be sent to the maintainer's email address.
17 ;; This code supports Emacs 21.1 and later
18 ;; And XEmacs 21.1 and later
19 ;; Please do not make changes that break Emacs 21. Thanks!
23 ;; This file is part of GNU Emacs.
25 ;; GNU Emacs is free software: you can redistribute it and/or modify
26 ;; it under the terms of the GNU General Public License as published by
27 ;; the Free Software Foundation, either version 3 of the License, or
28 ;; (at your option) any later version.
30 ;; GNU Emacs is distributed in the hope that it will be useful,
31 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
32 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 ;; GNU General Public License for more details.
35 ;; You should have received a copy of the GNU General Public License
36 ;; along with GNU Emacs. If not, see <http://www.gnu.org/licenses/>.
43 ;; A major mode for editing Verilog and SystemVerilog HDL source code (IEEE
44 ;; 1364-2005 and IEEE 1800-2012 standards). When you have entered Verilog
45 ;; mode, you may get more info by pressing C-h m. You may also get online
46 ;; help describing various functions by: C-h f <Name of function you want
49 ;; KNOWN BUGS / BUG REPORTS
50 ;; =======================
52 ;; SystemVerilog is a rapidly evolving language, and hence this mode is
53 ;; under continuous development. Please report any issues to the issue
56 ;; http://www.veripool.org/verilog-mode
58 ;; Please use verilog-submit-bug-report to submit a report; type C-c
59 ;; C-b to invoke this and as a result we will have a much easier time
60 ;; of reproducing the bug you find, and hence fixing it.
62 ;; INSTALLING THE MODE
63 ;; ===================
65 ;; An older version of this mode may be already installed as a part of
66 ;; your environment, and one method of updating would be to update
67 ;; your Emacs environment. Sometimes this is difficult for local
68 ;; political/control reasons, and hence you can always install a
69 ;; private copy (or even a shared copy) which overrides the system
72 ;; You can get step by step help in installing this file by going to
73 ;; <http://www.verilog.com/emacs_install.html>
75 ;; The short list of installation instructions are: To set up
76 ;; automatic Verilog mode, put this file in your load path, and put
77 ;; the following in code (please un comment it first!) in your
78 ;; .emacs, or in your site's site-load.el
80 ; (autoload 'verilog-mode "verilog-mode" "Verilog mode" t )
81 ; (add-to-list 'auto-mode-alist '("\\.[ds]?vh?\\'" . verilog-mode))
83 ;; Be sure to examine at the help for verilog-auto, and the other
84 ;; verilog-auto-* functions for some major coding time savers.
86 ;; If you want to customize Verilog mode to fit your needs better,
87 ;; you may add the below lines (the values of the variables presented
88 ;; here are the defaults). Note also that if you use an Emacs that
89 ;; supports custom, it's probably better to use the custom menu to
90 ;; edit these. If working as a member of a large team these settings
91 ;; should be common across all users (in a site-start file), or set
92 ;; in Local Variables in every file. Otherwise, different people's
93 ;; AUTO expansion may result different whitespace changes.
95 ; ;; Enable syntax highlighting of **all** languages
96 ; (global-font-lock-mode t)
98 ; ;; User customization for Verilog mode
99 ; (setq verilog-indent-level 3
100 ; verilog-indent-level-module 3
101 ; verilog-indent-level-declaration 3
102 ; verilog-indent-level-behavioral 3
103 ; verilog-indent-level-directive 1
104 ; verilog-case-indent 2
105 ; verilog-auto-newline t
106 ; verilog-auto-indent-on-newline t
107 ; verilog-tab-always-indent t
108 ; verilog-auto-endcomments t
109 ; verilog-minimum-comment-distance 40
110 ; verilog-indent-begin-after-if t
111 ; verilog-auto-lineup 'declarations
112 ; verilog-highlight-p1800-keywords nil
113 ; verilog-linter "my_lint_shell_command"
120 ;; See commit history at http://www.veripool.org/verilog-mode.html
121 ;; (This section is required to appease checkdoc.)
125 ;; This variable will always hold the version number of the mode
126 (defconst verilog-mode-version "2014-03-15-702457d-vpo"
127 "Version of this Verilog mode.")
128 (defconst verilog-mode-release-emacs t
129 "If non-nil, this version of Verilog mode was released with Emacs itself.")
131 (defun verilog-version ()
132 "Inform caller of the version of this file."
134 (message "Using verilog-mode version %s" verilog-mode-version))
136 ;; Insure we have certain packages, and deal with it if we don't
137 ;; Be sure to note which Emacs flavor and version added each feature.
139 ;; Provide stuff if we are XEmacs
140 (when (featurep 'xemacs)
145 (require 'regexp-opt)
147 ;; Bug in 19.28 through 19.30 skeleton.el, not provided.
154 (defmacro when (cond &rest body)
155 (list 'if cond (cons 'progn body))))
158 (if (fboundp 'unless)
160 (defmacro unless (cond &rest body)
161 (cons 'if (cons cond (cons nil body)))))
164 (if (fboundp 'store-match-data)
166 (defmacro store-match-data (&rest _args) nil))
169 (if (fboundp 'char-before)
171 (defmacro char-before (&rest _body)
172 (char-after (1- (point)))))
177 (defsubst point-at-bol (&optional N)
178 (save-excursion (beginning-of-line N) (point))))
183 (defsubst point-at-eol (&optional N)
184 (save-excursion (end-of-line N) (point))))
190 (if (fboundp 'match-string-no-properties)
192 (defsubst match-string-no-properties (num &optional string)
193 "Return string of text matched by last search, without text properties.
194 NUM specifies which parenthesized expression in the last regexp.
195 Value is nil if NUMth pair didn't match, or there were less than NUM pairs.
196 Zero means the entire text matched by the whole regexp or whole string.
197 STRING should be given if the last search was by `string-match' on STRING."
198 (if (match-beginning num)
202 (match-beginning num) (match-end num))))
203 (set-text-properties 0 (length result) nil result)
205 (buffer-substring-no-properties (match-beginning num)
210 (if (and (featurep 'custom) (fboundp 'custom-declare-variable))
211 nil ;; We've got what we needed
212 ;; We have the old custom-library, hack around it!
213 (defmacro defgroup (&rest _args) nil)
214 (defmacro customize (&rest _args)
216 "Sorry, Customize is not available with this version of Emacs"))
217 (defmacro defcustom (var value doc &rest _args)
218 `(defvar ,var ,value ,doc))
220 (if (fboundp 'defface)
222 (defmacro defface (var values doc &rest _args)
226 (if (and (featurep 'custom) (fboundp 'customize-group))
227 nil ;; We've got what we needed
228 ;; We have an intermediate custom-library, hack around it!
229 (defmacro customize-group (var &rest _args)
233 (unless (boundp 'inhibit-point-motion-hooks)
234 (defvar inhibit-point-motion-hooks nil))
235 (unless (boundp 'deactivate-mark)
236 (defvar deactivate-mark nil))
239 ;; OK, do this stuff if we are NOT XEmacs:
240 (unless (featurep 'xemacs)
241 (unless (fboundp 'region-active-p)
242 (defmacro region-active-p ()
243 `(and transient-mark-mode mark-active))))
246 ;; Provide a regular expression optimization routine, using regexp-opt
247 ;; if provided by the user's elisp libraries
249 ;; The below were disabled when GNU Emacs 22 was released;
250 ;; perhaps some still need to be there to support Emacs 21.
251 (if (featurep 'xemacs)
252 (if (fboundp 'regexp-opt)
253 ;; regexp-opt is defined, does it take 3 or 2 arguments?
254 (if (fboundp 'function-max-args)
255 (let ((args (function-max-args `regexp-opt)))
257 ((eq args 3) ;; It takes 3
258 (condition-case nil ; Hide this defun from emacses
259 ;with just a two input regexp
260 (defun verilog-regexp-opt (a b)
261 "Deal with differing number of required arguments for `regexp-opt'.
262 Call `regexp-opt' on A and B."
266 ((eq args 2) ;; It takes 2
267 (defun verilog-regexp-opt (a b)
268 "Call `regexp-opt' on A and B."
272 ;; We can't tell; assume it takes 2
273 (defun verilog-regexp-opt (a b)
274 "Call `regexp-opt' on A and B."
277 ;; There is no regexp-opt, provide our own
278 (defun verilog-regexp-opt (strings &optional paren _shy)
279 (let ((open (if paren "\\(" "")) (close (if paren "\\)" "")))
280 (concat open (mapconcat 'regexp-quote strings "\\|") close)))
283 (defalias 'verilog-regexp-opt 'regexp-opt)))
286 ;; Both xemacs and emacs
288 (require 'diff) ;; diff-command and diff-switches
291 (require 'compile) ;; compilation-error-regexp-alist-alist
294 (unless (fboundp 'buffer-chars-modified-tick) ;; Emacs 22 added
295 (defmacro buffer-chars-modified-tick () (buffer-modified-tick)))
297 ;; Added in Emacs 24.1
299 (unless (fboundp 'prog-mode)
300 (define-derived-mode prog-mode fundamental-mode "Prog"))
304 (defun verilog-regexp-words (a)
305 "Call 'regexp-opt' with word delimiters for the words A."
306 (concat "\\<" (verilog-regexp-opt a t) "\\>")))
307 (defun verilog-regexp-words (a)
308 "Call 'regexp-opt' with word delimiters for the words A."
309 ;; The FAQ references this function, so user LISP sometimes calls it
310 (concat "\\<" (verilog-regexp-opt a t) "\\>"))
312 (defun verilog-easy-menu-filter (menu)
313 "Filter `easy-menu-define' MENU to support new features."
314 (cond ((not (featurep 'xemacs))
315 menu) ;; GNU Emacs - passthru
316 ;; XEmacs doesn't support :help. Strip it.
317 ;; Recursively filter the a submenu
319 (mapcar 'verilog-easy-menu-filter menu))
320 ;; Look for [:help "blah"] and remove
322 (let ((i 0) (out []))
323 (while (< i (length menu))
324 (if (equal `:help (aref menu i))
326 (setq out (vconcat out (vector (aref menu i)))
329 (t menu))) ;; Default - ok
330 ;;(verilog-easy-menu-filter
331 ;; `("Verilog" ("MA" ["SAA" nil :help "Help SAA"] ["SAB" nil :help "Help SAA"])
332 ;; "----" ["MB" nil :help "Help MB"]))
334 (defun verilog-define-abbrev (table name expansion &optional hook)
335 "Filter `define-abbrev' TABLE NAME EXPANSION and call HOOK.
336 Provides SYSTEM-FLAG in newer Emacs."
338 (define-abbrev table name expansion hook 0 t)
340 (define-abbrev table name expansion hook))))
342 (defun verilog-customize ()
343 "Customize variables and other settings used by Verilog-Mode."
345 (customize-group 'verilog-mode))
347 (defun verilog-font-customize ()
348 "Customize fonts used by Verilog-Mode."
350 (if (fboundp 'customize-apropos)
351 (customize-apropos "font-lock-*" 'faces)))
353 (defun verilog-booleanp (value)
354 "Return t if VALUE is boolean.
355 This implements GNU Emacs 22.1's `booleanp' function in earlier Emacs.
356 This function may be removed when Emacs 21 is no longer supported."
357 (or (equal value t) (equal value nil)))
359 (defun verilog-insert-last-command-event ()
360 "Insert the `last-command-event'."
361 (insert (if (featurep 'xemacs)
362 ;; XEmacs 21.5 doesn't like last-command-event
364 ;; And GNU Emacs 22 has obsoleted last-command-char
365 last-command-event)))
367 (defvar verilog-no-change-functions nil
368 "True if `after-change-functions' is disabled.
369 Use of `syntax-ppss' may break, as ppss's cache may get corrupted.")
371 (defvar verilog-in-hooks nil
372 "True when within a `verilog-run-hooks' block.")
374 (defmacro verilog-run-hooks (&rest hooks)
375 "Run each hook in HOOKS using `run-hooks'.
376 Set `verilog-in-hooks' during this time, to assist AUTO caches."
377 `(let ((verilog-in-hooks t))
378 (run-hooks ,@hooks)))
380 (defun verilog-syntax-ppss (&optional pos)
381 (when verilog-no-change-functions
383 (verilog-scan-cache-flush)
384 ;; else don't let the AUTO code itself get away with flushing the cache,
385 ;; as that'll make things very slow
387 (error "%s: Internal problem; use of syntax-ppss when cache may be corrupt"
388 (verilog-point-text))))
389 (if (fboundp 'syntax-ppss)
391 (parse-partial-sexp (point-min) (or pos (point)))))
393 (defgroup verilog-mode nil
394 "Major mode for Verilog source code."
398 ; (defgroup verilog-mode-fonts nil
399 ; "Facilitates easy customization fonts used in Verilog source text"
400 ; :link '(customize-apropos "font-lock-*" 'faces)
401 ; :group 'verilog-mode)
403 (defgroup verilog-mode-indent nil
404 "Customize indentation and highlighting of Verilog source text."
405 :group 'verilog-mode)
407 (defgroup verilog-mode-actions nil
408 "Customize actions on Verilog source text."
409 :group 'verilog-mode)
411 (defgroup verilog-mode-auto nil
412 "Customize AUTO actions when expanding Verilog source text."
413 :group 'verilog-mode)
415 (defvar verilog-debug nil
416 "Non-nil means enable debug messages for `verilog-mode' internals.")
418 (defvar verilog-warn-fatal nil
419 "Non-nil means `verilog-warn-error' warnings are fatal `error's.")
421 (defcustom verilog-linter
422 "echo 'No verilog-linter set, see \"M-x describe-variable verilog-linter\"'"
423 "Unix program and arguments to call to run a lint checker on Verilog source.
424 Depending on the `verilog-set-compile-command', this may be invoked when
425 you type \\[compile]. When the compile completes, \\[next-error] will take
426 you to the next lint error."
428 :group 'verilog-mode-actions)
429 ;; We don't mark it safe, as it's used as a shell command
431 (defcustom verilog-coverage
432 "echo 'No verilog-coverage set, see \"M-x describe-variable verilog-coverage\"'"
433 "Program and arguments to use to annotate for coverage Verilog source.
434 Depending on the `verilog-set-compile-command', this may be invoked when
435 you type \\[compile]. When the compile completes, \\[next-error] will take
436 you to the next lint error."
438 :group 'verilog-mode-actions)
439 ;; We don't mark it safe, as it's used as a shell command
441 (defcustom verilog-simulator
442 "echo 'No verilog-simulator set, see \"M-x describe-variable verilog-simulator\"'"
443 "Program and arguments to use to interpret Verilog source.
444 Depending on the `verilog-set-compile-command', this may be invoked when
445 you type \\[compile]. When the compile completes, \\[next-error] will take
446 you to the next lint error."
448 :group 'verilog-mode-actions)
449 ;; We don't mark it safe, as it's used as a shell command
451 (defcustom verilog-compiler
452 "echo 'No verilog-compiler set, see \"M-x describe-variable verilog-compiler\"'"
453 "Program and arguments to use to compile Verilog source.
454 Depending on the `verilog-set-compile-command', this may be invoked when
455 you type \\[compile]. When the compile completes, \\[next-error] will take
456 you to the next lint error."
458 :group 'verilog-mode-actions)
459 ;; We don't mark it safe, as it's used as a shell command
461 (defcustom verilog-preprocessor
462 ;; Very few tools give preprocessed output, so we'll default to Verilog-Perl
463 "vppreproc __FLAGS__ __FILE__"
464 "Program and arguments to use to preprocess Verilog source.
465 This is invoked with `verilog-preprocess', and depending on the
466 `verilog-set-compile-command', may also be invoked when you type
467 \\[compile]. When the compile completes, \\[next-error] will
468 take you to the next lint error."
470 :group 'verilog-mode-actions)
471 ;; We don't mark it safe, as it's used as a shell command
473 (defvar verilog-preprocess-history nil
474 "History for `verilog-preprocess'.")
476 (defvar verilog-tool 'verilog-linter
477 "Which tool to use for building compiler-command.
478 Either nil, `verilog-linter, `verilog-compiler,
479 `verilog-coverage, `verilog-preprocessor, or `verilog-simulator.
480 Alternatively use the \"Choose Compilation Action\" menu. See
481 `verilog-set-compile-command' for more information.")
483 (defcustom verilog-highlight-translate-off nil
484 "Non-nil means background-highlight code excluded from translation.
485 That is, all code between \"// synopsys translate_off\" and
486 \"// synopsys translate_on\" is highlighted using a different background color
487 \(face `verilog-font-lock-translate-off-face').
489 Note: This will slow down on-the-fly fontification (and thus editing).
491 Note: Activate the new setting in a Verilog buffer by re-fontifying it (menu
492 entry \"Fontify Buffer\"). XEmacs: turn off and on font locking."
494 :group 'verilog-mode-indent)
495 ;; Note we don't use :safe, as that would break on Emacsen before 22.0.
496 (put 'verilog-highlight-translate-off 'safe-local-variable 'verilog-booleanp)
498 (defcustom verilog-auto-lineup 'declarations
499 "Type of statements to lineup across multiple lines.
500 If 'all' is selected, then all line ups described below are done.
502 If 'declarations', then just declarations are lined up with any
503 preceding declarations, taking into account widths and the like,
504 so or example the code:
511 If 'assignment', then assignments are lined up with any preceding
512 assignments, so for example the code
513 a_long_variable <= b + c;
516 a_long_variable <= b + c;
519 In order to speed up editing, large blocks of statements are lined up
520 only when a \\[verilog-pretty-expr] is typed; and large blocks of declarations
521 are lineup only when \\[verilog-pretty-declarations] is typed."
523 :type '(radio (const :tag "Line up Assignments and Declarations" all)
524 (const :tag "Line up Assignment statements" assignments )
525 (const :tag "Line up Declarations" declarations)
526 (function :tag "Other"))
527 :group 'verilog-mode-indent )
528 (put 'verilog-auto-lineup 'safe-local-variable
529 '(lambda (x) (memq x '(nil all assignments declarations))))
531 (defcustom verilog-indent-level 3
532 "Indentation of Verilog statements with respect to containing block."
533 :group 'verilog-mode-indent
535 (put 'verilog-indent-level 'safe-local-variable 'integerp)
537 (defcustom verilog-indent-level-module 3
538 "Indentation of Module level Verilog statements (eg always, initial).
539 Set to 0 to get initial and always statements lined up on the left side of
541 :group 'verilog-mode-indent
543 (put 'verilog-indent-level-module 'safe-local-variable 'integerp)
545 (defcustom verilog-indent-level-declaration 3
546 "Indentation of declarations with respect to containing block.
547 Set to 0 to get them list right under containing block."
548 :group 'verilog-mode-indent
550 (put 'verilog-indent-level-declaration 'safe-local-variable 'integerp)
552 (defcustom verilog-indent-declaration-macros nil
553 "How to treat macro expansions in a declaration.
558 If non nil, treat as:
562 :group 'verilog-mode-indent
564 (put 'verilog-indent-declaration-macros 'safe-local-variable 'verilog-booleanp)
566 (defcustom verilog-indent-lists t
567 "How to treat indenting items in a list.
568 If t (the default), indent as:
569 always @( posedge a or
573 always @( posedge a or
575 :group 'verilog-mode-indent
577 (put 'verilog-indent-lists 'safe-local-variable 'verilog-booleanp)
579 (defcustom verilog-indent-level-behavioral 3
580 "Absolute indentation of first begin in a task or function block.
581 Set to 0 to get such code to start at the left side of the screen."
582 :group 'verilog-mode-indent
584 (put 'verilog-indent-level-behavioral 'safe-local-variable 'integerp)
586 (defcustom verilog-indent-level-directive 1
587 "Indentation to add to each level of `ifdef declarations.
588 Set to 0 to have all directives start at the left side of the screen."
589 :group 'verilog-mode-indent
591 (put 'verilog-indent-level-directive 'safe-local-variable 'integerp)
593 (defcustom verilog-cexp-indent 2
594 "Indentation of Verilog statements split across lines."
595 :group 'verilog-mode-indent
597 (put 'verilog-cexp-indent 'safe-local-variable 'integerp)
599 (defcustom verilog-case-indent 2
600 "Indentation for case statements."
601 :group 'verilog-mode-indent
603 (put 'verilog-case-indent 'safe-local-variable 'integerp)
605 (defcustom verilog-auto-newline t
606 "Non-nil means automatically newline after semicolons."
607 :group 'verilog-mode-indent
609 (put 'verilog-auto-newline 'safe-local-variable 'verilog-booleanp)
611 (defcustom verilog-auto-indent-on-newline t
612 "Non-nil means automatically indent line after newline."
613 :group 'verilog-mode-indent
615 (put 'verilog-auto-indent-on-newline 'safe-local-variable 'verilog-booleanp)
617 (defcustom verilog-tab-always-indent t
618 "Non-nil means TAB should always re-indent the current line.
619 A nil value means TAB will only reindent when at the beginning of the line."
620 :group 'verilog-mode-indent
622 (put 'verilog-tab-always-indent 'safe-local-variable 'verilog-booleanp)
624 (defcustom verilog-tab-to-comment nil
625 "Non-nil means TAB moves to the right hand column in preparation for a comment."
626 :group 'verilog-mode-actions
628 (put 'verilog-tab-to-comment 'safe-local-variable 'verilog-booleanp)
630 (defcustom verilog-indent-begin-after-if t
631 "Non-nil means indent begin statements following if, else, while, etc.
632 Otherwise, line them up."
633 :group 'verilog-mode-indent
635 (put 'verilog-indent-begin-after-if 'safe-local-variable 'verilog-booleanp)
637 (defcustom verilog-align-ifelse nil
638 "Non-nil means align `else' under matching `if'.
639 Otherwise else is lined up with first character on line holding matching if."
640 :group 'verilog-mode-indent
642 (put 'verilog-align-ifelse 'safe-local-variable 'verilog-booleanp)
644 (defcustom verilog-minimum-comment-distance 10
645 "Minimum distance (in lines) between begin and end required before a comment.
646 Setting this variable to zero results in every end acquiring a comment; the
647 default avoids too many redundant comments in tight quarters."
648 :group 'verilog-mode-indent
650 (put 'verilog-minimum-comment-distance 'safe-local-variable 'integerp)
652 (defcustom verilog-highlight-p1800-keywords nil
653 "Non-nil means highlight words newly reserved by IEEE-1800.
654 These will appear in `verilog-font-lock-p1800-face' in order to gently
655 suggest changing where these words are used as variables to something else.
656 A nil value means highlight these words as appropriate for the SystemVerilog
657 IEEE-1800 standard. Note that changing this will require restarting Emacs
658 to see the effect as font color choices are cached by Emacs."
659 :group 'verilog-mode-indent
661 (put 'verilog-highlight-p1800-keywords 'safe-local-variable 'verilog-booleanp)
663 (defcustom verilog-highlight-grouping-keywords nil
664 "Non-nil means highlight grouping keywords more dramatically.
665 If false, these words are in the `font-lock-type-face'; if True then they are in
666 `verilog-font-lock-ams-face'. Some find that special highlighting on these
667 grouping constructs allow the structure of the code to be understood at a glance."
668 :group 'verilog-mode-indent
670 (put 'verilog-highlight-grouping-keywords 'safe-local-variable 'verilog-booleanp)
672 (defcustom verilog-highlight-modules nil
673 "Non-nil means highlight module statements for `verilog-load-file-at-point'.
674 When true, mousing over module names will allow jumping to the
675 module definition. If false, this is not supported. Setting
676 this is experimental, and may lead to bad performance."
677 :group 'verilog-mode-indent
679 (put 'verilog-highlight-modules 'safe-local-variable 'verilog-booleanp)
681 (defcustom verilog-highlight-includes t
682 "Non-nil means highlight module statements for `verilog-load-file-at-point'.
683 When true, mousing over include file names will allow jumping to the
684 file referenced. If false, this is not supported."
685 :group 'verilog-mode-indent
687 (put 'verilog-highlight-includes 'safe-local-variable 'verilog-booleanp)
689 (defcustom verilog-auto-declare-nettype nil
690 "Non-nil specifies the data type to use with `verilog-auto-input' etc.
691 Set this to \"wire\" if the Verilog code uses \"`default_nettype
692 none\". Note using `default_nettype none isn't recommended practice; this
693 mode is experimental."
694 :version "24.1" ;; rev670
695 :group 'verilog-mode-actions
697 (put 'verilog-auto-declare-nettype 'safe-local-variable `stringp)
699 (defcustom verilog-auto-wire-type nil
700 "Non-nil specifies the data type to use with `verilog-auto-wire' etc.
701 Set this to \"logic\" for SystemVerilog code, or use `verilog-auto-logic'."
702 :version "24.1" ;; rev673
703 :group 'verilog-mode-actions
705 (put 'verilog-auto-wire-type 'safe-local-variable `stringp)
707 (defcustom verilog-auto-endcomments t
708 "Non-nil means insert a comment /* ... */ after 'end's.
709 The name of the function or case will be set between the braces."
710 :group 'verilog-mode-actions
712 (put 'verilog-auto-endcomments 'safe-local-variable 'verilog-booleanp)
714 (defcustom verilog-auto-delete-trailing-whitespace nil
715 "Non-nil means to `delete-trailing-whitespace' in `verilog-auto'."
716 :version "24.1" ;; rev703
717 :group 'verilog-mode-actions
719 (put 'verilog-auto-delete-trailing-whitespace 'safe-local-variable 'verilog-booleanp)
721 (defcustom verilog-auto-ignore-concat nil
722 "Non-nil means ignore signals in {...} concatenations for AUTOWIRE etc.
723 This will exclude signals referenced as pin connections in {...}
724 from AUTOWIRE, AUTOOUTPUT and friends. This flag should be set
725 for backward compatibility only and not set in new designs; it
726 may be removed in future versions."
727 :group 'verilog-mode-actions
729 (put 'verilog-auto-ignore-concat 'safe-local-variable 'verilog-booleanp)
731 (defcustom verilog-auto-read-includes nil
732 "Non-nil means to automatically read includes before AUTOs.
733 This will do a `verilog-read-defines' and `verilog-read-includes' before
734 each AUTO expansion. This makes it easier to embed defines and includes,
735 but can result in very slow reading times if there are many or large
737 :group 'verilog-mode-actions
739 (put 'verilog-auto-read-includes 'safe-local-variable 'verilog-booleanp)
741 (defcustom verilog-auto-save-policy nil
742 "Non-nil indicates action to take when saving a Verilog buffer with AUTOs.
743 A value of `force' will always do a \\[verilog-auto] automatically if
744 needed on every save. A value of `detect' will do \\[verilog-auto]
745 automatically when it thinks necessary. A value of `ask' will query the
746 user when it thinks updating is needed.
748 You should not rely on the 'ask or 'detect policies, they are safeguards
749 only. They do not detect when AUTOINSTs need to be updated because a
750 sub-module's port list has changed."
751 :group 'verilog-mode-actions
752 :type '(choice (const nil) (const ask) (const detect) (const force)))
754 (defcustom verilog-auto-star-expand t
755 "Non-nil means to expand SystemVerilog .* instance ports.
756 They will be expanded in the same way as if there was an AUTOINST in the
757 instantiation. See also `verilog-auto-star' and `verilog-auto-star-save'."
758 :group 'verilog-mode-actions
760 (put 'verilog-auto-star-expand 'safe-local-variable 'verilog-booleanp)
762 (defcustom verilog-auto-star-save nil
763 "Non-nil means save to disk SystemVerilog .* instance expansions.
764 A nil value indicates direct connections will be removed before saving.
765 Only meaningful to those created due to `verilog-auto-star-expand' being set.
767 Instead of setting this, you may want to use /*AUTOINST*/, which will
769 :group 'verilog-mode-actions
771 (put 'verilog-auto-star-save 'safe-local-variable 'verilog-booleanp)
773 (defvar verilog-auto-update-tick nil
774 "Modification tick at which autos were last performed.")
776 (defvar verilog-auto-last-file-locals nil
777 "Text from file-local-variables during last evaluation.")
779 (defvar verilog-diff-function 'verilog-diff-report
780 "Function to run when `verilog-diff-auto' detects differences.
781 Function takes three arguments, the original buffer, the
782 difference buffer, and the point in original buffer with the
787 (defvar verilog-error-regexp-added nil)
789 (defvar verilog-error-regexp-emacs-alist
792 "\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 3)
794 "([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 1 3)
796 ".*\\*[WE],[0-9A-Z]+\\(\[[0-9A-Z_,]+\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)" 2 3)
798 "[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 2)
800 "\\(WARNING\\|ERROR\\|INFO\\)[^:]*: \\([^,]+\\),\\s-+\\(line \\)?\\([0-9]+\\):" 2 4 )
803 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
804 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 2 5)
806 "\\(Error\\|Warning\\).*in file (\\([^ \t]+\\) at line *\\([0-9]+\\))" 2 3)
808 "\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 3)
810 "Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 2)
812 "\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 3)
814 "syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 2)
816 "%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4)
818 "^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 1 2)
820 "List of regexps for Verilog compilers.
821 See `compilation-error-regexp-alist' for the formatting. For Emacs 22+.")
823 (defvar verilog-error-regexp-xemacs-alist
824 ;; Emacs form is '((v-tool "re" 1 2) ...)
825 ;; XEmacs form is '(verilog ("re" 1 2) ...)
826 ;; So we can just map from Emacs to XEmacs
827 (cons 'verilog (mapcar 'cdr verilog-error-regexp-emacs-alist))
828 "List of regexps for Verilog compilers.
829 See `compilation-error-regexp-alist-alist' for the formatting. For XEmacs.")
831 (defvar verilog-error-font-lock-keywords
834 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t)
835 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t)
837 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 1 bold t)
838 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 3 bold t)
839 ;; verilog-IES (nc-verilog)
840 (".*\\*[WE],[0-9A-Z]+\\(\[[0-9A-Z_,]+\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)|" 2 bold t)
841 (".*\\*[WE],[0-9A-Z]+\\(\[[0-9A-Z_,]+\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)|" 3 bold t)
842 ;; verilog-surefire-1
843 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 bold t)
844 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 2 bold t)
845 ;; verilog-surefire-2
846 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 2 bold t)
847 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 3 bold t)
850 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
851 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t)
853 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
854 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t)
856 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 bold t)
857 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 3 bold t)
859 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t)
860 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t)
862 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t)
863 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 3 bold t)
865 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 bold t)
866 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t)
868 (".*%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 bold t)
869 (".*%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 4 bold t)
871 ("^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 1 bold t)
872 ("^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 2 bold t)
874 "Keywords to also highlight in Verilog *compilation* buffers.
875 Only used in XEmacs; GNU Emacs uses `verilog-error-regexp-emacs-alist'.")
877 (defcustom verilog-library-flags '("")
878 "List of standard Verilog arguments to use for /*AUTOINST*/.
879 These arguments are used to find files for `verilog-auto', and match
880 the flags accepted by a standard Verilog-XL simulator.
882 -f filename Reads more `verilog-library-flags' from the filename.
883 +incdir+dir Adds the directory to `verilog-library-directories'.
884 -Idir Adds the directory to `verilog-library-directories'.
885 -y dir Adds the directory to `verilog-library-directories'.
886 +libext+.v Adds the extensions to `verilog-library-extensions'.
887 -v filename Adds the filename to `verilog-library-files'.
889 filename Adds the filename to `verilog-library-files'.
890 This is not recommended, -v is a better choice.
892 You might want these defined in each file; put at the *END* of your file
896 // verilog-library-flags:(\"-y dir -y otherdir\")
899 Verilog-mode attempts to detect changes to this local variable, but they
900 are only insured to be correct when the file is first visited. Thus if you
901 have problems, use \\[find-alternate-file] RET to have these take effect.
903 See also the variables mentioned above."
904 :group 'verilog-mode-auto
905 :type '(repeat string))
906 (put 'verilog-library-flags 'safe-local-variable 'listp)
908 (defcustom verilog-library-directories '(".")
909 "List of directories when looking for files for /*AUTOINST*/.
910 The directory may be relative to the current file, or absolute.
911 Environment variables are also expanded in the directory names.
912 Having at least the current directory is a good idea.
914 You might want these defined in each file; put at the *END* of your file
918 // verilog-library-directories:(\".\" \"subdir\" \"subdir2\")
921 Verilog-mode attempts to detect changes to this local variable, but they
922 are only insured to be correct when the file is first visited. Thus if you
923 have problems, use \\[find-alternate-file] RET to have these take effect.
925 See also `verilog-library-flags', `verilog-library-files'
926 and `verilog-library-extensions'."
927 :group 'verilog-mode-auto
928 :type '(repeat file))
929 (put 'verilog-library-directories 'safe-local-variable 'listp)
931 (defcustom verilog-library-files '()
932 "List of files to search for modules.
933 AUTOINST will use this when it needs to resolve a module name.
934 This is a complete path, usually to a technology file with many standard
937 You might want these defined in each file; put at the *END* of your file
941 // verilog-library-files:(\"/some/path/technology.v\" \"/some/path/tech2.v\")
944 Verilog-mode attempts to detect changes to this local variable, but they
945 are only insured to be correct when the file is first visited. Thus if you
946 have problems, use \\[find-alternate-file] RET to have these take effect.
948 See also `verilog-library-flags', `verilog-library-directories'."
949 :group 'verilog-mode-auto
950 :type '(repeat directory))
951 (put 'verilog-library-files 'safe-local-variable 'listp)
953 (defcustom verilog-library-extensions '(".v" ".sv")
954 "List of extensions to use when looking for files for /*AUTOINST*/.
955 See also `verilog-library-flags', `verilog-library-directories'."
956 :type '(repeat string)
957 :group 'verilog-mode-auto)
958 (put 'verilog-library-extensions 'safe-local-variable 'listp)
960 (defcustom verilog-active-low-regexp nil
961 "If true, treat signals matching this regexp as active low.
962 This is used for AUTORESET and AUTOTIEOFF. For proper behavior,
963 you will probably also need `verilog-auto-reset-widths' set."
964 :group 'verilog-mode-auto
965 :type '(choice (const nil) regexp))
966 (put 'verilog-active-low-regexp 'safe-local-variable 'stringp)
968 (defcustom verilog-auto-sense-include-inputs nil
969 "Non-nil means AUTOSENSE should include all inputs.
970 If nil, only inputs that are NOT output signals in the same block are
972 :group 'verilog-mode-auto
974 (put 'verilog-auto-sense-include-inputs 'safe-local-variable 'verilog-booleanp)
976 (defcustom verilog-auto-sense-defines-constant nil
977 "Non-nil means AUTOSENSE should assume all defines represent constants.
978 When true, the defines will not be included in sensitivity lists. To
979 maintain compatibility with other sites, this should be set at the bottom
980 of each Verilog file that requires it, rather than being set globally."
981 :group 'verilog-mode-auto
983 (put 'verilog-auto-sense-defines-constant 'safe-local-variable 'verilog-booleanp)
985 (defcustom verilog-auto-reset-blocking-in-non t
986 "Non-nil means AUTORESET will reset blocking statements.
987 When true, AUTORESET will reset in blocking statements those
988 signals which were assigned with blocking assignments (=) even in
989 a block with non-blocking assignments (<=).
991 If nil, all blocking assigned signals are ignored when any
992 non-blocking assignment is in the AUTORESET block. This allows
993 blocking assignments to be used for temporary values and not have
994 those temporaries reset. See example in `verilog-auto-reset'."
995 :version "24.1" ;; rev718
997 :group 'verilog-mode-auto)
998 (put 'verilog-auto-reset-blocking-in-non 'safe-local-variable 'verilog-booleanp)
1000 (defcustom verilog-auto-reset-widths t
1001 "True means AUTORESET should determine the width of signals.
1002 This is then used to set the width of the zero (32'h0 for example). This
1003 is required by some lint tools that aren't smart enough to ignore widths of
1004 the constant zero. This may result in ugly code when parameters determine
1005 the MSB or LSB of a signal inside an AUTORESET.
1007 If nil, AUTORESET uses \"0\" as the constant.
1009 If 'unbased', AUTORESET used the unbased unsized literal \"'0\"
1010 as the constant. This setting is strongly recommended for
1011 SystemVerilog designs."
1013 :group 'verilog-mode-auto)
1014 (put 'verilog-auto-reset-widths 'safe-local-variable
1015 '(lambda (x) (memq x '(nil t unbased))))
1017 (defcustom verilog-assignment-delay ""
1018 "Text used for delays in delayed assignments. Add a trailing space if set."
1019 :group 'verilog-mode-auto
1021 (put 'verilog-assignment-delay 'safe-local-variable 'stringp)
1023 (defcustom verilog-auto-arg-sort nil
1024 "Non-nil means AUTOARG signal names will be sorted, not in declaration order.
1025 Declaration order is advantageous with order based instantiations
1026 and is the default for backward compatibility. Sorted order
1027 reduces changes when declarations are moved around in a file, and
1028 it's bad practice to rely on order based instantiations anyhow.
1030 See also `verilog-auto-inst-sort'."
1031 :group 'verilog-mode-auto
1033 (put 'verilog-auto-arg-sort 'safe-local-variable 'verilog-booleanp)
1035 (defcustom verilog-auto-inst-dot-name nil
1036 "Non-nil means when creating ports with AUTOINST, use .name syntax.
1037 This will use \".port\" instead of \".port(port)\" when possible.
1038 This is only legal in SystemVerilog files, and will confuse older
1039 simulators. Setting `verilog-auto-inst-vector' to nil may also
1040 be desirable to increase how often .name will be used."
1041 :group 'verilog-mode-auto
1043 (put 'verilog-auto-inst-dot-name 'safe-local-variable 'verilog-booleanp)
1045 (defcustom verilog-auto-inst-param-value nil
1046 "Non-nil means AUTOINST will replace parameters with the parameter value.
1047 If nil, leave parameters as symbolic names.
1049 Parameters must be in Verilog 2001 format #(...), and if a parameter is not
1050 listed as such there (as when the default value is acceptable), it will not
1051 be replaced, and will remain symbolic.
1053 For example, imagine a submodule uses parameters to declare the size of its
1054 inputs. This is then used by an upper module:
1056 module InstModule (o,i);
1058 input [WIDTH-1:0] i;
1068 Note even though PARAM=10, the AUTOINST has left the parameter as a
1069 symbolic name. If `verilog-auto-inst-param-value' is set, this will
1078 :group 'verilog-mode-auto
1080 (put 'verilog-auto-inst-param-value 'safe-local-variable 'verilog-booleanp)
1082 (defcustom verilog-auto-inst-sort nil
1083 "Non-nil means AUTOINST signals will be sorted, not in declaration order.
1084 Also affects AUTOINSTPARAM. Declaration order is the default for
1085 backward compatibility, and as some teams prefer signals that are
1086 declared together to remain together. Sorted order reduces
1087 changes when declarations are moved around in a file.
1089 See also `verilog-auto-arg-sort'."
1090 :version "24.1" ;; rev688
1091 :group 'verilog-mode-auto
1093 (put 'verilog-auto-inst-sort 'safe-local-variable 'verilog-booleanp)
1095 (defcustom verilog-auto-inst-vector t
1096 "Non-nil means when creating default ports with AUTOINST, use bus subscripts.
1097 If nil, skip the subscript when it matches the entire bus as declared in
1098 the module (AUTOWIRE signals always are subscripted, you must manually
1099 declare the wire to have the subscripts removed.) Setting this to nil may
1100 speed up some simulators, but is less general and harder to read, so avoid."
1101 :group 'verilog-mode-auto
1103 (put 'verilog-auto-inst-vector 'safe-local-variable 'verilog-booleanp)
1105 (defcustom verilog-auto-inst-template-numbers nil
1106 "If true, when creating templated ports with AUTOINST, add a comment.
1108 If t, the comment will add the line number of the template that
1109 was used for that port declaration. This setting is suggested
1110 only for debugging use, as regular use may cause a large numbers
1113 If 'lhs', the comment will show the left hand side of the
1114 AUTO_TEMPLATE rule that is matched. This is less precise than
1115 numbering (t) when multiple rules have the same pin name, but
1116 won't merge conflict."
1117 :group 'verilog-mode-auto
1118 :type '(choice (const nil) (const t) (const lhs)))
1119 (put 'verilog-auto-inst-template-numbers 'safe-local-variable
1120 '(lambda (x) (memq x '(nil t lhs))))
1122 (defcustom verilog-auto-inst-column 40
1123 "Indent-to column number for net name part of AUTOINST created pin."
1124 :group 'verilog-mode-indent
1126 (put 'verilog-auto-inst-column 'safe-local-variable 'integerp)
1128 (defcustom verilog-auto-inst-interfaced-ports nil
1129 "Non-nil means include interfaced ports in AUTOINST expansions."
1130 :version "24.3" ;; rev773, default change rev815
1131 :group 'verilog-mode-auto
1133 (put 'verilog-auto-inst-interfaced-ports 'safe-local-variable 'verilog-booleanp)
1135 (defcustom verilog-auto-input-ignore-regexp nil
1136 "If non-nil, when creating AUTOINPUT, ignore signals matching this regexp.
1137 See the \\[verilog-faq] for examples on using this."
1138 :group 'verilog-mode-auto
1139 :type '(choice (const nil) regexp))
1140 (put 'verilog-auto-input-ignore-regexp 'safe-local-variable 'stringp)
1142 (defcustom verilog-auto-inout-ignore-regexp nil
1143 "If non-nil, when creating AUTOINOUT, ignore signals matching this regexp.
1144 See the \\[verilog-faq] for examples on using this."
1145 :group 'verilog-mode-auto
1146 :type '(choice (const nil) regexp))
1147 (put 'verilog-auto-inout-ignore-regexp 'safe-local-variable 'stringp)
1149 (defcustom verilog-auto-output-ignore-regexp nil
1150 "If non-nil, when creating AUTOOUTPUT, ignore signals matching this regexp.
1151 See the \\[verilog-faq] for examples on using this."
1152 :group 'verilog-mode-auto
1153 :type '(choice (const nil) regexp))
1154 (put 'verilog-auto-output-ignore-regexp 'safe-local-variable 'stringp)
1156 (defcustom verilog-auto-template-warn-unused nil
1157 "Non-nil means report warning if an AUTO_TEMPLATE line is not used.
1158 This feature is not supported before Emacs 21.1 or XEmacs 21.4."
1159 :version "24.3" ;;rev787
1160 :group 'verilog-mode-auto
1162 (put 'verilog-auto-template-warn-unused 'safe-local-variable 'verilog-booleanp)
1164 (defcustom verilog-auto-tieoff-declaration "wire"
1165 "Data type used for the declaration for AUTOTIEOFF.
1166 If \"wire\" then create a wire, if \"assign\" create an
1167 assignment, else the data type for variable creation."
1168 :version "24.1" ;; rev713
1169 :group 'verilog-mode-auto
1171 (put 'verilog-auto-tieoff-declaration 'safe-local-variable 'stringp)
1173 (defcustom verilog-auto-tieoff-ignore-regexp nil
1174 "If non-nil, when creating AUTOTIEOFF, ignore signals matching this regexp.
1175 See the \\[verilog-faq] for examples on using this."
1176 :group 'verilog-mode-auto
1177 :type '(choice (const nil) regexp))
1178 (put 'verilog-auto-tieoff-ignore-regexp 'safe-local-variable 'stringp)
1180 (defcustom verilog-auto-unused-ignore-regexp nil
1181 "If non-nil, when creating AUTOUNUSED, ignore signals matching this regexp.
1182 See the \\[verilog-faq] for examples on using this."
1183 :group 'verilog-mode-auto
1184 :type '(choice (const nil) regexp))
1185 (put 'verilog-auto-unused-ignore-regexp 'safe-local-variable 'stringp)
1187 (defcustom verilog-case-fold t
1188 "Non-nil means `verilog-mode' regexps should ignore case.
1189 This variable is t for backward compatibility; nil is suggested."
1191 :group 'verilog-mode
1193 (put 'verilog-case-fold 'safe-local-variable 'verilog-booleanp)
1195 (defcustom verilog-typedef-regexp nil
1196 "If non-nil, regular expression that matches Verilog-2001 typedef names.
1197 For example, \"_t$\" matches typedefs named with _t, as in the C language.
1198 See also `verilog-case-fold'."
1199 :group 'verilog-mode-auto
1200 :type '(choice (const nil) regexp))
1201 (put 'verilog-typedef-regexp 'safe-local-variable 'stringp)
1203 (defcustom verilog-mode-hook 'verilog-set-compile-command
1204 "Hook run after Verilog mode is loaded."
1206 :group 'verilog-mode)
1208 (defcustom verilog-auto-hook nil
1209 "Hook run after `verilog-mode' updates AUTOs."
1210 :group 'verilog-mode-auto
1213 (defcustom verilog-before-auto-hook nil
1214 "Hook run before `verilog-mode' updates AUTOs."
1215 :group 'verilog-mode-auto
1218 (defcustom verilog-delete-auto-hook nil
1219 "Hook run after `verilog-mode' deletes AUTOs."
1220 :group 'verilog-mode-auto
1223 (defcustom verilog-before-delete-auto-hook nil
1224 "Hook run before `verilog-mode' deletes AUTOs."
1225 :group 'verilog-mode-auto
1228 (defcustom verilog-getopt-flags-hook nil
1229 "Hook run after `verilog-getopt-flags' determines the Verilog option lists."
1230 :group 'verilog-mode-auto
1233 (defcustom verilog-before-getopt-flags-hook nil
1234 "Hook run before `verilog-getopt-flags' determines the Verilog option lists."
1235 :group 'verilog-mode-auto
1238 (defcustom verilog-before-save-font-hook nil
1239 "Hook run before `verilog-save-font-mods' removes highlighting."
1240 :version "24.3" ;;rev735
1241 :group 'verilog-mode-auto
1244 (defcustom verilog-after-save-font-hook nil
1245 "Hook run after `verilog-save-font-mods' restores highlighting."
1246 :version "24.3" ;;rev735
1247 :group 'verilog-mode-auto
1250 (defvar verilog-imenu-generic-expression
1251 '((nil "^\\s-*\\(\\(m\\(odule\\|acromodule\\)\\)\\|primitive\\)\\s-+\\([a-zA-Z0-9_.:]+\\)" 4)
1252 ("*Vars*" "^\\s-*\\(reg\\|wire\\)\\s-+\\(\\|\\[[^]]+\\]\\s-+\\)\\([A-Za-z0-9_]+\\)" 3))
1253 "Imenu expression for Verilog mode. See `imenu-generic-expression'.")
1256 ;; provide a verilog-header function.
1257 ;; Customization variables:
1259 (defvar verilog-date-scientific-format nil
1260 "If non-nil, dates are written in scientific format (e.g. 1997/09/17).
1261 If nil, in European format (e.g. 17.09.1997). The brain-dead American
1262 format (e.g. 09/17/1997) is not supported.")
1264 (defvar verilog-company nil
1265 "Default name of Company for Verilog header.
1266 If set will become buffer local.")
1267 (make-variable-buffer-local 'verilog-company)
1269 (defvar verilog-project nil
1270 "Default name of Project for Verilog header.
1271 If set will become buffer local.")
1272 (make-variable-buffer-local 'verilog-project)
1274 (defvar verilog-mode-map
1275 (let ((map (make-sparse-keymap)))
1276 (define-key map ";" 'electric-verilog-semi)
1277 (define-key map [(control 59)] 'electric-verilog-semi-with-comment)
1278 (define-key map ":" 'electric-verilog-colon)
1279 ;;(define-key map "=" 'electric-verilog-equal)
1280 (define-key map "\`" 'electric-verilog-tick)
1281 (define-key map "\t" 'electric-verilog-tab)
1282 (define-key map "\r" 'electric-verilog-terminate-line)
1283 ;; backspace/delete key bindings
1284 (define-key map [backspace] 'backward-delete-char-untabify)
1285 (unless (boundp 'delete-key-deletes-forward) ; XEmacs variable
1286 (define-key map [delete] 'delete-char)
1287 (define-key map [(meta delete)] 'kill-word))
1288 (define-key map "\M-\C-b" 'electric-verilog-backward-sexp)
1289 (define-key map "\M-\C-f" 'electric-verilog-forward-sexp)
1290 (define-key map "\M-\r" `electric-verilog-terminate-and-indent)
1291 (define-key map "\M-\t" 'verilog-complete-word)
1292 (define-key map "\M-?" 'verilog-show-completions)
1293 ;; Note \C-c and letter are reserved for users
1294 (define-key map "\C-c\`" 'verilog-lint-off)
1295 (define-key map "\C-c\*" 'verilog-delete-auto-star-implicit)
1296 (define-key map "\C-c\?" 'verilog-diff-auto)
1297 (define-key map "\C-c\C-r" 'verilog-label-be)
1298 (define-key map "\C-c\C-i" 'verilog-pretty-declarations)
1299 (define-key map "\C-c=" 'verilog-pretty-expr)
1300 (define-key map "\C-c\C-b" 'verilog-submit-bug-report)
1301 (define-key map "\M-*" 'verilog-star-comment)
1302 (define-key map "\C-c\C-c" 'verilog-comment-region)
1303 (define-key map "\C-c\C-u" 'verilog-uncomment-region)
1304 (when (featurep 'xemacs)
1305 (define-key map [(meta control h)] 'verilog-mark-defun)
1306 (define-key map "\M-\C-a" 'verilog-beg-of-defun)
1307 (define-key map "\M-\C-e" 'verilog-end-of-defun))
1308 (define-key map "\C-c\C-d" 'verilog-goto-defun)
1309 (define-key map "\C-c\C-k" 'verilog-delete-auto)
1310 (define-key map "\C-c\C-a" 'verilog-auto)
1311 (define-key map "\C-c\C-s" 'verilog-auto-save-compile)
1312 (define-key map "\C-c\C-p" 'verilog-preprocess)
1313 (define-key map "\C-c\C-z" 'verilog-inject-auto)
1314 (define-key map "\C-c\C-e" 'verilog-expand-vector)
1315 (define-key map "\C-c\C-h" 'verilog-header)
1317 "Keymap used in Verilog mode.")
1321 verilog-menu verilog-mode-map "Menu for Verilog mode"
1322 (verilog-easy-menu-filter
1324 ("Choose Compilation Action"
1327 (setq verilog-tool nil)
1328 (verilog-set-compile-command))
1330 :selected (equal verilog-tool nil)
1331 :help "When invoking compilation, use compile-command"]
1334 (setq verilog-tool 'verilog-linter)
1335 (verilog-set-compile-command))
1337 :selected (equal verilog-tool `verilog-linter)
1338 :help "When invoking compilation, use lint checker"]
1341 (setq verilog-tool 'verilog-coverage)
1342 (verilog-set-compile-command))
1344 :selected (equal verilog-tool `verilog-coverage)
1345 :help "When invoking compilation, annotate for coverage"]
1348 (setq verilog-tool 'verilog-simulator)
1349 (verilog-set-compile-command))
1351 :selected (equal verilog-tool `verilog-simulator)
1352 :help "When invoking compilation, interpret Verilog source"]
1355 (setq verilog-tool 'verilog-compiler)
1356 (verilog-set-compile-command))
1358 :selected (equal verilog-tool `verilog-compiler)
1359 :help "When invoking compilation, compile Verilog source"]
1362 (setq verilog-tool 'verilog-preprocessor)
1363 (verilog-set-compile-command))
1365 :selected (equal verilog-tool `verilog-preprocessor)
1366 :help "When invoking compilation, preprocess Verilog source, see also `verilog-preprocess'"]
1369 ["Beginning of function" verilog-beg-of-defun
1371 :help "Move backward to the beginning of the current function or procedure"]
1372 ["End of function" verilog-end-of-defun
1374 :help "Move forward to the end of the current function or procedure"]
1375 ["Mark function" verilog-mark-defun
1377 :help "Mark the current Verilog function or procedure"]
1378 ["Goto function/module" verilog-goto-defun
1379 :help "Move to specified Verilog module/task/function"]
1380 ["Move to beginning of block" electric-verilog-backward-sexp
1381 :help "Move backward over one balanced expression"]
1382 ["Move to end of block" electric-verilog-forward-sexp
1383 :help "Move forward over one balanced expression"]
1386 ["Comment Region" verilog-comment-region
1387 :help "Put marked area into a comment"]
1388 ["UnComment Region" verilog-uncomment-region
1389 :help "Uncomment an area commented with Comment Region"]
1390 ["Multi-line comment insert" verilog-star-comment
1391 :help "Insert Verilog /* */ comment at point"]
1392 ["Lint error to comment" verilog-lint-off
1393 :help "Convert a Verilog linter warning line into a disable statement"]
1397 :help "Perform compilation-action (above) on the current buffer"]
1398 ["AUTO, Save, Compile" verilog-auto-save-compile
1399 :help "Recompute AUTOs, save buffer, and compile"]
1400 ["Next Compile Error" next-error
1401 :help "Visit next compilation error message and corresponding source code"]
1402 ["Ignore Lint Warning at point" verilog-lint-off
1403 :help "Convert a Verilog linter warning line into a disable statement"]
1405 ["Line up declarations around point" verilog-pretty-declarations
1406 :help "Line up declarations around point"]
1407 ["Line up equations around point" verilog-pretty-expr
1408 :help "Line up expressions around point"]
1409 ["Redo/insert comments on every end" verilog-label-be
1410 :help "Label matching begin ... end statements"]
1411 ["Expand [x:y] vector line" verilog-expand-vector
1412 :help "Take a signal vector on the current line and expand it to multiple lines"]
1413 ["Insert begin-end block" verilog-insert-block
1414 :help "Insert begin ... end"]
1415 ["Complete word" verilog-complete-word
1416 :help "Complete word at point"]
1418 ["Recompute AUTOs" verilog-auto
1419 :help "Expand AUTO meta-comment statements"]
1420 ["Kill AUTOs" verilog-delete-auto
1421 :help "Remove AUTO expansions"]
1422 ["Diff AUTOs" verilog-diff-auto
1423 :help "Show differences in AUTO expansions"]
1424 ["Inject AUTOs" verilog-inject-auto
1425 :help "Inject AUTOs into legacy non-AUTO buffer"]
1427 ["AUTO General" (describe-function 'verilog-auto)
1428 :help "Help introduction on AUTOs"]
1429 ["AUTO Library Flags" (describe-variable 'verilog-library-flags)
1430 :help "Help on verilog-library-flags"]
1431 ["AUTO Library Path" (describe-variable 'verilog-library-directories)
1432 :help "Help on verilog-library-directories"]
1433 ["AUTO Library Files" (describe-variable 'verilog-library-files)
1434 :help "Help on verilog-library-files"]
1435 ["AUTO Library Extensions" (describe-variable 'verilog-library-extensions)
1436 :help "Help on verilog-library-extensions"]
1437 ["AUTO `define Reading" (describe-function 'verilog-read-defines)
1438 :help "Help on reading `defines"]
1439 ["AUTO `include Reading" (describe-function 'verilog-read-includes)
1440 :help "Help on parsing `includes"]
1441 ["AUTOARG" (describe-function 'verilog-auto-arg)
1442 :help "Help on AUTOARG - declaring module port list"]
1443 ["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum)
1444 :help "Help on AUTOASCIIENUM - creating ASCII for enumerations"]
1445 ["AUTOASSIGNMODPORT" (describe-function 'verilog-auto-assign-modport)
1446 :help "Help on AUTOASSIGNMODPORT - creating assignments to/from modports"]
1447 ["AUTOINOUT" (describe-function 'verilog-auto-inout)
1448 :help "Help on AUTOINOUT - adding inouts from cells"]
1449 ["AUTOINOUTCOMP" (describe-function 'verilog-auto-inout-comp)
1450 :help "Help on AUTOINOUTCOMP - copying complemented i/o from another file"]
1451 ["AUTOINOUTIN" (describe-function 'verilog-auto-inout-in)
1452 :help "Help on AUTOINOUTIN - copying i/o from another file as all inputs"]
1453 ["AUTOINOUTMODPORT" (describe-function 'verilog-auto-inout-modport)
1454 :help "Help on AUTOINOUTMODPORT - copying i/o from an interface modport"]
1455 ["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module)
1456 :help "Help on AUTOINOUTMODULE - copying i/o from another file"]
1457 ["AUTOINOUTPARAM" (describe-function 'verilog-auto-inout-param)
1458 :help "Help on AUTOINOUTPARAM - copying parameters from another file"]
1459 ["AUTOINPUT" (describe-function 'verilog-auto-input)
1460 :help "Help on AUTOINPUT - adding inputs from cells"]
1461 ["AUTOINSERTLISP" (describe-function 'verilog-auto-insert-lisp)
1462 :help "Help on AUTOINSERTLISP - insert text from a lisp function"]
1463 ["AUTOINST" (describe-function 'verilog-auto-inst)
1464 :help "Help on AUTOINST - adding pins for cells"]
1465 ["AUTOINST (.*)" (describe-function 'verilog-auto-star)
1466 :help "Help on expanding Verilog-2001 .* pins"]
1467 ["AUTOINSTPARAM" (describe-function 'verilog-auto-inst-param)
1468 :help "Help on AUTOINSTPARAM - adding parameter pins to cells"]
1469 ["AUTOLOGIC" (describe-function 'verilog-auto-logic)
1470 :help "Help on AUTOLOGIC - declaring logic signals"]
1471 ["AUTOOUTPUT" (describe-function 'verilog-auto-output)
1472 :help "Help on AUTOOUTPUT - adding outputs from cells"]
1473 ["AUTOOUTPUTEVERY" (describe-function 'verilog-auto-output-every)
1474 :help "Help on AUTOOUTPUTEVERY - adding outputs of all signals"]
1475 ["AUTOREG" (describe-function 'verilog-auto-reg)
1476 :help "Help on AUTOREG - declaring registers for non-wires"]
1477 ["AUTOREGINPUT" (describe-function 'verilog-auto-reg-input)
1478 :help "Help on AUTOREGINPUT - declaring inputs for non-wires"]
1479 ["AUTORESET" (describe-function 'verilog-auto-reset)
1480 :help "Help on AUTORESET - resetting always blocks"]
1481 ["AUTOSENSE or AS" (describe-function 'verilog-auto-sense)
1482 :help "Help on AUTOSENSE - sensitivity lists for always blocks"]
1483 ["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff)
1484 :help "Help on AUTOTIEOFF - tying off unused outputs"]
1485 ["AUTOUNDEF" (describe-function 'verilog-auto-undef)
1486 :help "Help on AUTOUNDEF - undefine all local defines"]
1487 ["AUTOUNUSED" (describe-function 'verilog-auto-unused)
1488 :help "Help on AUTOUNUSED - terminating unused inputs"]
1489 ["AUTOWIRE" (describe-function 'verilog-auto-wire)
1490 :help "Help on AUTOWIRE - declaring wires for cells"]
1493 ["Submit bug report" verilog-submit-bug-report
1494 :help "Submit via mail a bug report on verilog-mode.el"]
1495 ["Version and FAQ" verilog-faq
1496 :help "Show the current version, and where to get the FAQ etc"]
1497 ["Customize Verilog Mode..." verilog-customize
1498 :help "Customize variables and other settings used by Verilog-Mode"]
1499 ["Customize Verilog Fonts & Colors" verilog-font-customize
1500 :help "Customize fonts used by Verilog-Mode."])))
1503 verilog-stmt-menu verilog-mode-map "Menu for statement templates in Verilog."
1504 (verilog-easy-menu-filter
1506 ["Header" verilog-sk-header
1507 :help "Insert a header block at the top of file"]
1508 ["Comment" verilog-sk-comment
1509 :help "Insert a comment block"]
1511 ["Module" verilog-sk-module
1512 :help "Insert a module .. (/*AUTOARG*/);.. endmodule block"]
1513 ["OVM Class" verilog-sk-ovm-class
1514 :help "Insert an OVM class block"]
1515 ["UVM Object" verilog-sk-uvm-object
1516 :help "Insert an UVM object block"]
1517 ["UVM Component" verilog-sk-uvm-component
1518 :help "Insert an UVM component block"]
1519 ["Primitive" verilog-sk-primitive
1520 :help "Insert a primitive .. (.. );.. endprimitive block"]
1522 ["Input" verilog-sk-input
1523 :help "Insert an input declaration"]
1524 ["Output" verilog-sk-output
1525 :help "Insert an output declaration"]
1526 ["Inout" verilog-sk-inout
1527 :help "Insert an inout declaration"]
1528 ["Wire" verilog-sk-wire
1529 :help "Insert a wire declaration"]
1530 ["Reg" verilog-sk-reg
1531 :help "Insert a register declaration"]
1532 ["Define thing under point as a register" verilog-sk-define-signal
1533 :help "Define signal under point as a register at the top of the module"]
1535 ["Initial" verilog-sk-initial
1536 :help "Insert an initial begin .. end block"]
1537 ["Always" verilog-sk-always
1538 :help "Insert an always @(AS) begin .. end block"]
1539 ["Function" verilog-sk-function
1540 :help "Insert a function .. begin .. end endfunction block"]
1541 ["Task" verilog-sk-task
1542 :help "Insert a task .. begin .. end endtask block"]
1543 ["Specify" verilog-sk-specify
1544 :help "Insert a specify .. endspecify block"]
1545 ["Generate" verilog-sk-generate
1546 :help "Insert a generate .. endgenerate block"]
1548 ["Begin" verilog-sk-begin
1549 :help "Insert a begin .. end block"]
1551 :help "Insert an if (..) begin .. end block"]
1552 ["(if) else" verilog-sk-else-if
1553 :help "Insert an else if (..) begin .. end block"]
1554 ["For" verilog-sk-for
1555 :help "Insert a for (...) begin .. end block"]
1556 ["While" verilog-sk-while
1557 :help "Insert a while (...) begin .. end block"]
1558 ["Fork" verilog-sk-fork
1559 :help "Insert a fork begin .. end .. join block"]
1560 ["Repeat" verilog-sk-repeat
1561 :help "Insert a repeat (..) begin .. end block"]
1562 ["Case" verilog-sk-case
1563 :help "Insert a case block, prompting for details"]
1564 ["Casex" verilog-sk-casex
1565 :help "Insert a casex (...) item: begin.. end endcase block"]
1566 ["Casez" verilog-sk-casez
1567 :help "Insert a casez (...) item: begin.. end endcase block"])))
1569 (defvar verilog-mode-abbrev-table nil
1570 "Abbrev table in use in Verilog-mode buffers.")
1572 (define-abbrev-table 'verilog-mode-abbrev-table ())
1573 (verilog-define-abbrev verilog-mode-abbrev-table "class" "" 'verilog-sk-ovm-class)
1574 (verilog-define-abbrev verilog-mode-abbrev-table "always" "" 'verilog-sk-always)
1575 (verilog-define-abbrev verilog-mode-abbrev-table "begin" nil `verilog-sk-begin)
1576 (verilog-define-abbrev verilog-mode-abbrev-table "case" "" `verilog-sk-case)
1577 (verilog-define-abbrev verilog-mode-abbrev-table "for" "" `verilog-sk-for)
1578 (verilog-define-abbrev verilog-mode-abbrev-table "generate" "" `verilog-sk-generate)
1579 (verilog-define-abbrev verilog-mode-abbrev-table "initial" "" `verilog-sk-initial)
1580 (verilog-define-abbrev verilog-mode-abbrev-table "fork" "" `verilog-sk-fork)
1581 (verilog-define-abbrev verilog-mode-abbrev-table "module" "" `verilog-sk-module)
1582 (verilog-define-abbrev verilog-mode-abbrev-table "primitive" "" `verilog-sk-primitive)
1583 (verilog-define-abbrev verilog-mode-abbrev-table "repeat" "" `verilog-sk-repeat)
1584 (verilog-define-abbrev verilog-mode-abbrev-table "specify" "" `verilog-sk-specify)
1585 (verilog-define-abbrev verilog-mode-abbrev-table "task" "" `verilog-sk-task)
1586 (verilog-define-abbrev verilog-mode-abbrev-table "while" "" `verilog-sk-while)
1587 (verilog-define-abbrev verilog-mode-abbrev-table "casex" "" `verilog-sk-casex)
1588 (verilog-define-abbrev verilog-mode-abbrev-table "casez" "" `verilog-sk-casez)
1589 (verilog-define-abbrev verilog-mode-abbrev-table "if" "" `verilog-sk-if)
1590 (verilog-define-abbrev verilog-mode-abbrev-table "else if" "" `verilog-sk-else-if)
1591 (verilog-define-abbrev verilog-mode-abbrev-table "assign" "" `verilog-sk-assign)
1592 (verilog-define-abbrev verilog-mode-abbrev-table "function" "" `verilog-sk-function)
1593 (verilog-define-abbrev verilog-mode-abbrev-table "input" "" `verilog-sk-input)
1594 (verilog-define-abbrev verilog-mode-abbrev-table "output" "" `verilog-sk-output)
1595 (verilog-define-abbrev verilog-mode-abbrev-table "inout" "" `verilog-sk-inout)
1596 (verilog-define-abbrev verilog-mode-abbrev-table "wire" "" `verilog-sk-wire)
1597 (verilog-define-abbrev verilog-mode-abbrev-table "reg" "" `verilog-sk-reg)
1603 (defsubst verilog-within-string ()
1604 (nth 3 (parse-partial-sexp (point-at-bol) (point))))
1606 (defsubst verilog-string-match-fold (regexp string &optional start)
1607 "Like `string-match', but use `verilog-case-fold'.
1608 Return index of start of first match for REGEXP in STRING, or nil.
1609 Matching ignores case if `verilog-case-fold' is non-nil.
1610 If third arg START is non-nil, start search at that index in STRING."
1611 (let ((case-fold-search verilog-case-fold))
1612 (string-match regexp string start)))
1614 (defsubst verilog-string-replace-matches (from-string to-string fixedcase literal string)
1615 "Replace occurrences of FROM-STRING with TO-STRING.
1616 FIXEDCASE and LITERAL as in `replace-match`. STRING is what to replace.
1617 The case (verilog-string-replace-matches \"o\" \"oo\" nil nil \"foobar\")
1618 will break, as the o's continuously replace. xa -> x works ok though."
1619 ;; Hopefully soon to an Emacs built-in
1620 ;; Also note \ in the replacement prevent multiple replacements; IE
1621 ;; (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil "wire@_@")
1622 ;; Gives "wire\([0-9]+\)_@" not "wire\([0-9]+\)_\([0-9]+\)"
1624 (while (string-match from-string string start)
1625 (setq string (replace-match to-string fixedcase literal string)
1626 start (min (length string) (+ (match-beginning 0) (length to-string)))))
1629 (defsubst verilog-string-remove-spaces (string)
1630 "Remove spaces surrounding STRING."
1632 (setq string (verilog-string-replace-matches "^\\s-+" "" nil nil string))
1633 (setq string (verilog-string-replace-matches "\\s-+$" "" nil nil string))
1636 (defsubst verilog-re-search-forward (REGEXP BOUND NOERROR)
1637 ;; checkdoc-params: (REGEXP BOUND NOERROR)
1638 "Like `re-search-forward', but skips over match in comments or strings."
1639 (let ((mdata '(nil nil))) ;; So match-end will return nil if no matches found
1641 (re-search-forward REGEXP BOUND NOERROR)
1642 (setq mdata (match-data))
1643 (and (verilog-skip-forward-comment-or-string)
1645 (setq mdata '(nil nil))
1649 (store-match-data mdata)
1652 (defsubst verilog-re-search-backward (REGEXP BOUND NOERROR)
1653 ;; checkdoc-params: (REGEXP BOUND NOERROR)
1654 "Like `re-search-backward', but skips over match in comments or strings."
1655 (let ((mdata '(nil nil))) ;; So match-end will return nil if no matches found
1657 (re-search-backward REGEXP BOUND NOERROR)
1658 (setq mdata (match-data))
1659 (and (verilog-skip-backward-comment-or-string)
1661 (setq mdata '(nil nil))
1665 (store-match-data mdata)
1668 (defsubst verilog-re-search-forward-quick (regexp bound noerror)
1669 "Like `verilog-re-search-forward', including use of REGEXP BOUND and NOERROR,
1670 but trashes match data and is faster for REGEXP that doesn't match often.
1671 This uses `verilog-scan' and text properties to ignore comments,
1672 so there may be a large up front penalty for the first search."
1674 (while (and (not pt)
1675 (re-search-forward regexp bound noerror))
1676 (if (verilog-inside-comment-or-string-p)
1677 (re-search-forward "[/\"\n]" nil t) ;; Only way a comment or quote can end
1678 (setq pt (match-end 0))))
1681 (defsubst verilog-re-search-backward-quick (regexp bound noerror)
1682 ;; checkdoc-params: (REGEXP BOUND NOERROR)
1683 "Like `verilog-re-search-backward', including use of REGEXP BOUND and NOERROR,
1684 but trashes match data and is faster for REGEXP that doesn't match often.
1685 This uses `verilog-scan' and text properties to ignore comments,
1686 so there may be a large up front penalty for the first search."
1688 (while (and (not pt)
1689 (re-search-backward regexp bound noerror))
1690 (if (verilog-inside-comment-or-string-p)
1691 (re-search-backward "[/\"]" nil t) ;; Only way a comment or quote can begin
1692 (setq pt (match-beginning 0))))
1695 (defsubst verilog-re-search-forward-substr (substr regexp bound noerror)
1696 "Like `re-search-forward', but first search for SUBSTR constant.
1697 Then searched for the normal REGEXP (which contains SUBSTR), with given
1698 BOUND and NOERROR. The REGEXP must fit within a single line.
1699 This speeds up complicated regexp matches."
1700 ;; Problem with overlap: search-forward BAR then FOOBARBAZ won't match.
1701 ;; thus require matches to be on one line, and use beginning-of-line.
1703 (while (and (not done)
1704 (search-forward substr bound noerror))
1707 (setq done (re-search-forward regexp (point-at-eol) noerror)))
1708 (unless (and (<= (match-beginning 0) (point))
1709 (>= (match-end 0) (point)))
1711 (when done (goto-char done))
1713 ;;(verilog-re-search-forward-substr "-end" "get-end-of" nil t) ;;-end (test bait)
1715 (defsubst verilog-re-search-backward-substr (substr regexp bound noerror)
1716 "Like `re-search-backward', but first search for SUBSTR constant.
1717 Then searched for the normal REGEXP (which contains SUBSTR), with given
1718 BOUND and NOERROR. The REGEXP must fit within a single line.
1719 This speeds up complicated regexp matches."
1720 ;; Problem with overlap: search-backward BAR then FOOBARBAZ won't match.
1721 ;; thus require matches to be on one line, and use beginning-of-line.
1723 (while (and (not done)
1724 (search-backward substr bound noerror))
1727 (setq done (re-search-backward regexp (point-at-bol) noerror)))
1728 (unless (and (<= (match-beginning 0) (point))
1729 (>= (match-end 0) (point)))
1731 (when done (goto-char done))
1733 ;;(verilog-re-search-backward-substr "-end" "get-end-of" nil t) ;;-end (test bait)
1735 (defun verilog-delete-trailing-whitespace ()
1736 "Delete trailing spaces or tabs, but not newlines nor linefeeds.
1737 Also add missing final newline.
1739 To call this from the command line, see \\[verilog-batch-diff-auto].
1741 To call on \\[verilog-auto], set `verilog-auto-delete-trailing-whitespace'."
1742 ;; Similar to `delete-trailing-whitespace' but that's not present in XEmacs
1744 (goto-char (point-min))
1745 (while (re-search-forward "[ \t]+$" nil t) ;; Not syntactic WS as no formfeed
1746 (replace-match "" nil nil))
1747 (goto-char (point-max))
1748 (unless (bolp) (insert "\n"))))
1750 (defvar compile-command)
1751 (defvar create-lockfiles) ;; Emacs 24
1753 ;; compilation program
1754 (defun verilog-set-compile-command ()
1755 "Function to compute shell command to compile Verilog.
1757 This reads `verilog-tool' and sets `compile-command'. This specifies the
1758 program that executes when you type \\[compile] or
1759 \\[verilog-auto-save-compile].
1761 By default `verilog-tool' uses a Makefile if one exists in the
1762 current directory. If not, it is set to the `verilog-linter',
1763 `verilog-compiler', `verilog-coverage', `verilog-preprocessor',
1764 or `verilog-simulator' variables, as selected with the Verilog ->
1765 \"Choose Compilation Action\" menu.
1767 You should set `verilog-tool' or the other variables to the path and
1768 arguments for your Verilog simulator. For example:
1771 \"(cd /tmp; surecov %s)\".
1773 In the former case, the path to the current buffer is concat'ed to the
1774 value of `verilog-tool'; in the later, the path to the current buffer is
1775 substituted for the %s.
1777 Where __FLAGS__ appears in the string `verilog-current-flags'
1778 will be substituted.
1780 Where __FILE__ appears in the string, the variable
1781 `buffer-file-name' of the current buffer, without the directory
1782 portion, will be substituted."
1785 ((or (file-exists-p "makefile") ;If there is a makefile, use it
1786 (file-exists-p "Makefile"))
1787 (set (make-local-variable 'compile-command) "make "))
1789 (set (make-local-variable 'compile-command)
1791 (if (string-match "%s" (eval verilog-tool))
1792 (format (eval verilog-tool) (or buffer-file-name ""))
1793 (concat (eval verilog-tool) " " (or buffer-file-name "")))
1795 (verilog-modify-compile-command))
1797 (defun verilog-expand-command (command)
1798 "Replace meta-information in COMMAND and return it.
1799 Where __FLAGS__ appears in the string `verilog-current-flags'
1800 will be substituted. Where __FILE__ appears in the string, the
1801 current buffer's file-name, without the directory portion, will
1803 (setq command (verilog-string-replace-matches
1804 ;; Note \\b only works if under verilog syntax table
1805 "\\b__FLAGS__\\b" (verilog-current-flags)
1807 (setq command (verilog-string-replace-matches
1808 "\\b__FILE__\\b" (file-name-nondirectory
1809 (or (buffer-file-name) ""))
1813 (defun verilog-modify-compile-command ()
1814 "Update `compile-command' using `verilog-expand-command'."
1816 (stringp compile-command)
1817 (string-match "\\b\\(__FLAGS__\\|__FILE__\\)\\b" compile-command))
1818 (set (make-local-variable 'compile-command)
1819 (verilog-expand-command compile-command))))
1821 (if (featurep 'xemacs)
1822 ;; Following code only gets called from compilation-mode-hook on XEmacs to add error handling.
1823 (defun verilog-error-regexp-add-xemacs ()
1824 "Teach XEmacs about verilog errors.
1825 Called by `compilation-mode-hook'. This allows \\[next-error] to
1828 (if (boundp 'compilation-error-regexp-systems-alist)
1830 (not (equal compilation-error-regexp-systems-list 'all))
1831 (not (member compilation-error-regexp-systems-list 'verilog)))
1832 (push 'verilog compilation-error-regexp-systems-list)))
1833 (if (boundp 'compilation-error-regexp-alist-alist)
1834 (if (not (assoc 'verilog compilation-error-regexp-alist-alist))
1835 (setcdr compilation-error-regexp-alist-alist
1836 (cons verilog-error-regexp-xemacs-alist
1837 (cdr compilation-error-regexp-alist-alist)))))
1838 (if (boundp 'compilation-font-lock-keywords)
1840 (set (make-local-variable 'compilation-font-lock-keywords)
1841 verilog-error-font-lock-keywords)
1842 (font-lock-set-defaults)))
1843 ;; Need to re-run compilation-error-regexp builder
1844 (if (fboundp 'compilation-build-compilation-error-regexp-alist)
1845 (compilation-build-compilation-error-regexp-alist))
1848 ;; Following code only gets called from compilation-mode-hook on Emacs to add error handling.
1849 (defun verilog-error-regexp-add-emacs ()
1850 "Tell Emacs compile that we are Verilog.
1851 Called by `compilation-mode-hook'. This allows \\[next-error] to
1854 (if (boundp 'compilation-error-regexp-alist-alist)
1856 (if (not (assoc 'verilog-xl-1 compilation-error-regexp-alist-alist))
1859 (push (car item) compilation-error-regexp-alist)
1860 (push item compilation-error-regexp-alist-alist)
1862 verilog-error-regexp-emacs-alist)))))
1864 (if (featurep 'xemacs) (add-hook 'compilation-mode-hook 'verilog-error-regexp-add-xemacs))
1865 (if (featurep 'emacs) (add-hook 'compilation-mode-hook 'verilog-error-regexp-add-emacs))
1867 (defconst verilog-directive-re
1869 (verilog-regexp-words
1871 "`case" "`default" "`define" "`else" "`elsif" "`endfor" "`endif"
1872 "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
1873 "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
1874 "`time_scale" "`undef" "`while" ))))
1876 (defconst verilog-directive-re-1
1877 (concat "[ \t]*" verilog-directive-re))
1879 (defconst verilog-directive-begin
1880 "\\<`\\(for\\|i\\(f\\|fdef\\|fndef\\)\\|switch\\|while\\)\\>")
1882 (defconst verilog-directive-middle
1883 "\\<`\\(else\\|elsif\\|default\\|case\\)\\>")
1885 (defconst verilog-directive-end
1886 "`\\(endfor\\|endif\\|endswitch\\|endwhile\\)\\>")
1888 (defconst verilog-ovm-begin-re
1892 "`ovm_component_utils_begin"
1893 "`ovm_component_param_utils_begin"
1894 "`ovm_field_utils_begin"
1895 "`ovm_object_utils_begin"
1896 "`ovm_object_param_utils_begin"
1897 "`ovm_sequence_utils_begin"
1898 "`ovm_sequencer_utils_begin"
1901 (defconst verilog-ovm-end-re
1905 "`ovm_component_utils_end"
1906 "`ovm_field_utils_end"
1907 "`ovm_object_utils_end"
1908 "`ovm_sequence_utils_end"
1909 "`ovm_sequencer_utils_end"
1912 (defconst verilog-uvm-begin-re
1916 "`uvm_component_utils_begin"
1917 "`uvm_component_param_utils_begin"
1918 "`uvm_field_utils_begin"
1919 "`uvm_object_utils_begin"
1920 "`uvm_object_param_utils_begin"
1921 "`uvm_sequence_utils_begin"
1922 "`uvm_sequencer_utils_begin"
1925 (defconst verilog-uvm-end-re
1929 "`uvm_component_utils_end"
1930 "`uvm_field_utils_end"
1931 "`uvm_object_utils_end"
1932 "`uvm_sequence_utils_end"
1933 "`uvm_sequencer_utils_end"
1936 (defconst verilog-vmm-begin-re
1940 "`vmm_data_member_begin"
1941 "`vmm_env_member_begin"
1942 "`vmm_scenario_member_begin"
1943 "`vmm_subenv_member_begin"
1944 "`vmm_xactor_member_begin"
1947 (defconst verilog-vmm-end-re
1951 "`vmm_data_member_end"
1952 "`vmm_env_member_end"
1953 "`vmm_scenario_member_end"
1954 "`vmm_subenv_member_end"
1955 "`vmm_xactor_member_end"
1958 (defconst verilog-vmm-statement-re
1962 ;; "`vmm_xactor_member_enum_array"
1963 "`vmm_\\(data\\|env\\|scenario\\|subenv\\|xactor\\)_member_\\(scalar\\|string\\|enum\\|vmm_data\\|channel\\|xactor\\|subenv\\|user_defined\\)\\(_array\\)?"
1964 ;; "`vmm_xactor_member_scalar_array"
1965 ;; "`vmm_xactor_member_scalar"
1968 (defconst verilog-ovm-statement-re
1977 "`ovm_analysis_imp_decl"
1978 "`ovm_blocking_get_imp_decl"
1979 "`ovm_blocking_get_peek_imp_decl"
1980 "`ovm_blocking_master_imp_decl"
1981 "`ovm_blocking_peek_imp_decl"
1982 "`ovm_blocking_put_imp_decl"
1983 "`ovm_blocking_slave_imp_decl"
1984 "`ovm_blocking_transport_imp_decl"
1985 "`ovm_component_registry"
1986 "`ovm_component_registry_param"
1987 "`ovm_component_utils"
1990 "`ovm_declare_sequence_lib"
1997 "`ovm_field_aa_int_byte"
1998 "`ovm_field_aa_int_byte_unsigned"
1999 "`ovm_field_aa_int_int"
2000 "`ovm_field_aa_int_int_unsigned"
2001 "`ovm_field_aa_int_integer"
2002 "`ovm_field_aa_int_integer_unsigned"
2003 "`ovm_field_aa_int_key"
2004 "`ovm_field_aa_int_longint"
2005 "`ovm_field_aa_int_longint_unsigned"
2006 "`ovm_field_aa_int_shortint"
2007 "`ovm_field_aa_int_shortint_unsigned"
2008 "`ovm_field_aa_int_string"
2009 "`ovm_field_aa_object_int"
2010 "`ovm_field_aa_object_string"
2011 "`ovm_field_aa_string_int"
2012 "`ovm_field_aa_string_string"
2013 "`ovm_field_array_int"
2014 "`ovm_field_array_object"
2015 "`ovm_field_array_string"
2020 "`ovm_field_queue_int"
2021 "`ovm_field_queue_object"
2022 "`ovm_field_queue_string"
2023 "`ovm_field_sarray_int"
2028 "`ovm_get_peek_imp_decl"
2035 "`ovm_master_imp_decl"
2037 "`ovm_non_blocking_transport_imp_decl"
2038 "`ovm_nonblocking_get_imp_decl"
2039 "`ovm_nonblocking_get_peek_imp_decl"
2040 "`ovm_nonblocking_master_imp_decl"
2041 "`ovm_nonblocking_peek_imp_decl"
2042 "`ovm_nonblocking_put_imp_decl"
2043 "`ovm_nonblocking_slave_imp_decl"
2044 "`ovm_object_registry"
2045 "`ovm_object_registry_param"
2047 "`ovm_peek_imp_decl"
2048 "`ovm_phase_func_decl"
2049 "`ovm_phase_task_decl"
2050 "`ovm_print_aa_int_object"
2051 "`ovm_print_aa_string_int"
2052 "`ovm_print_aa_string_object"
2053 "`ovm_print_aa_string_string"
2054 "`ovm_print_array_int"
2055 "`ovm_print_array_object"
2056 "`ovm_print_array_string"
2057 "`ovm_print_object_queue"
2058 "`ovm_print_queue_int"
2059 "`ovm_print_string_queue"
2062 "`ovm_rand_send_with"
2064 "`ovm_sequence_utils"
2065 "`ovm_slave_imp_decl"
2066 "`ovm_transport_imp_decl"
2067 "`ovm_update_sequence_lib"
2068 "`ovm_update_sequence_lib_and_item"
2071 "`static_message") nil )))
2073 (defconst verilog-uvm-statement-re
2078 "`uvm_analysis_imp_decl"
2079 "`uvm_blocking_get_imp_decl"
2080 "`uvm_blocking_get_peek_imp_decl"
2081 "`uvm_blocking_master_imp_decl"
2082 "`uvm_blocking_peek_imp_decl"
2083 "`uvm_blocking_put_imp_decl"
2084 "`uvm_blocking_slave_imp_decl"
2085 "`uvm_blocking_transport_imp_decl"
2086 "`uvm_component_param_utils"
2087 "`uvm_component_registry"
2088 "`uvm_component_registry_param"
2089 "`uvm_component_utils"
2092 "`uvm_create_seq" ;; Undocumented in 1.1
2093 "`uvm_declare_p_sequencer"
2094 "`uvm_declare_sequence_lib" ;; Deprecated in 1.1
2097 "`uvm_do_callbacks_exit_on"
2098 "`uvm_do_obj_callbacks"
2099 "`uvm_do_obj_callbacks_exit_on"
2102 "`uvm_do_on_pri_with"
2106 "`uvm_do_seq" ;; Undocumented in 1.1
2107 "`uvm_do_seq_with" ;; Undocumented in 1.1
2110 "`uvm_error_context"
2112 "`uvm_fatal_context"
2113 "`uvm_field_aa_int_byte"
2114 "`uvm_field_aa_int_byte_unsigned"
2115 "`uvm_field_aa_int_enum"
2116 "`uvm_field_aa_int_int"
2117 "`uvm_field_aa_int_int_unsigned"
2118 "`uvm_field_aa_int_integer"
2119 "`uvm_field_aa_int_integer_unsigned"
2120 "`uvm_field_aa_int_key"
2121 "`uvm_field_aa_int_longint"
2122 "`uvm_field_aa_int_longint_unsigned"
2123 "`uvm_field_aa_int_shortint"
2124 "`uvm_field_aa_int_shortint_unsigned"
2125 "`uvm_field_aa_int_string"
2126 "`uvm_field_aa_object_int"
2127 "`uvm_field_aa_object_string"
2128 "`uvm_field_aa_string_int"
2129 "`uvm_field_aa_string_string"
2130 "`uvm_field_array_enum"
2131 "`uvm_field_array_int"
2132 "`uvm_field_array_object"
2133 "`uvm_field_array_string"
2138 "`uvm_field_queue_enum"
2139 "`uvm_field_queue_int"
2140 "`uvm_field_queue_object"
2141 "`uvm_field_queue_string"
2143 "`uvm_field_sarray_enum"
2144 "`uvm_field_sarray_int"
2145 "`uvm_field_sarray_object"
2146 "`uvm_field_sarray_string"
2149 "`uvm_file" ;; Undocumented in 1.1, use `__FILE__
2151 "`uvm_get_peek_imp_decl"
2154 "`uvm_line" ;; Undocumented in 1.1, use `__LINE__
2155 "`uvm_master_imp_decl"
2156 "`uvm_non_blocking_transport_imp_decl" ;; Deprecated in 1.1
2157 "`uvm_nonblocking_get_imp_decl"
2158 "`uvm_nonblocking_get_peek_imp_decl"
2159 "`uvm_nonblocking_master_imp_decl"
2160 "`uvm_nonblocking_peek_imp_decl"
2161 "`uvm_nonblocking_put_imp_decl"
2162 "`uvm_nonblocking_slave_imp_decl"
2163 "`uvm_nonblocking_transport_imp_decl"
2164 "`uvm_object_param_utils"
2165 "`uvm_object_registry"
2166 "`uvm_object_registry_param" ;; Undocumented in 1.1
2180 "`uvm_peek_imp_decl"
2183 "`uvm_rand_send_pri"
2184 "`uvm_rand_send_pri_with"
2185 "`uvm_rand_send_with"
2186 "`uvm_record_attribute"
2191 "`uvm_sequence_utils" ;; Deprecated in 1.1
2192 "`uvm_set_super_type"
2193 "`uvm_slave_imp_decl"
2194 "`uvm_transport_imp_decl"
2196 "`uvm_unpack_arrayN"
2202 "`uvm_unpack_queueN"
2204 "`uvm_unpack_sarray"
2205 "`uvm_unpack_sarrayN"
2206 "`uvm_unpack_string"
2207 "`uvm_update_sequence_lib" ;; Deprecated in 1.1
2208 "`uvm_update_sequence_lib_and_item" ;; Deprecated in 1.1
2210 "`uvm_warning_context") nil )))
2214 ;; Regular expressions used to calculate indent, etc.
2216 (defconst verilog-symbol-re "\\<[a-zA-Z_][a-zA-Z_0-9.]*\\>")
2223 (defconst verilog-assignment-operator-re
2227 ;; blocking assignment_operator
2228 "=" "+=" "-=" "*=" "/=" "%=" "&=" "|=" "^=" "<<=" ">>=" "<<<=" ">>>="
2229 ;; non blocking assignment operator
2232 "==" "!=" "===" "!===" "<=" ">=" "==\?" "!=\?"
2237 ;; Is this a legal verilog operator?
2241 (defconst verilog-assignment-operation-re
2243 ; "\\(^\\s-*[A-Za-z0-9_]+\\(\\[\\([A-Za-z0-9_]+\\)\\]\\)*\\s-*\\)"
2244 ; "\\(^\\s-*[^=<>+-*/%&|^:\\s-]+[^=<>+-*/%&|^\n]*?\\)"
2245 "\\(^.*?\\)" "\\B" verilog-assignment-operator-re "\\B" ))
2247 (defconst verilog-label-re (concat verilog-symbol-re "\\s-*:\\s-*"))
2248 (defconst verilog-property-re
2249 (concat "\\(" verilog-label-re "\\)?"
2250 "\\(\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(assert\\)"))
2251 ;; "\\(assert\\|assume\\|cover\\)\\s-+property\\>"
2253 (defconst verilog-no-indent-begin-re
2254 "\\<\\(if\\|else\\|while\\|for\\|repeat\\|always\\|always_comb\\|always_ff\\|always_latch\\)\\>")
2256 (defconst verilog-ends-re
2257 ;; Parenthesis indicate type of keyword found
2259 "\\(\\<else\\>\\)\\|" ; 1
2260 "\\(\\<if\\>\\)\\|" ; 2
2261 "\\(\\<assert\\>\\)\\|" ; 3
2262 "\\(\\<end\\>\\)\\|" ; 3.1
2263 "\\(\\<endcase\\>\\)\\|" ; 4
2264 "\\(\\<endfunction\\>\\)\\|" ; 5
2265 "\\(\\<endtask\\>\\)\\|" ; 6
2266 "\\(\\<endspecify\\>\\)\\|" ; 7
2267 "\\(\\<endtable\\>\\)\\|" ; 8
2268 "\\(\\<endgenerate\\>\\)\\|" ; 9
2269 "\\(\\<join\\(_any\\|_none\\)?\\>\\)\\|" ; 10
2270 "\\(\\<endclass\\>\\)\\|" ; 11
2271 "\\(\\<endgroup\\>\\)\\|" ; 12
2273 "\\(\\<`vmm_data_member_end\\>\\)\\|"
2274 "\\(\\<`vmm_env_member_end\\>\\)\\|"
2275 "\\(\\<`vmm_scenario_member_end\\>\\)\\|"
2276 "\\(\\<`vmm_subenv_member_end\\>\\)\\|"
2277 "\\(\\<`vmm_xactor_member_end\\>\\)\\|"
2279 "\\(\\<`ovm_component_utils_end\\>\\)\\|"
2280 "\\(\\<`ovm_field_utils_end\\>\\)\\|"
2281 "\\(\\<`ovm_object_utils_end\\>\\)\\|"
2282 "\\(\\<`ovm_sequence_utils_end\\>\\)\\|"
2283 "\\(\\<`ovm_sequencer_utils_end\\>\\)"
2285 "\\(\\<`uvm_component_utils_end\\>\\)\\|"
2286 "\\(\\<`uvm_field_utils_end\\>\\)\\|"
2287 "\\(\\<`uvm_object_utils_end\\>\\)\\|"
2288 "\\(\\<`uvm_sequence_utils_end\\>\\)\\|"
2289 "\\(\\<`uvm_sequencer_utils_end\\>\\)"
2292 (defconst verilog-auto-end-comment-lines-re
2293 ;; Matches to names in this list cause auto-end-commenting
2295 verilog-directive-re "\\)\\|\\("
2297 (verilog-regexp-words
2325 ;;; NOTE: verilog-leap-to-head expects that verilog-end-block-re and
2326 ;;; verilog-end-block-ordered-re matches exactly the same strings.
2327 (defconst verilog-end-block-ordered-re
2328 ;; Parenthesis indicate type of keyword found
2329 (concat "\\(\\<endcase\\>\\)\\|" ; 1
2330 "\\(\\<end\\>\\)\\|" ; 2
2331 "\\(\\<end" ; 3, but not used
2332 "\\(" ; 4, but not used
2333 "\\(function\\)\\|" ; 5
2335 "\\(module\\)\\|" ; 7
2336 "\\(primitive\\)\\|" ; 8
2337 "\\(interface\\)\\|" ; 9
2338 "\\(package\\)\\|" ; 10
2339 "\\(class\\)\\|" ; 11
2340 "\\(group\\)\\|" ; 12
2341 "\\(program\\)\\|" ; 13
2342 "\\(sequence\\)\\|" ; 14
2343 "\\(clocking\\)\\|" ; 15
2345 (defconst verilog-end-block-re
2347 (verilog-regexp-words
2349 `("end" ;; closes begin
2350 "endcase" ;; closes any of case, casex casez or randcase
2351 "join" "join_any" "join_none" ;; closes fork
2366 "`ovm_component_utils_end"
2367 "`ovm_field_utils_end"
2368 "`ovm_object_utils_end"
2369 "`ovm_sequence_utils_end"
2370 "`ovm_sequencer_utils_end"
2372 "`uvm_component_utils_end"
2373 "`uvm_field_utils_end"
2374 "`uvm_object_utils_end"
2375 "`uvm_sequence_utils_end"
2376 "`uvm_sequencer_utils_end"
2378 "`vmm_data_member_end"
2379 "`vmm_env_member_end"
2380 "`vmm_scenario_member_end"
2381 "`vmm_subenv_member_end"
2382 "`vmm_xactor_member_end"
2386 (defconst verilog-endcomment-reason-re
2387 ;; Parenthesis indicate type of keyword found
2389 "\\(\\<begin\\>\\)\\|" ; 1
2390 "\\(\\<else\\>\\)\\|" ; 2
2391 "\\(\\<end\\>\\s-+\\<else\\>\\)\\|" ; 3
2392 "\\(\\<always_comb\\>\\(\[ \t\]*@\\)?\\)\\|" ; 4
2393 "\\(\\<always_ff\\>\\(\[ \t\]*@\\)?\\)\\|" ; 5
2394 "\\(\\<always_latch\\>\\(\[ \t\]*@\\)?\\)\\|" ; 6
2395 "\\(\\<fork\\>\\)\\|" ; 7
2396 "\\(\\<always\\>\\(\[ \t\]*@\\)?\\)\\|"
2398 verilog-property-re "\\|"
2399 "\\(\\(" verilog-label-re "\\)?\\<assert\\>\\)\\|"
2400 "\\(\\<clocking\\>\\)\\|"
2401 "\\(\\<task\\>\\)\\|"
2402 "\\(\\<function\\>\\)\\|"
2403 "\\(\\<initial\\>\\)\\|"
2404 "\\(\\<interface\\>\\)\\|"
2405 "\\(\\<package\\>\\)\\|"
2406 "\\(\\<final\\>\\)\\|"
2408 "\\(\\<while\\>\\)\\|"
2409 "\\(\\<for\\(ever\\|each\\)?\\>\\)\\|"
2410 "\\(\\<repeat\\>\\)\\|\\(\\<wait\\>\\)\\|"
2413 (defconst verilog-named-block-re "begin[ \t]*:")
2415 ;; These words begin a block which can occur inside a module which should be indented,
2416 ;; and closed with the respective word from the end-block list
2418 (defconst verilog-beg-block-re
2420 (verilog-regexp-words
2422 "case" "casex" "casez" "randcase"
2432 "`ovm_component_utils_begin"
2433 "`ovm_component_param_utils_begin"
2434 "`ovm_field_utils_begin"
2435 "`ovm_object_utils_begin"
2436 "`ovm_object_param_utils_begin"
2437 "`ovm_sequence_utils_begin"
2438 "`ovm_sequencer_utils_begin"
2440 "`uvm_component_utils_begin"
2441 "`uvm_component_param_utils_begin"
2442 "`uvm_field_utils_begin"
2443 "`uvm_object_utils_begin"
2444 "`uvm_object_param_utils_begin"
2445 "`uvm_sequence_utils_begin"
2446 "`uvm_sequencer_utils_begin"
2448 "`vmm_data_member_begin"
2449 "`vmm_env_member_begin"
2450 "`vmm_scenario_member_begin"
2451 "`vmm_subenv_member_begin"
2452 "`vmm_xactor_member_begin"
2454 ;; These are the same words, in a specific order in the regular
2455 ;; expression so that matching will work nicely for
2456 ;; verilog-forward-sexp and verilog-calc-indent
2457 (defconst verilog-beg-block-re-ordered
2458 ( concat "\\(\\<begin\\>\\)" ;1
2459 "\\|\\(\\<randcase\\>\\|\\(\\<unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\>\\)" ; 2,3
2460 "\\|\\(\\(\\<disable\\>\\s-+\\|\\<wait\\>\\s-+\\)?fork\\>\\)" ;4,5
2461 "\\|\\(\\<class\\>\\)" ;6
2462 "\\|\\(\\<table\\>\\)" ;7
2463 "\\|\\(\\<specify\\>\\)" ;8
2464 "\\|\\(\\<function\\>\\)" ;9
2465 "\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)*\\<function\\>\\)" ;10
2466 "\\|\\(\\<task\\>\\)" ;14
2467 "\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)*\\<task\\>\\)" ;15
2468 "\\|\\(\\<generate\\>\\)" ;18
2469 "\\|\\(\\<covergroup\\>\\)" ;16 20
2470 "\\|\\(\\(\\(\\<cover\\>\\s-+\\)\\|\\(\\<assert\\>\\s-+\\)\\)*\\<property\\>\\)" ;17 21
2471 "\\|\\(\\<\\(rand\\)?sequence\\>\\)" ;21 25
2472 "\\|\\(\\<clocking\\>\\)" ;22 27
2473 "\\|\\(\\<`[ou]vm_[a-z_]+_begin\\>\\)" ;28
2474 "\\|\\(\\<`vmm_[a-z_]+_member_begin\\>\\)"
2478 (defconst verilog-end-block-ordered-rry
2479 [ "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
2480 "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)"
2481 "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
2482 "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)"
2483 "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)"
2484 "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)"
2485 "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)"
2486 "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)"
2487 "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)"
2488 "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)"
2489 "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)"
2490 "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)"
2491 "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)"
2494 (defconst verilog-nameable-item-re
2496 (verilog-regexp-words
2499 "join" "join_any" "join_none"
2516 (defconst verilog-declaration-opener
2518 (verilog-regexp-words
2519 `("module" "begin" "task" "function"))))
2521 (defconst verilog-declaration-prefix-re
2523 (verilog-regexp-words
2526 "inout" "input" "output" "ref"
2528 "const" "static" "protected" "local"
2530 "localparam" "parameter" "var"
2534 (defconst verilog-declaration-core-re
2536 (verilog-regexp-words
2538 ;; port direction (by themselves)
2539 "inout" "input" "output"
2540 ;; integer_atom_type
2541 "byte" "shortint" "int" "longint" "integer" "time"
2542 ;; integer_vector_type
2545 "shortreal" "real" "realtime"
2547 "supply0" "supply1" "tri" "triand" "trior" "trireg" "tri0" "tri1" "uwire" "wire" "wand" "wor"
2549 "string" "event" "chandle" "virtual" "enum" "genvar"
2552 "mailbox" "semaphore"
2554 (defconst verilog-declaration-re
2555 (concat "\\(" verilog-declaration-prefix-re "\\s-*\\)?" verilog-declaration-core-re))
2556 (defconst verilog-range-re "\\(\\[[^]]*\\]\\s-*\\)+")
2557 (defconst verilog-optional-signed-re "\\s-*\\(signed\\)?")
2558 (defconst verilog-optional-signed-range-re
2560 "\\s-*\\(\\<\\(reg\\|wire\\)\\>\\s-*\\)?\\(\\<signed\\>\\s-*\\)?\\(" verilog-range-re "\\)?"))
2561 (defconst verilog-macroexp-re "`\\sw+")
2563 (defconst verilog-delay-re "#\\s-*\\(\\([0-9_]+\\('s?[hdxbo][0-9a-fA-F_xz]+\\)?\\)\\|\\(([^()]*)\\)\\|\\(\\sw+\\)\\)")
2564 (defconst verilog-declaration-re-2-no-macro
2565 (concat "\\s-*" verilog-declaration-re
2566 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
2568 (defconst verilog-declaration-re-2-macro
2569 (concat "\\s-*" verilog-declaration-re
2570 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
2571 "\\|\\(" verilog-macroexp-re "\\)"
2573 (defconst verilog-declaration-re-1-macro
2574 (concat "^" verilog-declaration-re-2-macro))
2576 (defconst verilog-declaration-re-1-no-macro (concat "^" verilog-declaration-re-2-no-macro))
2578 (defconst verilog-defun-re
2579 (eval-when-compile (verilog-regexp-words `("macromodule" "module" "class" "program" "interface" "package" "primitive" "config"))))
2580 (defconst verilog-end-defun-re
2581 (eval-when-compile (verilog-regexp-words `("endmodule" "endclass" "endprogram" "endinterface" "endpackage" "endprimitive" "endconfig"))))
2582 (defconst verilog-zero-indent-re
2583 (concat verilog-defun-re "\\|" verilog-end-defun-re))
2584 (defconst verilog-inst-comment-re
2585 (eval-when-compile (verilog-regexp-words `("Outputs" "Inouts" "Inputs" "Interfaces" "Interfaced"))))
2587 (defconst verilog-behavioral-block-beg-re
2588 (eval-when-compile (verilog-regexp-words `("initial" "final" "always" "always_comb" "always_latch" "always_ff"
2589 "function" "task"))))
2590 (defconst verilog-coverpoint-re "\\w+\\s*:\\s*\\(coverpoint\\|cross\\constraint\\)" )
2591 (defconst verilog-in-constraint-re ;; keywords legal in constraint blocks starting a statement/block
2592 (eval-when-compile (verilog-regexp-words `("if" "else" "solve" "foreach"))))
2594 (defconst verilog-indent-re
2596 (verilog-regexp-words
2599 "always" "always_latch" "always_ff" "always_comb"
2601 ; "unique" "priority"
2602 "case" "casex" "casez" "randcase" "endcase"
2604 "clocking" "endclocking"
2605 "config" "endconfig"
2606 "covergroup" "endgroup"
2607 "fork" "join" "join_any" "join_none"
2608 "function" "endfunction"
2610 "generate" "endgenerate"
2612 "interface" "endinterface"
2613 "module" "macromodule" "endmodule"
2614 "package" "endpackage"
2615 "primitive" "endprimitive"
2616 "program" "endprogram"
2617 "property" "endproperty"
2618 "sequence" "randsequence" "endsequence"
2619 "specify" "endspecify"
2626 "`if" "`ifdef" "`ifndef" "`else" "`elsif" "`endif"
2627 "`while" "`endwhile"
2632 "`protect" "`endprotect"
2633 "`switch" "`endswitch"
2637 "`ovm_component_utils_begin"
2638 "`ovm_component_param_utils_begin"
2639 "`ovm_field_utils_begin"
2640 "`ovm_object_utils_begin"
2641 "`ovm_object_param_utils_begin"
2642 "`ovm_sequence_utils_begin"
2643 "`ovm_sequencer_utils_begin"
2645 "`ovm_component_utils_end"
2646 "`ovm_field_utils_end"
2647 "`ovm_object_utils_end"
2648 "`ovm_sequence_utils_end"
2649 "`ovm_sequencer_utils_end"
2651 "`uvm_component_utils_begin"
2652 "`uvm_component_param_utils_begin"
2653 "`uvm_field_utils_begin"
2654 "`uvm_object_utils_begin"
2655 "`uvm_object_param_utils_begin"
2656 "`uvm_sequence_utils_begin"
2657 "`uvm_sequencer_utils_begin"
2659 "`uvm_component_utils_end" ;; Typo in spec, it's not uvm_component_end
2660 "`uvm_field_utils_end"
2661 "`uvm_object_utils_end"
2662 "`uvm_sequence_utils_end"
2663 "`uvm_sequencer_utils_end"
2665 "`vmm_data_member_begin"
2666 "`vmm_env_member_begin"
2667 "`vmm_scenario_member_begin"
2668 "`vmm_subenv_member_begin"
2669 "`vmm_xactor_member_begin"
2671 "`vmm_data_member_end"
2672 "`vmm_env_member_end"
2673 "`vmm_scenario_member_end"
2674 "`vmm_subenv_member_end"
2675 "`vmm_xactor_member_end"
2678 (defconst verilog-defun-level-not-generate-re
2680 (verilog-regexp-words
2681 `( "module" "macromodule" "primitive" "class" "program"
2682 "interface" "package" "config"))))
2684 (defconst verilog-defun-level-re
2686 (verilog-regexp-words
2688 `( "module" "macromodule" "primitive" "class" "program"
2689 "interface" "package" "config")
2690 `( "initial" "final" "always" "always_comb" "always_ff"
2691 "always_latch" "endtask" "endfunction" )))))
2693 (defconst verilog-defun-level-generate-only-re
2695 (verilog-regexp-words
2696 `( "initial" "final" "always" "always_comb" "always_ff"
2697 "always_latch" "endtask" "endfunction" ))))
2699 (defconst verilog-cpp-level-re
2701 (verilog-regexp-words
2703 "endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass"
2705 (defconst verilog-disable-fork-re "\\(disable\\|wait\\)\\s-+fork\\>")
2706 (defconst verilog-extended-case-re "\\(\\(unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
2707 (defconst verilog-extended-complete-re
2708 (concat "\\(\\(\\<extern\\s-+\\|\\<\\(\\<pure\\>\\s-+\\)?virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)\\)"
2709 "\\|\\(\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)\\)"
2710 "\\|\\(\\(\\<import\\>\\s-+\\)?\\(\"DPI-C\"\\s-+\\)?\\(\\<pure\\>\\s-+\\)?\\(function\\>\\|task\\>\\)\\)"
2711 "\\|" verilog-extended-case-re ))
2712 (defconst verilog-basic-complete-re
2714 (verilog-regexp-words
2716 "always" "assign" "always_latch" "always_ff" "always_comb" "constraint"
2717 "import" "initial" "final" "module" "macromodule" "repeat" "randcase" "while"
2718 "if" "for" "forever" "foreach" "else" "parameter" "do" "localparam" "assert"
2720 (defconst verilog-complete-reg
2722 verilog-extended-complete-re "\\|\\(" verilog-basic-complete-re "\\)"))
2724 (defconst verilog-end-statement-re
2725 (concat "\\(" verilog-beg-block-re "\\)\\|\\("
2726 verilog-end-block-re "\\)"))
2728 (defconst verilog-endcase-re
2729 (concat verilog-extended-case-re "\\|"
2734 (defconst verilog-exclude-str-start "/* -----\\/----- EXCLUDED -----\\/-----"
2735 "String used to mark beginning of excluded text.")
2736 (defconst verilog-exclude-str-end " -----/\\----- EXCLUDED -----/\\----- */"
2737 "String used to mark end of excluded text.")
2738 (defconst verilog-preprocessor-re
2740 (verilog-regexp-words
2742 "`define" "`include" "`ifdef" "`ifndef" "`if" "`endif" "`else"
2745 (defconst verilog-keywords
2746 '( "`case" "`default" "`define" "`else" "`endfor" "`endif"
2747 "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
2748 "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
2749 "`time_scale" "`undef" "`while"
2751 "after" "alias" "always" "always_comb" "always_ff" "always_latch" "and"
2752 "assert" "assign" "assume" "automatic" "before" "begin" "bind"
2753 "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte"
2754 "case" "casex" "casez" "cell" "chandle" "class" "clocking" "cmos"
2755 "config" "const" "constraint" "context" "continue" "cover"
2756 "covergroup" "coverpoint" "cross" "deassign" "default" "defparam"
2757 "design" "disable" "dist" "do" "edge" "else" "end" "endcase"
2758 "endclass" "endclocking" "endconfig" "endfunction" "endgenerate"
2759 "endgroup" "endinterface" "endmodule" "endpackage" "endprimitive"
2760 "endprogram" "endproperty" "endspecify" "endsequence" "endtable"
2761 "endtask" "enum" "event" "expect" "export" "extends" "extern"
2762 "final" "first_match" "for" "force" "foreach" "forever" "fork"
2763 "forkjoin" "function" "generate" "genvar" "highz0" "highz1" "if"
2764 "iff" "ifnone" "ignore_bins" "illegal_bins" "import" "incdir"
2765 "include" "initial" "inout" "input" "inside" "instance" "int"
2766 "integer" "interface" "intersect" "join" "join_any" "join_none"
2767 "large" "liblist" "library" "local" "localparam" "logic"
2768 "longint" "macromodule" "mailbox" "matches" "medium" "modport" "module"
2769 "nand" "negedge" "new" "nmos" "nor" "noshowcancelled" "not"
2770 "notif0" "notif1" "null" "or" "output" "package" "packed"
2771 "parameter" "pmos" "posedge" "primitive" "priority" "program"
2772 "property" "protected" "pull0" "pull1" "pulldown" "pullup"
2773 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
2774 "randcase" "randsequence" "rcmos" "real" "realtime" "ref" "reg"
2775 "release" "repeat" "return" "rnmos" "rpmos" "rtran" "rtranif0"
2776 "rtranif1" "scalared" "semaphore" "sequence" "shortint" "shortreal"
2777 "showcancelled" "signed" "small" "solve" "specify" "specparam"
2778 "static" "string" "strong0" "strong1" "struct" "super" "supply0"
2779 "supply1" "table" "tagged" "task" "this" "throughout" "time"
2780 "timeprecision" "timeunit" "tran" "tranif0" "tranif1" "tri"
2781 "tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union"
2782 "unique" "unsigned" "use" "uwire" "var" "vectored" "virtual" "void"
2783 "wait" "wait_order" "wand" "weak0" "weak1" "while" "wildcard"
2784 "wire" "with" "within" "wor" "xnor" "xor"
2786 "accept_on" "checker" "endchecker" "eventually" "global" "implies"
2787 "let" "nexttime" "reject_on" "restrict" "s_always" "s_eventually"
2788 "s_nexttime" "s_until" "s_until_with" "strong" "sync_accept_on"
2789 "sync_reject_on" "unique0" "until" "until_with" "untyped" "weak"
2791 "implements" "interconnect" "nettype" "soft"
2793 "List of Verilog keywords.")
2795 (defconst verilog-comment-start-regexp "//\\|/\\*"
2796 "Dual comment value for `comment-start-regexp'.")
2798 (defvar verilog-mode-syntax-table
2799 (let ((table (make-syntax-table)))
2800 ;; Populate the syntax TABLE.
2801 (modify-syntax-entry ?\\ "\\" table)
2802 (modify-syntax-entry ?+ "." table)
2803 (modify-syntax-entry ?- "." table)
2804 (modify-syntax-entry ?= "." table)
2805 (modify-syntax-entry ?% "." table)
2806 (modify-syntax-entry ?< "." table)
2807 (modify-syntax-entry ?> "." table)
2808 (modify-syntax-entry ?& "." table)
2809 (modify-syntax-entry ?| "." table)
2810 ;; FIXME: This goes against Emacs conventions. Use "_" syntax instead and
2811 ;; then use regexps with things like "\\_<...\\_>".
2812 (modify-syntax-entry ?` "w" table) ;; ` is part of definition symbols in Verilog
2813 (modify-syntax-entry ?_ "w" table)
2814 (modify-syntax-entry ?\' "." table)
2816 ;; Set up TABLE to handle block and line style comments.
2817 (if (featurep 'xemacs)
2819 ;; XEmacs (formerly Lucid) has the best implementation
2820 (modify-syntax-entry ?/ ". 1456" table)
2821 (modify-syntax-entry ?* ". 23" table)
2822 (modify-syntax-entry ?\n "> b" table))
2823 ;; Emacs does things differently, but we can work with it
2824 (modify-syntax-entry ?/ ". 124b" table)
2825 (modify-syntax-entry ?* ". 23" table)
2826 (modify-syntax-entry ?\n "> b" table))
2828 "Syntax table used in Verilog mode buffers.")
2830 (defvar verilog-font-lock-keywords nil
2831 "Default highlighting for Verilog mode.")
2833 (defvar verilog-font-lock-keywords-1 nil
2834 "Subdued level highlighting for Verilog mode.")
2836 (defvar verilog-font-lock-keywords-2 nil
2837 "Medium level highlighting for Verilog mode.
2838 See also `verilog-font-lock-extra-types'.")
2840 (defvar verilog-font-lock-keywords-3 nil
2841 "Gaudy level highlighting for Verilog mode.
2842 See also `verilog-font-lock-extra-types'.")
2844 (defvar verilog-font-lock-translate-off-face
2845 'verilog-font-lock-translate-off-face
2846 "Font to use for translated off regions.")
2847 (defface verilog-font-lock-translate-off-face
2850 (:background "gray90" :italic t ))
2853 (:background "gray10" :italic t ))
2854 (((class grayscale) (background light))
2855 (:foreground "DimGray" :italic t))
2856 (((class grayscale) (background dark))
2857 (:foreground "LightGray" :italic t))
2859 "Font lock mode face used to background highlight translate-off regions."
2860 :group 'font-lock-highlighting-faces)
2862 (defvar verilog-font-lock-p1800-face
2863 'verilog-font-lock-p1800-face
2864 "Font to use for p1800 keywords.")
2865 (defface verilog-font-lock-p1800-face
2868 (:foreground "DarkOrange3" :bold t ))
2871 (:foreground "orange1" :bold t ))
2873 "Font lock mode face used to highlight P1800 keywords."
2874 :group 'font-lock-highlighting-faces)
2876 (defvar verilog-font-lock-ams-face
2877 'verilog-font-lock-ams-face
2878 "Font to use for Analog/Mixed Signal keywords.")
2879 (defface verilog-font-lock-ams-face
2882 (:foreground "Purple" :bold t ))
2885 (:foreground "orange1" :bold t ))
2887 "Font lock mode face used to highlight AMS keywords."
2888 :group 'font-lock-highlighting-faces)
2890 (defvar verilog-font-grouping-keywords-face
2891 'verilog-font-lock-grouping-keywords-face
2892 "Font to use for Verilog Grouping Keywords (such as begin..end).")
2893 (defface verilog-font-lock-grouping-keywords-face
2896 (:foreground "red4" :bold t ))
2899 (:foreground "red4" :bold t ))
2901 "Font lock mode face used to highlight verilog grouping keywords."
2902 :group 'font-lock-highlighting-faces)
2904 (let* ((verilog-type-font-keywords
2908 "and" "bit" "buf" "bufif0" "bufif1" "cmos" "defparam"
2909 "event" "genvar" "inout" "input" "integer" "localparam"
2910 "logic" "mailbox" "nand" "nmos" "not" "notif0" "notif1" "or"
2911 "output" "parameter" "pmos" "pull0" "pull1" "pulldown" "pullup"
2912 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran"
2913 "rtranif0" "rtranif1" "semaphore" "signed" "struct" "supply"
2914 "supply0" "supply1" "time" "tran" "tranif0" "tranif1"
2915 "tri" "tri0" "tri1" "triand" "trior" "trireg" "typedef"
2916 "uwire" "vectored" "wand" "wire" "wor" "xnor" "xor"
2919 (verilog-pragma-keywords
2922 '("surefire" "auto" "synopsys" "rtl_synthesis" "verilint" "leda" "0in"
2925 (verilog-1800-2005-keywords
2928 '("alias" "assert" "assume" "automatic" "before" "bind"
2929 "bins" "binsof" "break" "byte" "cell" "chandle" "class"
2930 "clocking" "config" "const" "constraint" "context" "continue"
2931 "cover" "covergroup" "coverpoint" "cross" "deassign" "design"
2932 "dist" "do" "edge" "endclass" "endclocking" "endconfig"
2933 "endgroup" "endprogram" "endproperty" "endsequence" "enum"
2934 "expect" "export" "extends" "extern" "first_match" "foreach"
2935 "forkjoin" "genvar" "highz0" "highz1" "ifnone" "ignore_bins"
2936 "illegal_bins" "import" "incdir" "include" "inside" "instance"
2937 "int" "intersect" "large" "liblist" "library" "local" "longint"
2938 "matches" "medium" "modport" "new" "noshowcancelled" "null"
2939 "packed" "program" "property" "protected" "pull0" "pull1"
2940 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
2941 "randcase" "randsequence" "ref" "release" "return" "scalared"
2942 "sequence" "shortint" "shortreal" "showcancelled" "small" "solve"
2943 "specparam" "static" "string" "strong0" "strong1" "struct"
2944 "super" "tagged" "this" "throughout" "timeprecision" "timeunit"
2945 "type" "union" "unsigned" "use" "var" "virtual" "void"
2946 "wait_order" "weak0" "weak1" "wildcard" "with" "within"
2949 (verilog-1800-2009-keywords
2952 '("accept_on" "checker" "endchecker" "eventually" "global"
2953 "implies" "let" "nexttime" "reject_on" "restrict" "s_always"
2954 "s_eventually" "s_nexttime" "s_until" "s_until_with" "strong"
2955 "sync_accept_on" "sync_reject_on" "unique0" "until"
2956 "until_with" "untyped" "weak" ) nil )))
2958 (verilog-1800-2012-keywords
2961 '("implements" "interconnect" "nettype" "soft" ) nil )))
2963 (verilog-ams-keywords
2966 '("above" "abs" "absdelay" "acos" "acosh" "ac_stim"
2967 "aliasparam" "analog" "analysis" "asin" "asinh" "atan" "atan2" "atanh"
2968 "branch" "ceil" "connectmodule" "connectrules" "cos" "cosh" "ddt"
2969 "ddx" "discipline" "driver_update" "enddiscipline" "endconnectrules"
2970 "endnature" "endparamset" "exclude" "exp" "final_step" "flicker_noise"
2971 "floor" "flow" "from" "ground" "hypot" "idt" "idtmod" "inf"
2972 "initial_step" "laplace_nd" "laplace_np" "laplace_zd" "laplace_zp"
2973 "last_crossing" "limexp" "ln" "log" "max" "min" "nature"
2974 "net_resolution" "noise_table" "paramset" "potential" "pow" "sin"
2975 "sinh" "slew" "sqrt" "tan" "tanh" "timer" "transition" "white_noise"
2976 "wreal" "zi_nd" "zi_np" "zi_zd" ) nil )))
2978 (verilog-font-keywords
2982 "assign" "case" "casex" "casez" "randcase" "deassign"
2983 "default" "disable" "else" "endcase" "endfunction"
2984 "endgenerate" "endinterface" "endmodule" "endprimitive"
2985 "endspecify" "endtable" "endtask" "final" "for" "force" "return" "break"
2986 "continue" "forever" "fork" "function" "generate" "if" "iff" "initial"
2987 "interface" "join" "join_any" "join_none" "macromodule" "module" "negedge"
2988 "package" "endpackage" "always" "always_comb" "always_ff"
2989 "always_latch" "posedge" "primitive" "priority" "release"
2990 "repeat" "specify" "table" "task" "unique" "wait" "while"
2991 "class" "program" "endclass" "endprogram"
2994 (verilog-font-grouping-keywords
2997 '( "begin" "end" ) nil ))))
2999 (setq verilog-font-lock-keywords
3001 ;; Fontify all builtin keywords
3002 (concat "\\<\\(" verilog-font-keywords "\\|"
3003 ;; And user/system tasks and functions
3004 "\\$[a-zA-Z][a-zA-Z0-9_\\$]*"
3006 ;; Fontify all types
3007 (if verilog-highlight-grouping-keywords
3008 (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
3009 'verilog-font-lock-ams-face)
3010 (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
3011 'font-lock-type-face))
3012 (cons (concat "\\<\\(" verilog-type-font-keywords "\\)\\>")
3013 'font-lock-type-face)
3014 ;; Fontify IEEE-1800-2005 keywords appropriately
3015 (if verilog-highlight-p1800-keywords
3016 (cons (concat "\\<\\(" verilog-1800-2005-keywords "\\)\\>")
3017 'verilog-font-lock-p1800-face)
3018 (cons (concat "\\<\\(" verilog-1800-2005-keywords "\\)\\>")
3019 'font-lock-type-face))
3020 ;; Fontify IEEE-1800-2009 keywords appropriately
3021 (if verilog-highlight-p1800-keywords
3022 (cons (concat "\\<\\(" verilog-1800-2009-keywords "\\)\\>")
3023 'verilog-font-lock-p1800-face)
3024 (cons (concat "\\<\\(" verilog-1800-2009-keywords "\\)\\>")
3025 'font-lock-type-face))
3026 ;; Fontify IEEE-1800-2012 keywords appropriately
3027 (if verilog-highlight-p1800-keywords
3028 (cons (concat "\\<\\(" verilog-1800-2012-keywords "\\)\\>")
3029 'verilog-font-lock-p1800-face)
3030 (cons (concat "\\<\\(" verilog-1800-2012-keywords "\\)\\>")
3031 'font-lock-type-face))
3032 ;; Fontify Verilog-AMS keywords
3033 (cons (concat "\\<\\(" verilog-ams-keywords "\\)\\>")
3034 'verilog-font-lock-ams-face)))
3036 (setq verilog-font-lock-keywords-1
3037 (append verilog-font-lock-keywords
3039 ;; Fontify module definitions
3041 "\\<\\(\\(macro\\)?module\\|primitive\\|class\\|program\\|interface\\|package\\|task\\)\\>\\s-*\\(\\sw+\\)"
3042 '(1 font-lock-keyword-face)
3043 '(3 font-lock-function-name-face 'prepend))
3044 ;; Fontify function definitions
3046 (concat "\\<function\\>\\s-+\\(integer\\|real\\(time\\)?\\|time\\)\\s-+\\(\\sw+\\)" )
3047 '(1 font-lock-keyword-face)
3048 '(3 font-lock-constant-face prepend))
3049 '("\\<function\\>\\s-+\\(\\[[^]]+\\]\\)\\s-+\\(\\sw+\\)"
3050 (1 font-lock-keyword-face)
3051 (2 font-lock-constant-face append))
3052 '("\\<function\\>\\s-+\\(\\sw+\\)"
3053 1 'font-lock-constant-face append))))
3055 (setq verilog-font-lock-keywords-2
3056 (append verilog-font-lock-keywords-1
3059 (concat "\\(//\\s-*\\(" verilog-pragma-keywords "\\)\\s-.*\\)")
3060 ;; Fontify escaped names
3061 '("\\(\\\\\\S-*\\s-\\)" 0 font-lock-function-name-face)
3062 ;; Fontify macro definitions/ uses
3063 '("`\\s-*[A-Za-z][A-Za-z0-9_]*" 0 (if (boundp 'font-lock-preprocessor-face)
3064 'font-lock-preprocessor-face
3065 'font-lock-type-face))
3066 ;; Fontify delays/numbers
3067 '("\\(@\\)\\|\\(#\\s-*\\(\\(\[0-9_.\]+\\('s?[hdxbo][0-9a-fA-F_xz]*\\)?\\)\\|\\(([^()]+)\\|\\sw+\\)\\)\\)"
3068 0 font-lock-type-face append)
3069 ;; Fontify instantiation names
3070 '("\\([A-Za-z][A-Za-z0-9_]*\\)\\s-*(" 1 font-lock-function-name-face)
3073 (setq verilog-font-lock-keywords-3
3074 (append verilog-font-lock-keywords-2
3075 (when verilog-highlight-translate-off
3077 ;; Fontify things in translate off regions
3078 '(verilog-match-translate-off
3079 (0 'verilog-font-lock-translate-off-face prepend))
3083 ;; Buffer state preservation
3085 (defmacro verilog-save-buffer-state (&rest body)
3086 "Execute BODY forms, saving state around insignificant change.
3087 Changes in text properties like `face' or `syntax-table' are
3088 considered insignificant. This macro allows text properties to
3089 be changed, even in a read-only buffer.
3091 A change is considered significant if it affects the buffer text
3092 in any way that isn't completely restored again. Any
3093 user-visible changes to the buffer must not be within a
3094 `verilog-save-buffer-state'."
3095 ;; From c-save-buffer-state
3096 `(let* ((modified (buffer-modified-p))
3097 (buffer-undo-list t)
3098 (inhibit-read-only t)
3099 (inhibit-point-motion-hooks t)
3100 (verilog-no-change-functions t)
3101 before-change-functions
3102 after-change-functions
3104 buffer-file-name ; Prevent primitives checking
3105 buffer-file-truename) ; for file modification
3110 (set-buffer-modified-p nil)))))
3112 (defmacro verilog-save-no-change-functions (&rest body)
3113 "Execute BODY forms, disabling all change hooks in BODY.
3114 For insignificant changes, see instead `verilog-save-buffer-state'."
3115 `(let* ((inhibit-point-motion-hooks t)
3116 (verilog-no-change-functions t)
3117 before-change-functions
3118 after-change-functions)
3121 (defvar verilog-save-font-mod-hooked nil
3122 "Local variable when inside a `verilog-save-font-mods' block.")
3123 (make-variable-buffer-local 'verilog-save-font-mod-hooked)
3125 (defmacro verilog-save-font-mods (&rest body)
3126 "Execute BODY forms, disabling text modifications to allow performing BODY.
3127 Includes temporary disabling of `font-lock' to restore the buffer
3128 to full text form for parsing. Additional actions may be specified with
3129 `verilog-before-save-font-hook' and `verilog-after-save-font-hook'."
3130 ;; Before version 20, match-string with font-lock returns a
3131 ;; vector that is not equal to the string. IE if on "input"
3132 ;; nil==(equal "input" (progn (looking-at "input") (match-string 0)))
3133 `(let* ((hooked (unless verilog-save-font-mod-hooked
3134 (verilog-run-hooks 'verilog-before-save-font-hook)
3136 (verilog-save-font-mod-hooked t)
3137 (fontlocked (when (and (boundp 'font-lock-mode) font-lock-mode)
3143 (when fontlocked (font-lock-mode t))
3144 (when hooked (verilog-run-hooks 'verilog-after-save-font-hook)))))
3147 ;; Comment detection and caching
3149 (defvar verilog-scan-cache-preserving nil
3150 "If true, the specified buffer's comment properties are static.
3151 Buffer changes will be ignored. See `verilog-inside-comment-or-string-p'
3152 and `verilog-scan'.")
3154 (defvar verilog-scan-cache-tick nil
3155 "Modification tick at which `verilog-scan' was last completed.")
3156 (make-variable-buffer-local 'verilog-scan-cache-tick)
3158 (defun verilog-scan-cache-flush ()
3159 "Flush the `verilog-scan' cache."
3160 (setq verilog-scan-cache-tick nil))
3162 (defun verilog-scan-cache-ok-p ()
3163 "Return t if the scan cache is up to date."
3164 (or (and verilog-scan-cache-preserving
3165 (eq verilog-scan-cache-preserving (current-buffer))
3166 verilog-scan-cache-tick)
3167 (equal verilog-scan-cache-tick (buffer-chars-modified-tick))))
3169 (defmacro verilog-save-scan-cache (&rest body)
3170 "Execute the BODY forms, allowing scan cache preservation within BODY.
3171 This requires that insertions must use `verilog-insert'."
3172 ;; If the buffer is out of date, trash it, as we'll not check later the tick
3173 ;; Note this must work properly if there's multiple layers of calls
3174 ;; to verilog-save-scan-cache even with differing ticks.
3176 (unless (verilog-scan-cache-ok-p) ;; Must be before let
3177 (setq verilog-scan-cache-tick nil))
3178 (let* ((verilog-scan-cache-preserving (current-buffer)))
3181 (defun verilog-scan-region (beg end)
3182 "Parse between BEG and END for `verilog-inside-comment-or-string-p'.
3183 This creates v-cmts properties where comments are in force."
3184 ;; Why properties and not overlays? Overlays have much slower non O(1)
3186 ;; This function is warm - called on every verilog-insert
3189 (verilog-save-buffer-state
3192 (while (< (point) end)
3193 (cond ((looking-at "//")
3195 (or (search-forward "\n" end t)
3197 ;; "1+": The leading // or /* itself isn't considered as
3198 ;; being "inside" the comment, so that a (search-backward)
3199 ;; that lands at the start of the // won't mis-indicate
3200 ;; it's inside a comment. Also otherwise it would be
3201 ;; hard to find a commented out /*AS*/ vs one that isn't
3202 (put-text-property (1+ pt) (point) 'v-cmts t))
3203 ((looking-at "/\\*")
3205 (or (search-forward "*/" end t)
3206 ;; No error - let later code indicate it so we can
3207 ;; use inside functions on-the-fly
3208 ;;(error "%s: Unmatched /* */, at char %d"
3209 ;; (verilog-point-text) (point))
3211 (put-text-property (1+ pt) (point) 'v-cmts t))
3214 (or (re-search-forward "[^\\]\"" end t) ;; don't forward-char first, since we look for a non backslash first
3215 ;; No error - let later code indicate it so we can
3217 (put-text-property (1+ pt) (point) 'v-cmts t))
3220 (if (re-search-forward "[/\"]" end t)
3222 (goto-char end))))))))))
3224 (defun verilog-scan ()
3225 "Parse the buffer, marking all comments with properties.
3226 Also assumes any text inserted since `verilog-scan-cache-tick'
3227 either is ok to parse as a non-comment, or `verilog-insert' was used."
3228 ;; See also `verilog-scan-debug' and `verilog-scan-and-debug'
3229 (unless (verilog-scan-cache-ok-p)
3231 (verilog-save-buffer-state
3233 (message "Scanning %s cache=%s cachetick=%S tick=%S" (current-buffer)
3234 verilog-scan-cache-preserving verilog-scan-cache-tick
3235 (buffer-chars-modified-tick)))
3236 (remove-text-properties (point-min) (point-max) '(v-cmts nil))
3237 (verilog-scan-region (point-min) (point-max))
3238 (setq verilog-scan-cache-tick (buffer-chars-modified-tick))
3239 (when verilog-debug (message "Scanning... done"))))))
3241 (defun verilog-scan-debug ()
3242 "For debugging, show with display face results of `verilog-scan'."
3244 ;;(if dbg (setq dbg (concat dbg (format "verilog-scan-debug\n"))))
3246 (goto-char (point-min))
3247 (remove-text-properties (point-min) (point-max) '(face nil))
3249 (cond ((get-text-property (point) 'v-cmts)
3250 (put-text-property (point) (1+ (point)) `face 'underline)
3251 ;;(if dbg (setq dbg (concat dbg (format " v-cmts at %S\n" (point)))))
3254 (goto-char (or (next-property-change (point)) (point-max))))))))
3256 (defun verilog-scan-and-debug ()
3257 "For debugging, run `verilog-scan' and `verilog-scan-debug'."
3258 (let (verilog-scan-cache-preserving
3259 verilog-scan-cache-tick)
3260 (goto-char (point-min))
3262 (verilog-scan-debug)))
3264 (defun verilog-inside-comment-or-string-p (&optional pos)
3265 "Check if optional point POS is inside a comment.
3266 This may require a slow pre-parse of the buffer with `verilog-scan'
3267 to establish comment properties on all text."
3268 ;; This function is very hot
3271 (and (>= pos (point-min))
3272 (get-text-property pos 'v-cmts))
3273 (get-text-property (point) 'v-cmts)))
3275 (defun verilog-insert (&rest stuff)
3276 "Insert STUFF arguments, tracking for `verilog-inside-comment-or-string-p'.
3277 Any insert that includes a comment must have the entire comment
3278 inserted using a single call to `verilog-insert'."
3281 (insert (car stuff))
3282 (setq stuff (cdr stuff)))
3283 (verilog-scan-region pt (point))))
3287 (defun verilog-declaration-end ()
3288 (search-forward ";"))
3290 (defun verilog-point-text (&optional pointnum)
3291 "Return text describing where POINTNUM or current point is (for errors).
3292 Use filename, if current buffer being edited shorten to just buffer name."
3293 (concat (or (and (equal (window-buffer) (current-buffer))
3297 ":" (int-to-string (1+ (count-lines (point-min) (or pointnum (point)))))))
3299 (defun electric-verilog-backward-sexp ()
3300 "Move backward over one balanced expression."
3302 ;; before that see if we are in a comment
3303 (verilog-backward-sexp))
3305 (defun electric-verilog-forward-sexp ()
3306 "Move forward over one balanced expression."
3308 ;; before that see if we are in a comment
3309 (verilog-forward-sexp))
3311 ;;;used by hs-minor-mode
3312 (defun verilog-forward-sexp-function (arg)
3314 (verilog-backward-sexp)
3315 (verilog-forward-sexp)))
3318 (defun verilog-backward-sexp ()
3323 (if (not (looking-at "\\<"))
3326 ((verilog-skip-backward-comment-or-string))
3327 ((looking-at "\\<else\\>")
3329 verilog-end-block-re
3330 "\\|\\(\\<else\\>\\)"
3331 "\\|\\(\\<if\\>\\)"))
3332 (while (and (not found)
3333 (verilog-re-search-backward reg nil 'move))
3335 ((match-end 1) ; matched verilog-end-block-re
3336 ;; try to leap back to matching outward block by striding across
3337 ;; indent level changing tokens then immediately
3338 ;; previous line governs indentation.
3339 (verilog-leap-to-head))
3340 ((match-end 2) ; else, we're in deep
3341 (setq elsec (1+ elsec)))
3342 ((match-end 3) ; found it
3343 (setq elsec (1- elsec))
3345 ;; Now previous line describes syntax
3346 (setq found 't))))))
3347 ((looking-at verilog-end-block-re)
3348 (verilog-leap-to-head))
3349 ((looking-at "\\(endmodule\\>\\)\\|\\(\\<endprimitive\\>\\)\\|\\(\\<endclass\\>\\)\\|\\(\\<endprogram\\>\\)\\|\\(\\<endinterface\\>\\)\\|\\(\\<endpackage\\>\\)")
3352 (verilog-re-search-backward "\\<\\(macro\\)?module\\>" nil 'move))
3354 (verilog-re-search-backward "\\<primitive\\>" nil 'move))
3356 (verilog-re-search-backward "\\<class\\>" nil 'move))
3358 (verilog-re-search-backward "\\<program\\>" nil 'move))
3360 (verilog-re-search-backward "\\<interface\\>" nil 'move))
3362 (verilog-re-search-backward "\\<package\\>" nil 'move))
3365 (backward-sexp 1))))
3370 (defun verilog-forward-sexp ()
3375 (if (not (looking-at "\\<"))
3378 ((verilog-skip-forward-comment-or-string)
3379 (verilog-forward-syntactic-ws))
3380 ((looking-at verilog-beg-block-re-ordered)
3383 ;; Search forward for matching end
3384 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
3386 ;; Search forward for matching endcase
3387 (setq reg "\\(\\<randcase\\>\\|\\(\\<unique0?\\>\\s-+\\|\\<priority\\>\\s-+\\)?\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )
3388 (setq md 3) ;; ender is third item in regexp
3391 ;; might be "disable fork" or "wait fork"
3395 (looking-at verilog-disable-fork-re)
3396 (and (looking-at "fork")
3398 (setq here (point)) ;; sometimes a fork is just a fork
3400 (looking-at verilog-disable-fork-re))))
3401 (progn ;; it is a disable fork; ignore it
3402 (goto-char (match-end 0))
3405 (progn ;; it is a nice simple fork
3406 (goto-char here) ;; return from looking for "disable fork"
3407 ;; Search forward for matching join
3408 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))))
3410 ;; Search forward for matching endclass
3411 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
3414 ;; Search forward for matching endtable
3415 (setq reg "\\<endtable\\>" )
3418 ;; Search forward for matching endspecify
3419 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
3421 ;; Search forward for matching endfunction
3422 (setq reg "\\<endfunction\\>" )
3425 ;; Search forward for matching endfunction
3426 (setq reg "\\<endfunction\\>" )
3429 ;; Search forward for matching endtask
3430 (setq reg "\\<endtask\\>" )
3433 ;; Search forward for matching endtask
3434 (setq reg "\\<endtask\\>" )
3437 ;; Search forward for matching endgenerate
3438 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
3440 ;; Search forward for matching endgroup
3441 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
3443 ;; Search forward for matching endproperty
3444 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
3446 ;; Search forward for matching endsequence
3447 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" )
3448 (setq md 3)) ; 3 to get to endsequence in the reg above
3450 ;; Search forward for matching endclocking
3451 (setq reg "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)" )))
3458 (while (verilog-re-search-forward reg nil 'move)
3460 ((match-end md) ; a closer in regular expression, so we are climbing out
3461 (setq depth (1- depth))
3462 (if (= 0 depth) ; we are out!
3464 ((match-end 1) ; an opener in the r-e, so we are in deeper now
3465 (setq here (point)) ; remember where we started
3466 (goto-char (match-beginning 1))
3469 (looking-at verilog-disable-fork-re)
3470 (and (looking-at "fork")
3473 (looking-at verilog-disable-fork-re))))
3474 (progn ;; it is a disable fork; another false alarm
3475 (goto-char (match-end 0)))
3476 (progn ;; it is a simple fork (or has nothing to do with fork)
3478 (setq depth (1+ depth))))))))))
3479 (if (verilog-re-search-forward reg nil 'move)
3480 (throw 'skip 1))))))
3482 ((looking-at (concat
3483 "\\(\\<\\(macro\\)?module\\>\\)\\|"
3484 "\\(\\<primitive\\>\\)\\|"
3485 "\\(\\<class\\>\\)\\|"
3486 "\\(\\<program\\>\\)\\|"
3487 "\\(\\<interface\\>\\)\\|"
3488 "\\(\\<package\\>\\)"))
3491 (verilog-re-search-forward "\\<endmodule\\>" nil 'move))
3493 (verilog-re-search-forward "\\<endprimitive\\>" nil 'move))
3495 (verilog-re-search-forward "\\<endclass\\>" nil 'move))
3497 (verilog-re-search-forward "\\<endprogram\\>" nil 'move))
3499 (verilog-re-search-forward "\\<endinterface\\>" nil 'move))
3501 (verilog-re-search-forward "\\<endpackage\\>" nil 'move))
3504 (if (= (following-char) ?\) )
3506 (forward-sexp 1)))))
3509 (if (= (following-char) ?\) )
3511 (forward-sexp 1))))))
3513 (defun verilog-declaration-beg ()
3514 (verilog-re-search-backward verilog-declaration-re (bobp) t))
3520 (defvar verilog-which-tool 1)
3522 (define-derived-mode verilog-mode prog-mode "Verilog"
3523 "Major mode for editing Verilog code.
3524 \\<verilog-mode-map>
3525 See \\[describe-function] verilog-auto (\\[verilog-auto]) for details on how
3526 AUTOs can improve coding efficiency.
3528 Use \\[verilog-faq] for a pointer to frequently asked questions.
3530 NEWLINE, TAB indents for Verilog code.
3531 Delete converts tabs to spaces as it moves back.
3533 Supports highlighting.
3535 Turning on Verilog mode calls the value of the variable `verilog-mode-hook'
3536 with no args, if that value is non-nil.
3538 Variables controlling indentation/edit style:
3540 variable `verilog-indent-level' (default 3)
3541 Indentation of Verilog statements with respect to containing block.
3542 `verilog-indent-level-module' (default 3)
3543 Absolute indentation of Module level Verilog statements.
3544 Set to 0 to get initial and always statements lined up
3545 on the left side of your screen.
3546 `verilog-indent-level-declaration' (default 3)
3547 Indentation of declarations with respect to containing block.
3548 Set to 0 to get them list right under containing block.
3549 `verilog-indent-level-behavioral' (default 3)
3550 Indentation of first begin in a task or function block
3551 Set to 0 to get such code to lined up underneath the task or
3553 `verilog-indent-level-directive' (default 1)
3554 Indentation of `ifdef/`endif blocks.
3555 `verilog-cexp-indent' (default 1)
3556 Indentation of Verilog statements broken across lines i.e.:
3559 `verilog-case-indent' (default 2)
3560 Indentation for case statements.
3561 `verilog-auto-newline' (default nil)
3562 Non-nil means automatically newline after semicolons and the punctuation
3564 `verilog-auto-indent-on-newline' (default t)
3565 Non-nil means automatically indent line after newline.
3566 `verilog-tab-always-indent' (default t)
3567 Non-nil means TAB in Verilog mode should always reindent the current line,
3568 regardless of where in the line point is when the TAB command is used.
3569 `verilog-indent-begin-after-if' (default t)
3570 Non-nil means to indent begin statements following a preceding
3571 if, else, while, for and repeat statements, if any. Otherwise,
3572 the begin is lined up with the preceding token. If t, you get:
3574 begin // amount of indent based on `verilog-cexp-indent'
3578 `verilog-auto-endcomments' (default t)
3579 Non-nil means a comment /* ... */ is set after the ends which ends
3580 cases, tasks, functions and modules.
3581 The type and name of the object will be set between the braces.
3582 `verilog-minimum-comment-distance' (default 10)
3583 Minimum distance (in lines) between begin and end required before a comment
3584 will be inserted. Setting this variable to zero results in every
3585 end acquiring a comment; the default avoids too many redundant
3586 comments in tight quarters.
3587 `verilog-auto-lineup' (default 'declarations)
3588 List of contexts where auto lineup of code should be done.
3590 Variables controlling other actions:
3592 `verilog-linter' (default surelint)
3593 Unix program to call to run the lint checker. This is the default
3594 command for \\[compile-command] and \\[verilog-auto-save-compile].
3596 See \\[customize] for the complete list of variables.
3598 AUTO expansion functions are, in part:
3600 \\[verilog-auto] Expand AUTO statements.
3601 \\[verilog-delete-auto] Remove the AUTOs.
3602 \\[verilog-inject-auto] Insert AUTOs for the first time.
3604 Some other functions are:
3606 \\[verilog-complete-word] Complete word with appropriate possibilities.
3607 \\[verilog-mark-defun] Mark function.
3608 \\[verilog-beg-of-defun] Move to beginning of current function.
3609 \\[verilog-end-of-defun] Move to end of current function.
3610 \\[verilog-label-be] Label matching begin ... end, fork ... join, etc statements.
3612 \\[verilog-comment-region] Put marked area in a comment.
3613 \\[verilog-uncomment-region] Uncomment an area commented with \\[verilog-comment-region].
3614 \\[verilog-insert-block] Insert begin ... end.
3615 \\[verilog-star-comment] Insert /* ... */.
3617 \\[verilog-sk-always] Insert an always @(AS) begin .. end block.
3618 \\[verilog-sk-begin] Insert a begin .. end block.
3619 \\[verilog-sk-case] Insert a case block, prompting for details.
3620 \\[verilog-sk-for] Insert a for (...) begin .. end block, prompting for details.
3621 \\[verilog-sk-generate] Insert a generate .. endgenerate block.
3622 \\[verilog-sk-header] Insert a header block at the top of file.
3623 \\[verilog-sk-initial] Insert an initial begin .. end block.
3624 \\[verilog-sk-fork] Insert a fork begin .. end .. join block.
3625 \\[verilog-sk-module] Insert a module .. (/*AUTOARG*/);.. endmodule block.
3626 \\[verilog-sk-ovm-class] Insert an OVM Class block.
3627 \\[verilog-sk-uvm-object] Insert an UVM Object block.
3628 \\[verilog-sk-uvm-component] Insert an UVM Component block.
3629 \\[verilog-sk-primitive] Insert a primitive .. (.. );.. endprimitive block.
3630 \\[verilog-sk-repeat] Insert a repeat (..) begin .. end block.
3631 \\[verilog-sk-specify] Insert a specify .. endspecify block.
3632 \\[verilog-sk-task] Insert a task .. begin .. end endtask block.
3633 \\[verilog-sk-while] Insert a while (...) begin .. end block, prompting for details.
3634 \\[verilog-sk-casex] Insert a casex (...) item: begin.. end endcase block, prompting for details.
3635 \\[verilog-sk-casez] Insert a casez (...) item: begin.. end endcase block, prompting for details.
3636 \\[verilog-sk-if] Insert an if (..) begin .. end block.
3637 \\[verilog-sk-else-if] Insert an else if (..) begin .. end block.
3638 \\[verilog-sk-comment] Insert a comment block.
3639 \\[verilog-sk-assign] Insert an assign .. = ..; statement.
3640 \\[verilog-sk-function] Insert a function .. begin .. end endfunction block.
3641 \\[verilog-sk-input] Insert an input declaration, prompting for details.
3642 \\[verilog-sk-output] Insert an output declaration, prompting for details.
3643 \\[verilog-sk-state-machine] Insert a state machine definition, prompting for details.
3644 \\[verilog-sk-inout] Insert an inout declaration, prompting for details.
3645 \\[verilog-sk-wire] Insert a wire declaration, prompting for details.
3646 \\[verilog-sk-reg] Insert a register declaration, prompting for details.
3647 \\[verilog-sk-define-signal] Define signal under point as a register at the top of the module.
3649 All key bindings can be seen in a Verilog-buffer with \\[describe-bindings].
3650 Key bindings specific to `verilog-mode-map' are:
3652 \\{verilog-mode-map}"
3653 :abbrev-table verilog-mode-abbrev-table
3654 (set (make-local-variable 'beginning-of-defun-function)
3655 'verilog-beg-of-defun)
3656 (set (make-local-variable 'end-of-defun-function)
3657 'verilog-end-of-defun)
3658 (set-syntax-table verilog-mode-syntax-table)
3659 (set (make-local-variable 'indent-line-function)
3660 #'verilog-indent-line-relative)
3661 (set (make-local-variable 'comment-indent-function) 'verilog-comment-indent)
3662 (set (make-local-variable 'parse-sexp-ignore-comments) nil)
3663 (set (make-local-variable 'comment-start) "// ")
3664 (set (make-local-variable 'comment-end) "")
3665 (set (make-local-variable 'comment-start-skip) "/\\*+ *\\|// *")
3666 (set (make-local-variable 'comment-multi-line) nil)
3667 ;; Set up for compilation
3668 (setq verilog-which-tool 1)
3669 (setq verilog-tool 'verilog-linter)
3670 (verilog-set-compile-command)
3671 (when (boundp 'hack-local-variables-hook) ;; Also modify any file-local-variables
3672 (add-hook 'hack-local-variables-hook 'verilog-modify-compile-command t))
3675 (when (featurep 'xemacs)
3676 (easy-menu-add verilog-stmt-menu)
3677 (easy-menu-add verilog-menu)
3678 (setq mode-popup-menu (cons "Verilog Mode" verilog-stmt-menu)))
3680 ;; Stuff for GNU Emacs
3681 (set (make-local-variable 'font-lock-defaults)
3682 `((verilog-font-lock-keywords
3683 verilog-font-lock-keywords-1
3684 verilog-font-lock-keywords-2
3685 verilog-font-lock-keywords-3)
3687 ,(if (functionp 'syntax-ppss)
3688 ;; verilog-beg-of-defun uses syntax-ppss, and syntax-ppss uses
3689 ;; font-lock-beginning-of-syntax-function, so
3690 ;; font-lock-beginning-of-syntax-function, can't use
3691 ;; verilog-beg-of-defun.
3693 'verilog-beg-of-defun)))
3694 ;;------------------------------------------------------------
3695 ;; now hook in 'verilog-highlight-include-files (eldo-mode.el&spice-mode.el)
3696 ;; all buffer local:
3697 (unless noninteractive ;; Else can't see the result, and change hooks are slow
3698 (when (featurep 'xemacs)
3699 (make-local-hook 'font-lock-mode-hook)
3700 (make-local-hook 'font-lock-after-fontify-buffer-hook); doesn't exist in Emacs
3701 (make-local-hook 'after-change-functions))
3702 (add-hook 'font-lock-mode-hook 'verilog-highlight-buffer t t)
3703 (add-hook 'font-lock-after-fontify-buffer-hook 'verilog-highlight-buffer t t) ; not in Emacs
3704 (add-hook 'after-change-functions 'verilog-highlight-region t t))
3706 ;; Tell imenu how to handle Verilog.
3707 (set (make-local-variable 'imenu-generic-expression)
3708 verilog-imenu-generic-expression)
3709 ;; Tell which-func-modes that imenu knows about verilog
3710 (when (and (boundp 'which-func-modes) (listp which-func-modes))
3711 (add-to-list 'which-func-modes 'verilog-mode))
3713 (when (boundp 'hs-special-modes-alist)
3714 (unless (assq 'verilog-mode hs-special-modes-alist)
3715 (setq hs-special-modes-alist
3716 (cons '(verilog-mode-mode "\\<begin\\>" "\\<end\\>" nil
3717 verilog-forward-sexp-function)
3718 hs-special-modes-alist))))
3721 (add-hook 'write-contents-hooks 'verilog-auto-save-check nil 'local)
3722 ;; verilog-mode-hook call added by define-derived-mode
3727 ;; Electric functions
3729 (defun electric-verilog-terminate-line (&optional arg)
3730 "Terminate line and indent next line.
3731 With optional ARG, remove existing end of line comments."
3733 ;; before that see if we are in a comment
3734 (let ((state (save-excursion (verilog-syntax-ppss))))
3736 ((nth 7 state) ; Inside // comment
3739 (delete-horizontal-space)
3744 (beginning-of-line)))
3745 (verilog-indent-line))
3746 ((nth 4 state) ; Inside any comment (hence /**/)
3748 (verilog-more-comment))
3750 ;; First, check if current line should be indented
3752 (delete-horizontal-space)
3754 (skip-chars-forward " \t")
3755 (if (looking-at verilog-auto-end-comment-lines-re)
3756 (let ((indent-str (verilog-indent-line)))
3757 ;; Maybe we should set some endcomments
3758 (if verilog-auto-endcomments
3759 (verilog-set-auto-endcomments indent-str arg))
3761 (delete-horizontal-space)
3768 (delete-horizontal-space)
3770 ;; see if we should line up assignments
3772 (if (or (eq 'all verilog-auto-lineup)
3773 (eq 'assignments verilog-auto-lineup))
3774 (verilog-pretty-expr t "\\(<\\|:\\)?=" ))
3778 (if verilog-auto-indent-on-newline
3779 (verilog-indent-line)))
3783 (defun electric-verilog-terminate-and-indent ()
3784 "Insert a newline and indent for the next statement."
3786 (electric-verilog-terminate-line 1))
3788 (defun electric-verilog-semi ()
3789 "Insert `;' character and reindent the line."
3791 (verilog-insert-last-command-event)
3793 (if (or (verilog-in-comment-or-string-p)
3794 (verilog-in-escaped-name-p))
3798 (verilog-forward-ws&directives)
3799 (verilog-indent-line))
3800 (if (and verilog-auto-newline
3801 (not (verilog-parenthesis-depth)))
3802 (electric-verilog-terminate-line))))
3804 (defun electric-verilog-semi-with-comment ()
3805 "Insert `;' character, reindent the line and indent for comment."
3810 (verilog-indent-line))
3811 (indent-for-comment))
3813 (defun electric-verilog-colon ()
3814 "Insert `:' and do all indentations except line indent on this line."
3816 (verilog-insert-last-command-event)
3817 ;; Do nothing if within string.
3819 (verilog-within-string)
3820 (not (verilog-in-case-region-p)))
3824 (lim (progn (verilog-beg-of-statement) (point))))
3826 (verilog-backward-case-item lim)
3827 (verilog-indent-line)))
3828 ;; (let ((verilog-tab-always-indent nil))
3829 ;; (verilog-indent-line))
3832 ;;(defun electric-verilog-equal ()
3833 ;; "Insert `=', and do indentation if within block."
3835 ;; (verilog-insert-last-command-event)
3836 ;; Could auto line up expressions, but not yet
3837 ;; (if (eq (car (verilog-calculate-indent)) 'block)
3838 ;; (let ((verilog-tab-always-indent nil))
3839 ;; (verilog-indent-command)))
3842 (defun electric-verilog-tick ()
3843 "Insert back-tick, and indent to column 0 if this is a CPP directive."
3845 (verilog-insert-last-command-event)
3847 (if (verilog-in-directive-p)
3848 (verilog-indent-line))))
3850 (defun electric-verilog-tab ()
3851 "Function called when TAB is pressed in Verilog mode."
3853 ;; If verilog-tab-always-indent, indent the beginning of the line.
3855 ;; The region is active, indent it.
3856 ((and (region-active-p)
3857 (not (eq (region-beginning) (region-end))))
3858 (indent-region (region-beginning) (region-end) nil))
3859 ((or verilog-tab-always-indent
3861 (skip-chars-backward " \t")
3863 (let* ((oldpnt (point))
3867 (skip-chars-forward " \t")
3868 (verilog-indent-line)
3869 (back-to-indentation)
3871 (if (< (point) boi-point)
3872 (back-to-indentation)
3873 (cond ((not verilog-tab-to-comment))
3877 (indent-for-comment)
3878 (when (and (eolp) (= oldpnt (point)))
3879 ; kill existing comment
3881 (re-search-forward comment-start-skip oldpnt 'move)
3882 (goto-char (match-beginning 0))
3883 (skip-chars-backward " \t")
3884 (kill-region (point) oldpnt)))))))
3885 (t (progn (insert "\t")))))
3890 ;; Interactive functions
3893 (defun verilog-indent-buffer ()
3894 "Indent-region the entire buffer as Verilog code.
3895 To call this from the command line, see \\[verilog-batch-indent]."
3898 (indent-region (point-min) (point-max) nil))
3900 (defun verilog-insert-block ()
3901 "Insert Verilog begin ... end; block in the code with right indentation."
3903 (verilog-indent-line)
3905 (electric-verilog-terminate-line)
3907 (electric-verilog-terminate-line)
3910 (verilog-indent-line)))
3912 (defun verilog-star-comment ()
3913 "Insert Verilog star comment at point."
3915 (verilog-indent-line)
3923 (defun verilog-insert-1 (fmt max)
3924 "Use format string FMT to insert integers 0 to MAX - 1.
3925 Inserts one integer per line, at the current column. Stops early
3926 if it reaches the end of the buffer."
3927 (let ((col (current-column))
3931 (insert (format fmt n))
3933 ;; Note that this function does not bother to check for lines
3934 ;; shorter than col.
3938 (move-to-column col))))))
3940 (defun verilog-insert-indices (max)
3941 "Insert a set of indices into a rectangle.
3942 The upper left corner is defined by point. Indices begin with 0
3943 and extend to the MAX - 1. If no prefix arg is given, the user
3944 is prompted for a value. The indices are surrounded by square
3945 brackets \[]. For example, the following code with the point
3946 located after the first 'a' gives:
3952 a = b ==> insert-indices ==> a[ 4] = b
3958 (interactive "NMAX: ")
3959 (verilog-insert-1 "[%3d]" max))
3961 (defun verilog-generate-numbers (max)
3962 "Insert a set of generated numbers into a rectangle.
3963 The upper left corner is defined by point. The numbers are padded to three
3964 digits, starting with 000 and extending to (MAX - 1). If no prefix argument
3965 is supplied, then the user is prompted for the MAX number. Consider the
3966 following code fragment:
3972 buf buf ==> generate-numbers ==> buf buf004
3978 (interactive "NMAX: ")
3979 (verilog-insert-1 "%3.3d" max))
3981 (defun verilog-mark-defun ()
3982 "Mark the current Verilog function (or procedure).
3983 This puts the mark at the end, and point at the beginning."
3985 (if (featurep 'xemacs)
3988 (verilog-end-of-defun)
3990 (verilog-beg-of-defun)
3991 (if (fboundp 'zmacs-activate-region)
3992 (zmacs-activate-region)))
3995 (defun verilog-comment-region (start end)
3996 ;; checkdoc-params: (start end)
3997 "Put the region into a Verilog comment.
3998 The comments that are in this area are \"deformed\":
3999 `*)' becomes `!(*' and `}' becomes `!{'.
4000 These deformed comments are returned to normal if you use
4001 \\[verilog-uncomment-region] to undo the commenting.
4003 The commented area starts with `verilog-exclude-str-start', and ends with
4004 `verilog-exclude-str-end'. But if you change these variables,
4005 \\[verilog-uncomment-region] won't recognize the comments."
4008 ;; Insert start and endcomments
4010 (if (and (save-excursion (skip-chars-forward " \t") (eolp))
4011 (not (save-excursion (skip-chars-backward " \t") (bolp))))
4013 (beginning-of-line))
4014 (insert verilog-exclude-str-end)
4019 (insert verilog-exclude-str-start)
4021 ;; Replace end-comments within commented area
4024 (while (re-search-backward "\\*/" start t)
4025 (replace-match "*-/" t t)))
4027 (let ((s+1 (1+ start)))
4028 (while (re-search-backward "/\\*" s+1 t)
4029 (replace-match "/-*" t t))))))
4031 (defun verilog-uncomment-region ()
4032 "Uncomment a commented area; change deformed comments back to normal.
4033 This command does nothing if the pointer is not in a commented
4034 area. See also `verilog-comment-region'."
4037 (let ((start (point))
4039 ;; Find the boundaries of the comment
4041 (setq start (progn (search-backward verilog-exclude-str-start nil t)
4043 (setq end (progn (search-forward verilog-exclude-str-end nil t)
4045 ;; Check if we're really inside a comment
4046 (if (or (equal start (point)) (<= end (point)))
4047 (message "Not standing within commented area.")
4049 ;; Remove endcomment
4052 (let ((pos (point)))
4054 (delete-region pos (1+ (point))))
4055 ;; Change comments back to normal
4057 (while (re-search-backward "\\*-/" start t)
4058 (replace-match "*/" t t)))
4060 (while (re-search-backward "/-\\*" start t)
4061 (replace-match "/*" t t)))
4062 ;; Remove start comment
4065 (let ((pos (point)))
4067 (delete-region pos (1+ (point)))))))))
4069 (defun verilog-beg-of-defun ()
4070 "Move backward to the beginning of the current function or procedure."
4072 (verilog-re-search-backward verilog-defun-re nil 'move))
4074 (defun verilog-beg-of-defun-quick ()
4075 "Move backward to the beginning of the current function or procedure.
4076 Uses `verilog-scan' cache."
4078 (verilog-re-search-backward-quick verilog-defun-re nil 'move))
4080 (defun verilog-end-of-defun ()
4081 "Move forward to the end of the current function or procedure."
4083 (verilog-re-search-forward verilog-end-defun-re nil 'move))
4085 (defun verilog-get-end-of-defun ()
4087 (cond ((verilog-re-search-forward-quick verilog-end-defun-re nil t)
4090 (error "%s: Can't find endmodule" (verilog-point-text))
4093 (defun verilog-label-be ()
4094 "Label matching begin ... end, fork ... join and case ... endcase statements."
4099 (verilog-beg-of-defun)
4102 (verilog-end-of-defun)
4104 (goto-char (marker-position b))
4106 (message "Relabeling module..."))
4108 (> (marker-position e) (point))
4109 (verilog-re-search-forward
4111 "\\<end\\(\\(function\\)\\|\\(task\\)\\|\\(module\\)\\|\\(primitive\\)\\|\\(interface\\)\\|\\(package\\)\\|\\(case\\)\\)?\\>"
4112 "\\|\\(`endif\\)\\|\\(`else\\)")
4114 (goto-char (match-beginning 0))
4115 (let ((indent-str (verilog-indent-line)))
4116 (verilog-set-auto-endcomments indent-str 't)
4118 (delete-horizontal-space))
4120 (if (= 9 (% cnt 10))
4121 (message "%d..." cnt)))
4126 (message "%d lines auto commented" cnt))))
4128 (defun verilog-beg-of-statement ()
4129 "Move backward to beginning of statement."
4131 ;; Move back token by token until we see the end
4132 ;; of some earlier line.
4135 ;; If the current point does not begin a new
4136 ;; statement, as in the character ahead of us is a ';', or SOF
4137 ;; or the string after us unambiguously starts a statement,
4138 ;; or the token before us unambiguously ends a statement,
4139 ;; then move back a token and test again.
4141 ;; stop if beginning of buffer
4143 ;; stop if we find a ;
4144 (= (preceding-char) ?\;)
4145 ;; stop if we see a named coverpoint
4146 (looking-at "\\w+\\W*:\\W*\\(coverpoint\\|cross\\|constraint\\)")
4147 ;; keep going if we are in the middle of a word
4148 (not (or (looking-at "\\<") (forward-word -1)))
4149 ;; stop if we see an assertion (perhaps labeled)
4151 (looking-at "\\(\\<\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(\\<assert\\>\\)")
4155 (verilog-backward-token)
4156 (if (looking-at verilog-label-re)
4159 ;; stop if we see an extended complete reg, perhaps a complete one
4161 (looking-at verilog-complete-reg)
4163 (while (and (looking-at verilog-extended-complete-re)
4164 (progn (setq p (point))
4165 (verilog-backward-token)
4168 ;; stop if we see a complete reg (previous found extended ones)
4169 (looking-at verilog-basic-complete-re)
4170 ;; stop if previous token is an ender
4172 (verilog-backward-token)
4174 (looking-at verilog-end-block-re)
4175 (looking-at verilog-preprocessor-re))))) ;; end of test
4176 (verilog-backward-syntactic-ws)
4177 (verilog-backward-token))
4178 ;; Now point is where the previous line ended.
4179 (verilog-forward-syntactic-ws)))
4181 (defun verilog-beg-of-statement-1 ()
4182 "Move backward to beginning of statement."
4184 (if (verilog-in-comment-p)
4185 (verilog-backward-syntactic-ws))
4188 (while (not (looking-at verilog-complete-reg))
4190 (verilog-backward-syntactic-ws)
4192 (= (preceding-char) ?\;)
4194 (verilog-backward-token)
4195 (looking-at verilog-ends-re)))
4199 (verilog-backward-token))))
4200 (verilog-forward-syntactic-ws)))
4203 ; (not (looking-at verilog-complete-reg))
4205 ; (not (= (preceding-char) ?\;)))
4206 ; (verilog-backward-token)
4207 ; (verilog-backward-syntactic-ws)
4208 ; (setq pt (point)))
4210 ; ;(verilog-forward-syntactic-ws)
4212 (defun verilog-end-of-statement ()
4213 "Move forward to end of current statement."
4217 ((verilog-in-directive-p)
4221 ((looking-at verilog-beg-block-re)
4222 (verilog-forward-sexp))
4224 ((equal (char-after) ?\})
4227 ;; Skip to end of statement
4228 ((condition-case nil
4233 (verilog-skip-forward-comment-or-string)
4236 (cond ((looking-at "[ \t]*;")
4237 (skip-chars-forward "^;")
4239 (throw 'found (point)))
4242 (looking-at verilog-beg-block-re))
4243 (goto-char (match-beginning 0))
4245 ((looking-at "[ \t]*)")
4246 (throw 'found (point)))
4248 (throw 'found (point)))
4254 ;; Skip a whole block
4257 (verilog-re-search-forward verilog-end-statement-re nil 'move)
4258 (setq nest (if (match-end 1)
4262 (throw 'found (point)))
4264 (throw 'found (verilog-end-of-statement))))))
4267 (defun verilog-in-case-region-p ()
4268 "Return true if in a case region.
4269 More specifically, point @ in the line foo : @ begin"
4273 (progn (verilog-forward-syntactic-ws)
4274 (looking-at "\\<begin\\>"))
4275 (progn (verilog-backward-syntactic-ws)
4276 (= (preceding-char) ?\:)))
4280 (verilog-re-search-backward
4281 (concat "\\(\\<module\\>\\)\\|\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|"
4282 "\\(\\<endcase\\>\\)\\>")
4286 (setq nest (1+ nest)))
4290 (setq nest (1- nest)))
4292 (throw 'found (= nest 0)))))))
4295 (defun verilog-backward-up-list (arg)
4296 "Call `backward-up-list' ARG, ignoring comments."
4297 (let ((parse-sexp-ignore-comments t))
4298 (backward-up-list arg)))
4300 (defun verilog-forward-sexp-cmt (arg)
4301 "Call `forward-sexp' ARG, inside comments."
4302 (let ((parse-sexp-ignore-comments nil))
4303 (forward-sexp arg)))
4305 (defun verilog-forward-sexp-ign-cmt (arg)
4306 "Call `forward-sexp' ARG, ignoring comments."
4307 (let ((parse-sexp-ignore-comments t))
4308 (forward-sexp arg)))
4310 (defun verilog-in-generate-region-p ()
4311 "Return true if in a generate region.
4312 More specifically, after a generate and before an endgenerate."
4319 (verilog-re-search-backward
4320 "\\<\\(module\\)\\|\\(generate\\)\\|\\(endgenerate\\)\\>" nil 'move)
4322 ((match-end 1) ; module - we have crawled out
4324 ((match-end 2) ; generate
4325 (setq nest (1- nest)))
4326 ((match-end 3) ; endgenerate
4327 (setq nest (1+ nest))))))))
4328 (= nest 0) )) ; return nest
4330 (defun verilog-in-fork-region-p ()
4331 "Return true if between a fork and join."
4333 (let ((lim (save-excursion (verilog-beg-of-defun) (point)))
4338 (verilog-re-search-backward "\\<\\(fork\\)\\|\\(join\\(_any\\|_none\\)?\\)\\>" lim 'move)
4340 ((match-end 1) ; fork
4341 (setq nest (1- nest)))
4342 ((match-end 2) ; join
4343 (setq nest (1+ nest)))))))
4344 (= nest 0) )) ; return nest
4346 (defun verilog-backward-case-item (lim)
4347 "Skip backward to nearest enclosing case item.
4348 Limit search to point LIM."
4354 (verilog-re-search-backward verilog-endcomment-reason-re
4357 ;; Try to find the real :
4358 (if (save-excursion (search-backward ":" lim1 t))
4364 (verilog-re-search-backward "\\(\\[\\)\\|\\(\\]\\)\\|\\(:\\)"
4368 (setq colon (1+ colon))
4370 (error "%s: unbalanced [" (verilog-point-text))))
4372 (setq colon (1- colon)))
4375 (setq colon (1+ colon)))))
4376 ;; Skip back to beginning of case item
4377 (skip-chars-backward "\t ")
4378 (verilog-skip-backward-comment-or-string)
4383 (verilog-re-search-backward
4384 "\\<\\(case[zx]?\\)\\>\\|;\\|\\<end\\>" nil 'move)
4388 (goto-char (match-end 1))
4389 (verilog-forward-ws&directives)
4390 (if (looking-at "(")
4393 (verilog-forward-ws&directives)))
4396 (goto-char (match-end 0))
4397 (verilog-forward-ws&directives)
4399 (error "Malformed case item"))))
4400 (setq str (buffer-substring b e))
4404 "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
4405 (setq str (concat (substring str 0 e) "...")))
4414 (defun verilog-kill-existing-comment ()
4415 "Kill auto comment on this line."
4423 (search-forward "//" e t))))
4425 (delete-region (- b 2) e)))))
4427 (defconst verilog-directive-nest-re
4428 (concat "\\(`else\\>\\)\\|"
4429 "\\(`endif\\>\\)\\|"
4431 "\\(`ifdef\\>\\)\\|"
4432 "\\(`ifndef\\>\\)\\|"
4435 (defun verilog-set-auto-endcomments (indent-str kill-existing-comment)
4436 "Add ending comment with given INDENT-STR.
4437 With KILL-EXISTING-COMMENT, remove what was there before.
4438 Insert `// case: 7 ' or `// NAME ' on this line if appropriate.
4439 Insert `// case expr ' if this line ends a case block.
4440 Insert `// ifdef FOO ' if this line ends code conditional on FOO.
4441 Insert `// NAME ' if this line ends a function, task, module,
4442 primitive or interface named NAME."
4445 (; Comment close preprocessor directives
4447 (looking-at "\\(`endif\\)\\|\\(`else\\)")
4448 (or kill-existing-comment
4449 (not (save-excursion
4451 (search-backward "//" (point-at-bol) t)))))
4454 (else (if (match-end 2) "!" " ")))
4456 (if kill-existing-comment
4457 (verilog-kill-existing-comment))
4458 (delete-horizontal-space)
4461 (while (and (/= nest 0)
4462 (verilog-re-search-backward verilog-directive-nest-re nil 'move))
4464 ((match-end 1) ; `else
4467 ((match-end 2) ; `endif
4468 (setq nest (1+ nest)))
4469 ((match-end 3) ; `if
4470 (setq nest (1- nest)))
4471 ((match-end 4) ; `ifdef
4472 (setq nest (1- nest)))
4473 ((match-end 5) ; `ifndef
4474 (setq nest (1- nest)))
4475 ((match-end 6) ; `elsif
4486 (skip-chars-forward "^ \t")
4487 (verilog-forward-syntactic-ws)
4490 (skip-chars-forward "a-zA-Z0-9_")
4493 (if (> (count-lines (point) b) verilog-minimum-comment-distance)
4494 (insert (concat " // " else m " " (buffer-substring b e))))
4496 (insert " // unmatched `else, `elsif or `endif")
4499 (; Comment close case/class/function/task/module and named block
4500 (and (looking-at "\\<end")
4501 (or kill-existing-comment
4502 (not (save-excursion
4504 (search-backward "//" (point-at-bol) t)))))
4505 (let ((type (car indent-str)))
4506 (unless (eq type 'declaration)
4507 (unless (looking-at (concat "\\(" verilog-end-block-ordered-re "\\)[ \t]*:")) ;; ignore named ends
4508 (if (looking-at verilog-end-block-ordered-re)
4510 (;- This is a case block; search back for the start of this case
4511 (match-end 1) ;; of verilog-end-block-ordered-re
4514 (str "UNMATCHED!!"))
4516 (verilog-leap-to-head)
4518 ((looking-at "\\<randcase\\>")
4519 (setq str "randcase")
4521 ((looking-at "\\(\\(unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
4522 (goto-char (match-end 0))
4523 (setq str (concat (match-string 0) " " (verilog-get-expr)))
4527 (if kill-existing-comment
4528 (verilog-kill-existing-comment))
4529 (delete-horizontal-space)
4530 (insert (concat " // " str ))
4531 (if err (ding 't))))
4533 (;- This is a begin..end block
4534 (match-end 2) ;; of verilog-end-block-ordered-re
4535 (let ((str " // UNMATCHED !!")
4541 (verilog-leap-to-head)
4542 (setq there (point))
4543 (if (not (match-end 0))
4547 (if kill-existing-comment
4548 (verilog-kill-existing-comment))
4549 (delete-horizontal-space)
4553 (save-excursion (verilog-beg-of-defun) (point)))
4556 (;-- handle named block differently
4557 (looking-at verilog-named-block-re)
4558 (search-forward ":")
4559 (setq there (point))
4560 (setq str (verilog-get-expr))
4562 (setq str (concat " // block: " str )))
4564 ((verilog-in-case-region-p) ;-- handle case item differently
4566 (setq str (verilog-backward-case-item lim))
4567 (setq there (point))
4569 (setq str (concat " // case: " str )))
4571 (;- try to find "reason" for this begin
4575 ;; (verilog-backward-token)
4576 (verilog-beg-of-statement)
4580 ((looking-at verilog-endcomment-reason-re)
4581 (setq there (match-end 0))
4582 (setq cntx (concat (match-string 0) " "))
4588 (if (and (verilog-continued-line)
4589 (looking-at "\\<repeat\\>\\|\\<wait\\>\\|\\<always\\>"))
4591 (goto-char (match-end 0))
4592 (setq there (point))
4594 (concat " // " (match-string 0) " " (verilog-get-expr))))
4600 ( reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)\\|\\(assert\\)"))
4602 (while (verilog-re-search-backward reg nil 'move)
4604 ((match-end 1) ; begin
4605 (setq nest (1- nest)))
4606 ((match-end 2) ; end
4607 (setq nest (1+ nest)))
4611 (goto-char (match-end 0))
4612 (setq there (point))
4614 (setq str (verilog-get-expr))
4615 (setq str (concat " // else: !if" str ))
4620 (goto-char (match-end 0))
4621 (setq there (point))
4623 (setq str (verilog-get-expr))
4624 (setq str (concat " // else: !assert " str ))
4625 (throw 'skip 1)))))))))
4630 (reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)\\|\\(assert\\)"))
4632 (while (verilog-re-search-backward reg nil 'move)
4634 ((match-end 1) ; begin
4635 (setq nest (1- nest)))
4636 ((match-end 2) ; end
4637 (setq nest (1+ nest)))
4641 (goto-char (match-end 0))
4642 (setq there (point))
4644 (setq str (verilog-get-expr))
4645 (setq str (concat " // else: !if" str ))
4650 (goto-char (match-end 0))
4651 (setq there (point))
4653 (setq str (verilog-get-expr))
4654 (setq str (concat " // else: !assert " str ))
4655 (throw 'skip 1)))))))))
4657 (; always_comb, always_ff, always_latch
4658 (or (match-end 4) (match-end 5) (match-end 6))
4659 (goto-char (match-end 0))
4660 (setq there (point))
4662 (setq str (concat " // " cntx )))
4664 (;- task/function/initial et cetera
4667 (goto-char (match-end 0))
4668 (setq there (point))
4670 (setq str (concat " // " cntx (verilog-get-expr))))
4673 (setq str " // auto-endcomment confused "))))
4676 (verilog-in-case-region-p) ;-- handle case item differently
4678 (setq there (point))
4680 (setq str (verilog-backward-case-item lim))))
4682 (setq str (concat " // case: " str )))
4684 ((verilog-in-fork-region-p)
4686 (setq str " // fork branch" ))
4688 ((looking-at "\\<end\\>")
4691 (verilog-forward-syntactic-ws)
4693 (setq str (verilog-get-expr))
4694 (setq str (concat " // " cntx str )))
4699 (if kill-existing-comment
4700 (verilog-kill-existing-comment))
4701 (delete-horizontal-space)
4703 (> (count-lines here there) verilog-minimum-comment-distance))
4707 (;- this is endclass, which can be nested
4708 (match-end 11) ;; of verilog-end-block-ordered-re
4711 (reg "\\<\\(class\\)\\|\\(endclass\\)\\|\\(package\\|primitive\\|\\(macro\\)?module\\)\\>")
4715 (while (verilog-re-search-backward reg nil 'move)
4717 ((match-end 3) ; endclass
4719 (setq string "unmatched endclass")
4722 ((match-end 2) ; endclass
4723 (setq nest (1+ nest)))
4725 ((match-end 1) ; class
4726 (setq nest (1- nest))
4729 (goto-char (match-end 0))
4732 (skip-chars-forward "^ \t")
4733 (verilog-forward-ws&directives)
4736 (skip-chars-forward "a-zA-Z0-9_")
4738 (setq string (buffer-substring b e)))
4742 (insert (concat " // " string ))))
4744 (;- this is end{function,generate,task,module,primitive,table,generate}
4745 ;- which can not be nested.
4747 (let (string reg (name-re nil))
4749 (if kill-existing-comment
4751 (verilog-kill-existing-comment)))
4752 (delete-horizontal-space)
4755 ((match-end 5) ;; of verilog-end-block-ordered-re
4756 (setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
4757 (setq name-re "\\w+\\s-*("))
4758 ((match-end 6) ;; of verilog-end-block-ordered-re
4759 (setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
4760 (setq name-re "\\w+\\s-*("))
4761 ((match-end 7) ;; of verilog-end-block-ordered-re
4762 (setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\<endmodule\\>"))
4763 ((match-end 8) ;; of verilog-end-block-ordered-re
4764 (setq reg "\\(\\<primitive\\>\\)\\|\\(\\<\\(endprimitive\\|package\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4765 ((match-end 9) ;; of verilog-end-block-ordered-re
4766 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<\\(endinterface\\|package\\|primitive\\|\\(macro\\)?module\\)\\>\\)"))
4767 ((match-end 10) ;; of verilog-end-block-ordered-re
4768 (setq reg "\\(\\<package\\>\\)\\|\\(\\<\\(endpackage\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4769 ((match-end 11) ;; of verilog-end-block-ordered-re
4770 (setq reg "\\(\\<class\\>\\)\\|\\(\\<\\(endclass\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4771 ((match-end 12) ;; of verilog-end-block-ordered-re
4772 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<\\(endcovergroup\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4773 ((match-end 13) ;; of verilog-end-block-ordered-re
4774 (setq reg "\\(\\<program\\>\\)\\|\\(\\<\\(endprogram\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4775 ((match-end 14) ;; of verilog-end-block-ordered-re
4776 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<\\(endsequence\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4777 ((match-end 15) ;; of verilog-end-block-ordered-re
4778 (setq reg "\\(\\<clocking\\>\\)\\|\\<endclocking\\>"))
4780 (t (error "Problem in verilog-set-auto-endcomments")))
4783 (verilog-re-search-backward reg nil 'move)
4787 (skip-chars-forward "^ \t")
4788 (verilog-forward-ws&directives)
4789 (if (looking-at "static\\|automatic")
4791 (goto-char (match-end 0))
4792 (verilog-forward-ws&directives)))
4793 (if (and name-re (verilog-re-search-forward name-re nil 'move))
4795 (goto-char (match-beginning 0))
4796 (verilog-forward-ws&directives)))
4799 (skip-chars-forward "a-zA-Z0-9_")
4801 (setq string (buffer-substring b e)))
4804 (setq string "unmatched end(function|task|module|primitive|interface|package|class|clocking)")))))
4806 (insert (concat " // " string )))
4809 (defun verilog-get-expr()
4810 "Grab expression at point, e.g., case ( a | b & (c ^d))."
4812 (verilog-forward-syntactic-ws)
4813 (skip-chars-forward " \t")
4819 (verilog-forward-syntactic-ws)
4820 (if (looking-at "(")
4823 (while (and (/= par 0)
4824 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
4827 (setq par (1+ par)))
4829 (setq par (1- par)))))))
4833 (while (and (/= par 0)
4834 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
4837 (setq par (1+ par)))
4839 (setq par (1- par)))))
4843 (while (and (/= par 0)
4844 (verilog-re-search-forward "\\(\\[\\)\\|\\(\\]\\)" nil 'move))
4847 (setq par (1+ par)))
4849 (setq par (1- par)))))
4850 (verilog-forward-syntactic-ws)
4851 (skip-chars-forward "^ \t\n\f")
4853 ((looking-at "/[/\\*]")
4856 (skip-chars-forward "^: \t\n\f")
4858 (str (buffer-substring b e)))
4859 (if (setq e (string-match "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
4860 (setq str (concat (substring str 0 e) "...")))
4863 (defun verilog-expand-vector ()
4864 "Take a signal vector on the current line and expand it to multiple lines.
4865 Useful for creating tri's and other expanded fields."
4867 (verilog-expand-vector-internal "[" "]"))
4869 (defun verilog-expand-vector-internal (bra ket)
4870 "Given BRA, the start brace and KET, the end brace, expand one line into many lines."
4873 (let ((signal-string (buffer-substring (point)
4875 (end-of-line) (point)))))
4879 "\\([0-9]*\\)\\(:[0-9]*\\|\\)\\(::[0-9---]*\\|\\)"
4881 "\\(.*\\)$") signal-string)
4882 (let* ((sig-head (match-string 1 signal-string))
4883 (vec-start (string-to-number (match-string 2 signal-string)))
4884 (vec-end (if (= (match-beginning 3) (match-end 3))
4887 (substring signal-string (1+ (match-beginning 3))
4890 (if (= (match-beginning 4) (match-end 4))
4893 (substring signal-string (+ 2 (match-beginning 4))
4895 (sig-tail (match-string 5 signal-string))
4900 (let ((tmp vec-start))
4901 (setq vec-start vec-end
4903 vec-range (- vec-range))))
4904 (if (< vec-end vec-start)
4905 (while (<= vec-end vec-start)
4906 (setq vec (append vec (list vec-start)))
4907 (setq vec-start (- vec-start vec-range)))
4908 (while (<= vec-start vec-end)
4909 (setq vec (append vec (list vec-start)))
4910 (setq vec-start (+ vec-start vec-range))))
4912 ;; Delete current line
4913 (delete-region (point) (progn (forward-line 0) (point)))
4917 (insert (concat sig-head bra
4918 (int-to-string (car vec)) ket sig-tail "\n"))
4919 (setq vec (cdr vec)))
4924 (defun verilog-strip-comments ()
4925 "Strip all comments from the Verilog code."
4927 (goto-char (point-min))
4928 (while (re-search-forward "//" nil t)
4929 (if (verilog-within-string)
4930 (re-search-forward "\"" nil t)
4931 (if (verilog-in-star-comment-p)
4932 (re-search-forward "\*/" nil t)
4933 (let ((bpt (- (point) 2)))
4935 (delete-region bpt (point))))))
4937 (goto-char (point-min))
4938 (while (re-search-forward "/\\*" nil t)
4939 (if (verilog-within-string)
4940 (re-search-forward "\"" nil t)
4941 (let ((bpt (- (point) 2)))
4942 (re-search-forward "\\*/")
4943 (delete-region bpt (point))))))
4945 (defun verilog-one-line ()
4946 "Convert structural Verilog instances to occupy one line."
4948 (goto-char (point-min))
4949 (while (re-search-forward "\\([^;]\\)[ \t]*\n[ \t]*" nil t)
4950 (replace-match "\\1 " nil nil)))
4952 (defun verilog-linter-name ()
4953 "Return name of linter, either surelint or verilint."
4954 (let ((compile-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
4956 (lint-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
4958 (cond ((equal compile-word1 "surelint") `surelint)
4959 ((equal compile-word1 "verilint") `verilint)
4960 ((equal lint-word1 "surelint") `surelint)
4961 ((equal lint-word1 "verilint") `verilint)
4962 (t `surelint)))) ;; back compatibility
4964 (defun verilog-lint-off ()
4965 "Convert a Verilog linter warning line into a disable statement.
4967 pci_bfm_null.v, line 46: Unused input: pci_rst_
4968 becomes a comment for the appropriate tool.
4970 The first word of the `compile-command' or `verilog-linter'
4971 variables is used to determine which product is being used.
4973 See \\[verilog-surelint-off] and \\[verilog-verilint-off]."
4975 (let ((linter (verilog-linter-name)))
4976 (cond ((equal linter `surelint)
4977 (verilog-surelint-off))
4978 ((equal linter `verilint)
4979 (verilog-verilint-off))
4980 (t (error "Linter name not set")))))
4982 (defvar compilation-last-buffer)
4983 (defvar next-error-last-buffer)
4985 (defun verilog-surelint-off ()
4986 "Convert a SureLint warning line into a disable statement.
4987 Run from Verilog source window; assumes there is a *compile* buffer
4988 with point set appropriately.
4991 WARNING [STD-UDDONX]: xx.v, line 8: output out is never assigned.
4993 // surefire lint_line_off UDDONX"
4995 (let ((buff (if (boundp 'next-error-last-buffer)
4996 next-error-last-buffer
4997 compilation-last-buffer)))
4998 (when (buffer-live-p buff)
5000 (switch-to-buffer buff)
5003 (looking-at "\\(INFO\\|WARNING\\|ERROR\\) \\[[^-]+-\\([^]]+\\)\\]: \\([^,]+\\), line \\([0-9]+\\): \\(.*\\)$")
5004 (let* ((code (match-string 2))
5005 (file (match-string 3))
5006 (line (match-string 4))
5007 (buffer (get-file-buffer file))
5012 (and (file-exists-p file)
5013 (find-file-noselect file)))
5015 (let* ((pop-up-windows t))
5016 (let ((name (expand-file-name
5018 (format "Find this error in: (default %s) "
5021 (if (file-directory-p name)
5022 (setq name (expand-file-name filename name)))
5024 (and (file-exists-p name)
5025 (find-file-noselect name))))))))
5026 (switch-to-buffer buffer)
5027 (goto-char (point-min))
5028 (forward-line (- (string-to-number line)))
5032 ((verilog-in-slash-comment-p)
5033 (re-search-backward "//")
5035 ((looking-at "// surefire lint_off_line ")
5036 (goto-char (match-end 0))
5037 (let ((lim (point-at-eol)))
5038 (if (re-search-forward code lim 'move)
5040 (insert (concat " " code)))))
5043 ((verilog-in-star-comment-p)
5044 (re-search-backward "/\*")
5045 (insert (format " // surefire lint_off_line %6s" code )))
5047 (insert (format " // surefire lint_off_line %6s" code ))
5050 (defun verilog-verilint-off ()
5051 "Convert a Verilint warning line into a disable statement.
5054 (W240) pci_bfm_null.v, line 46: Unused input: pci_rst_
5056 //Verilint 240 off // WARNING: Unused input"
5060 (when (looking-at "\\(.*\\)([WE]\\([0-9A-Z]+\\)).*,\\s +line\\s +[0-9]+:\\s +\\([^:\n]+\\):?.*$")
5061 (replace-match (format
5062 ;; %3s makes numbers 1-999 line up nicely
5063 "\\1//Verilint %3s off // WARNING: \\3"
5066 (verilog-indent-line))))
5068 (defun verilog-auto-save-compile ()
5069 "Update automatics with \\[verilog-auto], save the buffer, and compile."
5071 (verilog-auto) ; Always do it for safety
5073 (compile compile-command))
5075 (defun verilog-preprocess (&optional command filename)
5076 "Preprocess the buffer, similar to `compile', but put output in Verilog-Mode.
5077 Takes optional COMMAND or defaults to `verilog-preprocessor', and
5078 FILENAME to find directory to run in, or defaults to `buffer-file-name`."
5081 (let ((default (verilog-expand-command verilog-preprocessor)))
5082 (set (make-local-variable `verilog-preprocessor)
5083 (read-from-minibuffer "Run Preprocessor (like this): "
5085 'verilog-preprocess-history default)))))
5086 (unless command (setq command (verilog-expand-command verilog-preprocessor)))
5087 (let* ((fontlocked (and (boundp 'font-lock-mode) font-lock-mode))
5088 (dir (file-name-directory (or filename buffer-file-name)))
5089 (cmd (concat "cd " dir "; " command)))
5090 (with-output-to-temp-buffer "*Verilog-Preprocessed*"
5091 (with-current-buffer (get-buffer "*Verilog-Preprocessed*")
5092 (insert (concat "// " cmd "\n"))
5093 (call-process shell-file-name nil t nil shell-command-switch cmd)
5095 ;; Without this force, it takes a few idle seconds
5096 ;; to get the color, which is very jarring
5097 (when fontlocked (font-lock-fontify-buffer))))))
5104 (defun verilog-warn (string &rest args)
5105 "Print a warning with `format' using STRING and optional ARGS."
5106 (apply 'message (concat "%%Warning: " string) args))
5108 (defun verilog-warn-error (string &rest args)
5109 "Call `error' using STRING and optional ARGS.
5110 If `verilog-warn-fatal' is non-nil, call `verilog-warn' instead."
5111 (if verilog-warn-fatal
5112 (apply 'error string args)
5113 (apply 'verilog-warn string args)))
5115 (defmacro verilog-batch-error-wrapper (&rest body)
5116 "Execute BODY and add error prefix to any errors found.
5117 This lets programs calling batch mode to easily extract error messages."
5118 `(let ((verilog-warn-fatal nil))
5122 (error "%%Error: %s%s" (error-message-string err)
5123 (if (featurep 'xemacs) "\n" "")))))) ;; XEmacs forgets to add a newline
5125 (defun verilog-batch-execute-func (funref &optional no-save)
5126 "Internal processing of a batch command.
5127 Runs FUNREF on all command arguments.
5128 Save the result unless optional NO-SAVE is t."
5129 (verilog-batch-error-wrapper
5130 ;; Setting global variables like that is *VERY NASTY* !!! --Stef
5131 ;; However, this function is called only when Emacs is being used as
5132 ;; a standalone language instead of as an editor, so we'll live.
5134 ;; General globals needed
5135 (setq make-backup-files nil)
5136 (setq-default make-backup-files nil)
5137 (setq enable-local-variables t)
5138 (setq enable-local-eval t)
5139 (setq create-lockfiles nil)
5140 ;; Make sure any sub-files we read get proper mode
5141 (setq-default major-mode 'verilog-mode)
5142 ;; Ditto files already read in
5144 (when (buffer-file-name buf)
5145 (with-current-buffer buf
5148 ;; Process the files
5149 (mapcar (lambda (buf)
5150 (when (buffer-file-name buf)
5152 (if (not (file-exists-p (buffer-file-name buf)))
5154 (concat "File not found: " (buffer-file-name buf))))
5155 (message (concat "Processing " (buffer-file-name buf)))
5158 (unless no-save (save-buffer)))))
5161 (defun verilog-batch-auto ()
5162 "For use with --batch, perform automatic expansions as a stand-alone tool.
5163 This sets up the appropriate Verilog mode environment, updates automatics
5164 with \\[verilog-auto] on all command-line files, and saves the buffers.
5165 For proper results, multiple filenames need to be passed on the command
5166 line in bottom-up order."
5167 (unless noninteractive
5168 (error "Use verilog-batch-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
5169 (verilog-batch-execute-func `verilog-auto))
5171 (defun verilog-batch-delete-auto ()
5172 "For use with --batch, perform automatic deletion as a stand-alone tool.
5173 This sets up the appropriate Verilog mode environment, deletes automatics
5174 with \\[verilog-delete-auto] on all command-line files, and saves the buffers."
5175 (unless noninteractive
5176 (error "Use verilog-batch-delete-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
5177 (verilog-batch-execute-func `verilog-delete-auto))
5179 (defun verilog-batch-delete-trailing-whitespace ()
5180 "For use with --batch, perform whitespace deletion as a stand-alone tool.
5181 This sets up the appropriate Verilog mode environment, removes
5182 whitespace with \\[verilog-delete-trailing-whitespace] on all
5183 command-line files, and saves the buffers."
5184 (unless noninteractive
5185 (error "Use verilog-batch-delete-trailing-whitespace only with --batch")) ;; Otherwise we'd mess up buffer modes
5186 (verilog-batch-execute-func `verilog-delete-trailing-whitespace))
5188 (defun verilog-batch-diff-auto ()
5189 "For use with --batch, perform automatic differences as a stand-alone tool.
5190 This sets up the appropriate Verilog mode environment, expand automatics
5191 with \\[verilog-diff-auto] on all command-line files, and reports an error
5192 if any differences are observed. This is appropriate for adding to regressions
5193 to insure automatics are always properly maintained."
5194 (unless noninteractive
5195 (error "Use verilog-batch-diff-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
5196 (verilog-batch-execute-func `verilog-diff-auto t))
5198 (defun verilog-batch-inject-auto ()
5199 "For use with --batch, perform automatic injection as a stand-alone tool.
5200 This sets up the appropriate Verilog mode environment, injects new automatics
5201 with \\[verilog-inject-auto] on all command-line files, and saves the buffers.
5202 For proper results, multiple filenames need to be passed on the command
5203 line in bottom-up order."
5204 (unless noninteractive
5205 (error "Use verilog-batch-inject-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
5206 (verilog-batch-execute-func `verilog-inject-auto))
5208 (defun verilog-batch-indent ()
5209 "For use with --batch, reindent an entire file as a stand-alone tool.
5210 This sets up the appropriate Verilog mode environment, calls
5211 \\[verilog-indent-buffer] on all command-line files, and saves the buffers."
5212 (unless noninteractive
5213 (error "Use verilog-batch-indent only with --batch")) ;; Otherwise we'd mess up buffer modes
5214 (verilog-batch-execute-func `verilog-indent-buffer))
5220 (defconst verilog-indent-alist
5221 '((block . (+ ind verilog-indent-level))
5222 (case . (+ ind verilog-case-indent))
5223 (cparenexp . (+ ind verilog-indent-level))
5224 (cexp . (+ ind verilog-cexp-indent))
5225 (defun . verilog-indent-level-module)
5226 (declaration . verilog-indent-level-declaration)
5227 (directive . (verilog-calculate-indent-directive))
5228 (tf . verilog-indent-level)
5229 (behavioral . (+ verilog-indent-level-behavioral verilog-indent-level-module))
5232 (comment . (verilog-comment-indent))
5236 (defun verilog-continued-line-1 (lim)
5237 "Return true if this is a continued line.
5238 Set point to where line starts. Limit search to point LIM."
5239 (let ((continued 't))
5240 (if (eq 0 (forward-line -1))
5243 (verilog-backward-ws&directives lim)
5245 (setq continued nil)
5246 (setq continued (verilog-backward-token))))
5247 (setq continued nil))
5250 (defun verilog-calculate-indent ()
5251 "Calculate the indent of the current Verilog line.
5252 Examine previous lines. Once a line is found that is definitive as to the
5253 type of the current line, return that lines' indent level and its type.
5254 Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
5256 (let* ((starting_position (point))
5258 (begin (looking-at "[ \t]*begin\\>"))
5259 (lim (save-excursion (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)" nil t)))
5261 (type (catch 'nesting
5262 ;; Keep working backwards until we can figure out
5263 ;; what type of statement this is.
5264 ;; Basically we need to figure out
5265 ;; 1) if this is a continuation of the previous line;
5266 ;; 2) are we in a block scope (begin..end)
5268 ;; if we are in a comment, done.
5269 (if (verilog-in-star-comment-p)
5270 (throw 'nesting 'comment))
5272 ;; if we have a directive, done.
5273 (if (save-excursion (beginning-of-line)
5274 (and (looking-at verilog-directive-re-1)
5275 (not (or (looking-at "[ \t]*`[ou]vm_")
5276 (looking-at "[ \t]*`vmm_")))))
5277 (throw 'nesting 'directive))
5278 ;; indent structs as if there were module level
5279 (setq structres (verilog-in-struct-nested-p))
5280 (cond ((not structres) nil)
5281 ;;((and structres (equal (char-after) ?\})) (throw 'nesting 'struct-close))
5282 ((> structres 0) (throw 'nesting 'nested-struct))
5283 ((= structres 0) (throw 'nesting 'block))
5286 ;; if we are in a parenthesized list, and the user likes to indent these, return.
5287 ;; unless we are in the newfangled coverpoint or constraint blocks
5289 verilog-indent-lists
5291 (not (verilog-in-coverage-p))
5294 (throw 'nesting 'block)))
5296 ;; See if we are continuing a previous line
5298 ;; trap out if we crawl off the top of the buffer
5299 (if (bobp) (throw 'nesting 'cpp))
5301 (if (and (verilog-continued-line-1 lim)
5302 (or (not (verilog-in-coverage-p))
5303 (looking-at verilog-in-constraint-re) )) ;; may still get hosed if concat in constraint
5306 (not (looking-at verilog-complete-reg))
5307 (verilog-continued-line-1 lim))
5308 (progn (goto-char sp)
5309 (throw 'nesting 'cexp))
5312 (if (and (verilog-in-coverage-p)
5313 (looking-at verilog-in-constraint-re))
5316 (skip-chars-forward " \t")
5317 (throw 'nesting 'constraint)))
5319 (not verilog-indent-begin-after-if)
5320 (looking-at verilog-no-indent-begin-re))
5323 (skip-chars-forward " \t")
5324 (throw 'nesting 'statement))
5326 (throw 'nesting 'cexp))))
5327 ;; not a continued line
5328 (goto-char starting_position))
5330 (if (looking-at "\\<else\\>")
5331 ;; search back for governing if, striding across begin..end pairs
5334 (while (verilog-re-search-backward verilog-ends-re nil 'move)
5336 ((match-end 1) ; else, we're in deep
5337 (setq elsec (1+ elsec)))
5339 (setq elsec (1- elsec))
5341 (if verilog-align-ifelse
5342 (throw 'nesting 'statement)
5343 (progn ;; back up to first word on this line
5345 (verilog-forward-syntactic-ws)
5346 (throw 'nesting 'statement)))))
5347 ((match-end 3) ; assert block
5348 (setq elsec (1- elsec))
5349 (verilog-beg-of-statement) ;; doesn't get to beginning
5350 (if (looking-at verilog-property-re)
5351 (throw 'nesting 'statement) ; We don't need an endproperty for these
5352 (throw 'nesting 'block) ;We still need an endproperty
5355 ; try to leap back to matching outward block by striding across
5356 ; indent level changing tokens then immediately
5357 ; previous line governs indentation.
5358 (let (( reg) (nest 1))
5359 ;; verilog-ends => else|if|end|join(_any|_none|)|endcase|endclass|endtable|endspecify|endfunction|endtask|endgenerate|endgroup
5361 ((match-end 4) ; end
5362 ;; Search back for matching begin
5363 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
5364 ((match-end 5) ; endcase
5365 ;; Search back for matching case
5366 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
5367 ((match-end 6) ; endfunction
5368 ;; Search back for matching function
5369 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
5370 ((match-end 7) ; endtask
5371 ;; Search back for matching task
5372 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
5373 ((match-end 8) ; endspecify
5374 ;; Search back for matching specify
5375 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
5376 ((match-end 9) ; endtable
5377 ;; Search back for matching table
5378 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
5379 ((match-end 10) ; endgenerate
5380 ;; Search back for matching generate
5381 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
5382 ((match-end 11) ; joins
5383 ;; Search back for matching fork
5384 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|none\\)?\\>\\)" ))
5385 ((match-end 12) ; class
5386 ;; Search back for matching class
5387 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
5388 ((match-end 13) ; covergroup
5389 ;; Search back for matching covergroup
5390 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" )))
5392 (while (verilog-re-search-backward reg nil 'move)
5394 ((match-end 1) ; begin
5395 (setq nest (1- nest))
5398 ((match-end 2) ; end
5399 (setq nest (1+ nest)))))
5401 (throw 'nesting (verilog-calc-1)))
5405 ;; Return type of block and indent level.
5408 (if (> par 0) ; Unclosed Parenthesis
5409 (list 'cparenexp par)
5412 (list type (verilog-case-indent-level)))
5413 ((eq type 'statement)
5414 (list type (current-column)))
5417 ((eq type 'constraint)
5418 (list 'block (current-column)))
5419 ((eq type 'nested-struct)
5420 (list 'block structres))
5422 (list type (verilog-current-indent-level))))))))
5424 (defun verilog-wai ()
5425 "Show matching nesting block for debugging."
5428 (let* ((type (verilog-calc-1))
5430 ;; Return type of block and indent level.
5434 verilog-indent-lists
5435 (not(or (verilog-in-coverage-p)
5436 (verilog-in-struct-p)))
5441 (setq depth (verilog-case-indent-level)))
5442 ((eq type 'statement)
5443 (setq depth (current-column)))
5447 (setq depth (verilog-current-indent-level)))))
5448 (message "You are at nesting %s depth %d" type depth))))
5450 (defun verilog-calc-1 ()
5452 (let ((re (concat "\\({\\|}\\|" verilog-indent-re "\\)"))
5453 (inconstraint (verilog-in-coverage-p)))
5454 (while (verilog-re-search-backward re nil 'move)
5457 ((equal (char-after) ?\{)
5458 ;; block type returned based on outer constraint { or inner
5459 (if (verilog-at-constraint-p)
5460 (cond (inconstraint (throw 'nesting 'constraint))
5461 (t (throw 'nesting 'statement)))))
5462 ((equal (char-after) ?\})
5464 (there (verilog-at-close-constraint-p)))
5465 (if there ;; we are at the } that closes a constraint. Find the { that opens it
5467 (if (> (verilog-in-paren-count) 0)
5469 (setq par-pos (verilog-parenthesis-depth))
5474 (backward-char 1)))))))
5476 ((looking-at verilog-beg-block-re-ordered)
5478 ((match-end 2) ; *sigh* could be "unique case" or "priority casex"
5479 (let ((here (point)))
5480 (verilog-beg-of-statement)
5481 (if (looking-at verilog-extended-case-re)
5482 (throw 'nesting 'case)
5484 (throw 'nesting 'case))
5486 ((match-end 4) ; *sigh* could be "disable fork"
5487 (let ((here (point)))
5488 (verilog-beg-of-statement)
5489 (if (looking-at verilog-disable-fork-re)
5490 t ; this is a normal statement
5491 (progn ; or is fork, starts a new block
5493 (throw 'nesting 'block)))))
5495 ((match-end 27) ; *sigh* might be a clocking declaration
5496 (let ((here (point)))
5497 (if (verilog-in-paren)
5498 t ; this is a normal statement
5499 (progn ; or is fork, starts a new block
5501 (throw 'nesting 'block)))))
5503 ;; need to consider typedef struct here...
5504 ((looking-at "\\<class\\|struct\\|function\\|task\\>")
5505 ; *sigh* These words have an optional prefix:
5506 ; extern {virtual|protected}? function a();
5507 ; typedef class foo;
5508 ; and we don't want to confuse this with
5513 (verilog-beg-of-statement)
5514 (if (looking-at verilog-beg-block-re-ordered)
5515 (throw 'nesting 'block)
5516 (throw 'nesting 'defun)))
5519 ((looking-at "\\<property\\>")
5521 ; {assert|assume|cover} property (); are complete
5522 ; and could also be labeled: - foo: assert property
5524 ; property ID () ... needs end_property
5525 (verilog-beg-of-statement)
5526 (if (looking-at verilog-property-re)
5527 (throw 'continue 'statement) ; We don't need an endproperty for these
5528 (throw 'nesting 'block) ;We still need an endproperty
5531 (t (throw 'nesting 'block))))
5533 ((looking-at verilog-end-block-re)
5534 (verilog-leap-to-head)
5535 (if (verilog-in-case-region-p)
5537 (verilog-leap-to-case-head)
5538 (if (looking-at verilog-extended-case-re)
5539 (throw 'nesting 'case)))))
5541 ((looking-at verilog-defun-level-re)
5542 (if (looking-at verilog-defun-level-generate-only-re)
5543 (if (verilog-in-generate-region-p)
5544 (throw 'continue 'foo) ; always block in a generate - keep looking
5545 (throw 'nesting 'defun))
5546 (throw 'nesting 'defun)))
5548 ((looking-at verilog-cpp-level-re)
5549 (throw 'nesting 'cpp))
5552 (throw 'nesting 'cpp)))))
5554 (throw 'nesting 'cpp))))
5556 (defun verilog-calculate-indent-directive ()
5557 "Return indentation level for directive.
5558 For speed, the searcher looks at the last directive, not the indent
5559 of the appropriate enclosing block."
5560 (let ((base -1) ;; Indent of the line that determines our indentation
5561 (ind 0)) ;; Relative offset caused by other directives (like `endif on same line as `else)
5562 ;; Start at current location, scan back for another directive
5566 (while (and (< base 0)
5567 (verilog-re-search-backward verilog-directive-re nil t))
5568 (cond ((save-excursion (skip-chars-backward " \t") (bolp))
5569 (setq base (current-indentation))))
5570 (cond ((and (looking-at verilog-directive-end) (< base 0)) ;; Only matters when not at BOL
5571 (setq ind (- ind verilog-indent-level-directive)))
5572 ((and (looking-at verilog-directive-middle) (>= base 0)) ;; Only matters when at BOL
5573 (setq ind (+ ind verilog-indent-level-directive)))
5574 ((looking-at verilog-directive-begin)
5575 (setq ind (+ ind verilog-indent-level-directive)))))
5576 ;; Adjust indent to starting indent of critical line
5577 (setq ind (max 0 (+ ind base))))
5581 (skip-chars-forward " \t")
5582 (cond ((or (looking-at verilog-directive-middle)
5583 (looking-at verilog-directive-end))
5584 (setq ind (max 0 (- ind verilog-indent-level-directive))))))
5587 (defun verilog-leap-to-case-head ()
5590 (verilog-re-search-backward
5592 "\\(\\<randcase\\>\\|\\(\\<unique0?\\s-+\\|priority\\s-+\\)?\\<case[xz]?\\>\\)"
5593 "\\|\\(\\<endcase\\>\\)" )
5597 (let ((here (point)))
5598 (verilog-beg-of-statement)
5599 (unless (looking-at verilog-extended-case-re)
5601 (setq nest (1- nest)))
5603 (setq nest (1+ nest)))
5608 (defun verilog-leap-to-head ()
5609 "Move point to the head of this block.
5610 Jump from end to matching begin, from endcase to matching case, and so on."
5616 ((looking-at "\\<end\\>")
5617 ;; 1: Search back for matching begin
5618 (setq reg (concat "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|"
5619 "\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))
5620 ((looking-at "\\<endtask\\>")
5621 ;; 2: Search back for matching task
5622 (setq reg "\\(\\<task\\>\\)\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)+\\<task\\>\\)")
5624 ((looking-at "\\<endcase\\>")
5626 (verilog-leap-to-case-head) )
5627 (setq reg nil) ; to force skip
5630 ((looking-at "\\<join\\(_any\\|_none\\)?\\>")
5631 ;; 4: Search back for matching fork
5632 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
5633 ((looking-at "\\<endclass\\>")
5634 ;; 5: Search back for matching class
5635 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
5636 ((looking-at "\\<endtable\\>")
5637 ;; 6: Search back for matching table
5638 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
5639 ((looking-at "\\<endspecify\\>")
5640 ;; 7: Search back for matching specify
5641 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
5642 ((looking-at "\\<endfunction\\>")
5643 ;; 8: Search back for matching function
5644 (setq reg "\\(\\<function\\>\\)\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)+\\<function\\>\\)")
5646 ;;(setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
5647 ((looking-at "\\<endgenerate\\>")
5648 ;; 8: Search back for matching generate
5649 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
5650 ((looking-at "\\<endgroup\\>")
5651 ;; 10: Search back for matching covergroup
5652 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
5653 ((looking-at "\\<endproperty\\>")
5654 ;; 11: Search back for matching property
5655 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
5656 ((looking-at verilog-uvm-end-re)
5657 ;; 12: Search back for matching sequence
5658 (setq reg (concat "\\(" verilog-uvm-begin-re "\\|" verilog-uvm-end-re "\\)")))
5659 ((looking-at verilog-ovm-end-re)
5660 ;; 12: Search back for matching sequence
5661 (setq reg (concat "\\(" verilog-ovm-begin-re "\\|" verilog-ovm-end-re "\\)")))
5662 ((looking-at verilog-vmm-end-re)
5663 ;; 12: Search back for matching sequence
5664 (setq reg (concat "\\(" verilog-vmm-begin-re "\\|" verilog-vmm-end-re "\\)")))
5665 ((looking-at "\\<endinterface\\>")
5666 ;; 12: Search back for matching interface
5667 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<endinterface\\>\\)" ))
5668 ((looking-at "\\<endsequence\\>")
5669 ;; 12: Search back for matching sequence
5670 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" ))
5671 ((looking-at "\\<endclocking\\>")
5672 ;; 12: Search back for matching clocking
5673 (setq reg "\\(\\<clocking\\)\\|\\(\\<endclocking\\>\\)" )))
5676 (if (eq nesting 'yes)
5678 (while (verilog-re-search-backward reg nil 'move)
5680 ((match-end 1) ; begin
5681 (if (looking-at "fork")
5682 (let ((here (point)))
5683 (verilog-beg-of-statement)
5684 (unless (looking-at verilog-disable-fork-re)
5686 (setq nest (1- nest))))
5687 (setq nest (1- nest)))
5689 ;; Now previous line describes syntax
5694 ((match-end 2) ; end
5695 (setq nest (1+ nest)))
5697 ;; endcase, jump to case
5699 (setq nest (1+ nest))
5701 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
5703 ;; join, jump to fork
5705 (setq nest (1+ nest))
5707 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
5711 (verilog-re-search-backward reg nil 'move)
5712 (match-end 1)) ; task -> could be virtual and/or protected
5714 (verilog-beg-of-statement)
5716 (throw 'skip 1)))))))
5718 (defun verilog-continued-line ()
5719 "Return true if this is a continued line.
5720 Set point to where line starts."
5721 (let ((continued 't))
5722 (if (eq 0 (forward-line -1))
5725 (verilog-backward-ws&directives)
5727 (setq continued nil)
5728 (while (and continued
5730 (skip-chars-backward " \t")
5732 (setq continued (verilog-backward-token)))))
5733 (setq continued nil))
5736 (defun verilog-backward-token ()
5737 "Step backward token, returning true if this is a continued line."
5739 (verilog-backward-syntactic-ws)
5743 (;-- Anything ending in a ; is complete
5744 (= (preceding-char) ?\;)
5746 (; If a "}" is prefixed by a ";", then this is a complete statement
5747 ; i.e.: constraint foo { a = b; }
5748 (= (preceding-char) ?\})
5751 (not(verilog-at-close-constraint-p))))
5752 (;-- constraint foo { a = b }
5753 ; is a complete statement. *sigh*
5754 (= (preceding-char) ?\{)
5757 (not (verilog-at-constraint-p))))
5759 (= (preceding-char) ?\")
5761 (verilog-skip-backward-comment-or-string)
5765 (= (preceding-char) ?\])
5767 (verilog-backward-open-bracket)
5770 (;-- Could be 'case (foo)' or 'always @(bar)' which is complete
5771 ; also could be simply '@(foo)'
5773 ; (b, ... which ISN'T complete
5774 ;;;; Do we need this???
5775 (= (preceding-char) ?\))
5778 (verilog-backward-up-list 1)
5779 (verilog-backward-syntactic-ws)
5780 (let ((back (point)))
5784 ((looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|case\\(\\|[xz]\\)\\|for\\(\\|each\\|ever\\)\\|i\\(f\\|nitial\\)\\|repeat\\|while\\)\\>")
5785 (not (looking-at "\\<randcase\\>\\|\\<case[xz]?\\>[^:]")))
5786 ((looking-at verilog-uvm-statement-re)
5788 ((looking-at verilog-uvm-begin-re)
5790 ((looking-at verilog-uvm-end-re)
5792 ((looking-at verilog-ovm-statement-re)
5794 ((looking-at verilog-ovm-begin-re)
5796 ((looking-at verilog-ovm-end-re)
5798 ;; JBA find VMM macros
5799 ((looking-at verilog-vmm-statement-re)
5801 ((looking-at verilog-vmm-begin-re)
5803 ((looking-at verilog-vmm-end-re)
5805 ;; JBA trying to catch macro lines with no ; at end
5806 ((looking-at "\\<`")
5811 ((= (preceding-char) ?\@)
5814 (verilog-backward-token)
5815 (not (looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|initial\\|while\\)\\>"))))
5816 ((= (preceding-char) ?\#)
5820 (;-- any of begin|initial|while are complete statements; 'begin : foo' is also complete
5823 (while (= (preceding-char) ?\_)
5826 ((looking-at "\\<else\\>")
5828 ((looking-at verilog-behavioral-block-beg-re)
5830 ((looking-at verilog-indent-re)
5835 (verilog-backward-syntactic-ws)
5837 ((= (preceding-char) ?\:)
5839 (verilog-backward-syntactic-ws)
5841 (if (looking-at verilog-nameable-item-re )
5844 ((= (preceding-char) ?\#)
5847 ((= (preceding-char) ?\`)
5855 (defun verilog-backward-syntactic-ws ()
5856 "Move backwards putting point after first non-whitespace non-comment."
5857 (verilog-skip-backward-comments)
5858 (forward-comment (- (buffer-size))))
5860 (defun verilog-backward-syntactic-ws-quick ()
5861 "As with `verilog-backward-syntactic-ws' but use `verilog-scan' cache."
5862 (while (cond ((bobp)
5864 ((> (skip-syntax-backward " ") 0)
5866 ((eq (preceding-char) ?\n) ;; \n's terminate // so aren't space syntax
5869 ((or (verilog-inside-comment-or-string-p (1- (point)))
5870 (verilog-inside-comment-or-string-p (point)))
5871 (re-search-backward "[/\"]" nil t) ;; Only way a comment or quote can begin
5874 (defun verilog-forward-syntactic-ws ()
5875 (verilog-skip-forward-comment-p)
5876 (forward-comment (buffer-size)))
5878 (defun verilog-backward-ws&directives (&optional bound)
5879 "Backward skip over syntactic whitespace and compiler directives for Emacs 19.
5880 Optional BOUND limits search."
5882 (let* ((bound (or bound (point-min)))
5885 (if (< bound (point))
5887 (let ((state (save-excursion (verilog-syntax-ppss))))
5889 ((nth 7 state) ;; in // comment
5890 (verilog-re-search-backward "//" nil 'move)
5891 (skip-chars-backward "/"))
5892 ((nth 4 state) ;; in /* */ comment
5893 (verilog-re-search-backward "/\*" nil 'move))))
5894 (narrow-to-region bound (point))
5895 (while (/= here (point))
5897 (verilog-skip-backward-comments)
5902 ((and verilog-highlight-translate-off
5903 (verilog-within-translate-off))
5904 (verilog-back-to-start-translate-off (point-min)))
5905 ((looking-at verilog-directive-re-1)
5909 (if p (goto-char p))))))))
5911 (defun verilog-forward-ws&directives (&optional bound)
5912 "Forward skip over syntactic whitespace and compiler directives for Emacs 19.
5913 Optional BOUND limits search."
5915 (let* ((bound (or bound (point-max)))
5918 (if (> bound (point))
5920 (let ((state (save-excursion (verilog-syntax-ppss))))
5922 ((nth 7 state) ;; in // comment
5925 (skip-chars-forward " \t\n\f")
5927 ((nth 4 state) ;; in /* */ comment
5928 (verilog-re-search-forward "\*\/\\s-*" nil 'move))))
5929 (narrow-to-region (point) bound)
5930 (while (/= here (point))
5933 (forward-comment (buffer-size))
5934 (and (looking-at "\\s-*(\\*.*\\*)\\s-*") ;; Attribute
5935 (goto-char (match-end 0)))
5938 (if (looking-at verilog-directive-re-1)
5941 (beginning-of-line 2))))))))
5943 (defun verilog-in-comment-p ()
5944 "Return true if in a star or // comment."
5945 (let ((state (save-excursion (verilog-syntax-ppss))))
5946 (or (nth 4 state) (nth 7 state))))
5948 (defun verilog-in-star-comment-p ()
5949 "Return true if in a star comment."
5950 (let ((state (save-excursion (verilog-syntax-ppss))))
5952 (nth 4 state) ; t if in a comment of style a // or b /**/
5954 (nth 7 state) ; t if in a comment of style b /**/
5957 (defun verilog-in-slash-comment-p ()
5958 "Return true if in a slash comment."
5959 (let ((state (save-excursion (verilog-syntax-ppss))))
5962 (defun verilog-in-comment-or-string-p ()
5963 "Return true if in a string or comment."
5964 (let ((state (save-excursion (verilog-syntax-ppss))))
5965 (or (nth 3 state) (nth 4 state) (nth 7 state)))) ; Inside string or comment)
5967 (defun verilog-in-attribute-p ()
5968 "Return true if point is in an attribute (* [] attribute *)."
5971 (verilog-re-search-backward "\\((\\*\\)\\|\\(\\*)\\)" nil 'move)
5972 (numberp (match-beginning 1)))))
5974 (defun verilog-in-parameter-p ()
5975 "Return true if point is in a parameter assignment #( p1=1, p2=5)."
5978 (verilog-re-search-backward "\\(#(\\)\\|\\()\\)" nil 'move)
5979 (numberp (match-beginning 1)))))
5981 (defun verilog-in-escaped-name-p ()
5982 "Return true if in an escaped name."
5985 (skip-chars-backward "^ \t\n\f")
5986 (if (equal (char-after (point) ) ?\\ )
5989 (defun verilog-in-directive-p ()
5990 "Return true if in a directive."
5993 (looking-at verilog-directive-re-1)))
5995 (defun verilog-in-parenthesis-p ()
5996 "Return true if in a ( ) expression (but not { } or [ ])."
5999 (verilog-re-search-backward "\\((\\)\\|\\()\\)" nil 'move)
6000 (numberp (match-beginning 1)))))
6002 (defun verilog-in-paren ()
6003 "Return true if in a parenthetical expression.
6004 May cache result using `verilog-syntax-ppss'."
6005 (let ((state (save-excursion (verilog-syntax-ppss))))
6006 (> (nth 0 state) 0 )))
6008 (defun verilog-in-paren-count ()
6009 "Return paren depth, floor to 0.
6010 May cache result using `verilog-syntax-ppss'."
6011 (let ((state (save-excursion (verilog-syntax-ppss))))
6012 (if (> (nth 0 state) 0)
6016 (defun verilog-in-paren-quick ()
6017 "Return true if in a parenthetical expression.
6018 Always starts from `point-min', to allow inserts with hooks disabled."
6019 ;; The -quick refers to its use alongside the other -quick functions,
6020 ;; not that it's likely to be faster than verilog-in-paren.
6021 (let ((state (save-excursion (parse-partial-sexp (point-min) (point)))))
6022 (> (nth 0 state) 0 )))
6024 (defun verilog-in-struct-p ()
6025 "Return true if in a struct declaration."
6028 (if (verilog-in-paren)
6030 (verilog-backward-up-list 1)
6031 (verilog-at-struct-p)
6035 (defun verilog-in-struct-nested-p ()
6036 "Return nil for not in struct.
6037 Return 0 for in non-nested struct.
6038 Return >0 for nested struct."
6042 (if (verilog-in-paren)
6044 (verilog-backward-up-list 1)
6045 (setq col (verilog-at-struct-mv-p))
6047 (if (verilog-in-struct-p) (current-column) 0)))
6050 (defun verilog-in-coverage-p ()
6051 "Return true if in a constraint or coverpoint expression."
6054 (if (verilog-in-paren)
6056 (verilog-backward-up-list 1)
6057 (verilog-at-constraint-p)
6060 (defun verilog-at-close-constraint-p ()
6061 "If at the } that closes a constraint or covergroup, return true."
6063 (equal (char-after) ?\})
6064 (verilog-in-coverage-p))
6067 (verilog-backward-ws&directives)
6068 (if (or (equal (char-before) ?\;)
6069 (equal (char-before) ?\}) ;; can end with inner constraint { } block or ;
6070 (equal (char-before) ?\{)) ;; empty constraint block
6074 (defun verilog-at-constraint-p ()
6075 "If at the { of a constraint or coverpoint definition, return true, moving point to constraint."
6078 (equal (char-after) ?\{)
6080 (progn (backward-char 1)
6081 (verilog-backward-ws&directives)
6082 (or (equal (char-before) ?\{) ;; empty case
6083 (equal (char-before) ?\;)
6084 (equal (char-before) ?\})))))
6086 (let ( (pt (point)) (pass 0))
6087 (verilog-backward-ws&directives)
6088 (verilog-backward-token)
6089 (if (looking-at (concat "\\<constraint\\|coverpoint\\|cross\\|with\\>\\|" verilog-in-constraint-re))
6090 (progn (setq pass 1)
6091 (if (looking-at "\\<with\\>")
6092 (progn (verilog-backward-ws&directives)
6093 (beginning-of-line) ;; 1
6094 (verilog-forward-ws&directives)
6096 (verilog-beg-of-statement)
6098 ;; if first word token not keyword, it maybe the instance name
6099 ;; check next word token
6100 (if (looking-at "\\<\\w+\\>\\|\\s-*(\\s-*\\w+")
6101 (progn (verilog-beg-of-statement)
6102 (if (looking-at (concat "\\<\\(constraint\\|"
6103 "\\(?:\\w+\\s-*:\\s-*\\)?\\(coverpoint\\|cross\\)"
6104 "\\|with\\)\\>\\|" verilog-in-constraint-re))
6107 (progn (goto-char pt) nil) 1)))
6111 (defun verilog-at-struct-p ()
6112 "If at the { of a struct, return true, not moving point."
6114 (if (and (equal (char-after) ?\{)
6115 (verilog-backward-token))
6116 (looking-at "\\<struct\\|union\\|packed\\|\\(un\\)?signed\\>")
6119 (defun verilog-at-struct-mv-p ()
6120 "If at the { of a struct, return true, moving point to struct."
6122 (if (and (equal (char-after) ?\{)
6123 (verilog-backward-token))
6124 (if (looking-at "\\<struct\\|union\\|packed\\|\\(un\\)?signed\\>")
6125 (progn (verilog-beg-of-statement) (point))
6126 (progn (goto-char pt) nil))
6127 (progn (goto-char pt) nil))))
6129 (defun verilog-at-close-struct-p ()
6130 "If at the } that closes a struct, return true."
6132 (equal (char-after) ?\})
6133 (verilog-in-struct-p))
6136 (if (looking-at "}\\(?:\\s-*\\w+\\s-*\\)?;") 1))
6140 (defun verilog-parenthesis-depth ()
6141 "Return non zero if in parenthetical-expression."
6142 (save-excursion (nth 1 (verilog-syntax-ppss))))
6145 (defun verilog-skip-forward-comment-or-string ()
6146 "Return true if in a string or comment."
6147 (let ((state (save-excursion (verilog-syntax-ppss))))
6149 ((nth 3 state) ;Inside string
6150 (search-forward "\"")
6152 ((nth 7 state) ;Inside // comment
6155 ((nth 4 state) ;Inside any comment (hence /**/)
6156 (search-forward "*/"))
6160 (defun verilog-skip-backward-comment-or-string ()
6161 "Return true if in a string or comment."
6162 (let ((state (save-excursion (verilog-syntax-ppss))))
6164 ((nth 3 state) ;Inside string
6165 (search-backward "\"")
6167 ((nth 7 state) ;Inside // comment
6168 (search-backward "//")
6169 (skip-chars-backward "/")
6171 ((nth 4 state) ;Inside /* */ comment
6172 (search-backward "/*")
6177 (defun verilog-skip-backward-comments ()
6178 "Return true if a comment was skipped."
6182 (let ((state (save-excursion (verilog-syntax-ppss))))
6184 ((nth 7 state) ;Inside // comment
6185 (search-backward "//")
6186 (skip-chars-backward "/")
6187 (skip-chars-backward " \t\n\f")
6189 ((nth 4 state) ;Inside /* */ comment
6190 (search-backward "/*")
6191 (skip-chars-backward " \t\n\f")
6194 (= (char-before) ?\/)
6195 (= (char-before (1- (point))) ?\*))
6196 (goto-char (- (point) 2))
6197 t) ;; Let nth 4 state handle the rest
6199 (= (char-before) ?\))
6200 (= (char-before (1- (point))) ?\*))
6201 (goto-char (- (point) 2))
6202 (if (search-backward "(*" nil t)
6204 (skip-chars-backward " \t\n\f")
6207 (goto-char (+ (point) 2))
6210 (/= (skip-chars-backward " \t\n\f") 0))))))))
6212 (defun verilog-skip-forward-comment-p ()
6213 "If in comment, move to end and return true."
6215 (state (save-excursion (verilog-syntax-ppss)))
6217 ((nth 3 state) ;Inside string
6219 ((nth 7 state) ;Inside // comment
6223 ((nth 4 state) ;Inside /* comment
6224 (search-forward "*/")
6226 ((verilog-in-attribute-p) ;Inside (* attribute
6227 (search-forward "*)" nil t)
6230 (skip-chars-forward " \t\n\f")
6233 ((looking-at "\\/\\*")
6236 (goto-char (match-end 0))
6237 (if (search-forward "*/" nil t)
6239 (skip-chars-forward " \t\n\f")
6244 ((looking-at "(\\*")
6247 (goto-char (match-end 0))
6248 (if (search-forward "*)" nil t)
6250 (skip-chars-forward " \t\n\f")
6258 (defun verilog-indent-line-relative ()
6259 "Cheap version of indent line.
6260 Only look at a few lines to determine indent level."
6264 (if (looking-at "^[ \t]*$")
6265 (cond ;- A blank line; No need to be too smart.
6267 (setq indent-str (list 'cpp 0)))
6268 ((verilog-continued-line)
6269 (let ((sp1 (point)))
6270 (if (verilog-continued-line)
6274 (list 'statement (verilog-current-indent-level))))
6276 (setq indent-str (list 'block (verilog-current-indent-level)))))
6279 (setq indent-str (verilog-calculate-indent))))
6280 (progn (skip-chars-forward " \t")
6281 (setq indent-str (verilog-calculate-indent))))
6282 (verilog-do-indent indent-str)))
6284 (defun verilog-indent-line ()
6285 "Indent for special part of code."
6286 (verilog-do-indent (verilog-calculate-indent)))
6288 (defun verilog-do-indent (indent-str)
6289 (let ((type (car indent-str))
6290 (ind (car (cdr indent-str))))
6292 (; handle continued exp
6294 (let ((here (point)))
6295 (verilog-backward-syntactic-ws)
6298 (= (preceding-char) ?\,)
6299 (= (preceding-char) ?\])
6301 (verilog-beg-of-statement-1)
6302 (looking-at verilog-declaration-re)))
6307 (verilog-beg-of-statement-1)
6309 (if (looking-at verilog-declaration-re)
6310 (progn ;; we have multiple words
6311 (goto-char (match-end 0))
6312 (skip-chars-forward " \t")
6314 ((and verilog-indent-declaration-macros
6315 (= (following-char) ?\`))
6319 (skip-chars-forward " \t")))
6320 ((= (following-char) ?\[)
6323 (verilog-backward-up-list -1)
6324 (skip-chars-forward " \t"))))
6328 (+ (current-column) verilog-cexp-indent))))))
6330 (indent-line-to val)
6331 (if (and (not verilog-indent-lists)
6333 (verilog-pretty-declarations-auto))
6335 ((= (preceding-char) ?\) )
6337 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
6338 (indent-line-to val)))
6342 (verilog-beg-of-statement-1)
6343 (if (and (< (point) here)
6344 (verilog-re-search-forward "=[ \\t]*" here 'move))
6345 (setq val (current-column))
6346 (setq val (eval (cdr (assoc type verilog-indent-alist)))))
6348 (indent-line-to val))))))
6350 (; handle inside parenthetical expressions
6351 (eq type 'cparenexp)
6353 (val (save-excursion
6354 (verilog-backward-up-list 1)
6356 (if verilog-indent-lists
6357 (skip-chars-forward " \t")
6358 (verilog-forward-syntactic-ws))
6362 (decl (save-excursion
6364 (verilog-forward-syntactic-ws)
6366 (looking-at verilog-declaration-re))))
6367 (indent-line-to val)
6369 (verilog-pretty-declarations-auto))))
6371 (;-- Handle the ends
6373 (looking-at verilog-end-block-re)
6374 (verilog-at-close-constraint-p)
6375 (verilog-at-close-struct-p))
6376 (let ((val (if (eq type 'statement)
6377 (- ind verilog-indent-level)
6379 (indent-line-to val)))
6381 (;-- Case -- maybe line 'em up
6382 (and (eq type 'case) (not (looking-at "^[ \t]*$")))
6385 ((looking-at "\\<endcase\\>")
6386 (indent-line-to ind))
6388 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
6389 (indent-line-to val))))))
6392 (and (eq type 'defun)
6393 (looking-at verilog-zero-indent-re))
6400 (looking-at verilog-declaration-re))
6401 (verilog-indent-declaration ind))
6403 (;-- Everything else
6405 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
6406 (indent-line-to val))))
6408 (if (looking-at "[ \t]+$")
6409 (skip-chars-forward " \t"))
6410 indent-str ; Return indent data
6413 (defun verilog-current-indent-level ()
6414 "Return the indent-level of the current statement."
6418 (setq par-pos (verilog-parenthesis-depth))
6422 (setq par-pos (verilog-parenthesis-depth)))
6423 (skip-chars-forward " \t")
6426 (defun verilog-case-indent-level ()
6427 "Return the indent-level of the current statement.
6428 Do not count named blocks or case-statements."
6430 (skip-chars-forward " \t")
6432 ((looking-at verilog-named-block-re)
6434 ((and (not (looking-at verilog-extended-case-re))
6435 (looking-at "^[^:;]+[ \t]*:"))
6436 (verilog-re-search-forward ":" nil t)
6437 (skip-chars-forward " \t")
6440 (current-column)))))
6442 (defun verilog-indent-comment ()
6443 "Indent current line as comment."
6446 ((verilog-in-star-comment-p)
6448 (re-search-backward "/\\*" nil t)
6449 (1+(current-column))))
6454 (re-search-backward "//" nil t)
6455 (current-column))))))
6456 (indent-line-to stcol)
6459 (defun verilog-more-comment ()
6460 "Make more comment lines like the previous."
6464 ((verilog-in-star-comment-p)
6467 (re-search-backward "/\\*" nil t)
6468 (1+(current-column))))
6473 (re-search-backward "//" nil t)
6474 (current-column))))))
6480 (skip-chars-forward " \t")
6484 (defun verilog-comment-indent (&optional _arg)
6485 "Return the column number the line should be indented to.
6486 _ARG is ignored, for `comment-indent-function' compatibility."
6488 ((verilog-in-star-comment-p)
6490 (re-search-backward "/\\*" nil t)
6491 (1+(current-column))))
6496 (re-search-backward "//" nil t)
6497 (current-column)))))
6501 (defun verilog-pretty-declarations-auto (&optional quiet)
6502 "Call `verilog-pretty-declarations' QUIET based on `verilog-auto-lineup'."
6503 (when (or (eq 'all verilog-auto-lineup)
6504 (eq 'declarations verilog-auto-lineup))
6505 (verilog-pretty-declarations quiet)))
6507 (defun verilog-pretty-declarations (&optional quiet)
6508 "Line up declarations around point.
6509 Be verbose about progress unless optional QUIET set."
6511 (let* ((m1 (make-marker))
6525 ; (verilog-beg-of-statement-1)
6527 (verilog-forward-syntactic-ws)
6528 (and (not (verilog-in-directive-p)) ;; could have `define input foo
6529 (looking-at verilog-declaration-re)))
6531 (if (verilog-parenthesis-depth)
6532 ;; in an argument list or parameter block
6533 (setq el (verilog-backward-up-list -1)
6536 (verilog-backward-up-list 1)
6537 (forward-line) ;; ignore ( input foo,
6538 (verilog-re-search-forward verilog-declaration-re el 'move)
6539 (goto-char (match-beginning 0))
6540 (skip-chars-backward " \t")
6542 startpos (set-marker (make-marker) start)
6545 (verilog-backward-up-list -1)
6547 (verilog-backward-syntactic-ws)
6549 endpos (set-marker (make-marker) end)
6553 (skip-chars-forward " \t")
6555 ;; in a declaration block (not in argument list)
6558 (verilog-beg-of-statement-1)
6559 (while (and (looking-at verilog-declaration-re)
6561 (skip-chars-backward " \t")
6564 (verilog-backward-syntactic-ws)
6566 (verilog-beg-of-statement-1))
6568 startpos (set-marker (make-marker) start)
6571 (verilog-end-of-statement)
6572 (setq e (point)) ;Might be on last line
6573 (verilog-forward-syntactic-ws)
6574 (while (looking-at verilog-declaration-re)
6575 (verilog-end-of-statement)
6577 (verilog-forward-syntactic-ws))
6579 endpos (set-marker (make-marker) end)
6582 (verilog-do-indent (verilog-calculate-indent))
6583 (verilog-forward-ws&directives)
6585 ;; OK, start and end are set
6586 (goto-char (marker-position startpos))
6587 (if (and (not quiet)
6588 (> (- end start) 100))
6589 (message "Lining up declarations..(please stand by)"))
6590 ;; Get the beginning of line indent first
6591 (while (progn (setq e (marker-position endpos))
6594 ((save-excursion (skip-chars-backward " \t")
6596 (verilog-forward-ws&directives)
6597 (indent-line-to base-ind)
6598 (verilog-forward-ws&directives)
6600 (verilog-re-search-forward "[ \t\n\f]" e 'move)))
6603 (verilog-re-search-forward "[ \t\n\f]" e 'move)))
6606 ;; Now find biggest prefix
6607 (setq ind (verilog-get-lineup-indent (marker-position startpos) endpos))
6608 ;; Now indent each line.
6609 (goto-char (marker-position startpos))
6610 (while (progn (setq e (marker-position endpos))
6611 (setq r (- e (point)))
6614 (unless quiet (message "%d" r))
6615 ;;(verilog-do-indent (verilog-calculate-indent)))
6616 (verilog-forward-ws&directives)
6618 ((or (and verilog-indent-declaration-macros
6619 (looking-at verilog-declaration-re-2-macro))
6620 (looking-at verilog-declaration-re-2-no-macro))
6621 (let ((p (match-end 0)))
6623 (if (verilog-re-search-forward "[[#`]" p 'move)
6627 (goto-char (marker-position m1))
6633 ((verilog-continued-line-1 (marker-position startpos))
6635 (indent-line-to ind))
6636 ((verilog-in-struct-p)
6637 ;; could have a declaration of a user defined item
6639 (verilog-end-of-statement))
6640 (t ; Must be comment or white space
6642 (verilog-forward-ws&directives)
6645 (unless quiet (message "")))))))
6647 (defun verilog-pretty-expr (&optional quiet _myre)
6648 "Line up expressions around point, optionally QUIET with regexp _MYRE ignored."
6650 (if (not (verilog-in-comment-or-string-p))
6652 (let ( (rexp (concat "^\\s-*" verilog-complete-reg))
6653 (rexp1 (concat "^\\s-*" verilog-basic-complete-re)))
6655 (if (and (not (looking-at rexp ))
6656 (looking-at verilog-assignment-operation-re)
6658 (goto-char (match-end 2))
6659 (and (not (verilog-in-attribute-p))
6660 (not (verilog-in-parameter-p))
6661 (not (verilog-in-comment-or-string-p)))))
6662 (let* ((here (point))
6668 (verilog-backward-syntactic-ws)
6670 (while (and (not (looking-at rexp1))
6671 (looking-at verilog-assignment-operation-re)
6675 (verilog-backward-syntactic-ws)
6677 ) ;Ack, need to grok `define
6683 (setq e (point)) ;Might be on last line
6684 (verilog-forward-syntactic-ws)
6687 (not (looking-at rexp1 ))
6688 (looking-at verilog-assignment-operation-re)
6691 (not (eq e (point)))))
6693 (verilog-forward-syntactic-ws)
6697 (endpos (set-marker (make-marker) end))
6701 (verilog-do-indent (verilog-calculate-indent))
6702 (if (and (not quiet)
6703 (> (- end start) 100))
6704 (message "Lining up expressions..(please stand by)"))
6706 ;; Set indent to minimum throughout region
6707 (while (< (point) (marker-position endpos))
6709 (verilog-just-one-space verilog-assignment-operation-re)
6711 (verilog-do-indent (verilog-calculate-indent))
6713 (verilog-forward-syntactic-ws)
6716 ;; Now find biggest prefix
6717 (setq ind (verilog-get-lineup-indent-2 verilog-assignment-operation-re start endpos))
6719 ;; Now indent each line.
6721 (while (progn (setq e (marker-position endpos))
6722 (setq r (- e (point)))
6725 (if (not quiet) (message "%d" r))
6727 ((looking-at verilog-assignment-operation-re)
6728 (goto-char (match-beginning 2))
6729 (if (not (or (verilog-in-parenthesis-p) ;; leave attributes and comparisons alone
6730 (verilog-in-coverage-p)))
6731 (if (eq (char-after) ?=)
6732 (indent-to (1+ ind)) ; line up the = of the <= with surrounding =
6736 ((verilog-continued-line-1 start)
6738 (indent-line-to ind))
6739 (t ; Must be comment or white space
6741 (verilog-forward-ws&directives)
6745 (unless quiet (message ""))
6748 (defun verilog-just-one-space (myre)
6749 "Remove extra spaces around regular expression MYRE."
6751 (if (and (not(looking-at verilog-complete-reg))
6753 (let ((p1 (match-end 1))
6759 (just-one-space)))))
6761 (defun verilog-indent-declaration (baseind)
6762 "Indent current lines as declaration.
6763 Line up the variable names based on previous declaration's indentation.
6764 BASEIND is the base indent to offset everything."
6766 (let ((pos (point-marker))
6767 (lim (save-excursion
6768 ;; (verilog-re-search-backward verilog-declaration-opener nil 'move)
6769 (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)\\|\\(\\<task\\>\\)" nil 'move)
6775 (+ baseind (eval (cdr (assoc 'declaration verilog-indent-alist)))))
6776 (indent-line-to val)
6778 ;; Use previous declaration (in this module) as template.
6779 (if (or (eq 'all verilog-auto-lineup)
6780 (eq 'declarations verilog-auto-lineup))
6781 (if (verilog-re-search-backward
6782 (or (and verilog-indent-declaration-macros
6783 verilog-declaration-re-1-macro)
6784 verilog-declaration-re-1-no-macro) lim t)
6786 (goto-char (match-end 0))
6787 (skip-chars-forward " \t")
6788 (setq ind (current-column))
6792 (eval (cdr (assoc 'declaration verilog-indent-alist)))))
6793 (indent-line-to val)
6794 (if (and verilog-indent-declaration-macros
6795 (looking-at verilog-declaration-re-2-macro))
6796 (let ((p (match-end 0)))
6798 (if (verilog-re-search-forward "[[#`]" p 'move)
6802 (goto-char (marker-position m1))
6805 (if (/= (current-column) ind)
6809 (if (looking-at verilog-declaration-re-2-no-macro)
6810 (let ((p (match-end 0)))
6812 (if (verilog-re-search-forward "[[`#]" p 'move)
6816 (goto-char (marker-position m1))
6819 (if (/= (current-column) ind)
6822 (indent-to ind))))))))))
6825 (defun verilog-get-lineup-indent (b edpos)
6826 "Return the indent level that will line up several lines within the region.
6827 Region is defined by B and EDPOS."
6831 ;; Get rightmost position
6832 (while (progn (setq e (marker-position edpos))
6834 (if (verilog-re-search-forward
6835 (or (and verilog-indent-declaration-macros
6836 verilog-declaration-re-1-macro)
6837 verilog-declaration-re-1-no-macro) e 'move)
6839 (goto-char (match-end 0))
6840 (verilog-backward-syntactic-ws)
6841 (if (> (current-column) ind)
6842 (setq ind (current-column)))
6843 (goto-char (match-end 0)))))
6846 ;; No lineup-string found
6849 (verilog-backward-syntactic-ws)
6850 ;;(skip-chars-backward " \t")
6851 (1+ (current-column))))))
6853 (defun verilog-get-lineup-indent-2 (myre b edpos)
6854 "Return the indent level that will line up several lines within the region."
6858 ;; Get rightmost position
6859 (while (progn (setq e (marker-position edpos))
6861 (if (and (verilog-re-search-forward myre e 'move)
6862 (not (verilog-in-attribute-p))) ;; skip attribute exprs
6864 (goto-char (match-beginning 2))
6865 (verilog-backward-syntactic-ws)
6866 (if (> (current-column) ind)
6867 (setq ind (current-column)))
6868 (goto-char (match-end 0)))
6872 ;; No lineup-string found
6875 (skip-chars-backward " \t")
6876 (1+ (current-column))))))
6878 (defun verilog-comment-depth (type val)
6879 "A useful mode debugging aide. TYPE and VAL are comments for insertion."
6886 (if (re-search-backward " /\\* \[#-\]# \[a-zA-Z\]+ \[0-9\]+ ## \\*/" b t)
6888 (replace-match " /* -# ## */")
6892 (insert " /* ## ## */"))))
6895 (format "%s %d" type val))))
6901 (defvar verilog-str nil)
6902 (defvar verilog-all nil)
6903 (defvar verilog-pred nil)
6904 (defvar verilog-buffer-to-use nil)
6905 (defvar verilog-flag nil)
6906 (defvar verilog-toggle-completions nil
6907 "True means \\<verilog-mode-map>\\[verilog-complete-word] should try all possible completions one by one.
6908 Repeated use of \\[verilog-complete-word] will show you all of them.
6909 Normally, when there is more than one possible completion,
6910 it displays a list of all possible completions.")
6913 (defvar verilog-type-keywords
6915 "and" "buf" "bufif0" "bufif1" "cmos" "defparam" "inout" "input"
6916 "integer" "localparam" "logic" "mailbox" "nand" "nmos" "nor" "not" "notif0"
6917 "notif1" "or" "output" "parameter" "pmos" "pull0" "pull1" "pulldown" "pullup"
6918 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran" "rtranif0"
6919 "rtranif1" "semaphore" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1"
6920 "triand" "trior" "trireg" "wand" "wire" "wor" "xnor" "xor"
6922 "Keywords for types used when completing a word in a declaration or parmlist.
6923 \(integer, real, reg...)")
6925 (defvar verilog-cpp-keywords
6926 '("module" "macromodule" "primitive" "timescale" "define" "ifdef" "ifndef" "else"
6928 "Keywords to complete when at first word of a line in declarative scope.
6929 \(initial, always, begin, assign...)
6930 The procedures and variables defined within the Verilog program
6931 will be completed at runtime and should not be added to this list.")
6933 (defvar verilog-defun-keywords
6936 "always" "always_comb" "always_ff" "always_latch" "assign"
6937 "begin" "end" "generate" "endgenerate" "module" "endmodule"
6938 "specify" "endspecify" "function" "endfunction" "initial" "final"
6939 "task" "endtask" "primitive" "endprimitive"
6941 verilog-type-keywords)
6942 "Keywords to complete when at first word of a line in declarative scope.
6943 \(initial, always, begin, assign...)
6944 The procedures and variables defined within the Verilog program
6945 will be completed at runtime and should not be added to this list.")
6947 (defvar verilog-block-keywords
6949 "begin" "break" "case" "continue" "else" "end" "endfunction"
6950 "endgenerate" "endinterface" "endpackage" "endspecify" "endtask"
6951 "for" "fork" "if" "join" "join_any" "join_none" "repeat" "return"
6953 "Keywords to complete when at first word of a line in behavioral scope.
6954 \(begin, if, then, else, for, fork...)
6955 The procedures and variables defined within the Verilog program
6956 will be completed at runtime and should not be added to this list.")
6958 (defvar verilog-tf-keywords
6959 '("begin" "break" "fork" "join" "join_any" "join_none" "case" "end" "endtask" "endfunction" "if" "else" "for" "while" "repeat")
6960 "Keywords to complete when at first word of a line in a task or function.
6961 \(begin, if, then, else, for, fork.)
6962 The procedures and variables defined within the Verilog program
6963 will be completed at runtime and should not be added to this list.")
6965 (defvar verilog-case-keywords
6966 '("begin" "fork" "join" "join_any" "join_none" "case" "end" "endcase" "if" "else" "for" "repeat")
6967 "Keywords to complete when at first word of a line in case scope.
6968 \(begin, if, then, else, for, fork...)
6969 The procedures and variables defined within the Verilog program
6970 will be completed at runtime and should not be added to this list.")
6972 (defvar verilog-separator-keywords
6973 '("else" "then" "begin")
6974 "Keywords to complete when NOT standing at the first word of a statement.
6975 \(else, then, begin...)
6976 Variables and function names defined within the Verilog program
6977 will be completed at runtime and should not be added to this list.")
6979 (defvar verilog-gate-ios
6980 ;; All these have an implied {"input"...} at the end
6994 ("pulldown" "output")
6999 ("rtran" "inout" "inout")
7000 ("rtranif0" "inout" "inout")
7001 ("rtranif1" "inout" "inout")
7002 ("tran" "inout" "inout")
7003 ("tranif0" "inout" "inout")
7004 ("tranif1" "inout" "inout")
7007 "Map of direction for each positional argument to each gate primitive.")
7009 (defvar verilog-gate-keywords (mapcar `car verilog-gate-ios)
7010 "Keywords for gate primitives.")
7012 (defun verilog-string-diff (str1 str2)
7013 "Return index of first letter where STR1 and STR2 differs."
7017 (if (or (> (1+ diff) (length str1))
7018 (> (1+ diff) (length str2)))
7020 (or (equal (aref str1 diff) (aref str2 diff))
7022 (setq diff (1+ diff))))))
7024 ;; Calculate all possible completions for functions if argument is `function',
7025 ;; completions for procedures if argument is `procedure' or both functions and
7026 ;; procedures otherwise.
7028 (defun verilog-func-completion (type)
7029 "Build regular expression for module/task/function names.
7030 TYPE is 'module, 'tf for task or function, or t if unknown."
7031 (if (string= verilog-str "")
7032 (setq verilog-str "[a-zA-Z_]"))
7033 (let ((verilog-str (concat (cond
7034 ((eq type 'module) "\\<\\(module\\)\\s +")
7035 ((eq type 'tf) "\\<\\(task\\|function\\)\\s +")
7036 (t "\\<\\(task\\|function\\|module\\)\\s +"))
7037 "\\<\\(" verilog-str "[a-zA-Z0-9_.]*\\)\\>"))
7040 (if (not (looking-at verilog-defun-re))
7041 (verilog-re-search-backward verilog-defun-re nil t))
7044 ;; Search through all reachable functions
7045 (goto-char (point-min))
7046 (while (verilog-re-search-forward verilog-str (point-max) t)
7047 (progn (setq match (buffer-substring (match-beginning 2)
7049 (if (or (null verilog-pred)
7050 (funcall verilog-pred match))
7051 (setq verilog-all (cons match verilog-all)))))
7052 (if (match-beginning 0)
7053 (goto-char (match-beginning 0)))))
7055 (defun verilog-get-completion-decl (end)
7056 "Macro for searching through current declaration (var, type or const)
7057 for matches of `str' and adding the occurrence tp `all' through point END."
7058 (let ((re (or (and verilog-indent-declaration-macros
7059 verilog-declaration-re-2-macro)
7060 verilog-declaration-re-2-no-macro))
7063 (while (and (< (point) end)
7064 (verilog-re-search-forward re end t))
7065 ;; Traverse current line
7066 (setq decl-end (save-excursion (verilog-declaration-end)))
7067 (while (and (verilog-re-search-forward verilog-symbol-re decl-end t)
7068 (not (match-end 1)))
7069 (setq match (buffer-substring (match-beginning 0) (match-end 0)))
7070 (if (string-match (concat "\\<" verilog-str) match)
7071 (if (or (null verilog-pred)
7072 (funcall verilog-pred match))
7073 (setq verilog-all (cons match verilog-all)))))
7077 (defun verilog-var-completion ()
7078 "Calculate all possible completions for variables (or constants)."
7079 (let ((start (point)))
7080 ;; Search for all reachable var declarations
7081 (verilog-beg-of-defun)
7083 ;; Check var declarations
7084 (verilog-get-completion-decl start))))
7086 (defun verilog-keyword-completion (keyword-list)
7087 "Give list of all possible completions of keywords in KEYWORD-LIST."
7089 (if (string-match (concat "\\<" verilog-str) s)
7090 (if (or (null verilog-pred)
7091 (funcall verilog-pred s))
7092 (setq verilog-all (cons s verilog-all)))))
7096 (defun verilog-completion (verilog-str verilog-pred verilog-flag)
7097 "Function passed to `completing-read', `try-completion' or `all-completions'.
7098 Called to get completion on VERILOG-STR. If VERILOG-PRED is non-nil, it
7099 must be a function to be called for every match to check if this should
7100 really be a match. If VERILOG-FLAG is t, the function returns a list of
7101 all possible completions. If VERILOG-FLAG is nil it returns a string,
7102 the longest possible completion, or t if VERILOG-STR is an exact match.
7103 If VERILOG-FLAG is 'lambda, the function returns t if VERILOG-STR is an
7104 exact match, nil otherwise."
7106 (let ((verilog-all nil))
7107 ;; Set buffer to use for searching labels. This should be set
7108 ;; within functions which use verilog-completions
7109 (set-buffer verilog-buffer-to-use)
7111 ;; Determine what should be completed
7112 (let ((state (car (verilog-calculate-indent))))
7113 (cond ((eq state 'defun)
7114 (save-excursion (verilog-var-completion))
7115 (verilog-func-completion 'module)
7116 (verilog-keyword-completion verilog-defun-keywords))
7118 ((eq state 'behavioral)
7119 (save-excursion (verilog-var-completion))
7120 (verilog-func-completion 'module)
7121 (verilog-keyword-completion verilog-defun-keywords))
7124 (save-excursion (verilog-var-completion))
7125 (verilog-func-completion 'tf)
7126 (verilog-keyword-completion verilog-block-keywords))
7129 (save-excursion (verilog-var-completion))
7130 (verilog-func-completion 'tf)
7131 (verilog-keyword-completion verilog-case-keywords))
7134 (save-excursion (verilog-var-completion))
7135 (verilog-func-completion 'tf)
7136 (verilog-keyword-completion verilog-tf-keywords))
7139 (save-excursion (verilog-var-completion))
7140 (verilog-keyword-completion verilog-cpp-keywords))
7142 ((eq state 'cparenexp)
7143 (save-excursion (verilog-var-completion)))
7146 (save-excursion (verilog-var-completion))
7147 (verilog-func-completion 'both)
7148 (verilog-keyword-completion verilog-separator-keywords))))
7150 ;; Now we have built a list of all matches. Give response to caller
7151 (verilog-completion-response))))
7153 (defun verilog-completion-response ()
7154 (cond ((or (equal verilog-flag 'lambda) (null verilog-flag))
7155 ;; This was not called by all-completions
7156 (if (null verilog-all)
7157 ;; Return nil if there was no matching label
7159 ;; Get longest string common in the labels
7160 ;; FIXME: Why not use `try-completion'?
7161 (let* ((elm (cdr verilog-all))
7162 (match (car verilog-all))
7163 (min (length match))
7165 (if (string= match verilog-str)
7166 ;; Return t if first match was an exact match
7168 (while (not (null elm))
7169 ;; Find longest common string
7170 (if (< (setq tmp (verilog-string-diff match (car elm))) min)
7173 (setq match (substring match 0 min))))
7174 ;; Terminate with match=t if this is an exact match
7175 (if (string= (car elm) verilog-str)
7179 (setq elm (cdr elm)))))
7180 ;; If this is a test just for exact match, return nil ot t
7181 (if (and (equal verilog-flag 'lambda) (not (equal match 't)))
7184 ;; If flag is t, this was called by all-completions. Return
7185 ;; list of all possible completions
7189 (defvar verilog-last-word-numb 0)
7190 (defvar verilog-last-word-shown nil)
7191 (defvar verilog-last-completions nil)
7193 (defun verilog-complete-word ()
7194 "Complete word at current point.
7195 \(See also `verilog-toggle-completions', `verilog-type-keywords',
7196 and `verilog-separator-keywords'.)"
7197 ;; FIXME: Provide completion-at-point-function.
7199 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
7200 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
7201 (verilog-str (buffer-substring b e))
7202 ;; The following variable is used in verilog-completion
7203 (verilog-buffer-to-use (current-buffer))
7204 (allcomp (if (and verilog-toggle-completions
7205 (string= verilog-last-word-shown verilog-str))
7206 verilog-last-completions
7207 (all-completions verilog-str 'verilog-completion)))
7208 (match (if verilog-toggle-completions
7210 verilog-str (mapcar (lambda (elm)
7211 (cons elm 0)) allcomp)))))
7212 ;; Delete old string
7215 ;; Toggle-completions inserts whole labels
7216 (if verilog-toggle-completions
7218 ;; Update entry number in list
7219 (setq verilog-last-completions allcomp
7220 verilog-last-word-numb
7221 (if (>= verilog-last-word-numb (1- (length allcomp)))
7223 (1+ verilog-last-word-numb)))
7224 (setq verilog-last-word-shown (elt allcomp verilog-last-word-numb))
7225 ;; Display next match or same string if no match was found
7226 (if (not (null allcomp))
7227 (insert "" verilog-last-word-shown)
7228 (insert "" verilog-str)
7229 (message "(No match)")))
7230 ;; The other form of completion does not necessarily do that.
7232 ;; Insert match if found, or the original string if no match
7233 (if (or (null match) (equal match 't))
7234 (progn (insert "" verilog-str)
7235 (message "(No match)"))
7237 ;; Give message about current status of completion
7238 (cond ((equal match 't)
7239 (if (not (null (cdr allcomp)))
7240 (message "(Complete but not unique)")
7241 (message "(Sole completion)")))
7242 ;; Display buffer if the current completion didn't help
7243 ;; on completing the label.
7244 ((and (not (null (cdr allcomp))) (= (length verilog-str)
7246 (with-output-to-temp-buffer "*Completions*"
7247 (display-completion-list allcomp))
7248 ;; Wait for a key press. Then delete *Completion* window
7249 (momentary-string-display "" (point))
7250 (delete-window (get-buffer-window (get-buffer "*Completions*")))
7253 (defun verilog-show-completions ()
7254 "Show all possible completions at current point."
7256 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
7257 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
7258 (verilog-str (buffer-substring b e))
7259 ;; The following variable is used in verilog-completion
7260 (verilog-buffer-to-use (current-buffer))
7261 (allcomp (if (and verilog-toggle-completions
7262 (string= verilog-last-word-shown verilog-str))
7263 verilog-last-completions
7264 (all-completions verilog-str 'verilog-completion))))
7265 ;; Show possible completions in a temporary buffer.
7266 (with-output-to-temp-buffer "*Completions*"
7267 (display-completion-list allcomp))
7268 ;; Wait for a key press. Then delete *Completion* window
7269 (momentary-string-display "" (point))
7270 (delete-window (get-buffer-window (get-buffer "*Completions*")))))
7273 (defun verilog-get-default-symbol ()
7274 "Return symbol around current point as a string."
7276 (buffer-substring (progn
7277 (skip-chars-backward " \t")
7278 (skip-chars-backward "a-zA-Z0-9_")
7281 (skip-chars-forward "a-zA-Z0-9_")
7284 (defun verilog-build-defun-re (str &optional arg)
7285 "Return function/task/module starting with STR as regular expression.
7286 With optional second ARG non-nil, STR is the complete name of the instruction."
7288 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "\\)\\>")
7289 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "[a-zA-Z0-9_]*\\)\\>")))
7291 (defun verilog-comp-defun (verilog-str verilog-pred verilog-flag)
7292 "Function passed to `completing-read', `try-completion' or `all-completions'.
7293 Returns a completion on any function name based on VERILOG-STR prefix. If
7294 VERILOG-PRED is non-nil, it must be a function to be called for every match
7295 to check if this should really be a match. If VERILOG-FLAG is t, the
7296 function returns a list of all possible completions. If it is nil it
7297 returns a string, the longest possible completion, or t if VERILOG-STR is
7298 an exact match. If VERILOG-FLAG is 'lambda, the function returns t if
7299 VERILOG-STR is an exact match, nil otherwise."
7301 (let ((verilog-all nil)
7304 ;; Set buffer to use for searching labels. This should be set
7305 ;; within functions which use verilog-completions
7306 (set-buffer verilog-buffer-to-use)
7308 (let ((verilog-str verilog-str))
7309 ;; Build regular expression for functions
7310 (if (string= verilog-str "")
7311 (setq verilog-str (verilog-build-defun-re "[a-zA-Z_]"))
7312 (setq verilog-str (verilog-build-defun-re verilog-str)))
7313 (goto-char (point-min))
7315 ;; Build a list of all possible completions
7316 (while (verilog-re-search-forward verilog-str nil t)
7317 (setq match (buffer-substring (match-beginning 2) (match-end 2)))
7318 (if (or (null verilog-pred)
7319 (funcall verilog-pred match))
7320 (setq verilog-all (cons match verilog-all)))))
7322 ;; Now we have built a list of all matches. Give response to caller
7323 (verilog-completion-response))))
7325 (defun verilog-goto-defun ()
7326 "Move to specified Verilog module/interface/task/function.
7327 The default is a name found in the buffer around point.
7328 If search fails, other files are checked based on
7329 `verilog-library-flags'."
7331 (let* ((default (verilog-get-default-symbol))
7332 ;; The following variable is used in verilog-comp-function
7333 (verilog-buffer-to-use (current-buffer))
7334 (label (if (not (string= default ""))
7335 ;; Do completion with default
7336 (completing-read (concat "Goto-Label: (default "
7338 'verilog-comp-defun nil nil "")
7339 ;; There is no default value. Complete without it
7340 (completing-read "Goto-Label: "
7341 'verilog-comp-defun nil nil "")))
7343 ;; Make sure library paths are correct, in case need to resolve module
7344 (verilog-auto-reeval-locals)
7345 (verilog-getopt-flags)
7346 ;; If there was no response on prompt, use default value
7347 (if (string= label "")
7348 (setq label default))
7349 ;; Goto right place in buffer if label is not an empty string
7350 (or (string= label "")
7353 (goto-char (point-min))
7355 (re-search-forward (verilog-build-defun-re label t) nil t)))
7358 (beginning-of-line))
7360 (verilog-goto-defun-file label))))
7362 ;; Eliminate compile warning
7363 (defvar occur-pos-list)
7365 (defun verilog-showscopes ()
7366 "List all scopes in this module."
7368 (let ((buffer (current-buffer))
7372 (prevpos (point-min))
7373 (final-context-start (make-marker))
7374 (regexp "\\(module\\s-+\\w+\\s-*(\\)\\|\\(\\w+\\s-+\\w+\\s-*(\\)"))
7375 (with-output-to-temp-buffer "*Occur*"
7377 (message (format "Searching for %s ..." regexp))
7378 ;; Find next match, but give up if prev match was at end of buffer.
7379 (while (and (not (= prevpos (point-max)))
7380 (verilog-re-search-forward regexp nil t))
7381 (goto-char (match-beginning 0))
7384 (setq linenum (+ linenum (count-lines prevpos (point)))))
7385 (setq prevpos (point))
7386 (goto-char (match-end 0))
7387 (let* ((start (save-excursion
7388 (goto-char (match-beginning 0))
7389 (forward-line (if (< nlines 0) nlines (- nlines)))
7391 (end (save-excursion
7392 (goto-char (match-end 0))
7394 (forward-line (1+ nlines))
7397 (tag (format "%3d" linenum))
7398 (empty (make-string (length tag) ?\ ))
7401 (setq tem (make-marker))
7402 (set-marker tem (point))
7403 (set-buffer standard-output)
7404 (setq occur-pos-list (cons tem occur-pos-list))
7405 (or first (zerop nlines)
7406 (insert "--------\n"))
7408 (insert-buffer-substring buffer start end)
7409 (backward-char (- end start))
7410 (setq tem (if (< nlines 0) (- nlines) nlines))
7414 (setq tem (1- tem)))
7415 (let ((this-linenum linenum))
7416 (set-marker final-context-start
7417 (+ (point) (- (match-end 0) (match-beginning 0))))
7418 (while (< (point) final-context-start)
7420 (setq tag (format "%3d" this-linenum)))
7421 (insert tag ?:)))))))
7422 (set-buffer-modified-p nil))))
7425 ;; Highlight helper functions
7426 (defconst verilog-directive-regexp "\\(translate\\|coverage\\|lint\\)_")
7427 (defun verilog-within-translate-off ()
7428 "Return point if within translate-off region, else nil."
7429 (and (save-excursion
7431 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "\\(on\\|off\\)\\>")
7433 (equal "off" (match-string 2))
7436 (defun verilog-start-translate-off (limit)
7437 "Return point before translate-off directive if before LIMIT, else nil."
7438 (when (re-search-forward
7439 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
7441 (match-beginning 0)))
7443 (defun verilog-back-to-start-translate-off (limit)
7444 "Return point before translate-off directive if before LIMIT, else nil."
7445 (when (re-search-backward
7446 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
7448 (match-beginning 0)))
7450 (defun verilog-end-translate-off (limit)
7451 "Return point after translate-on directive if before LIMIT, else nil."
7453 (re-search-forward (concat
7454 "//\\s-*.*\\s-*" verilog-directive-regexp "on\\>") limit t))
7456 (defun verilog-match-translate-off (limit)
7457 "Match a translate-off block, setting `match-data' and returning t, else nil.
7458 Bound search by LIMIT."
7459 (when (< (point) limit)
7460 (let ((start (or (verilog-within-translate-off)
7461 (verilog-start-translate-off limit)))
7462 (case-fold-search t))
7464 (let ((end (or (verilog-end-translate-off limit) limit)))
7465 (set-match-data (list start end))
7466 (goto-char end))))))
7468 (defun verilog-font-lock-match-item (limit)
7469 "Match, and move over, any declaration item after point.
7470 Bound search by LIMIT. Adapted from
7471 `font-lock-match-c-style-declaration-item-and-skip-to-next'."
7474 (narrow-to-region (point-min) limit)
7476 (when (looking-at "\\s-*\\([a-zA-Z]\\w*\\)")
7478 (goto-char (match-end 1))
7479 ;; move to next item
7480 (if (looking-at "\\(\\s-*,\\)")
7481 (goto-char (match-end 1))
7486 ;; Added by Subbu Meiyappan for Header
7488 (defun verilog-header ()
7489 "Insert a standard Verilog file header.
7490 See also `verilog-sk-header' for an alternative format."
7492 (let ((start (point)))
7494 //-----------------------------------------------------------------------------
7496 // Project : <project>
7497 //-----------------------------------------------------------------------------
7498 // File : <filename>
7499 // Author : <author>
7500 // Created : <credate>
7501 // Last modified : <moddate>
7502 //-----------------------------------------------------------------------------
7505 //-----------------------------------------------------------------------------
7506 // Copyright (c) <copydate> by <company> This model is the confidential and
7507 // proprietary property of <company> and the possession or use of this
7508 // file requires a written license from <company>.
7509 //------------------------------------------------------------------------------
7510 // Modification history :
7512 //-----------------------------------------------------------------------------
7516 (search-forward "<filename>")
7517 (replace-match (buffer-name) t t)
7518 (search-forward "<author>") (replace-match "" t t)
7519 (insert (user-full-name))
7520 (insert " <" (user-login-name) "@" (system-name) ">")
7521 (search-forward "<credate>") (replace-match "" t t)
7522 (verilog-insert-date)
7523 (search-forward "<moddate>") (replace-match "" t t)
7524 (verilog-insert-date)
7525 (search-forward "<copydate>") (replace-match "" t t)
7526 (verilog-insert-year)
7527 (search-forward "<modhist>") (replace-match "" t t)
7528 (verilog-insert-date)
7529 (insert " : created")
7532 (setq string (read-string "title: "))
7533 (search-forward "<title>")
7534 (replace-match string t t)
7535 (setq string (read-string "project: " verilog-project))
7536 (setq verilog-project string)
7537 (search-forward "<project>")
7538 (replace-match string t t)
7539 (setq string (read-string "Company: " verilog-company))
7540 (setq verilog-company string)
7541 (search-forward "<company>")
7542 (replace-match string t t)
7543 (search-forward "<company>")
7544 (replace-match string t t)
7545 (search-forward "<company>")
7546 (replace-match string t t)
7547 (search-backward "<description>")
7548 (replace-match "" t t))))
7550 ;; verilog-header Uses the verilog-insert-date function
7552 (defun verilog-insert-date ()
7553 "Insert date from the system."
7555 (if verilog-date-scientific-format
7556 (insert (format-time-string "%Y/%m/%d"))
7557 (insert (format-time-string "%d.%m.%Y"))))
7559 (defun verilog-insert-year ()
7560 "Insert year from the system."
7562 (insert (format-time-string "%Y")))
7566 ;; Signal list parsing
7569 ;; Elements of a signal list
7570 ;; Unfortunately we use 'assoc' on this, so can't be a vector
7571 (defsubst verilog-sig-new (name bits comment mem enum signed type multidim modport)
7572 (list name bits comment mem enum signed type multidim modport))
7573 (defsubst verilog-sig-name (sig)
7575 (defsubst verilog-sig-bits (sig) ;; First element of packed array (pre signal-name)
7577 (defsubst verilog-sig-comment (sig)
7579 (defsubst verilog-sig-memory (sig) ;; Unpacked array (post signal-name)
7581 (defsubst verilog-sig-enum (sig)
7583 (defsubst verilog-sig-signed (sig)
7585 (defsubst verilog-sig-type (sig)
7587 (defsubst verilog-sig-type-set (sig type)
7588 (setcar (nthcdr 6 sig) type))
7589 (defsubst verilog-sig-multidim (sig) ;; Second and additional elements of packed array
7591 (defsubst verilog-sig-multidim-string (sig)
7592 (if (verilog-sig-multidim sig)
7593 (let ((str "") (args (verilog-sig-multidim sig)))
7595 (setq str (concat str (car args)))
7596 (setq args (cdr args)))
7598 (defsubst verilog-sig-modport (sig)
7600 (defsubst verilog-sig-width (sig)
7601 (verilog-make-width-expression (verilog-sig-bits sig)))
7603 (defsubst verilog-alw-new (outputs-del outputs-imm temps inputs)
7604 (vector outputs-del outputs-imm temps inputs))
7605 (defsubst verilog-alw-get-outputs-delayed (sigs)
7607 (defsubst verilog-alw-get-outputs-immediate (sigs)
7609 (defsubst verilog-alw-get-temps (sigs)
7611 (defsubst verilog-alw-get-inputs (sigs)
7613 (defsubst verilog-alw-get-uses-delayed (sigs)
7616 (defsubst verilog-modport-new (name clockings decls)
7617 (list name clockings decls))
7618 (defsubst verilog-modport-name (sig)
7620 (defsubst verilog-modport-clockings (sig)
7621 (nth 1 sig)) ;; Returns list of names
7622 (defsubst verilog-modport-clockings-add (sig val)
7623 (setcar (nthcdr 1 sig) (cons val (nth 1 sig))))
7624 (defsubst verilog-modport-decls (sig)
7625 (nth 2 sig)) ;; Returns verilog-decls-* structure
7626 (defsubst verilog-modport-decls-set (sig val)
7627 (setcar (nthcdr 2 sig) val))
7629 (defsubst verilog-modi-new (name fob pt type)
7630 (vector name fob pt type))
7631 (defsubst verilog-modi-name (modi)
7633 (defsubst verilog-modi-file-or-buffer (modi)
7635 (defsubst verilog-modi-get-point (modi)
7637 (defsubst verilog-modi-get-type (modi) ;; "module" or "interface"
7639 (defsubst verilog-modi-get-decls (modi)
7640 (verilog-modi-cache-results modi 'verilog-read-decls))
7641 (defsubst verilog-modi-get-sub-decls (modi)
7642 (verilog-modi-cache-results modi 'verilog-read-sub-decls))
7644 ;; Signal reading for given module
7645 ;; Note these all take modi's - as returned from verilog-modi-current
7646 (defsubst verilog-decls-new (out inout in vars modports assigns consts gparams interfaces)
7647 (vector out inout in vars modports assigns consts gparams interfaces))
7648 (defsubst verilog-decls-append (a b)
7649 (cond ((not a) b) ((not b) a)
7650 (t (vector (append (aref a 0) (aref b 0)) (append (aref a 1) (aref b 1))
7651 (append (aref a 2) (aref b 2)) (append (aref a 3) (aref b 3))
7652 (append (aref a 4) (aref b 4)) (append (aref a 5) (aref b 5))
7653 (append (aref a 6) (aref b 6)) (append (aref a 7) (aref b 7))
7654 (append (aref a 8) (aref b 8))))))
7655 (defsubst verilog-decls-get-outputs (decls)
7657 (defsubst verilog-decls-get-inouts (decls)
7659 (defsubst verilog-decls-get-inputs (decls)
7661 (defsubst verilog-decls-get-vars (decls)
7663 (defsubst verilog-decls-get-modports (decls) ;; Also for clocking blocks; contains another verilog-decls struct
7664 (aref decls 4)) ;; Returns verilog-modport* structure
7665 (defsubst verilog-decls-get-assigns (decls)
7667 (defsubst verilog-decls-get-consts (decls)
7669 (defsubst verilog-decls-get-gparams (decls)
7671 (defsubst verilog-decls-get-interfaces (decls)
7675 (defsubst verilog-subdecls-new (out inout in intf intfd)
7676 (vector out inout in intf intfd))
7677 (defsubst verilog-subdecls-get-outputs (subdecls)
7679 (defsubst verilog-subdecls-get-inouts (subdecls)
7681 (defsubst verilog-subdecls-get-inputs (subdecls)
7683 (defsubst verilog-subdecls-get-interfaces (subdecls)
7685 (defsubst verilog-subdecls-get-interfaced (subdecls)
7688 (defun verilog-signals-from-signame (signame-list)
7689 "Return signals in standard form from SIGNAME-LIST, a simple list of names."
7690 (mapcar (lambda (name) (verilog-sig-new name nil nil nil nil nil nil nil nil))
7693 (defun verilog-signals-in (in-list not-list)
7694 "Return list of signals in IN-LIST that are also in NOT-LIST.
7695 Also remove any duplicates in IN-LIST.
7696 Signals must be in standard (base vector) form."
7697 ;; This function is hot, so implemented as O(1)
7698 (cond ((eval-when-compile (fboundp 'make-hash-table))
7699 (let ((ht (make-hash-table :test 'equal :rehash-size 4.0))
7700 (ht-not (make-hash-table :test 'equal :rehash-size 4.0))
7703 (puthash (car (car not-list)) t ht-not)
7704 (setq not-list (cdr not-list)))
7706 (when (and (gethash (verilog-sig-name (car in-list)) ht-not)
7707 (not (gethash (verilog-sig-name (car in-list)) ht)))
7708 (setq out-list (cons (car in-list) out-list))
7709 (puthash (verilog-sig-name (car in-list)) t ht))
7710 (setq in-list (cdr in-list)))
7711 (nreverse out-list)))
7712 ;; Slower Fallback if no hash tables (pre Emacs 21.1/XEmacs 21.4)
7716 (if (and (assoc (verilog-sig-name (car in-list)) not-list)
7717 (not (assoc (verilog-sig-name (car in-list)) out-list)))
7718 (setq out-list (cons (car in-list) out-list)))
7719 (setq in-list (cdr in-list)))
7720 (nreverse out-list)))))
7721 ;;(verilog-signals-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("C" "")))
7723 (defun verilog-signals-not-in (in-list not-list)
7724 "Return list of signals in IN-LIST that aren't also in NOT-LIST.
7725 Also remove any duplicates in IN-LIST.
7726 Signals must be in standard (base vector) form."
7727 ;; This function is hot, so implemented as O(1)
7728 (cond ((eval-when-compile (fboundp 'make-hash-table))
7729 (let ((ht (make-hash-table :test 'equal :rehash-size 4.0))
7732 (puthash (car (car not-list)) t ht)
7733 (setq not-list (cdr not-list)))
7735 (when (not (gethash (verilog-sig-name (car in-list)) ht))
7736 (setq out-list (cons (car in-list) out-list))
7737 (puthash (verilog-sig-name (car in-list)) t ht))
7738 (setq in-list (cdr in-list)))
7739 (nreverse out-list)))
7740 ;; Slower Fallback if no hash tables (pre Emacs 21.1/XEmacs 21.4)
7744 (if (and (not (assoc (verilog-sig-name (car in-list)) not-list))
7745 (not (assoc (verilog-sig-name (car in-list)) out-list)))
7746 (setq out-list (cons (car in-list) out-list)))
7747 (setq in-list (cdr in-list)))
7748 (nreverse out-list)))))
7749 ;;(verilog-signals-not-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" "")))
7751 (defun verilog-signals-memory (in-list)
7752 "Return list of signals in IN-LIST that are memorized (multidimensional)."
7755 (if (nth 3 (car in-list))
7756 (setq out-list (cons (car in-list) out-list)))
7757 (setq in-list (cdr in-list)))
7759 ;;(verilog-signals-memory '(("A" nil nil "[3:0]")) '(("B" nil nil nil)))
7761 (defun verilog-signals-sort-compare (a b)
7762 "Compare signal A and B for sorting."
7763 (string< (verilog-sig-name a) (verilog-sig-name b)))
7765 (defun verilog-signals-not-params (in-list)
7766 "Return list of signals in IN-LIST that aren't parameters or numeric constants."
7769 ;; Namespace intentionally short for AUTOs and compatibility
7770 (unless (boundp (intern (concat "vh-" (verilog-sig-name (car in-list)))))
7771 (setq out-list (cons (car in-list) out-list)))
7772 (setq in-list (cdr in-list)))
7773 (nreverse out-list)))
7775 (defun verilog-signals-with (func in-list)
7776 "Return list of signals where FUNC is true executed on each signal in IN-LIST."
7779 (when (funcall func (car in-list))
7780 (setq out-list (cons (car in-list) out-list)))
7781 (setq in-list (cdr in-list)))
7782 (nreverse out-list)))
7784 (defun verilog-signals-combine-bus (in-list)
7785 "Return a list of signals in IN-LIST, with buses combined.
7786 Duplicate signals are also removed. For example A[2] and A[1] become A[2:1]."
7789 sig highbit lowbit ; Temp information about current signal
7790 sv-name sv-highbit sv-lowbit ; Details about signal we are forming
7791 sv-comment sv-memory sv-enum sv-signed sv-type sv-multidim sv-busstring
7794 ;; Shove signals so duplicated signals will be adjacent
7795 (setq in-list (sort in-list `verilog-signals-sort-compare))
7797 (setq sig (car in-list))
7798 ;; No current signal; form from existing details
7800 (setq sv-name (verilog-sig-name sig)
7803 sv-comment (verilog-sig-comment sig)
7804 sv-memory (verilog-sig-memory sig)
7805 sv-enum (verilog-sig-enum sig)
7806 sv-signed (verilog-sig-signed sig)
7807 sv-type (verilog-sig-type sig)
7808 sv-multidim (verilog-sig-multidim sig)
7809 sv-modport (verilog-sig-modport sig)
7812 ;; Extract bus details
7813 (setq bus (verilog-sig-bits sig))
7814 (setq bus (and bus (verilog-simplify-range-expression bus)))
7816 (or (and (string-match "\\[\\([0-9]+\\):\\([0-9]+\\)\\]" bus)
7817 (setq highbit (string-to-number (match-string 1 bus))
7818 lowbit (string-to-number
7819 (match-string 2 bus))))
7820 (and (string-match "\\[\\([0-9]+\\)\\]" bus)
7821 (setq highbit (string-to-number (match-string 1 bus))
7823 ;; Combine bits in bus
7825 (setq sv-highbit (max highbit sv-highbit)
7826 sv-lowbit (min lowbit sv-lowbit))
7827 (setq sv-highbit highbit
7830 ;; String, probably something like `preproc:0
7831 (setq sv-busstring bus)))
7832 ;; Peek ahead to next signal
7833 (setq in-list (cdr in-list))
7834 (setq sig (car in-list))
7835 (cond ((and sig (equal sv-name (verilog-sig-name sig)))
7836 ;; Combine with this signal
7837 (when (and sv-busstring
7838 (not (equal sv-busstring (verilog-sig-bits sig))))
7839 (when nil ;; Debugging
7840 (message (concat "Warning, can't merge into single bus "
7842 ", the AUTOs may be wrong")))
7843 (setq buswarn ", Couldn't Merge"))
7844 (if (verilog-sig-comment sig) (setq combo ", ..."))
7845 (setq sv-memory (or sv-memory (verilog-sig-memory sig))
7846 sv-enum (or sv-enum (verilog-sig-enum sig))
7847 sv-signed (or sv-signed (verilog-sig-signed sig))
7848 sv-type (or sv-type (verilog-sig-type sig))
7849 sv-multidim (or sv-multidim (verilog-sig-multidim sig))
7850 sv-modport (or sv-modport (verilog-sig-modport sig))))
7851 ;; Doesn't match next signal, add to queue, zero in prep for next
7852 ;; Note sig may also be nil for the last signal in the list
7855 (cons (verilog-sig-new
7859 (concat "[" (int-to-string sv-highbit) ":"
7860 (int-to-string sv-lowbit) "]")))
7861 (concat sv-comment combo buswarn)
7862 sv-memory sv-enum sv-signed sv-type sv-multidim sv-modport)
7868 (defun verilog-sig-tieoff (sig)
7869 "Return tieoff expression for given SIG, with appropriate width.
7870 Tieoff value uses `verilog-active-low-regexp' and
7871 `verilog-auto-reset-widths'."
7873 (if (and verilog-active-low-regexp
7874 (verilog-string-match-fold verilog-active-low-regexp (verilog-sig-name sig)))
7876 (cond ((not verilog-auto-reset-widths)
7878 ((equal verilog-auto-reset-widths 'unbased)
7880 ;; Else presume verilog-auto-reset-widths is true
7882 (let* ((width (verilog-sig-width sig)))
7885 ((string-match "^[0-9]+$" width)
7886 (concat width (if (verilog-sig-signed sig) "'sh0" "'h0")))
7888 (concat "{" width "{1'b0}}"))))))))
7894 (defun verilog-decls-princ (decls &optional header prefix)
7895 "For debug, dump the `verilog-read-decls' structure DECLS."
7897 (if header (princ header))
7898 (setq prefix (or prefix ""))
7899 (verilog-signals-princ (verilog-decls-get-outputs decls)
7900 (concat prefix "Outputs:\n") (concat prefix " "))
7901 (verilog-signals-princ (verilog-decls-get-inouts decls)
7902 (concat prefix "Inout:\n") (concat prefix " "))
7903 (verilog-signals-princ (verilog-decls-get-inputs decls)
7904 (concat prefix "Inputs:\n") (concat prefix " "))
7905 (verilog-signals-princ (verilog-decls-get-vars decls)
7906 (concat prefix "Vars:\n") (concat prefix " "))
7907 (verilog-signals-princ (verilog-decls-get-assigns decls)
7908 (concat prefix "Assigns:\n") (concat prefix " "))
7909 (verilog-signals-princ (verilog-decls-get-consts decls)
7910 (concat prefix "Consts:\n") (concat prefix " "))
7911 (verilog-signals-princ (verilog-decls-get-gparams decls)
7912 (concat prefix "Gparams:\n") (concat prefix " "))
7913 (verilog-signals-princ (verilog-decls-get-interfaces decls)
7914 (concat prefix "Interfaces:\n") (concat prefix " "))
7915 (verilog-modport-princ (verilog-decls-get-modports decls)
7916 (concat prefix "Modports:\n") (concat prefix " "))
7919 (defun verilog-signals-princ (signals &optional header prefix)
7920 "For debug, dump internal SIGNALS structures, with HEADER and PREFIX."
7922 (if header (princ header))
7924 (let ((sig (car signals)))
7925 (setq signals (cdr signals))
7927 (princ "\"") (princ (verilog-sig-name sig)) (princ "\"")
7928 (princ " bits=") (princ (verilog-sig-bits sig))
7929 (princ " cmt=") (princ (verilog-sig-comment sig))
7930 (princ " mem=") (princ (verilog-sig-memory sig))
7931 (princ " enum=") (princ (verilog-sig-enum sig))
7932 (princ " sign=") (princ (verilog-sig-signed sig))
7933 (princ " type=") (princ (verilog-sig-type sig))
7934 (princ " dim=") (princ (verilog-sig-multidim sig))
7935 (princ " modp=") (princ (verilog-sig-modport sig))
7938 (defun verilog-modport-princ (modports &optional header prefix)
7939 "For debug, dump internal MODPORT structures, with HEADER and PREFIX."
7941 (if header (princ header))
7943 (let ((sig (car modports)))
7944 (setq modports (cdr modports))
7946 (princ "\"") (princ (verilog-modport-name sig)) (princ "\"")
7947 (princ " clockings=") (princ (verilog-modport-clockings sig))
7949 (verilog-decls-princ (verilog-modport-decls sig)
7950 (concat prefix " syms:\n")
7951 (concat prefix " "))))))
7954 ;; Port/Wire/Etc Reading
7957 (defun verilog-read-inst-backward-name ()
7958 "Internal. Move point back to beginning of inst-name."
7959 (verilog-backward-open-paren)
7962 (verilog-re-search-backward-quick "\\()\\|\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil) ; ] isn't word boundary
7963 (cond ((looking-at ")")
7964 (verilog-backward-open-paren))
7965 (t (setq done t)))))
7966 (while (looking-at "\\]")
7967 (verilog-backward-open-bracket)
7968 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil))
7969 (skip-chars-backward "a-zA-Z0-9`_$"))
7971 (defun verilog-read-inst-module-matcher ()
7972 "Set match data 0 with module_name when point is inside instantiation."
7973 (verilog-read-inst-backward-name)
7974 ;; Skip over instantiation name
7975 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary
7976 ;; Check for parameterized instantiations
7977 (when (looking-at ")")
7978 (verilog-backward-open-paren)
7979 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil))
7980 (skip-chars-backward "a-zA-Z0-9'_$")
7981 ;; #1 is legal syntax for gate primitives
7982 (when (save-excursion
7983 (verilog-backward-syntactic-ws-quick)
7984 (eq ?# (char-before)))
7985 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil)
7986 (skip-chars-backward "a-zA-Z0-9'_$"))
7987 (looking-at "[a-zA-Z0-9`_\$]+")
7988 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
7989 (buffer-substring-no-properties (match-beginning 0) (match-end 0))
7990 ;; Caller assumes match-beginning/match-end is still set
7993 (defun verilog-read-inst-module ()
7994 "Return module_name when point is inside instantiation."
7996 (verilog-read-inst-module-matcher)))
7998 (defun verilog-read-inst-name ()
7999 "Return instance_name when point is inside instantiation."
8001 (verilog-read-inst-backward-name)
8002 (looking-at "[a-zA-Z0-9`_\$]+")
8003 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
8004 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
8006 (defun verilog-read-module-name ()
8007 "Return module name when after its ( or ;."
8009 (re-search-backward "[(;]")
8010 ;; Due to "module x import y (" we must search for declaration begin
8011 (verilog-re-search-backward-quick verilog-defun-re nil nil)
8012 (goto-char (match-end 0))
8013 (verilog-re-search-forward-quick "\\b[a-zA-Z0-9`_\$]+" nil nil)
8014 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
8015 (verilog-symbol-detick
8016 (buffer-substring-no-properties (match-beginning 0) (match-end 0)) t)))
8018 (defun verilog-read-inst-param-value ()
8019 "Return list of parameters and values when point is inside instantiation."
8021 (verilog-read-inst-backward-name)
8022 ;; Skip over instantiation name
8023 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary
8024 ;; If there are parameterized instantiations
8025 (when (looking-at ")")
8026 (let ((end-pt (point))
8028 param-name paren-beg-pt param-value)
8029 (verilog-backward-open-paren)
8030 (while (verilog-re-search-forward-quick "\\." end-pt t)
8031 (verilog-re-search-forward-quick "\\([a-zA-Z0-9`_\$]\\)" nil nil)
8032 (skip-chars-backward "a-zA-Z0-9'_$")
8033 (looking-at "[a-zA-Z0-9`_\$]+")
8034 (setq param-name (buffer-substring-no-properties
8035 (match-beginning 0) (match-end 0)))
8036 (verilog-re-search-forward-quick "(" nil nil)
8037 (setq paren-beg-pt (point))
8038 (verilog-forward-close-paren)
8039 (setq param-value (verilog-string-remove-spaces
8040 (buffer-substring-no-properties
8041 paren-beg-pt (1- (point)))))
8042 (setq params (cons (list param-name param-value) params)))
8045 (defun verilog-read-auto-params (num-param &optional max-param)
8046 "Return parameter list inside auto.
8047 Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters."
8050 ;; /*AUTOPUNT("parameter", "parameter")*/
8052 (while (looking-at "(?\\s *\"\\([^\"]*\\)\"\\s *,?")
8053 (setq olist (cons (match-string 1) olist))
8054 (goto-char (match-end 0))))
8055 (or (eq nil num-param)
8056 (<= num-param (length olist))
8057 (error "%s: Expected %d parameters" (verilog-point-text) num-param))
8058 (if (eq max-param nil) (setq max-param num-param))
8059 (or (eq nil max-param)
8060 (>= max-param (length olist))
8061 (error "%s: Expected <= %d parameters" (verilog-point-text) max-param))
8064 (defun verilog-read-decls ()
8065 "Compute signal declaration information for the current module at point.
8066 Return an array of [outputs inouts inputs wire reg assign const]."
8067 (let ((end-mod-point (or (verilog-get-end-of-defun) (point-max)))
8068 (functask 0) (paren 0) (sig-paren 0) (v2kargs-ok t)
8069 in-modport in-clocking in-ign-to-semi ptype ign-prop
8070 sigs-in sigs-out sigs-inout sigs-var sigs-assign sigs-const
8071 sigs-gparam sigs-intf sigs-modports
8072 vec expect-signal keywd newsig rvalue enum io signed typedefed multidim
8075 ;;(if dbg (setq dbg (concat dbg (format "\n\nverilog-read-decls START PT %s END %s\n" (point) end-mod-point))))
8077 (verilog-beg-of-defun-quick)
8078 (setq sigs-const (verilog-read-auto-constants (point) end-mod-point))
8079 (while (< (point) end-mod-point)
8080 ;;(if dbg (setq dbg (concat dbg (format "Pt %s Vec %s C%c Kwd'%s'\n" (point) vec (following-char) keywd))))
8083 (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
8084 (setq enum (match-string 2)))
8085 (search-forward "\n"))
8086 ((looking-at "/\\*")
8088 (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
8089 (setq enum (match-string 2)))
8090 (or (search-forward "*/")
8091 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8092 ((looking-at "(\\*")
8093 ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
8095 (or (search-forward "*)")
8096 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
8097 ((eq ?\" (following-char))
8098 (or (re-search-forward "[^\\]\"" nil t) ;; don't forward-char first, since we look for a non backslash first
8099 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
8100 ((eq ?\; (following-char))
8101 (cond (in-ign-to-semi ;; Such as inside a "import ...;" in a module header
8102 (setq in-ign-to-semi nil))
8103 ((and in-modport (not (eq in-modport t))) ;; end of a modport declaration
8104 (verilog-modport-decls-set
8106 (verilog-decls-new sigs-out sigs-inout sigs-in
8107 nil nil nil nil nil nil))
8108 ;; Pop from varstack to restore state to pre-clocking
8109 (setq tmp (car varstack)
8110 varstack (cdr varstack)
8111 sigs-out (aref tmp 0)
8112 sigs-inout (aref tmp 1)
8113 sigs-in (aref tmp 2))
8114 (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil
8115 v2kargs-ok nil in-modport nil ign-prop nil))
8117 (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil
8118 v2kargs-ok nil in-modport nil ign-prop nil)))
8120 ((eq ?= (following-char))
8121 (setq rvalue t newsig nil)
8123 ((and (eq ?, (following-char))
8124 (eq paren sig-paren))
8127 ;; ,'s can occur inside {} & funcs
8128 ((looking-at "[{(]")
8129 (setq paren (1+ paren))
8131 ((looking-at "[})]")
8132 (setq paren (1- paren))
8134 (when (< paren sig-paren)
8135 (setq expect-signal nil rvalue nil))) ; ) that ends variables inside v2k arg list
8136 ((looking-at "\\s-*\\(\\[[^]]+\\]\\)")
8137 (goto-char (match-end 0))
8138 (cond (newsig ; Memory, not just width. Patch last signal added's memory (nth 3)
8139 (setcar (cdr (cdr (cdr newsig)))
8140 (if (verilog-sig-memory newsig)
8141 (concat (verilog-sig-memory newsig) (match-string 1))
8143 (vec ;; Multidimensional
8144 (setq multidim (cons vec multidim))
8145 (setq vec (verilog-string-replace-matches
8146 "\\s-+" "" nil nil (match-string 1))))
8148 (setq vec (verilog-string-replace-matches
8149 "\\s-+" "" nil nil (match-string 1))))))
8150 ;; Normal or escaped identifier -- note we remember the \ if escaped
8151 ((looking-at "\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
8152 (goto-char (match-end 0))
8153 (setq keywd (match-string 1))
8154 (when (string-match "^\\\\" (match-string 1))
8155 (setq keywd (concat keywd " "))) ;; Escaped ID needs space at end
8156 ;; Add any :: package names to same identifier
8157 (while (looking-at "\\s-*::\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
8158 (goto-char (match-end 0))
8159 (setq keywd (concat keywd "::" (match-string 1)))
8160 (when (string-match "^\\\\" (match-string 1))
8161 (setq keywd (concat keywd " ")))) ;; Escaped ID needs space at end
8162 (cond ((equal keywd "input")
8163 (setq vec nil enum nil rvalue nil newsig nil signed nil
8164 typedefed nil multidim nil ptype nil modport nil
8165 expect-signal 'sigs-in io t sig-paren paren))
8166 ((equal keywd "output")
8167 (setq vec nil enum nil rvalue nil newsig nil signed nil
8168 typedefed nil multidim nil ptype nil modport nil
8169 expect-signal 'sigs-out io t sig-paren paren))
8170 ((equal keywd "inout")
8171 (setq vec nil enum nil rvalue nil newsig nil signed nil
8172 typedefed nil multidim nil ptype nil modport nil
8173 expect-signal 'sigs-inout io t sig-paren paren))
8174 ((equal keywd "parameter")
8175 (setq vec nil enum nil rvalue nil signed nil
8176 typedefed nil multidim nil ptype nil modport nil
8177 expect-signal 'sigs-gparam io t sig-paren paren))
8178 ((member keywd '("wire" "reg" ; Fast
8180 "tri" "tri0" "tri1" "triand" "trior" "trireg"
8181 "uwire" "wand" "wor"
8182 ;; integer_atom_type
8183 "byte" "shortint" "int" "longint" "integer" "time"
8185 ;; integer_vector_type - "reg" above
8188 "shortreal" "real" "realtime"
8190 "string" "event" "chandle"))
8193 (if typedefed (concat typedefed " " keywd) keywd)))
8194 (t (setq vec nil enum nil rvalue nil signed nil
8195 typedefed nil multidim nil sig-paren paren
8196 expect-signal 'sigs-var modport nil))))
8197 ((equal keywd "assign")
8198 (setq vec nil enum nil rvalue nil signed nil
8199 typedefed nil multidim nil ptype nil modport nil
8200 expect-signal 'sigs-assign sig-paren paren))
8201 ((member keywd '("localparam" "genvar"))
8203 (setq vec nil enum nil rvalue nil signed nil
8204 typedefed nil multidim nil ptype nil modport nil
8205 expect-signal 'sigs-const sig-paren paren)))
8206 ((member keywd '("signed" "unsigned"))
8207 (setq signed keywd))
8208 ((member keywd '("assert" "assume" "cover" "expect" "restrict"))
8210 ((member keywd '("class" "covergroup" "function"
8211 "property" "randsequence" "sequence" "task"))
8213 (setq functask (1+ functask))))
8214 ((member keywd '("endclass" "endgroup" "endfunction"
8215 "endproperty" "endsequence" "endtask"))
8216 (setq functask (1- functask)))
8217 ((equal keywd "modport")
8218 (setq in-modport t))
8219 ((equal keywd "clocking")
8220 (setq in-clocking t))
8221 ((equal keywd "import")
8222 (if v2kargs-ok ;; import in module header, not a modport import
8223 (setq in-ign-to-semi t rvalue t)))
8224 ((equal keywd "type")
8226 ((equal keywd "var"))
8227 ;; Ifdef? Ignore name of define
8228 ((member keywd '("`ifdef" "`ifndef" "`elsif"))
8232 (verilog-typedef-name-p keywd))
8235 (if typedefed (concat typedefed " " keywd) keywd)))
8236 (t (setq vec nil enum nil rvalue nil signed nil
8237 typedefed nil multidim nil sig-paren paren
8238 expect-signal 'sigs-var modport nil))))
8239 ;; Interface with optional modport in v2k arglist?
8240 ;; Skip over parsing modport, and take the interface name as the type
8244 (looking-at "\\s-*\\(\\.\\(\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*\\)\\|\\)\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*"))
8245 (when (match-end 2) (goto-char (match-end 2)))
8246 (setq vec nil enum nil rvalue nil signed nil
8247 typedefed keywd multidim nil ptype nil modport (match-string 2)
8248 newsig nil sig-paren paren
8249 expect-signal 'sigs-intf io t ))
8250 ;; Ignore dotted LHS assignments: "assign foo.bar = z;"
8251 ((looking-at "\\s-*\\.")
8252 (goto-char (match-end 0))
8254 (setq expect-signal nil)))
8255 ;; "modport <keywd>"
8256 ((and (eq in-modport t)
8257 (not (member keywd verilog-keywords)))
8258 (setq in-modport (verilog-modport-new keywd nil nil))
8259 (setq sigs-modports (cons in-modport sigs-modports))
8260 ;; Push old sig values to stack and point to new signal list
8261 (setq varstack (cons (vector sigs-out sigs-inout sigs-in)
8263 (setq sigs-in nil sigs-inout nil sigs-out nil))
8264 ;; "modport x (clocking <keywd>)"
8265 ((and in-modport in-clocking)
8266 (verilog-modport-clockings-add in-modport keywd)
8267 (setq in-clocking nil))
8270 (equal keywd "endclocking"))
8271 (unless (eq in-clocking t)
8272 (verilog-modport-decls-set
8274 (verilog-decls-new sigs-out sigs-inout sigs-in
8275 nil nil nil nil nil nil))
8276 ;; Pop from varstack to restore state to pre-clocking
8277 (setq tmp (car varstack)
8278 varstack (cdr varstack)
8279 sigs-out (aref tmp 0)
8280 sigs-inout (aref tmp 1)
8281 sigs-in (aref tmp 2)))
8282 (setq in-clocking nil))
8283 ;; "clocking <keywd>"
8284 ((and (eq in-clocking t)
8285 (not (member keywd verilog-keywords)))
8286 (setq in-clocking (verilog-modport-new keywd nil nil))
8287 (setq sigs-modports (cons in-clocking sigs-modports))
8288 ;; Push old sig values to stack and point to new signal list
8289 (setq varstack (cons (vector sigs-out sigs-inout sigs-in)
8291 (setq sigs-in nil sigs-inout nil sigs-out nil))
8292 ;; New signal, maybe?
8296 (not (member keywd verilog-keywords)))
8297 ;; Add new signal to expect-signal's variable
8298 ;;(if dbg (setq dbg (concat dbg (format "Pt %s New sig %s'\n" (point) keywd))))
8299 (setq newsig (verilog-sig-new keywd vec nil nil enum signed typedefed multidim modport))
8300 (set expect-signal (cons newsig
8301 (symbol-value expect-signal))))))
8304 (skip-syntax-forward " "))
8306 (setq tmp (verilog-decls-new (nreverse sigs-out)
8307 (nreverse sigs-inout)
8310 (nreverse sigs-modports)
8311 (nreverse sigs-assign)
8312 (nreverse sigs-const)
8313 (nreverse sigs-gparam)
8314 (nreverse sigs-intf)))
8315 ;;(if dbg (verilog-decls-princ tmp))
8318 (defvar verilog-read-sub-decls-in-interfaced nil
8319 "For `verilog-read-sub-decls', process next signal as under interfaced block.")
8321 (defvar verilog-read-sub-decls-gate-ios nil
8322 "For `verilog-read-sub-decls', gate IO pins remaining, nil if non-primitive.")
8325 ;; Prevent compile warnings; these are let's, not globals
8326 ;; Do not remove the eval-when-compile
8327 ;; - we want an error when we are debugging this code if they are refed.
8335 (defvar sigs-out-unk)
8337 ;; These are known to be from other packages and may not be defined
8338 (defvar diff-command nil)
8339 (defvar vector-skip-list)
8340 ;; There are known to be from newer versions of Emacs
8341 (defvar create-lockfiles))
8343 (defun verilog-read-sub-decls-sig (submoddecls comment port sig vec multidim)
8344 "For `verilog-read-sub-decls-line', add a signal."
8345 ;; sig eq t to indicate .name syntax
8346 ;;(message "vrsds: %s(%S)" port sig)
8347 (let ((dotname (eq sig t))
8350 (setq port (verilog-symbol-detick-denumber port))
8351 (setq sig (if dotname port (verilog-symbol-detick-denumber sig)))
8352 (if vec (setq vec (verilog-symbol-detick-denumber vec)))
8353 (if multidim (setq multidim (mapcar `verilog-symbol-detick-denumber multidim)))
8354 (unless (or (not sig)
8355 (equal sig "")) ;; Ignore .foo(1'b1) assignments
8356 (cond ((or (setq portdata (assoc port (verilog-decls-get-inouts submoddecls)))
8357 (equal "inout" verilog-read-sub-decls-gate-ios))
8359 (cons (verilog-sig-new
8361 (if dotname (verilog-sig-bits portdata) vec)
8362 (concat "To/From " comment)
8363 (verilog-sig-memory portdata)
8365 (verilog-sig-signed portdata)
8366 (unless (member (verilog-sig-type portdata) '("wire" "reg"))
8367 (verilog-sig-type portdata))
8370 ((or (setq portdata (assoc port (verilog-decls-get-outputs submoddecls)))
8371 (equal "output" verilog-read-sub-decls-gate-ios))
8373 (cons (verilog-sig-new
8375 (if dotname (verilog-sig-bits portdata) vec)
8376 (concat "From " comment)
8377 (verilog-sig-memory portdata)
8379 (verilog-sig-signed portdata)
8380 ;; Though ok in SV, in V2K code, propagating the
8381 ;; "reg" in "output reg" upwards isn't legal.
8382 ;; Also for backwards compatibility we don't propagate
8383 ;; "input wire" upwards.
8384 ;; See also `verilog-signals-edit-wire-reg'.
8385 (unless (member (verilog-sig-type portdata) '("wire" "reg"))
8386 (verilog-sig-type portdata))
8389 ((or (setq portdata (assoc port (verilog-decls-get-inputs submoddecls)))
8390 (equal "input" verilog-read-sub-decls-gate-ios))
8392 (cons (verilog-sig-new
8394 (if dotname (verilog-sig-bits portdata) vec)
8395 (concat "To " comment)
8396 (verilog-sig-memory portdata)
8398 (verilog-sig-signed portdata)
8399 (unless (member (verilog-sig-type portdata) '("wire" "reg"))
8400 (verilog-sig-type portdata))
8403 ((setq portdata (assoc port (verilog-decls-get-interfaces submoddecls)))
8405 (cons (verilog-sig-new
8407 (if dotname (verilog-sig-bits portdata) vec)
8408 (concat "To/From " comment)
8409 (verilog-sig-memory portdata)
8411 (verilog-sig-signed portdata)
8412 (verilog-sig-type portdata)
8415 ((setq portdata (and verilog-read-sub-decls-in-interfaced
8416 (assoc port (verilog-decls-get-vars submoddecls))))
8418 (cons (verilog-sig-new
8420 (if dotname (verilog-sig-bits portdata) vec)
8421 (concat "To/From " comment)
8422 (verilog-sig-memory portdata)
8424 (verilog-sig-signed portdata)
8425 (verilog-sig-type portdata)
8428 ;; (t -- warning pin isn't defined.) ; Leave for lint tool
8431 (defun verilog-read-sub-decls-expr (submoddecls comment port expr)
8432 "For `verilog-read-sub-decls-line', parse a subexpression and add signals."
8433 ;;(message "vrsde: '%s'" expr)
8434 ;; Replace special /*[....]*/ comments inserted by verilog-auto-inst-port
8435 (setq expr (verilog-string-replace-matches "/\\*\\(\\[[^*]+\\]\\)\\*/" "\\1" nil nil expr))
8436 ;; Remove front operators
8437 (setq expr (verilog-string-replace-matches "^\\s-*[---+~!|&]+\\s-*" "" nil nil expr))
8440 ;; {..., a, b} requires us to recurse on a,b
8441 ;; To support {#{},{#{a,b}} we'll just split everything on [{},]
8442 ((string-match "^\\s-*{\\(.*\\)}\\s-*$" expr)
8443 (unless verilog-auto-ignore-concat
8444 (let ((mlst (split-string (match-string 1 expr) "[{},]"))
8446 (while (setq mstr (pop mlst))
8447 (verilog-read-sub-decls-expr submoddecls comment port mstr)))))
8449 (let (sig vec multidim)
8450 ;; Remove leading reduction operators, etc
8451 (setq expr (verilog-string-replace-matches "^\\s-*[---+~!|&]+\\s-*" "" nil nil expr))
8452 ;;(message "vrsde-ptop: '%s'" expr)
8453 (cond ;; Find \signal. Final space is part of escaped signal name
8454 ((string-match "^\\s-*\\(\\\\[^ \t\n\f]+\\s-\\)" expr)
8455 ;;(message "vrsde-s: '%s'" (match-string 1 expr))
8456 (setq sig (match-string 1 expr)
8457 expr (substring expr (match-end 0))))
8459 ((string-match "^\\s-*\\([a-zA-Z_][a-zA-Z_0-9]*\\)" expr)
8460 ;;(message "vrsde-s: '%s'" (match-string 1 expr))
8461 (setq sig (verilog-string-remove-spaces (match-string 1 expr))
8462 expr (substring expr (match-end 0)))))
8463 ;; Find [vector] or [multi][multi][multi][vector]
8464 (while (string-match "^\\s-*\\(\\[[^]]+\\]\\)" expr)
8465 ;;(message "vrsde-v: '%s'" (match-string 1 expr))
8466 (when vec (setq multidim (cons vec multidim)))
8467 (setq vec (match-string 1 expr)
8468 expr (substring expr (match-end 0))))
8469 ;; If found signal, and nothing unrecognized, add the signal
8470 ;;(message "vrsde-rem: '%s'" expr)
8471 (when (and sig (string-match "^\\s-*$" expr))
8472 (verilog-read-sub-decls-sig submoddecls comment port sig vec multidim))))))
8474 (defun verilog-read-sub-decls-line (submoddecls comment)
8475 "For `verilog-read-sub-decls', read lines of port defs until none match.
8476 Inserts the list of signals found, using submodi to look up each port."
8482 (cond ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*(\\s-*")
8483 (setq port (match-string 1))
8484 (goto-char (match-end 0)))
8486 ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*(\\s-*")
8487 (setq port (concat (match-string 1) " ")) ;; escaped id's need trailing space
8488 (goto-char (match-end 0)))
8490 ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*[,)/]")
8491 (verilog-read-sub-decls-sig
8492 submoddecls comment (match-string 1) t ; sig==t for .name
8493 nil nil) ; vec multidim
8496 ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*[,)/]")
8497 (verilog-read-sub-decls-sig
8498 submoddecls comment (concat (match-string 1) " ") t ; sig==t for .name
8499 nil nil) ; vec multidim
8502 ((looking-at "\\s-*\\.[^(]*(")
8503 (setq port nil) ;; skip this line
8504 (goto-char (match-end 0)))
8506 (setq port nil done t))) ;; Unknown, ignore rest of line
8507 ;; Get signal name. Point is at the first-non-space after (
8508 ;; We intentionally ignore (non-escaped) signals with .s in them
8509 ;; this prevents AUTOWIRE etc from noticing hierarchical sigs.
8511 (cond ((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*)")
8512 (verilog-read-sub-decls-sig
8513 submoddecls comment port
8514 (verilog-string-remove-spaces (match-string 1)) ; sig
8515 nil nil)) ; vec multidim
8517 ((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*)")
8518 (verilog-read-sub-decls-sig
8519 submoddecls comment port
8520 (verilog-string-remove-spaces (match-string 1)) ; sig
8521 (match-string 2) nil)) ; vec multidim
8522 ;; Fastpath was above looking-at's.
8523 ;; For something more complicated invoke a parser
8524 ((looking-at "[^)]+")
8525 (verilog-read-sub-decls-expr
8526 submoddecls comment port
8528 (point) (1- (progn (search-backward "(") ; start at (
8529 (verilog-forward-sexp-ign-cmt 1)
8530 (point)))))))) ; expr
8532 (forward-line 1)))))
8534 (defun verilog-read-sub-decls-gate (submoddecls comment submod end-inst-point)
8535 "For `verilog-read-sub-decls', read lines of UDP gate decl until none match.
8536 Inserts the list of signals found."
8538 (let ((iolist (cdr (assoc submod verilog-gate-ios))))
8539 (while (< (point) end-inst-point)
8540 ;; Get primitive's signal name, as will never have port, and no trailing )
8541 (cond ((looking-at "//")
8542 (search-forward "\n"))
8543 ((looking-at "/\\*")
8544 (or (search-forward "*/")
8545 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8546 ((looking-at "(\\*")
8547 ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
8549 (or (search-forward "*)")
8550 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
8551 ;; On pins, parse and advance to next pin
8552 ;; Looking at pin, but *not* an // Output comment, or ) to end the inst
8553 ((looking-at "\\s-*[a-zA-Z0-9`_$({}\\\\][^,]*")
8554 (goto-char (match-end 0))
8555 (setq verilog-read-sub-decls-gate-ios (or (car iolist) "input")
8556 iolist (cdr iolist))
8557 (verilog-read-sub-decls-expr
8558 submoddecls comment "primitive_port"
8562 (skip-syntax-forward " ")))))))
8564 (defun verilog-read-sub-decls ()
8565 "Internally parse signals going to modules under this module.
8566 Return an array of [ outputs inouts inputs ] signals for modules that are
8567 instantiated in this module. For example if declare A A (.B(SIG)) and SIG
8568 is an output, then SIG will be included in the list.
8570 This only works on instantiations created with /*AUTOINST*/ converted by
8571 \\[verilog-auto-inst]. Otherwise, it would have to read in the whole
8572 component library to determine connectivity of the design.
8574 One work around for this problem is to manually create // Inputs and //
8575 Outputs comments above subcell signals, for example:
8583 (let ((end-mod-point (verilog-get-end-of-defun))
8584 st-point end-inst-point
8585 ;; below 3 modified by verilog-read-sub-decls-line
8586 sigs-out sigs-inout sigs-in sigs-intf sigs-intfd)
8587 (verilog-beg-of-defun-quick)
8588 (while (verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-mod-point t)
8590 (goto-char (match-beginning 0))
8591 (unless (verilog-inside-comment-or-string-p)
8592 ;; Attempt to snarf a comment
8593 (let* ((submod (verilog-read-inst-module))
8594 (inst (verilog-read-inst-name))
8595 (subprim (member submod verilog-gate-keywords))
8596 (comment (concat inst " of " submod ".v"))
8597 submodi submoddecls)
8600 (setq submodi `primitive
8601 submoddecls (verilog-decls-new nil nil nil nil nil nil nil nil nil)
8602 comment (concat inst " of " submod))
8603 (verilog-backward-open-paren)
8604 (setq end-inst-point (save-excursion (verilog-forward-sexp-ign-cmt 1)
8608 (verilog-read-sub-decls-gate submoddecls comment submod end-inst-point))
8611 (when (setq submodi (verilog-modi-lookup submod t))
8612 (setq submoddecls (verilog-modi-get-decls submodi)
8613 verilog-read-sub-decls-gate-ios nil)
8614 (verilog-backward-open-paren)
8615 (setq end-inst-point (save-excursion (verilog-forward-sexp-ign-cmt 1)
8618 ;; This could have used a list created by verilog-auto-inst
8619 ;; However I want it to be runnable even on user's manually added signals
8620 (let ((verilog-read-sub-decls-in-interfaced t))
8621 (while (re-search-forward "\\s *(?\\s *// Interfaced" end-inst-point t)
8622 (verilog-read-sub-decls-line submoddecls comment))) ;; Modifies sigs-ifd
8623 (goto-char st-point)
8624 (while (re-search-forward "\\s *(?\\s *// Interfaces" end-inst-point t)
8625 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-out
8626 (goto-char st-point)
8627 (while (re-search-forward "\\s *(?\\s *// Outputs" end-inst-point t)
8628 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-out
8629 (goto-char st-point)
8630 (while (re-search-forward "\\s *(?\\s *// Inouts" end-inst-point t)
8631 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-inout
8632 (goto-char st-point)
8633 (while (re-search-forward "\\s *(?\\s *// Inputs" end-inst-point t)
8634 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-in
8636 ;; Combine duplicate bits
8637 ;;(setq rr (vector sigs-out sigs-inout sigs-in))
8638 (verilog-subdecls-new
8639 (verilog-signals-combine-bus (nreverse sigs-out))
8640 (verilog-signals-combine-bus (nreverse sigs-inout))
8641 (verilog-signals-combine-bus (nreverse sigs-in))
8642 (verilog-signals-combine-bus (nreverse sigs-intf))
8643 (verilog-signals-combine-bus (nreverse sigs-intfd))))))
8645 (defun verilog-read-inst-pins ()
8646 "Return an array of [ pins ] for the current instantiation at point.
8647 For example if declare A A (.B(SIG)) then B will be included in the list."
8649 (let ((end-mod-point (point)) ;; presume at /*AUTOINST*/ point
8651 (verilog-backward-open-paren)
8652 (while (re-search-forward "\\.\\([^(,) \t\n\f]*\\)\\s-*" end-mod-point t)
8653 (setq pin (match-string 1))
8654 (unless (verilog-inside-comment-or-string-p)
8655 (setq pins (cons (list pin) pins))
8656 (when (looking-at "(")
8657 (verilog-forward-sexp-ign-cmt 1))))
8660 (defun verilog-read-arg-pins ()
8661 "Return an array of [ pins ] for the current argument declaration at point."
8663 (let ((end-mod-point (point)) ;; presume at /*AUTOARG*/ point
8665 (verilog-backward-open-paren)
8666 (while (re-search-forward "\\([a-zA-Z0-9$_.%`]+\\)" end-mod-point t)
8667 (setq pin (match-string 1))
8668 (unless (verilog-inside-comment-or-string-p)
8669 (setq pins (cons (list pin) pins))))
8672 (defun verilog-read-auto-constants (beg end-mod-point)
8673 "Return a list of AUTO_CONSTANTs used in the region from BEG to END-MOD-POINT."
8676 (let (sig-list tpl-end-pt)
8678 (while (re-search-forward "\\<AUTO_CONSTANT" end-mod-point t)
8679 (if (not (looking-at "\\s *("))
8680 (error "%s: Missing () after AUTO_CONSTANT" (verilog-point-text)))
8681 (search-forward "(" end-mod-point)
8682 (setq tpl-end-pt (save-excursion
8684 (verilog-forward-sexp-cmt 1) ;; Moves to paren that closes argdecl's
8687 (while (re-search-forward "\\s-*\\([\"a-zA-Z0-9$_.%`]+\\)\\s-*,*" tpl-end-pt t)
8688 (setq sig-list (cons (list (match-string 1) nil nil) sig-list))))
8691 (defvar verilog-cache-has-lisp nil "True if any AUTO_LISP in buffer.")
8692 (make-variable-buffer-local 'verilog-cache-has-lisp)
8694 (defun verilog-read-auto-lisp-present ()
8695 "Set `verilog-cache-has-lisp' if any AUTO_LISP in this buffer."
8697 (goto-char (point-min))
8698 (setq verilog-cache-has-lisp (re-search-forward "\\<AUTO_LISP(" nil t))))
8700 (defun verilog-read-auto-lisp (start end)
8701 "Look for and evaluate an AUTO_LISP between START and END.
8702 Must call `verilog-read-auto-lisp-present' before this function."
8703 ;; This function is expensive for large buffers, so we cache if any AUTO_LISP exists
8704 (when verilog-cache-has-lisp
8707 (while (re-search-forward "\\<AUTO_LISP(" end t)
8709 (let* ((beg-pt (prog1 (point)
8710 (verilog-forward-sexp-cmt 1))) ;; Closing paren
8712 (verilog-in-hooks t))
8713 (eval-region beg-pt end-pt nil))))))
8715 (defun verilog-read-always-signals-recurse
8716 (exit-keywd rvalue temp-next)
8717 "Recursive routine for parentheses/bracket matching.
8718 EXIT-KEYWD is expression to stop at, nil if top level.
8719 RVALUE is true if at right hand side of equal.
8720 IGNORE-NEXT is true to ignore next token, fake from inside case statement."
8721 (let* ((semi-rvalue (equal "endcase" exit-keywd)) ;; true if after a ; we are looking for rvalue
8722 keywd last-keywd sig-tolk sig-last-tolk gotend got-sig got-list end-else-check
8724 ;;(if dbg (setq dbg (concat dbg (format "Recursion %S %S %S\n" exit-keywd rvalue temp-next))))
8725 (while (not (or (eobp) gotend))
8728 (search-forward "\n"))
8729 ((looking-at "/\\*")
8730 (or (search-forward "*/")
8731 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8732 ((looking-at "(\\*")
8733 ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
8735 (or (search-forward "*)")
8736 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
8737 (t (setq keywd (buffer-substring-no-properties
8739 (save-excursion (when (eq 0 (skip-chars-forward "a-zA-Z0-9$_.%`"))
8742 sig-last-tolk sig-tolk
8744 ;;(if dbg (setq dbg (concat dbg (format "\tPt=%S %S\trv=%S in=%S ee=%S gs=%S\n" (point) keywd rvalue ignore-next end-else-check got-sig))))
8747 (or (re-search-forward "[^\\]\"" nil t)
8748 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
8749 ;; else at top level loop, keep parsing
8750 ((and end-else-check (equal keywd "else"))
8751 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else %s\n" keywd))))
8752 ;; no forward movement, want to see else in lower loop
8753 (setq end-else-check nil))
8754 ;; End at top level loop
8755 ((and end-else-check (looking-at "[^ \t\n\f]"))
8756 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else-other %s\n" keywd))))
8759 ((and exit-keywd (equal keywd exit-keywd))
8761 (forward-char (length keywd)))
8762 ;; Standard tokens...
8764 (setq ignore-next nil rvalue semi-rvalue)
8765 ;; Final statement at top level loop?
8766 (when (not exit-keywd)
8767 ;;(if dbg (setq dbg (concat dbg (format "\ttop-end-check %s\n" keywd))))
8768 (setq end-else-check t))
8771 (if (looking-at "'[sS]?[hdxboHDXBO]?[ \t]*[0-9a-fA-F_xzXZ?]+")
8772 (goto-char (match-end 0))
8774 ((equal keywd ":") ;; Case statement, begin/end label, x?y:z
8775 (cond ((equal "endcase" exit-keywd) ;; case x: y=z; statement next
8776 (setq ignore-next nil rvalue nil))
8777 ((equal "?" exit-keywd) ;; x?y:z rvalue
8779 ((equal "]" exit-keywd) ;; [x:y] rvalue
8781 (got-sig ;; label: statement
8782 (setq ignore-next nil rvalue semi-rvalue got-sig nil))
8783 ((not rvalue) ;; begin label
8784 (setq ignore-next t rvalue nil)))
8788 ;;(if dbg (setq dbg (concat dbg (format "\t\tequal got-sig=%S got-list=%s\n" got-sig got-list))))
8789 (set got-list (cons got-sig (symbol-value got-list)))
8792 (if (eq (char-before) ?< )
8793 (setq sigs-out-d (append sigs-out-d sigs-out-unk)
8795 (setq sigs-out-i (append sigs-out-i sigs-out-unk)
8797 (setq ignore-next nil rvalue t)
8801 (verilog-read-always-signals-recurse ":" rvalue nil))
8804 (verilog-read-always-signals-recurse "]" t nil))
8807 (cond (sig-last-tolk ;; Function call; zap last signal
8808 (setq got-sig nil)))
8809 (cond ((equal last-keywd "for")
8810 ;; temp-next: Variables on LHS are lvalues, but generally we want
8811 ;; to ignore them, assuming they are loop increments
8812 (verilog-read-always-signals-recurse ";" nil t)
8813 (verilog-read-always-signals-recurse ";" t nil)
8814 (verilog-read-always-signals-recurse ")" nil nil))
8815 (t (verilog-read-always-signals-recurse ")" t nil))))
8816 ((equal keywd "begin")
8817 (skip-syntax-forward "w_")
8818 (verilog-read-always-signals-recurse "end" nil nil)
8819 ;;(if dbg (setq dbg (concat dbg (format "\tgot-end %s\n" exit-keywd))))
8820 (setq ignore-next nil rvalue semi-rvalue)
8821 (if (not exit-keywd) (setq end-else-check t)))
8822 ((member keywd '("case" "casex" "casez"))
8823 (skip-syntax-forward "w_")
8824 (verilog-read-always-signals-recurse "endcase" t nil)
8825 (setq ignore-next nil rvalue semi-rvalue)
8826 (if (not exit-keywd) (setq gotend t))) ;; top level begin/end
8827 ((string-match "^[$`a-zA-Z_]" keywd) ;; not exactly word constituent
8828 (cond ((member keywd '("`ifdef" "`ifndef" "`elsif"))
8829 (setq ignore-next t))
8831 (member keywd verilog-keywords)
8832 (string-match "^\\$" keywd)) ;; PLI task
8833 (setq ignore-next nil))
8835 (setq keywd (verilog-symbol-detick-denumber keywd))
8837 (set got-list (cons got-sig (symbol-value got-list)))
8838 ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S got-list=%S\n" got-sig got-list))))
8840 (setq got-list (cond (temp-next 'sigs-temp)
8843 got-sig (if (or (not keywd)
8844 (assoc keywd (symbol-value got-list)))
8845 nil (list keywd nil nil))
8848 (skip-chars-forward "a-zA-Z0-9$_.%`"))
8851 ;; End of non-comment token
8852 (setq last-keywd keywd)))
8853 (skip-syntax-forward " "))
8854 ;; Append the final pending signal
8856 ;;(if dbg (setq dbg (concat dbg (format "\t\tfinal got-sig=%S got-list=%s\n" got-sig got-list))))
8857 (set got-list (cons got-sig (symbol-value got-list)))
8859 ;;(if dbg (setq dbg (concat dbg (format "ENDRecursion %s\n" exit-keywd))))
8862 (defun verilog-read-always-signals ()
8863 "Parse always block at point and return list of (outputs inout inputs)."
8866 sigs-out-d sigs-out-i sigs-out-unk sigs-temp sigs-in)
8867 (search-forward ")")
8868 (verilog-read-always-signals-recurse nil nil nil)
8869 (setq sigs-out-i (append sigs-out-i sigs-out-unk)
8871 ;;(if dbg (with-current-buffer (get-buffer-create "*vl-dbg*")) (delete-region (point-min) (point-max)) (insert dbg) (setq dbg ""))
8872 ;; Return what was found
8873 (verilog-alw-new sigs-out-d sigs-out-i sigs-temp sigs-in))))
8875 (defun verilog-read-instants ()
8876 "Parse module at point and return list of ( ( file instance ) ... )."
8877 (verilog-beg-of-defun-quick)
8878 (let* ((end-mod-point (verilog-get-end-of-defun))
8880 (instants-list nil))
8882 (while (< (point) end-mod-point)
8883 ;; Stay at level 0, no comments
8885 (setq state (parse-partial-sexp (point) end-mod-point 0 t nil))
8886 (or (> (car state) 0) ; in parens
8887 (nth 5 state) ; comment
8891 (if (looking-at "^\\s-*\\([a-zA-Z0-9`_$]+\\)\\s-+\\([a-zA-Z0-9`_$]+\\)\\s-*(")
8892 ;;(if (looking-at "^\\(.+\\)$")
8893 (let ((module (match-string 1))
8894 (instant (match-string 2)))
8895 (if (not (member module verilog-keywords))
8896 (setq instants-list (cons (list module instant) instants-list)))))
8901 (defun verilog-read-auto-template-middle ()
8902 "With point in middle of an AUTO_TEMPLATE, parse it.
8903 Returns REGEXP and list of ( (signal_name connection_name)... )."
8906 (let ((tpl-regexp "\\([0-9]+\\)")
8907 (lineno -1) ; -1 to offset for the AUTO_TEMPLATE's newline
8909 tpl-sig-list tpl-wild-list tpl-end-pt rep)
8911 ;; We reserve @"..." for future lisp expressions that evaluate
8912 ;; once-per-AUTOINST
8913 (when (looking-at "\\s-*\"\\([^\"]*\\)\"")
8914 (setq tpl-regexp (match-string 1))
8915 (goto-char (match-end 0)))
8916 (search-forward "(")
8917 ;; Parse lines in the template
8918 (when (or verilog-auto-inst-template-numbers
8919 verilog-auto-template-warn-unused)
8921 (let ((pre-pt (point)))
8922 (goto-char (point-min))
8923 (while (search-forward "AUTO_TEMPLATE" pre-pt t)
8924 (setq templateno (1+ templateno)))
8925 (while (< (point) pre-pt)
8927 (setq lineno (1+ lineno))))))
8928 (setq tpl-end-pt (save-excursion
8930 (verilog-forward-sexp-cmt 1) ;; Moves to paren that closes argdecl's
8934 (while (< (point) tpl-end-pt)
8935 (cond ((looking-at "\\s-*\\.\\([a-zA-Z0-9`_$]+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
8938 (match-string-no-properties 1)
8939 (match-string-no-properties 2)
8942 (goto-char (match-end 0)))
8945 ;; Regexp bug in XEmacs disallows ][ inside [], and wants + last
8946 "\\s-*\\.\\(\\([a-zA-Z0-9`_$+@^.*?|---]+\\|[][]\\|\\\\[()|]\\)+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
8947 (setq rep (match-string-no-properties 3))
8948 (goto-char (match-end 0))
8952 (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil
8958 ((looking-at "[ \t\f]+")
8959 (goto-char (match-end 0)))
8961 (setq lineno (1+ lineno))
8962 (goto-char (match-end 0)))
8964 (search-forward "\n")
8965 (setq lineno (1+ lineno)))
8966 ((looking-at "/\\*")
8968 (or (search-forward "*/")
8969 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8971 (error "%s: AUTO_TEMPLATE parsing error: %s"
8972 (verilog-point-text)
8973 (progn (looking-at ".*$") (match-string 0))))))
8976 (list tpl-sig-list tpl-wild-list)))))
8978 (defun verilog-read-auto-template (module)
8979 "Look for an auto_template for the instantiation of the given MODULE.
8980 If found returns `verilog-read-auto-template-inside' structure."
8984 ;; Note this search is expensive, as we hunt from mod-begin to point
8985 ;; for every instantiation. Likewise in verilog-read-auto-lisp.
8986 ;; So, we look first for an exact string rather than a slow regexp.
8987 ;; Someday we may keep a cache of every template, but this would also
8988 ;; need to record the relative position of each AUTOINST, as multiple
8989 ;; templates exist for each module, and we're inserting lines.
8991 ;; See also regexp in `verilog-auto-template-lint'
8992 (verilog-re-search-backward-substr
8994 (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)
8995 ;; Also try forward of this AUTOINST
8996 ;; This is for historical support; this isn't speced as working
8999 (verilog-re-search-forward-substr
9001 (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)))
9002 (goto-char (match-end 0))
9003 (verilog-read-auto-template-middle))
9004 ;; If no template found
9005 (t (vector "" nil))))))
9006 ;;(progn (find-file "auto-template.v") (verilog-read-auto-template "ptl_entry"))
9008 (defvar verilog-auto-template-hits nil "Successful lookups with `verilog-read-auto-template-hit'.")
9009 (make-variable-buffer-local 'verilog-auto-template-hits)
9011 (defun verilog-read-auto-template-hit (tpl-ass)
9012 "Record that TPL-ASS template from `verilog-read-auto-template' was used."
9013 (when (eval-when-compile (fboundp 'make-hash-table)) ;; else feature not allowed
9014 (when verilog-auto-template-warn-unused
9015 (unless verilog-auto-template-hits
9016 (setq verilog-auto-template-hits
9017 (make-hash-table :test 'equal :rehash-size 4.0)))
9018 (puthash (vector (nth 2 tpl-ass) (nth 3 tpl-ass)) t
9019 verilog-auto-template-hits))))
9021 (defun verilog-set-define (defname defvalue &optional buffer enumname)
9022 "Set the definition DEFNAME to the DEFVALUE in the given BUFFER.
9023 Optionally associate it with the specified enumeration ENUMNAME."
9024 (with-current-buffer (or buffer (current-buffer))
9025 ;; Namespace intentionally short for AUTOs and compatibility
9026 (let ((mac (intern (concat "vh-" defname))))
9027 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
9028 ;; Need to define to a constant if no value given
9029 (set (make-local-variable mac)
9030 (if (equal defvalue "") "1" defvalue)))
9032 ;; Namespace intentionally short for AUTOs and compatibility
9033 (let ((enumvar (intern (concat "venum-" enumname))))
9034 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
9035 (unless (boundp enumvar) (set enumvar nil))
9036 (add-to-list (make-local-variable enumvar) defname)))))
9038 (defun verilog-read-defines (&optional filename recurse subcall)
9039 "Read `defines and parameters for the current file, or optional FILENAME.
9040 If the filename is provided, `verilog-library-flags' will be used to
9041 resolve it. If optional RECURSE is non-nil, recurse through `includes.
9043 Parameters must be simple assignments to constants, or have their own
9044 \"parameter\" label rather than a list of parameters. Thus:
9046 parameter X = 5, Y = 10; // Ok
9047 parameter X = {1'b1, 2'h2}; // Ok
9048 parameter X = {1'b1, 2'h2}, Y = 10; // Bad, make into 2 parameter lines
9050 Defines must be simple text substitutions, one on a line, starting
9051 at the beginning of the line. Any ifdefs or multiline comments around the
9054 Defines are stored inside Emacs variables using the name vh-{definename}.
9056 This function is useful for setting vh-* variables. The file variables
9057 feature can be used to set defines that `verilog-mode' can see; put at the
9058 *END* of your file something like:
9061 // vh-macro:\"macro_definition\"
9064 If macros are defined earlier in the same file and you want their values,
9065 you can read them automatically (provided `enable-local-eval' is on):
9068 // eval:(verilog-read-defines)
9069 // eval:(verilog-read-defines \"group_standard_includes.v\")
9072 Note these are only read when the file is first visited, you must use
9073 \\[find-alternate-file] RET to have these take effect after editing them!
9075 If you want to disable the \"Process `eval' or hook local variables\"
9076 warning message, you need to add to your init file:
9078 (setq enable-local-eval t)"
9079 (let ((origbuf (current-buffer)))
9081 (unless subcall (verilog-getopt-flags))
9083 (let ((fns (verilog-library-filenames filename (buffer-file-name))))
9085 (set-buffer (find-file-noselect (car fns)))
9086 (error (concat (verilog-point-text)
9087 ": Can't find verilog-read-defines file: " filename)))))
9089 (goto-char (point-min))
9090 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
9091 (let ((inc (verilog-string-replace-matches
9092 "\"" "" nil nil (match-string-no-properties 1))))
9093 (unless (verilog-inside-comment-or-string-p)
9094 (verilog-read-defines inc recurse t)))))
9096 ;; note we don't use verilog-re... it's faster this way, and that
9097 ;; function has problems when comments are at the end of the define
9098 (goto-char (point-min))
9099 (while (re-search-forward "^\\s-*`define\\s-+\\([a-zA-Z0-9_$]+\\)\\s-+\\(.*\\)$" nil t)
9100 (let ((defname (match-string-no-properties 1))
9101 (defvalue (match-string-no-properties 2)))
9102 (unless (verilog-inside-comment-or-string-p (match-beginning 0))
9103 (setq defvalue (verilog-string-replace-matches "\\s-*/[/*].*$" "" nil nil defvalue))
9104 (verilog-set-define defname defvalue origbuf))))
9105 ;; Hack: Read parameters
9106 (goto-char (point-min))
9107 (while (re-search-forward
9108 "^\\s-*\\(parameter\\|localparam\\)\\(\\s-*\\[[^]]*\\]\\)?\\s-*" nil t)
9110 ;; The primary way of getting defines is verilog-read-decls
9111 ;; However, that isn't called yet for included files, so we'll add another scheme
9112 (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
9113 (setq enumname (match-string-no-properties 2)))
9114 (forward-comment 99999)
9115 (while (looking-at (concat "\\s-*,?\\s-*\\(?:/[/*].*?$\\)?\\s-*\\([a-zA-Z0-9_$]+\\)"
9116 "\\s-*=\\s-*\\([^;,]*\\),?\\s-*\\(/[/*].*?$\\)?\\s-*"))
9117 (unless (verilog-inside-comment-or-string-p (match-beginning 0))
9118 (verilog-set-define (match-string-no-properties 1)
9119 (match-string-no-properties 2) origbuf enumname))
9120 (goto-char (match-end 0))
9121 (forward-comment 99999)))))))
9123 (defun verilog-read-includes ()
9124 "Read `includes for the current file.
9125 This will find all of the `includes which are at the beginning of lines,
9126 ignoring any ifdefs or multiline comments around them.
9127 `verilog-read-defines' is then performed on the current and each included
9130 It is often useful put at the *END* of your file something like:
9133 // eval:(verilog-read-defines)
9134 // eval:(verilog-read-includes)
9137 Note includes are only read when the file is first visited, you must use
9138 \\[find-alternate-file] RET to have these take effect after editing them!
9140 It is good to get in the habit of including all needed files in each .v
9141 file that needs it, rather than waiting for compile time. This will aid
9142 this process, Verilint, and readability. To prevent defining the same
9143 variable over and over when many modules are compiled together, put a test
9144 around the inside each include file:
9146 foo.v (an include file):
9147 `ifdef _FOO_V // include if not already included
9150 ... contents of file
9152 ;;slow: (verilog-read-defines nil t)
9154 (verilog-getopt-flags)
9155 (goto-char (point-min))
9156 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
9157 (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string 1))))
9158 (verilog-read-defines inc nil t)))))
9160 (defun verilog-read-signals (&optional start end)
9161 "Return a simple list of all possible signals in the file.
9162 Bounded by optional region from START to END. Overly aggressive but fast.
9163 Some macros and such are also found and included. For dinotrace.el."
9164 (let (sigs-all keywd)
9165 (progn;save-excursion
9166 (goto-char (or start (point-min)))
9167 (setq end (or end (point-max)))
9168 (while (re-search-forward "[\"/a-zA-Z_.%`]" end t)
9172 (search-forward "\n"))
9173 ((looking-at "/\\*")
9174 (search-forward "*/"))
9175 ((looking-at "(\\*")
9176 (or (looking-at "(\\*\\s-*)") ; It's a "always @ (*)"
9177 (search-forward "*)")))
9178 ((eq ?\" (following-char))
9179 (re-search-forward "[^\\]\"")) ;; don't forward-char first, since we look for a non backslash first
9180 ((looking-at "\\s-*\\([a-zA-Z0-9$_.%`]+\\)")
9181 (goto-char (match-end 0))
9182 (setq keywd (match-string-no-properties 1))
9183 (or (member keywd verilog-keywords)
9184 (member keywd sigs-all)
9185 (setq sigs-all (cons keywd sigs-all))))
9186 (t (forward-char 1))))
9191 ;; Argument file parsing
9194 (defun verilog-getopt (arglist)
9195 "Parse -f, -v etc arguments in ARGLIST list or string."
9196 (unless (listp arglist) (setq arglist (list arglist)))
9197 (let ((space-args '())
9199 ;; Split on spaces, so users can pass whole command lines
9201 (setq arg (car arglist)
9202 arglist (cdr arglist))
9203 (while (string-match "^\\([^ \t\n\f]+\\)[ \t\n\f]*\\(.*$\\)" arg)
9204 (setq space-args (append space-args
9205 (list (match-string-no-properties 1 arg))))
9206 (setq arg (match-string 2 arg))))
9209 (setq arg (car space-args)
9210 space-args (cdr space-args))
9214 (setq next-param arg))
9216 (setq next-param arg))
9218 (setq next-param arg))
9219 ;; +libext+(ext1)+(ext2)...
9220 ((string-match "^\\+libext\\+\\(.*\\)" arg)
9221 (setq arg (match-string 1 arg))
9222 (while (string-match "\\([^+]+\\)\\+?\\(.*\\)" arg)
9223 (verilog-add-list-unique `verilog-library-extensions
9224 (match-string 1 arg))
9225 (setq arg (match-string 2 arg))))
9227 ((or (string-match "^-D\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; -Ddefine=val
9228 (string-match "^-D\\([^+=]*\\)\\(\\)" arg) ;; -Ddefine
9229 (string-match "^\\+define\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; +define+val
9230 (string-match "^\\+define\\([^+=]*\\)\\(\\)" arg)) ;; +define+define
9231 (verilog-set-define (match-string 1 arg) (match-string 2 arg)))
9233 ((or (string-match "^\\+incdir\\+\\(.*\\)" arg) ;; +incdir+dir
9234 (string-match "^-I\\(.*\\)" arg)) ;; -Idir
9235 (verilog-add-list-unique `verilog-library-directories
9236 (match-string 1 (substitute-in-file-name arg))))
9238 ((equal "+librescan" arg))
9239 ((string-match "^-U\\(.*\\)" arg)) ;; -Udefine
9240 ;; Second parameters
9241 ((equal next-param "-f")
9242 (setq next-param nil)
9243 (verilog-getopt-file (substitute-in-file-name arg)))
9244 ((equal next-param "-v")
9245 (setq next-param nil)
9246 (verilog-add-list-unique `verilog-library-files
9247 (substitute-in-file-name arg)))
9248 ((equal next-param "-y")
9249 (setq next-param nil)
9250 (verilog-add-list-unique `verilog-library-directories
9251 (substitute-in-file-name arg)))
9253 ((string-match "^[^-+]" arg)
9254 (verilog-add-list-unique `verilog-library-files
9255 (substitute-in-file-name arg)))
9256 ;; Default - ignore; no warning
9258 ;;(verilog-getopt (list "+libext+.a+.b" "+incdir+foodir" "+define+a+aval" "-f" "otherf" "-v" "library" "-y" "dir"))
9260 (defun verilog-getopt-file (filename)
9261 "Read Verilog options from the specified FILENAME."
9263 (let ((fns (verilog-library-filenames filename (buffer-file-name)))
9264 (orig-buffer (current-buffer))
9267 (set-buffer (find-file-noselect (car fns)))
9268 (error (concat (verilog-point-text)
9269 ": Can't find verilog-getopt-file -f file: " filename)))
9270 (goto-char (point-min))
9272 (setq line (buffer-substring (point) (point-at-eol)))
9274 (when (string-match "//" line)
9275 (setq line (substring line 0 (match-beginning 0))))
9276 (with-current-buffer orig-buffer ; Variables are buffer-local, so need right context.
9277 (verilog-getopt line))))))
9279 (defun verilog-getopt-flags ()
9280 "Convert `verilog-library-flags' into standard library variables."
9281 ;; If the flags are local, then all the outputs should be local also
9282 (when (local-variable-p `verilog-library-flags (current-buffer))
9283 (mapc 'make-local-variable '(verilog-library-extensions
9284 verilog-library-directories
9285 verilog-library-files
9286 verilog-library-flags)))
9287 ;; Allow user to customize
9288 (verilog-run-hooks 'verilog-before-getopt-flags-hook)
9289 ;; Process arguments
9290 (verilog-getopt verilog-library-flags)
9291 ;; Allow user to customize
9292 (verilog-run-hooks 'verilog-getopt-flags-hook))
9294 (defun verilog-add-list-unique (varref object)
9295 "Append to VARREF list the given OBJECT,
9296 unless it is already a member of the variable's list."
9297 (unless (member object (symbol-value varref))
9298 (set varref (append (symbol-value varref) (list object))))
9300 ;;(progn (setq l '()) (verilog-add-list-unique `l "a") (verilog-add-list-unique `l "a") l)
9302 (defun verilog-current-flags ()
9303 "Convert `verilog-library-flags' and similar variables to command line.
9304 Used for __FLAGS__ in `verilog-expand-command'."
9305 (let ((cmd (mapconcat `concat verilog-library-flags " ")))
9306 (when (equal cmd "")
9308 "+libext+" (mapconcat `concat verilog-library-extensions "+")
9309 (mapconcat (lambda (i) (concat " -y " i " +incdir+" i))
9310 verilog-library-directories "")
9311 (mapconcat (lambda (i) (concat " -v " i))
9312 verilog-library-files ""))))
9314 ;;(verilog-current-flags)
9318 ;; Cached directory support
9321 (defvar verilog-dir-cache-preserving nil
9322 "If true, the directory cache is enabled, and file system changes are ignored.
9323 See `verilog-dir-exists-p' and `verilog-dir-files'.")
9325 ;; If adding new cached variable, add also to verilog-preserve-dir-cache
9326 (defvar verilog-dir-cache-list nil
9327 "Alist of (((Cwd Dirname) Results)...) for caching `verilog-dir-files'.")
9328 (defvar verilog-dir-cache-lib-filenames nil
9329 "Cached data for `verilog-library-filenames'.")
9331 (defmacro verilog-preserve-dir-cache (&rest body)
9332 "Execute the BODY forms, allowing directory cache preservation within BODY.
9333 This means that changes inside BODY made to the file system will not be
9334 seen by the `verilog-dir-files' and related functions."
9335 `(let ((verilog-dir-cache-preserving (current-buffer))
9336 verilog-dir-cache-list
9337 verilog-dir-cache-lib-filenames)
9340 (defun verilog-dir-files (dirname)
9341 "Return all filenames in the DIRNAME directory.
9342 Relative paths depend on the `default-directory'.
9343 Results are cached if inside `verilog-preserve-dir-cache'."
9344 (unless verilog-dir-cache-preserving
9345 (setq verilog-dir-cache-list nil)) ;; Cache disabled
9346 ;; We don't use expand-file-name on the dirname to make key, as it's slow
9347 (let* ((cache-key (list dirname default-directory))
9348 (fass (assoc cache-key verilog-dir-cache-list))
9350 (cond (fass ;; Return data from cache hit
9353 (setq exp-dirname (expand-file-name dirname)
9354 data (and (file-directory-p exp-dirname)
9355 (directory-files exp-dirname nil nil nil)))
9356 ;; Note we also encache nil for non-existing dirs.
9357 (setq verilog-dir-cache-list (cons (list cache-key data)
9358 verilog-dir-cache-list))
9360 ;; Miss-and-hit test:
9361 ;;(verilog-preserve-dir-cache (prin1 (verilog-dir-files "."))
9362 ;; (prin1 (verilog-dir-files ".")) nil)
9364 (defun verilog-dir-file-exists-p (filename)
9365 "Return true if FILENAME exists.
9366 Like `file-exists-p' but results are cached if inside
9367 `verilog-preserve-dir-cache'."
9368 (let* ((dirname (file-name-directory filename))
9369 ;; Correct for file-name-nondirectory returning same if no slash.
9370 (dirnamed (if (or (not dirname) (equal dirname filename))
9371 default-directory dirname))
9372 (flist (verilog-dir-files dirnamed)))
9374 (member (file-name-nondirectory filename) flist)
9376 ;;(verilog-dir-file-exists-p "verilog-mode.el")
9377 ;;(verilog-dir-file-exists-p "../verilog-mode/verilog-mode.el")
9381 ;; Module name lookup
9384 (defun verilog-module-inside-filename-p (module filename)
9385 "Return modi if MODULE is specified inside FILENAME, else nil.
9386 Allows version control to check out the file if need be."
9387 (and (or (file-exists-p filename)
9388 (and (fboundp 'vc-backend)
9389 (vc-backend filename)))
9391 (with-current-buffer (find-file-noselect filename)
9393 (goto-char (point-min))
9395 ;; It may be tempting to look for verilog-defun-re,
9396 ;; don't, it slows things down a lot!
9397 (verilog-re-search-forward-quick "\\<\\(module\\|interface\\|program\\)\\>" nil t)
9398 (setq type (match-string-no-properties 0))
9399 (verilog-re-search-forward-quick "[(;]" nil t))
9400 (if (equal module (verilog-read-module-name))
9401 (setq modi (verilog-modi-new module filename (point) type))))
9404 (defun verilog-is-number (symbol)
9405 "Return true if SYMBOL is number-like."
9406 (or (string-match "^[0-9 \t:]+$" symbol)
9407 (string-match "^[---]*[0-9]+$" symbol)
9408 (string-match "^[0-9 \t]+'s?[hdxbo][0-9a-fA-F_xz? \t]*$" symbol)))
9410 (defun verilog-symbol-detick (symbol wing-it)
9411 "Return an expanded SYMBOL name without any defines.
9412 If the variable vh-{symbol} is defined, return that value.
9413 If undefined, and WING-IT, return just SYMBOL without the tick, else nil."
9414 (while (and symbol (string-match "^`" symbol))
9415 (setq symbol (substring symbol 1))
9417 ;; Namespace intentionally short for AUTOs and compatibility
9418 (if (boundp (intern (concat "vh-" symbol)))
9419 ;; Emacs has a bug where boundp on a buffer-local
9420 ;; variable in only one buffer returns t in another.
9421 ;; This can confuse, so check for nil.
9422 ;; Namespace intentionally short for AUTOs and compatibility
9423 (let ((val (eval (intern (concat "vh-" symbol)))))
9425 (if wing-it symbol nil)
9427 (if wing-it symbol nil))))
9429 ;;(verilog-symbol-detick "`mod" nil)
9431 (defun verilog-symbol-detick-denumber (symbol)
9432 "Return SYMBOL with defines converted and any numbers dropped to nil."
9433 (when (string-match "^`" symbol)
9434 ;; This only will work if the define is a simple signal, not
9435 ;; something like a[b]. Sorry, it should be substituted into the parser
9437 (verilog-string-replace-matches
9438 "\[[^0-9: \t]+\]" "" nil nil
9439 (or (verilog-symbol-detick symbol nil)
9440 (if verilog-auto-sense-defines-constant
9443 (if (verilog-is-number symbol)
9447 (defun verilog-symbol-detick-text (text)
9448 "Return TEXT without any known defines.
9449 If the variable vh-{symbol} is defined, substitute that value."
9450 (let ((ok t) symbol val)
9451 (while (and ok (string-match "`\\([a-zA-Z0-9_]+\\)" text))
9452 (setq symbol (match-string 1 text))
9455 ;; Namespace intentionally short for AUTOs and compatibility
9456 (boundp (intern (concat "vh-" symbol)))
9457 ;; Emacs has a bug where boundp on a buffer-local
9458 ;; variable in only one buffer returns t in another.
9459 ;; This can confuse, so check for nil.
9460 ;; Namespace intentionally short for AUTOs and compatibility
9461 (setq val (eval (intern (concat "vh-" symbol)))))
9462 (setq text (replace-match val nil nil text)))
9463 (t (setq ok nil)))))
9465 ;;(progn (setq vh-mod "`foo" vh-foo "bar") (verilog-symbol-detick-text "bar `mod `undefed"))
9467 (defun verilog-expand-dirnames (&optional dirnames)
9468 "Return a list of existing directories given a list of wildcarded DIRNAMES.
9469 Or, just the existing dirnames themselves if there are no wildcards."
9470 ;; Note this function is performance critical.
9471 ;; Do not call anything that requires disk access that cannot be cached.
9473 (unless dirnames (error "`verilog-library-directories' should include at least '.'"))
9474 (setq dirnames (reverse dirnames)) ; not nreverse
9476 pattern dirfile dirfiles dirname root filename rest basefile)
9478 (setq dirname (substitute-in-file-name (car dirnames))
9479 dirnames (cdr dirnames))
9480 (cond ((string-match (concat "^\\(\\|[/\\]*[^*?]*[/\\]\\)" ;; root
9481 "\\([^/\\]*[*?][^/\\]*\\)" ;; filename with *?
9484 (setq root (match-string 1 dirname)
9485 filename (match-string 2 dirname)
9486 rest (match-string 3 dirname)
9488 ;; now replace those * and ? with .+ and .
9489 ;; use ^ and /> to get only whole file names
9490 (setq pattern (verilog-string-replace-matches "[*]" ".+" nil nil pattern)
9491 pattern (verilog-string-replace-matches "[?]" "." nil nil pattern)
9492 pattern (concat "^" pattern "$")
9493 dirfiles (verilog-dir-files root))
9495 (setq basefile (car dirfiles)
9496 dirfile (expand-file-name (concat root basefile rest))
9497 dirfiles (cdr dirfiles))
9498 (if (and (string-match pattern basefile)
9499 ;; Don't allow abc/*/rtl to match abc/rtl via ..
9500 (not (equal basefile "."))
9501 (not (equal basefile ".."))
9502 (file-directory-p dirfile))
9503 (setq dirlist (cons dirfile dirlist)))))
9506 (if (file-directory-p dirname)
9507 (setq dirlist (cons dirname dirlist))))))
9509 ;;(verilog-expand-dirnames (list "." ".." "nonexist" "../*" "/home/wsnyder/*/v"))
9511 (defun verilog-library-filenames (filename &optional current check-ext)
9512 "Return a search path to find the given FILENAME or module name.
9513 Uses the optional CURRENT filename or variable `buffer-file-name', plus
9514 `verilog-library-directories' and `verilog-library-extensions'
9515 variables to build the path. With optional CHECK-EXT also check
9516 `verilog-library-extensions'."
9517 (unless current (setq current (buffer-file-name)))
9518 (unless verilog-dir-cache-preserving
9519 (setq verilog-dir-cache-lib-filenames nil))
9520 (let* ((cache-key (list filename current check-ext))
9521 (fass (assoc cache-key verilog-dir-cache-lib-filenames))
9522 chkdirs chkdir chkexts fn outlist)
9523 (cond (fass ;; Return data from cache hit
9526 ;; Note this expand can't be easily cached, as we need to
9527 ;; pick up buffer-local variables for newly read sub-module files
9528 (setq chkdirs (verilog-expand-dirnames verilog-library-directories))
9530 (setq chkdir (expand-file-name (car chkdirs)
9531 (file-name-directory current))
9532 chkexts (if check-ext verilog-library-extensions `("")))
9534 (setq fn (expand-file-name (concat filename (car chkexts))
9536 ;;(message "Check for %s" fn)
9537 (if (verilog-dir-file-exists-p fn)
9538 (setq outlist (cons (expand-file-name
9539 fn (file-name-directory current))
9541 (setq chkexts (cdr chkexts)))
9542 (setq chkdirs (cdr chkdirs)))
9543 (setq outlist (nreverse outlist))
9544 (setq verilog-dir-cache-lib-filenames
9545 (cons (list cache-key outlist)
9546 verilog-dir-cache-lib-filenames))
9549 (defun verilog-module-filenames (module current)
9550 "Return a search path to find the given MODULE name.
9551 Uses the CURRENT filename, `verilog-library-extensions',
9552 `verilog-library-directories' and `verilog-library-files'
9553 variables to build the path."
9554 ;; Return search locations for it
9555 (append (list current) ; first, current buffer
9556 (verilog-library-filenames module current t)
9557 verilog-library-files)) ; finally, any libraries
9560 ;; Module Information
9562 ;; Many of these functions work on "modi" a module information structure
9563 ;; A modi is: [module-name-string file-name begin-point]
9565 (defvar verilog-cache-enabled t
9566 "Non-nil enables caching of signals, etc. Set to nil for debugging to make things SLOW!")
9568 (defvar verilog-modi-cache-list nil
9569 "Cache of ((Module Function) Buf-Tick Buf-Modtime Func-Returns)...
9570 For speeding up verilog-modi-get-* commands.
9572 (make-variable-buffer-local 'verilog-modi-cache-list)
9574 (defvar verilog-modi-cache-preserve-tick nil
9575 "Modification tick after which the cache is still considered valid.
9576 Use `verilog-preserve-modi-cache' to set it.")
9577 (defvar verilog-modi-cache-preserve-buffer nil
9578 "Modification tick after which the cache is still considered valid.
9579 Use `verilog-preserve-modi-cache' to set it.")
9580 (defvar verilog-modi-cache-current-enable nil
9581 "Non-nil means allow caching `verilog-modi-current', set by let().")
9582 (defvar verilog-modi-cache-current nil
9583 "Currently active `verilog-modi-current', if any, set by let().")
9584 (defvar verilog-modi-cache-current-max nil
9585 "Current endmodule point for `verilog-modi-cache-current', if any.")
9587 (defun verilog-modi-current ()
9588 "Return the modi structure for the module currently at point, possibly cached."
9589 (cond ((and verilog-modi-cache-current
9590 (>= (point) (verilog-modi-get-point verilog-modi-cache-current))
9591 (<= (point) verilog-modi-cache-current-max))
9592 ;; Slow assertion, for debugging the cache:
9593 ;;(or (equal verilog-modi-cache-current (verilog-modi-current-get)) (debug))
9594 verilog-modi-cache-current)
9595 (verilog-modi-cache-current-enable
9596 (setq verilog-modi-cache-current (verilog-modi-current-get)
9597 verilog-modi-cache-current-max
9598 ;; The cache expires when we pass "endmodule" as then the
9599 ;; current modi may change to the next module
9600 ;; This relies on the AUTOs generally inserting, not deleting text
9602 (verilog-re-search-forward-quick verilog-end-defun-re nil nil)))
9603 verilog-modi-cache-current)
9605 (verilog-modi-current-get))))
9607 (defun verilog-modi-current-get ()
9608 "Return the modi structure for the module currently at point."
9609 (let* (name type pt)
9610 ;; read current module's name
9612 (verilog-re-search-backward-quick verilog-defun-re nil nil)
9613 (setq type (match-string-no-properties 0))
9614 (verilog-re-search-forward-quick "(" nil nil)
9615 (setq name (verilog-read-module-name))
9617 ;; return modi - note this vector built two places
9618 (verilog-modi-new name (or (buffer-file-name) (current-buffer)) pt type)))
9620 (defvar verilog-modi-lookup-cache nil "Hash of (modulename modi).")
9621 (make-variable-buffer-local 'verilog-modi-lookup-cache)
9622 (defvar verilog-modi-lookup-last-current nil "Cache of `current-buffer' at last lookup.")
9623 (defvar verilog-modi-lookup-last-tick nil "Cache of `buffer-chars-modified-tick' at last lookup.")
9625 (defun verilog-modi-lookup (module allow-cache &optional ignore-error)
9626 "Find the file and point at which MODULE is defined.
9627 If ALLOW-CACHE is set, check and remember cache of previous lookups.
9628 Return modi if successful, else print message unless IGNORE-ERROR is true."
9629 (let* ((current (or (buffer-file-name) (current-buffer)))
9632 ;;(message "verilog-modi-lookup: %s" module)
9633 (cond ((and verilog-modi-lookup-cache
9634 verilog-cache-enabled
9636 (setq modi (gethash module verilog-modi-lookup-cache))
9637 (equal verilog-modi-lookup-last-current current)
9638 ;; Iff hit is in current buffer, then tick must match
9639 (or (equal verilog-modi-lookup-last-tick (buffer-chars-modified-tick))
9640 (not (equal current (verilog-modi-file-or-buffer modi)))))
9641 ;;(message "verilog-modi-lookup: HIT %S" modi)
9644 (t (let* ((realname (verilog-symbol-detick module t))
9645 (orig-filenames (verilog-module-filenames realname current))
9646 (filenames orig-filenames)
9648 (while (and filenames (not mif))
9649 (if (not (setq mif (verilog-module-inside-filename-p realname (car filenames))))
9650 (setq filenames (cdr filenames))))
9651 ;; mif has correct form to become later elements of modi
9652 (cond (mif (setq modi mif))
9655 (error (concat (verilog-point-text)
9656 ": Can't locate " module " module definition"
9657 (if (not (equal module realname))
9658 (concat " (Expanded macro to " realname ")")
9660 "\n Check the verilog-library-directories variable."
9661 "\n I looked in (if not listed, doesn't exist):\n\t"
9662 (mapconcat 'concat orig-filenames "\n\t"))))))
9663 (when (eval-when-compile (fboundp 'make-hash-table))
9664 (unless verilog-modi-lookup-cache
9665 (setq verilog-modi-lookup-cache
9666 (make-hash-table :test 'equal :rehash-size 4.0)))
9667 (puthash module modi verilog-modi-lookup-cache))
9668 (setq verilog-modi-lookup-last-current current
9669 verilog-modi-lookup-last-tick (buffer-chars-modified-tick)))))
9672 (defun verilog-modi-filename (modi)
9673 "Filename of MODI, or name of buffer if it's never been saved."
9674 (if (bufferp (verilog-modi-file-or-buffer modi))
9675 (or (buffer-file-name (verilog-modi-file-or-buffer modi))
9676 (buffer-name (verilog-modi-file-or-buffer modi)))
9677 (verilog-modi-file-or-buffer modi)))
9679 (defun verilog-modi-goto (modi)
9680 "Move point/buffer to specified MODI."
9681 (or modi (error "Passed unfound modi to goto, check earlier"))
9682 (set-buffer (if (bufferp (verilog-modi-file-or-buffer modi))
9683 (verilog-modi-file-or-buffer modi)
9684 (find-file-noselect (verilog-modi-file-or-buffer modi))))
9685 (or (equal major-mode `verilog-mode) ;; Put into Verilog mode to get syntax
9687 (goto-char (verilog-modi-get-point modi)))
9689 (defun verilog-goto-defun-file (module)
9690 "Move point to the file at which a given MODULE is defined."
9691 (interactive "sGoto File for Module: ")
9692 (let* ((modi (verilog-modi-lookup module nil)))
9694 (verilog-modi-goto modi)
9695 (switch-to-buffer (current-buffer)))))
9697 (defun verilog-modi-cache-results (modi function)
9698 "Run on MODI the given FUNCTION. Locate the module in a file.
9699 Cache the output of function so next call may have faster access."
9701 (save-excursion ;; Cache is buffer-local so can't avoid this.
9702 (verilog-modi-goto modi)
9703 (if (and (setq fass (assoc (list modi function)
9704 verilog-modi-cache-list))
9705 ;; Destroy caching when incorrect; Modified or file changed
9706 (not (and verilog-cache-enabled
9707 (or (equal (buffer-chars-modified-tick) (nth 1 fass))
9708 (and verilog-modi-cache-preserve-tick
9709 (<= verilog-modi-cache-preserve-tick (nth 1 fass))
9710 (equal verilog-modi-cache-preserve-buffer (current-buffer))))
9711 (equal (visited-file-modtime) (nth 2 fass)))))
9712 (setq verilog-modi-cache-list nil
9715 ;; Return data from cache hit
9719 ;; Clear then restore any highlighting to make emacs19 happy
9721 (verilog-save-font-mods
9722 (setq func-returns (funcall function)))
9723 ;; Cache for next time
9724 (setq verilog-modi-cache-list
9725 (cons (list (list modi function)
9726 (buffer-chars-modified-tick)
9727 (visited-file-modtime)
9729 verilog-modi-cache-list))
9732 (defun verilog-modi-cache-add (modi function element sig-list)
9733 "Add function return results to the module cache.
9734 Update MODI's cache for given FUNCTION so that the return ELEMENT of that
9735 function now contains the additional SIG-LIST parameters."
9738 (verilog-modi-goto modi)
9739 (if (setq fass (assoc (list modi function)
9740 verilog-modi-cache-list))
9741 (let ((func-returns (nth 3 fass)))
9742 (aset func-returns element
9743 (append sig-list (aref func-returns element))))))))
9745 (defmacro verilog-preserve-modi-cache (&rest body)
9746 "Execute the BODY forms, allowing cache preservation within BODY.
9747 This means that changes to the buffer will not result in the cache being
9748 flushed. If the changes affect the modsig state, they must call the
9749 modsig-cache-add-* function, else the results of later calls may be
9750 incorrect. Without this, changes are assumed to be adding/removing signals
9751 and invalidating the cache."
9752 `(let ((verilog-modi-cache-preserve-tick (buffer-chars-modified-tick))
9753 (verilog-modi-cache-preserve-buffer (current-buffer)))
9757 (defun verilog-modi-modport-lookup-one (modi name &optional ignore-error)
9758 "Given a MODI, return the declarations related to the given modport NAME."
9759 ;; Recursive routine - see below
9760 (let* ((realname (verilog-symbol-detick name t))
9761 (modport (assoc name (verilog-decls-get-modports (verilog-modi-get-decls modi)))))
9762 (or modport ignore-error
9763 (error (concat (verilog-point-text)
9764 ": Can't locate " name " modport definition"
9765 (if (not (equal name realname))
9766 (concat " (Expanded macro to " realname ")")
9768 (let* ((decls (verilog-modport-decls modport))
9769 (clks (verilog-modport-clockings modport)))
9770 ;; Now expand any clocking's
9772 (setq decls (verilog-decls-append
9774 (verilog-modi-modport-lookup-one modi (car clks) ignore-error)))
9775 (setq clks (cdr clks)))
9778 (defun verilog-modi-modport-lookup (modi name-re &optional ignore-error)
9779 "Given a MODI, return the declarations related to the given modport NAME-RE.
9780 If the modport points to any clocking blocks, expand the signals to include
9781 those clocking block's signals."
9782 ;; Recursive routine - see below
9783 (let* ((mod-decls (verilog-modi-get-decls modi))
9784 (clks (verilog-decls-get-modports mod-decls))
9785 (name-re (concat "^" name-re "$"))
9786 (decls (verilog-decls-new nil nil nil nil nil nil nil nil nil)))
9787 ;; Pull in all modports
9789 (when (string-match name-re (verilog-modport-name (car clks)))
9790 (setq decls (verilog-decls-append
9792 (verilog-modi-modport-lookup-one modi (verilog-modport-name (car clks)) ignore-error))))
9793 (setq clks (cdr clks)))
9796 (defun verilog-signals-matching-enum (in-list enum)
9797 "Return all signals in IN-LIST matching the given ENUM."
9800 (if (equal (verilog-sig-enum (car in-list)) enum)
9801 (setq out-list (cons (car in-list) out-list)))
9802 (setq in-list (cdr in-list)))
9804 ;; Namespace intentionally short for AUTOs and compatibility
9805 (let* ((enumvar (intern (concat "venum-" enum)))
9806 (enumlist (and (boundp enumvar) (eval enumvar))))
9808 (add-to-list 'out-list (list (car enumlist)))
9809 (setq enumlist (cdr enumlist))))
9810 (nreverse out-list)))
9812 (defun verilog-signals-matching-regexp (in-list regexp)
9813 "Return all signals in IN-LIST matching the given REGEXP, if non-nil."
9814 (if (or (not regexp) (equal regexp ""))
9816 (let ((case-fold-search verilog-case-fold)
9819 (if (string-match regexp (verilog-sig-name (car in-list)))
9820 (setq out-list (cons (car in-list) out-list)))
9821 (setq in-list (cdr in-list)))
9822 (nreverse out-list))))
9824 (defun verilog-signals-not-matching-regexp (in-list regexp)
9825 "Return all signals in IN-LIST not matching the given REGEXP, if non-nil."
9826 (if (or (not regexp) (equal regexp ""))
9828 (let ((case-fold-search verilog-case-fold)
9831 (if (not (string-match regexp (verilog-sig-name (car in-list))))
9832 (setq out-list (cons (car in-list) out-list)))
9833 (setq in-list (cdr in-list)))
9834 (nreverse out-list))))
9836 (defun verilog-signals-matching-dir-re (in-list decl-type regexp)
9837 "Return all signals in IN-LIST matching the given DECL-TYPE and REGEXP,
9839 (if (or (not regexp) (equal regexp ""))
9841 (let (out-list to-match)
9843 ;; Note verilog-insert-one-definition matches on this order
9844 (setq to-match (concat
9846 " " (verilog-sig-signed (car in-list))
9847 " " (verilog-sig-multidim (car in-list))
9848 (verilog-sig-bits (car in-list))))
9849 (if (string-match regexp to-match)
9850 (setq out-list (cons (car in-list) out-list)))
9851 (setq in-list (cdr in-list)))
9852 (nreverse out-list))))
9854 (defun verilog-signals-edit-wire-reg (in-list)
9855 "Return all signals in IN-LIST with wire/reg data types made blank."
9856 (mapcar (lambda (sig)
9857 (when (member (verilog-sig-type sig) '("wire" "reg"))
9858 (verilog-sig-type-set sig nil))
9862 (defun verilog-decls-get-signals (decls)
9863 "Return all declared signals in DECLS, excluding 'assign' statements."
9865 (verilog-decls-get-outputs decls)
9866 (verilog-decls-get-inouts decls)
9867 (verilog-decls-get-inputs decls)
9868 (verilog-decls-get-vars decls)
9869 (verilog-decls-get-consts decls)
9870 (verilog-decls-get-gparams decls)))
9872 (defun verilog-decls-get-ports (decls)
9874 (verilog-decls-get-outputs decls)
9875 (verilog-decls-get-inouts decls)
9876 (verilog-decls-get-inputs decls)))
9878 (defun verilog-decls-get-iovars (decls)
9880 (verilog-decls-get-vars decls)
9881 (verilog-decls-get-outputs decls)
9882 (verilog-decls-get-inouts decls)
9883 (verilog-decls-get-inputs decls)))
9885 (defsubst verilog-modi-cache-add-outputs (modi sig-list)
9886 (verilog-modi-cache-add modi 'verilog-read-decls 0 sig-list))
9887 (defsubst verilog-modi-cache-add-inouts (modi sig-list)
9888 (verilog-modi-cache-add modi 'verilog-read-decls 1 sig-list))
9889 (defsubst verilog-modi-cache-add-inputs (modi sig-list)
9890 (verilog-modi-cache-add modi 'verilog-read-decls 2 sig-list))
9891 (defsubst verilog-modi-cache-add-vars (modi sig-list)
9892 (verilog-modi-cache-add modi 'verilog-read-decls 3 sig-list))
9893 (defsubst verilog-modi-cache-add-gparams (modi sig-list)
9894 (verilog-modi-cache-add modi 'verilog-read-decls 7 sig-list))
9898 ;; Auto creation utilities
9901 (defun verilog-auto-re-search-do (search-for func)
9902 "Search for the given auto text regexp SEARCH-FOR, and perform FUNC where it occurs."
9903 (goto-char (point-min))
9904 (while (verilog-re-search-forward-quick search-for nil t)
9907 (defun verilog-insert-one-definition (sig type indent-pt)
9908 "Print out a definition for SIG of the given TYPE,
9909 with appropriate INDENT-PT indentation."
9910 (indent-to indent-pt)
9911 ;; Note verilog-signals-matching-dir-re matches on this order
9913 (when (verilog-sig-modport sig)
9914 (insert "." (verilog-sig-modport sig)))
9915 (when (verilog-sig-signed sig)
9916 (insert " " (verilog-sig-signed sig)))
9917 (when (verilog-sig-multidim sig)
9918 (insert " " (verilog-sig-multidim-string sig)))
9919 (when (verilog-sig-bits sig)
9920 (insert " " (verilog-sig-bits sig)))
9921 (indent-to (max 24 (+ indent-pt 16)))
9922 (unless (= (char-syntax (preceding-char)) ?\ )
9923 (insert " ")) ; Need space between "]name" if indent-to did nothing
9924 (insert (verilog-sig-name sig))
9925 (when (verilog-sig-memory sig)
9926 (insert " " (verilog-sig-memory sig))))
9928 (defun verilog-insert-definition (modi sigs direction indent-pt v2k &optional dont-sort)
9929 "Print out a definition for MODI's list of SIGS of the given DIRECTION,
9930 with appropriate INDENT-PT indentation. If V2K, use Verilog 2001 I/O
9931 format. Sort unless DONT-SORT. DIRECTION is normally wire/reg/output.
9932 When MODI is non-null, also add to modi-cache, for tracking."
9934 (cond ((equal direction "wire")
9935 (verilog-modi-cache-add-vars modi sigs))
9936 ((equal direction "reg")
9937 (verilog-modi-cache-add-vars modi sigs))
9938 ((equal direction "output")
9939 (verilog-modi-cache-add-outputs modi sigs)
9940 (when verilog-auto-declare-nettype
9941 (verilog-modi-cache-add-vars modi sigs)))
9942 ((equal direction "input")
9943 (verilog-modi-cache-add-inputs modi sigs)
9944 (when verilog-auto-declare-nettype
9945 (verilog-modi-cache-add-vars modi sigs)))
9946 ((equal direction "inout")
9947 (verilog-modi-cache-add-inouts modi sigs)
9948 (when verilog-auto-declare-nettype
9949 (verilog-modi-cache-add-vars modi sigs)))
9950 ((equal direction "interface"))
9951 ((equal direction "parameter")
9952 (verilog-modi-cache-add-gparams modi sigs))
9954 (error "Unsupported verilog-insert-definition direction: %s" direction))))
9956 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
9958 (let ((sig (car sigs)))
9959 (verilog-insert-one-definition
9961 ;; Want "type x" or "output type x", not "wire type x"
9962 (cond ((or (verilog-sig-type sig)
9963 verilog-auto-wire-type)
9965 (when (member direction '("input" "output" "inout"))
9966 (concat direction " "))
9967 (or (verilog-sig-type sig)
9968 verilog-auto-wire-type)))
9969 ((and verilog-auto-declare-nettype
9970 (member direction '("input" "output" "inout")))
9971 (concat direction " " verilog-auto-declare-nettype))
9975 (insert (if v2k "," ";"))
9976 (if (or (not (verilog-sig-comment sig))
9977 (equal "" (verilog-sig-comment sig)))
9979 (indent-to (max 48 (+ indent-pt 40)))
9980 (verilog-insert "// " (verilog-sig-comment sig) "\n"))
9981 (setq sigs (cdr sigs)))))
9984 (if (not (boundp 'indent-pt))
9985 (defvar indent-pt nil "Local used by insert-indent")))
9987 (defun verilog-insert-indent (&rest stuff)
9988 "Indent to position stored in local `indent-pt' variable, then insert STUFF.
9989 Presumes that any newlines end a list element."
9990 (let ((need-indent t))
9992 (if need-indent (indent-to indent-pt))
9993 (setq need-indent nil)
9994 (verilog-insert (car stuff))
9995 (setq need-indent (string-match "\n$" (car stuff))
9996 stuff (cdr stuff)))))
9997 ;;(let ((indent-pt 10)) (verilog-insert-indent "hello\n" "addon" "there\n"))
9999 (defun verilog-forward-or-insert-line ()
10000 "Move forward a line, unless at EOB, then insert a newline."
10001 (if (eobp) (insert "\n")
10004 (defun verilog-repair-open-comma ()
10005 "Insert comma if previous argument is other than an open parenthesis or endif."
10006 ;; We can't just search backward for ) as it might be inside another expression.
10007 ;; Also want "`ifdef X input foo `endif" to just leave things to the human to deal with
10009 (verilog-backward-syntactic-ws-quick)
10010 (when (and (not (save-excursion ;; Not beginning (, or existing ,
10012 (looking-at "[(,]")))
10013 (not (save-excursion ;; Not `endif, or user define
10015 (skip-chars-backward "[a-zA-Z0-9_`]")
10016 (looking-at "`"))))
10019 (defun verilog-repair-close-comma ()
10020 "If point is at a comma followed by a close parenthesis, fix it.
10021 This repairs those mis-inserted by an AUTOARG."
10022 ;; It would be much nicer if Verilog allowed extra commas like Perl does!
10024 (verilog-forward-close-paren)
10026 (verilog-backward-syntactic-ws-quick)
10028 (when (looking-at ",")
10031 (defun verilog-make-width-expression (range-exp)
10032 "Return an expression calculating the length of a range [x:y] in RANGE-EXP."
10033 ;; strip off the []
10034 (cond ((not range-exp)
10037 (if (string-match "^\\[\\(.*\\)\\]$" range-exp)
10038 (setq range-exp (match-string 1 range-exp)))
10039 (cond ((not range-exp)
10041 ;; [#:#] We can compute a numeric result
10042 ((string-match "^\\s *\\([0-9]+\\)\\s *:\\s *\\([0-9]+\\)\\s *$"
10045 (1+ (abs (- (string-to-number (match-string 1 range-exp))
10046 (string-to-number (match-string 2 range-exp)))))))
10047 ;; [PARAM-1:0] can just return PARAM
10048 ((string-match "^\\s *\\([a-zA-Z_][a-zA-Z0-9_]*\\)\\s *-\\s *1\\s *:\\s *0\\s *$" range-exp)
10049 (match-string 1 range-exp))
10050 ;; [arbitrary] need math
10051 ((string-match "^\\(.*\\)\\s *:\\s *\\(.*\\)\\s *$" range-exp)
10052 (concat "(1+(" (match-string 1 range-exp) ")"
10053 (if (equal "0" (match-string 2 range-exp))
10054 "" ;; Don't bother with -(0)
10055 (concat "-(" (match-string 2 range-exp) ")"))
10058 ;;(verilog-make-width-expression "`A:`B")
10060 (defun verilog-simplify-range-expression (expr)
10061 "Return a simplified range expression with constants eliminated from EXPR."
10062 ;; Note this is always called with brackets; ie [z] or [z:z]
10063 (if (not (string-match "[---+*()]" expr))
10064 expr ;; short-circuit
10067 (while (not (equal last-pass out))
10068 (setq last-pass out)
10069 ;; Prefix regexp needs beginning of match, or some symbol of
10070 ;; lesser or equal precedence. We assume the [:]'s exist in expr.
10072 (while (string-match
10073 (concat "\\([[({:*+-]\\)" ; - must be last
10074 "(\\<\\([0-9A-Za-z_]+\\))"
10077 (setq out (replace-match "\\1\\2\\3" nil nil out)))
10078 (while (string-match
10079 (concat "\\([[({:*+-]\\)" ; - must be last
10080 "\\$clog2\\s *(\\<\\([0-9]+\\))"
10083 (setq out (replace-match
10085 (match-string 1 out)
10086 (int-to-string (verilog-clog2 (string-to-number (match-string 2 out))))
10087 (match-string 3 out))
10089 ;; For precedence do * before +/-
10090 (while (string-match
10091 (concat "\\([[({:*+-]\\)"
10092 "\\([0-9]+\\)\\s *\\([*]\\)\\s *\\([0-9]+\\)"
10095 (setq out (replace-match
10096 (concat (match-string 1 out)
10097 (int-to-string (* (string-to-number (match-string 2 out))
10098 (string-to-number (match-string 4 out))))
10099 (match-string 5 out))
10101 (while (string-match
10102 (concat "\\([[({:+-]\\)" ; No * here as higher prec
10103 "\\([0-9]+\\)\\s *\\([---+]\\)\\s *\\([0-9]+\\)"
10106 (let ((pre (match-string 1 out))
10107 (lhs (string-to-number (match-string 2 out)))
10108 (rhs (string-to-number (match-string 4 out)))
10109 (post (match-string 5 out))
10111 (when (equal pre "-")
10112 (setq lhs (- lhs)))
10113 (setq val (if (equal (match-string 3 out) "-")
10117 (concat (if (and (equal pre "-")
10119 "" ;; Not "--20" but just "-20"
10121 (int-to-string val)
10126 ;;(verilog-simplify-range-expression "[1:3]") ;; 1
10127 ;;(verilog-simplify-range-expression "[(1):3]") ;; 1
10128 ;;(verilog-simplify-range-expression "[(((16)+1)+1+(1+1))]") ;;20
10129 ;;(verilog-simplify-range-expression "[(2*3+6*7)]") ;; 48
10130 ;;(verilog-simplify-range-expression "[(FOO*4-1*2)]") ;; FOO*4-2
10131 ;;(verilog-simplify-range-expression "[(FOO*4+1-1)]") ;; FOO*4+0
10132 ;;(verilog-simplify-range-expression "[(func(BAR))]") ;; func(BAR)
10133 ;;(verilog-simplify-range-expression "[FOO-1+1-1+1]") ;; FOO-0
10134 ;;(verilog-simplify-range-expression "[$clog2(2)]") ;; 1
10135 ;;(verilog-simplify-range-expression "[$clog2(7)]") ;; 3
10137 (defun verilog-clog2 (value)
10138 "Compute $clog2 - ceiling log2 of VALUE."
10141 (ceiling (/ (log value) (log 2)))))
10143 (defun verilog-typedef-name-p (variable-name)
10144 "Return true if the VARIABLE-NAME is a type definition."
10145 (when verilog-typedef-regexp
10146 (verilog-string-match-fold verilog-typedef-regexp variable-name)))
10152 (defun verilog-delete-autos-lined ()
10153 "Delete autos that occupy multiple lines, between begin and end comments."
10154 ;; The newline must not have a comment property, so we must
10155 ;; delete the end auto's newline, not the first newline
10157 (let ((pt (point)))
10159 (looking-at "\\s-*// Beginning")
10160 (search-forward "// End of automatic" nil t))
10164 (delete-region pt (point)))))
10166 (defun verilog-delete-empty-auto-pair ()
10167 "Delete begin/end auto pair at point, if empty."
10169 (when (looking-at (concat "\\s-*// Beginning of automatic.*\n"
10170 "\\s-*// End of automatics\n"))
10171 (delete-region (point) (save-excursion (forward-line 2) (point)))))
10173 (defun verilog-forward-close-paren ()
10174 "Find the close parenthesis that match the current point.
10175 Ignore other close parenthesis with matching open parens."
10177 (while (> parens 0)
10178 (unless (verilog-re-search-forward-quick "[()]" nil t)
10179 (error "%s: Mismatching ()" (verilog-point-text)))
10180 (cond ((= (preceding-char) ?\( )
10181 (setq parens (1+ parens)))
10182 ((= (preceding-char) ?\) )
10183 (setq parens (1- parens)))))))
10185 (defun verilog-backward-open-paren ()
10186 "Find the open parenthesis that match the current point.
10187 Ignore other open parenthesis with matching close parens."
10189 (while (> parens 0)
10190 (unless (verilog-re-search-backward-quick "[()]" nil t)
10191 (error "%s: Mismatching ()" (verilog-point-text)))
10192 (cond ((= (following-char) ?\) )
10193 (setq parens (1+ parens)))
10194 ((= (following-char) ?\( )
10195 (setq parens (1- parens)))))))
10197 (defun verilog-backward-open-bracket ()
10198 "Find the open bracket that match the current point.
10199 Ignore other open bracket with matching close bracket."
10201 (while (> parens 0)
10202 (unless (verilog-re-search-backward-quick "[][]" nil t)
10203 (error "%s: Mismatching []" (verilog-point-text)))
10204 (cond ((= (following-char) ?\] )
10205 (setq parens (1+ parens)))
10206 ((= (following-char) ?\[ )
10207 (setq parens (1- parens)))))))
10209 (defun verilog-delete-to-paren ()
10210 "Delete the automatic inst/sense/arg created by autos.
10211 Deletion stops at the matching end parenthesis, outside comments."
10212 (delete-region (point)
10214 (verilog-backward-open-paren)
10215 (verilog-forward-sexp-ign-cmt 1) ;; Moves to paren that closes argdecl's
10219 (defun verilog-auto-star-safe ()
10220 "Return if a .* AUTOINST is safe to delete or expand.
10221 It was created by the AUTOS themselves, or by the user."
10222 (and verilog-auto-star-expand
10224 (concat "[ \t\n\f,]*\\([)]\\|// " verilog-inst-comment-re "\\)"))))
10226 (defun verilog-delete-auto-star-all ()
10227 "Delete a .* AUTOINST, if it is safe."
10228 (when (verilog-auto-star-safe)
10229 (verilog-delete-to-paren)))
10231 (defun verilog-delete-auto-star-implicit ()
10232 "Delete all .* implicit connections created by `verilog-auto-star'.
10233 This function will be called automatically at save unless
10234 `verilog-auto-star-save' is set, any non-templated expanded pins will be
10237 (let (paren-pt indent have-close-paren)
10239 (goto-char (point-min))
10240 ;; We need to match these even outside of comments.
10241 ;; For reasonable performance, we don't check if inside comments, sorry.
10242 (while (re-search-forward "// Implicit \\.\\*" nil t)
10243 (setq paren-pt (point))
10244 (beginning-of-line)
10245 (setq have-close-paren
10247 (when (search-forward ");" paren-pt t)
10248 (setq indent (current-indentation))
10250 (delete-region (point) (+ 1 paren-pt)) ; Nuke line incl CR
10251 (when have-close-paren
10252 ;; Delete extra commentary
10256 (looking-at (concat "\\s *//\\s *" verilog-inst-comment-re "\n")))
10257 (delete-region (match-beginning 0) (match-end 0))))
10258 ;; If it is simple, we can put the ); on the same line as the last text
10259 (let ((rtn-pt (point)))
10261 (while (progn (backward-char 1)
10262 (looking-at "[ \t\n\f]")))
10263 (when (looking-at ",")
10264 (delete-region (+ 1 (point)) rtn-pt))))
10266 (indent-to indent))
10268 ;; Still need to kill final comma - always is one as we put one after the .*
10269 (re-search-backward ",")
10270 (delete-char 1))))))
10272 (defun verilog-delete-auto ()
10273 "Delete the automatic outputs, regs, and wires created by \\[verilog-auto].
10274 Use \\[verilog-auto] to re-insert the updated AUTOs.
10276 The hooks `verilog-before-delete-auto-hook' and `verilog-delete-auto-hook' are
10277 called before and after this function, respectively."
10280 (if (buffer-file-name)
10281 (find-file-noselect (buffer-file-name))) ;; To check we have latest version
10282 (verilog-save-no-change-functions
10283 (verilog-save-scan-cache
10284 ;; Allow user to customize
10285 (verilog-run-hooks 'verilog-before-delete-auto-hook)
10287 ;; Remove those that have multi-line insertions, possibly with parameters
10288 ;; We allow anything beginning with AUTO, so that users can add their own
10290 (verilog-auto-re-search-do
10291 (concat "/\\*AUTO[A-Za-z0-9_]+"
10292 ;; Optional parens or quoted parameter or .* for (((...)))
10293 "\\(\\|([^)]*)\\|(\"[^\"]*\")\\).*?"
10295 'verilog-delete-autos-lined)
10296 ;; Remove those that are in parenthesis
10297 (verilog-auto-re-search-do
10300 (verilog-regexp-words
10301 `("AS" "AUTOARG" "AUTOCONCATWIDTH" "AUTOINST" "AUTOINSTPARAM"
10304 'verilog-delete-to-paren)
10305 ;; Do .* instantiations, but avoid removing any user pins by looking for our magic comments
10306 (verilog-auto-re-search-do "\\.\\*"
10307 'verilog-delete-auto-star-all)
10308 ;; Remove template comments ... anywhere in case was pasted after AUTOINST removed
10309 (goto-char (point-min))
10310 (while (re-search-forward "\\s-*// \\(Templated\\|Implicit \\.\\*\\)\\([ \tLT0-9]*\\| LHS: .*\\)?$" nil t)
10311 (replace-match ""))
10314 (verilog-run-hooks 'verilog-delete-auto-hook)))))
10320 (defun verilog-inject-auto ()
10321 "Examine legacy non-AUTO code and insert AUTOs in appropriate places.
10323 Any always @ blocks with sensitivity lists that match computed lists will
10324 be replaced with /*AS*/ comments.
10326 Any cells will get /*AUTOINST*/ added to the end of the pin list.
10327 Pins with have identical names will be deleted.
10329 Argument lists will not be deleted, /*AUTOARG*/ will only be inserted to
10330 support adding new ports. You may wish to delete older ports yourself.
10334 module ExampInject (i, o);
10340 InstModule instName
10345 Typing \\[verilog-inject-auto] will make this into:
10347 module ExampInject (i, o/*AUTOARG*/
10352 always @ (/*AS*/i or j)
10354 InstModule instName
10363 (defun verilog-inject-arg ()
10364 "Inject AUTOARG into new code. See `verilog-inject-auto'."
10365 ;; Presume one module per file.
10367 (goto-char (point-min))
10368 (while (verilog-re-search-forward-quick "\\<module\\>" nil t)
10369 (let ((endmodp (save-excursion
10370 (verilog-re-search-forward-quick "\\<endmodule\\>" nil t)
10372 ;; See if there's already a comment .. inside a comment so not verilog-re-search
10373 (when (not (re-search-forward "/\\*AUTOARG\\*/" endmodp t))
10374 (verilog-re-search-forward-quick ";" nil t)
10376 (verilog-backward-syntactic-ws-quick)
10377 (backward-char 1) ; Moves to paren that closes argdecl's
10378 (when (looking-at ")")
10379 (verilog-insert "/*AUTOARG*/")))))))
10381 (defun verilog-inject-sense ()
10382 "Inject AUTOSENSE into new code. See `verilog-inject-auto'."
10384 (goto-char (point-min))
10385 (while (verilog-re-search-forward-quick "\\<always\\s *@\\s *(" nil t)
10386 (let* ((start-pt (point))
10387 (modi (verilog-modi-current))
10388 (moddecls (verilog-modi-get-decls modi))
10392 (verilog-forward-sexp-ign-cmt 1)
10393 (backward-char 1) ;; End )
10394 (when (not (verilog-re-search-backward-quick "/\\*\\(AUTOSENSE\\|AS\\)\\*/" start-pt t))
10395 (setq pre-sigs (verilog-signals-from-signame
10396 (verilog-read-signals start-pt (point)))
10397 got-sigs (verilog-auto-sense-sigs moddecls nil))
10398 (when (not (or (verilog-signals-not-in pre-sigs got-sigs) ; Both are equal?
10399 (verilog-signals-not-in got-sigs pre-sigs)))
10400 (delete-region start-pt (point))
10401 (verilog-insert "/*AS*/")))))))
10403 (defun verilog-inject-inst ()
10404 "Inject AUTOINST into new code. See `verilog-inject-auto'."
10406 (goto-char (point-min))
10407 ;; It's hard to distinguish modules; we'll instead search for pins.
10408 (while (verilog-re-search-forward-quick "\\.\\s *[a-zA-Z0-9`_\$]+\\s *(\\s *[a-zA-Z0-9`_\$]+\\s *)" nil t)
10409 (verilog-backward-open-paren) ;; Inst start
10411 ((= (preceding-char) ?\#) ;; #(...) parameter section, not pin. Skip.
10413 (verilog-forward-close-paren)) ;; Parameters done
10416 (let ((indent-pt (+ (current-column)))
10417 (end-pt (save-excursion (verilog-forward-close-paren) (point))))
10418 (cond ((verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-pt t)
10419 (goto-char end-pt)) ;; Already there, continue search with next instance
10421 ;; Delete identical interconnect
10422 (let ((case-fold-search nil)) ;; So we don't convert upper-to-lower, etc
10423 (while (verilog-re-search-forward-quick "\\.\\s *\\([a-zA-Z0-9`_\$]+\\)*\\s *(\\s *\\1\\s *)\\s *" end-pt t)
10424 (delete-region (match-beginning 0) (match-end 0))
10425 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))) ;; Keep it correct
10426 (while (or (looking-at "[ \t\n\f,]+")
10427 (looking-at "//[^\n]*"))
10428 (delete-region (match-beginning 0) (match-end 0))
10429 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))))))
10430 (verilog-forward-close-paren)
10432 ;; Not verilog-re-search, as we don't want to strip comments
10433 (while (re-search-backward "[ \t\n\f]+" (- (point) 1) t)
10434 (delete-region (match-beginning 0) (match-end 0)))
10435 (verilog-insert "\n")
10436 (verilog-insert-indent "/*AUTOINST*/")))))))))
10442 (defun verilog-diff-buffers-p (b1 b2 &optional whitespace)
10443 "Return nil if buffers B1 and B2 have same contents.
10444 Else, return point in B1 that first mismatches.
10445 If optional WHITESPACE true, ignore whitespace."
10447 (let* ((case-fold-search nil) ;; compare-buffer-substrings cares
10448 (p1 (with-current-buffer b1 (goto-char (point-min))))
10449 (p2 (with-current-buffer b2 (goto-char (point-min))))
10450 (maxp1 (with-current-buffer b1 (point-max)))
10451 (maxp2 (with-current-buffer b2 (point-max)))
10454 (while (not (and (eq p1 op1) (eq p2 op2)))
10455 ;; If both windows have whitespace optionally skip over it.
10457 ;; skip-syntax-* doesn't count \n
10458 (with-current-buffer b1
10460 (skip-chars-forward " \t\n\r\f\v")
10462 (with-current-buffer b2
10464 (skip-chars-forward " \t\n\r\f\v")
10465 (setq p2 (point))))
10466 (setq size (min (- maxp1 p1) (- maxp2 p2)))
10467 (setq progress (compare-buffer-substrings b2 p2 (+ size p2)
10468 b1 p1 (+ size p1)))
10469 (setq progress (if (zerop progress) size (1- (abs progress))))
10470 (setq op1 p1 op2 p2
10472 p2 (+ p2 progress)))
10474 (if (and (eq p1 maxp1) (eq p2 maxp2))
10477 (defun verilog-diff-file-with-buffer (f1 b2 &optional whitespace show)
10478 "View the differences between file F1 and buffer B2.
10479 This requires the external program `diff-command' to be in your `exec-path',
10480 and uses `diff-switches' in which you may want to have \"-u\" flag.
10481 Ignores WHITESPACE if t, and writes output to stdout if SHOW."
10482 ;; Similar to `diff-buffer-with-file' but works on XEmacs, and doesn't
10483 ;; call `diff' as `diff' has different calling semantics on different
10484 ;; versions of Emacs.
10485 (if (not (file-exists-p f1))
10486 (message "Buffer %s has no associated file on disc" (buffer-name b2))
10487 (with-temp-buffer "*Verilog-Diff*"
10488 (let ((outbuf (current-buffer))
10489 (f2 (make-temp-file "vm-diff-auto-")))
10492 (with-current-buffer b2
10495 (write-region (point-min) (point-max) f2 nil 'nomessage)))
10496 (call-process diff-command nil outbuf t
10497 diff-switches ;; User may want -u in diff-switches
10498 (if whitespace "-b" "")
10500 ;; Print out results. Alternatively we could have call-processed
10501 ;; ourself, but this way we can reuse diff switches
10503 (with-current-buffer outbuf (message "%s" (buffer-string))))))
10505 (when (file-exists-p f2)
10506 (delete-file f2))))))
10508 (defun verilog-diff-report (b1 b2 diffpt)
10509 "Report differences detected with `verilog-diff-auto'.
10510 Differences are between buffers B1 and B2, starting at point
10511 DIFFPT. This function is called via `verilog-diff-function'."
10512 (let ((name1 (with-current-buffer b1 (buffer-file-name))))
10513 (verilog-warn "%s:%d: Difference in AUTO expansion found"
10514 name1 (with-current-buffer b1
10515 (count-lines (point-min) diffpt)))
10516 (cond (noninteractive
10517 (verilog-diff-file-with-buffer name1 b2 t t))
10519 (ediff-buffers b1 b2)))))
10521 (defun verilog-diff-auto ()
10522 "Expand AUTOs in a temporary buffer and indicate any change.
10523 Whitespace is ignored when detecting differences, but once a
10524 difference is detected, whitespace differences may be shown.
10526 To call this from the command line, see \\[verilog-batch-diff-auto].
10528 The action on differences is selected with
10529 `verilog-diff-function'. The default is `verilog-diff-report'
10530 which will report an error and run `ediff' in interactive mode,
10531 or `diff' in batch mode."
10533 (let ((b1 (current-buffer)) b2 diffpt
10534 (name1 (buffer-file-name))
10535 (newname "*Verilog-Diff*"))
10537 (when (get-buffer newname)
10538 (kill-buffer newname))
10539 (setq b2 (let (buffer-file-name) ;; Else clone is upset
10540 (clone-buffer newname)))
10541 (with-current-buffer b2
10542 ;; auto requires the filename, but can't have same filename in two
10543 ;; buffers; so override both b1 and b2's names
10544 (let ((buffer-file-name name1))
10547 (with-current-buffer b1 (setq buffer-file-name nil))
10549 (when (not verilog-auto-star-save)
10550 (verilog-delete-auto-star-implicit)))
10551 ;; Restore name if unwind
10552 (with-current-buffer b1 (setq buffer-file-name name1)))))
10554 (setq diffpt (verilog-diff-buffers-p b1 b2 t))
10555 (cond ((not diffpt)
10556 (unless noninteractive (message "AUTO expansion identical"))
10557 (kill-buffer newname)) ;; Nice to cleanup after oneself
10559 (funcall verilog-diff-function b1 b2 diffpt)))
10560 ;; Return result of compare
10568 (defun verilog-auto-save-check ()
10569 "On saving see if we need auto update."
10570 (cond ((not verilog-auto-save-policy)) ; disabled
10571 ((not (save-excursion
10573 (let ((case-fold-search nil))
10574 (goto-char (point-min))
10575 (re-search-forward "AUTO" nil t))))))
10576 ((eq verilog-auto-save-policy 'force)
10578 ((not (buffer-modified-p)))
10579 ((eq verilog-auto-update-tick (buffer-chars-modified-tick))) ; up-to-date
10580 ((eq verilog-auto-save-policy 'detect)
10583 (when (yes-or-no-p "AUTO statements not recomputed, do it now? ")
10585 ;; Don't ask again if didn't update
10586 (set (make-local-variable 'verilog-auto-update-tick) (buffer-chars-modified-tick))))
10587 (when (not verilog-auto-star-save)
10588 (verilog-delete-auto-star-implicit))
10589 nil) ;; Always return nil -- we don't write the file ourselves
10591 (defun verilog-auto-read-locals ()
10592 "Return file local variable segment at bottom of file."
10594 (goto-char (point-max))
10595 (if (re-search-backward "Local Variables:" nil t)
10596 (buffer-substring-no-properties (point) (point-max))
10599 (defun verilog-auto-reeval-locals (&optional force)
10600 "Read file local variable segment at bottom of file if it has changed.
10601 If FORCE, always reread it."
10602 (let ((curlocal (verilog-auto-read-locals)))
10603 (when (or force (not (equal verilog-auto-last-file-locals curlocal)))
10604 (set (make-local-variable 'verilog-auto-last-file-locals) curlocal)
10605 ;; Note this may cause this function to be recursively invoked,
10606 ;; because hack-local-variables may call (verilog-mode)
10607 ;; The above when statement will prevent it from recursing forever.
10608 (hack-local-variables)
10615 (defun verilog-auto-arg-ports (sigs message indent-pt)
10616 "Print a list of ports for an AUTOINST.
10617 Takes SIGS list, adds MESSAGE to front and inserts each at INDENT-PT."
10619 (when verilog-auto-arg-sort
10620 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
10622 (indent-to indent-pt)
10626 (indent-to indent-pt)
10628 (cond ((> (+ 2 (current-column) (length (verilog-sig-name (car sigs)))) fill-column)
10630 (indent-to indent-pt))
10631 (t (insert space)))
10632 (insert (verilog-sig-name (car sigs)) ",")
10633 (setq sigs (cdr sigs)
10636 (defun verilog-auto-arg ()
10637 "Expand AUTOARG statements.
10638 Replace the argument declarations at the beginning of the
10639 module with ones automatically derived from input and output
10640 statements. This can be dangerous if the module is instantiated
10641 using position-based connections, so use only name-based when
10642 instantiating the resulting module. Long lines are split based
10643 on the `fill-column', see \\[set-fill-column].
10646 Concatenation and outputting partial buses is not supported.
10648 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
10652 module ExampArg (/*AUTOARG*/);
10657 Typing \\[verilog-auto] will make this into:
10659 module ExampArg (/*AUTOARG*/
10669 The argument declarations may be printed in declaration order to best suit
10670 order based instantiations, or alphabetically, based on the
10671 `verilog-auto-arg-sort' variable.
10673 Any ports declared between the ( and /*AUTOARG*/ are presumed to be
10674 predeclared and are not redeclared by AUTOARG. AUTOARG will make a
10675 conservative guess on adding a comma for the first signal, if you have
10676 any ifdefs or complicated expressions before the AUTOARG you will need
10677 to choose the comma yourself.
10679 Avoid declaring ports manually, as it makes code harder to maintain."
10681 (let* ((modi (verilog-modi-current))
10682 (moddecls (verilog-modi-get-decls modi))
10683 (skip-pins (aref (verilog-read-arg-pins) 0)))
10684 (verilog-repair-open-comma)
10685 (verilog-auto-arg-ports (verilog-signals-not-in
10686 (verilog-decls-get-outputs moddecls)
10689 verilog-indent-level-declaration)
10690 (verilog-auto-arg-ports (verilog-signals-not-in
10691 (verilog-decls-get-inouts moddecls)
10694 verilog-indent-level-declaration)
10695 (verilog-auto-arg-ports (verilog-signals-not-in
10696 (verilog-decls-get-inputs moddecls)
10699 verilog-indent-level-declaration)
10700 (verilog-repair-close-comma)
10701 (unless (eq (char-before) ?/ )
10703 (indent-to verilog-indent-level-declaration))))
10705 (defun verilog-auto-assign-modport ()
10706 "Expand AUTOASSIGNMODPORT statements, as part of \\[verilog-auto].
10707 Take input/output/inout statements from the specified interface
10708 and modport and use to build assignments into the modport, for
10709 making verification modules that connect to UVM interfaces.
10711 The first parameter is the name of an interface.
10713 The second parameter is a regexp of modports to read from in
10716 The third parameter is the instance name to use to dot reference into.
10718 The optional fourth parameter is a regular expression, and only
10719 signals matching the regular expression will be included.
10723 Interface names must be resolvable to filenames. See `verilog-auto-inst'.
10725 Inouts are not supported, as assignments must be unidirectional.
10727 If a signal is part of the interface header and in both a
10728 modport and the interface itself, it will not be listed. (As
10729 this would result in a syntax error when the connections are
10732 See the example in `verilog-auto-inout-modport'."
10734 (let* ((params (verilog-read-auto-params 3 4))
10735 (submod (nth 0 params))
10736 (modport-re (nth 1 params))
10737 (inst-name (nth 2 params))
10738 (regexp (nth 3 params))
10739 direction-re submodi) ;; direction argument not supported until requested
10740 ;; Lookup position, etc of co-module
10741 ;; Note this may raise an error
10742 (when (setq submodi (verilog-modi-lookup submod t))
10743 (let* ((indent-pt (current-indentation))
10744 (submoddecls (verilog-modi-get-decls submodi))
10745 (submodportdecls (verilog-modi-modport-lookup submodi modport-re))
10746 (sig-list-i (verilog-signals-in ;; Decls doesn't have data types, must resolve
10747 (verilog-decls-get-vars submoddecls)
10748 (verilog-signals-not-in
10749 (verilog-decls-get-inputs submodportdecls)
10750 (verilog-decls-get-ports submoddecls))))
10751 (sig-list-o (verilog-signals-in ;; Decls doesn't have data types, must resolve
10752 (verilog-decls-get-vars submoddecls)
10753 (verilog-signals-not-in
10754 (verilog-decls-get-outputs submodportdecls)
10755 (verilog-decls-get-ports submoddecls)))))
10757 (setq sig-list-i (verilog-signals-edit-wire-reg
10758 (verilog-signals-matching-dir-re
10759 (verilog-signals-matching-regexp sig-list-i regexp)
10760 "input" direction-re))
10761 sig-list-o (verilog-signals-edit-wire-reg
10762 (verilog-signals-matching-dir-re
10763 (verilog-signals-matching-regexp sig-list-o regexp)
10764 "output" direction-re)))
10765 (setq sig-list-i (sort (copy-alist sig-list-i) `verilog-signals-sort-compare))
10766 (setq sig-list-o (sort (copy-alist sig-list-o) `verilog-signals-sort-compare))
10767 (when (or sig-list-i sig-list-o)
10768 (verilog-insert-indent "// Beginning of automatic assignments from modport\n")
10769 ;; Don't sort them so an upper AUTOINST will match the main module
10770 (let ((sigs sig-list-o))
10772 (verilog-insert-indent "assign " (verilog-sig-name (car sigs))
10774 "." (verilog-sig-name (car sigs)) ";\n")
10775 (setq sigs (cdr sigs))))
10776 (let ((sigs sig-list-i))
10778 (verilog-insert-indent "assign " inst-name
10779 "." (verilog-sig-name (car sigs))
10780 " = " (verilog-sig-name (car sigs)) ";\n")
10781 (setq sigs (cdr sigs))))
10782 (verilog-insert-indent "// End of automatics\n")))))))
10784 (defun verilog-auto-inst-port-map (_port-st)
10787 (defvar vl-cell-type nil "See `verilog-auto-inst'.") ; Prevent compile warning
10788 (defvar vl-cell-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
10789 (defvar vl-modport nil "See `verilog-auto-inst'.") ; Prevent compile warning
10790 (defvar vl-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
10791 (defvar vl-width nil "See `verilog-auto-inst'.") ; Prevent compile warning
10792 (defvar vl-dir nil "See `verilog-auto-inst'.") ; Prevent compile warning
10793 (defvar vl-bits nil "See `verilog-auto-inst'.") ; Prevent compile warning
10794 (defvar vl-mbits nil "See `verilog-auto-inst'.") ; Prevent compile warning
10796 (defun verilog-auto-inst-port (port-st indent-pt tpl-list tpl-num for-star par-values)
10797 "Print out an instantiation connection for this PORT-ST.
10798 Insert to INDENT-PT, use template TPL-LIST.
10799 @ are instantiation numbers, replaced with TPL-NUM.
10800 @\"(expression @)\" are evaluated, with @ as a variable.
10801 If FOR-STAR add comment it is a .* expansion.
10802 If PAR-VALUES replace final strings with these parameter values."
10803 (let* ((port (verilog-sig-name port-st))
10804 (tpl-ass (or (assoc port (car tpl-list))
10805 (verilog-auto-inst-port-map port-st)))
10806 ;; vl-* are documented for user use
10807 (vl-name (verilog-sig-name port-st))
10808 (vl-width (verilog-sig-width port-st))
10809 (vl-modport (verilog-sig-modport port-st))
10810 (vl-mbits (if (verilog-sig-multidim port-st)
10811 (verilog-sig-multidim-string port-st) ""))
10812 (vl-bits (if (or verilog-auto-inst-vector
10813 (not (assoc port vector-skip-list))
10814 (not (equal (verilog-sig-bits port-st)
10815 (verilog-sig-bits (assoc port vector-skip-list)))))
10816 (or (verilog-sig-bits port-st) "")
10818 (case-fold-search nil)
10819 (check-values par-values)
10821 ;; Replace parameters in bit-width
10822 (when (and check-values
10823 (not (equal vl-bits "")))
10824 (while check-values
10825 (setq vl-bits (verilog-string-replace-matches
10826 (concat "\\<" (nth 0 (car check-values)) "\\>")
10827 (concat "(" (nth 1 (car check-values)) ")")
10829 vl-mbits (verilog-string-replace-matches
10830 (concat "\\<" (nth 0 (car check-values)) "\\>")
10831 (concat "(" (nth 1 (car check-values)) ")")
10833 check-values (cdr check-values)))
10834 (setq vl-bits (verilog-simplify-range-expression vl-bits)
10835 vl-mbits (verilog-simplify-range-expression vl-mbits)
10836 vl-width (verilog-make-width-expression vl-bits))) ; Not in the loop for speed
10837 ;; Default net value if not found
10838 (setq dflt-bits (if (and (verilog-sig-bits port-st)
10839 (or (verilog-sig-multidim port-st)
10840 (verilog-sig-memory port-st)))
10841 (concat "/*" vl-mbits vl-bits "*/")
10843 tpl-net (concat port
10844 (if vl-modport (concat "." vl-modport) "")
10847 (cond (tpl-ass ; Template of exact port name
10848 (setq tpl-net (nth 1 tpl-ass)))
10849 ((nth 1 tpl-list) ; Wildcards in template, search them
10850 (let ((wildcards (nth 1 tpl-list)))
10852 (when (string-match (nth 0 (car wildcards)) port)
10853 (setq tpl-ass (car wildcards) ; so allow @ parsing
10854 tpl-net (replace-match (nth 1 (car wildcards))
10856 (setq wildcards (cdr wildcards))))))
10857 ;; Parse Templated variable
10859 ;; Evaluate @"(lispcode)"
10860 (when (string-match "@\".*[^\\]\"" tpl-net)
10861 (while (string-match "@\"\\(\\([^\\\"]*\\(\\\\.\\)*\\)*\\)\"" tpl-net)
10864 (substring tpl-net 0 (match-beginning 0))
10866 (let* ((expr (match-string 1 tpl-net))
10869 (setq expr (verilog-string-replace-matches "\\\\\"" "\"" nil nil expr))
10870 (setq expr (verilog-string-replace-matches "@" tpl-num nil nil expr))
10871 (prin1 (eval (car (read-from-string expr)))
10872 (lambda (_ch) ())))))
10873 (if (numberp value) (setq value (number-to-string value)))
10875 (substring tpl-net (match-end 0))))))
10876 ;; Replace @ and [] magic variables in final output
10877 (setq tpl-net (verilog-string-replace-matches "@" tpl-num nil nil tpl-net))
10878 (setq tpl-net (verilog-string-replace-matches "\\[\\]\\[\\]" dflt-bits nil nil tpl-net))
10879 (setq tpl-net (verilog-string-replace-matches "\\[\\]" vl-bits nil nil tpl-net)))
10881 (indent-to indent-pt)
10883 (unless (and verilog-auto-inst-dot-name
10884 (equal port tpl-net))
10885 (indent-to verilog-auto-inst-column)
10886 (insert "(" tpl-net ")"))
10889 (verilog-read-auto-template-hit tpl-ass)
10890 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
10891 verilog-auto-inst-column))
10892 ;; verilog-insert requires the complete comment in one call - including the newline
10893 (cond ((equal verilog-auto-inst-template-numbers `lhs)
10894 (verilog-insert " // Templated"
10895 " LHS: " (nth 0 tpl-ass)
10897 (verilog-auto-inst-template-numbers
10898 (verilog-insert " // Templated"
10899 " T" (int-to-string (nth 2 tpl-ass))
10900 " L" (int-to-string (nth 3 tpl-ass))
10903 (verilog-insert " // Templated\n"))))
10905 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
10906 verilog-auto-inst-column))
10907 (verilog-insert " // Implicit .\*\n")) ;For some reason the . or * must be escaped...
10910 ;;(verilog-auto-inst-port (list "foo" "[5:0]") 10 (list (list "foo" "a@\"(% (+ @ 1) 4)\"a")) "3")
10911 ;;(x "incom[@\"(+ (* 8 @) 7)\":@\"(* 8 @)\"]")
10912 ;;(x ".out (outgo[@\"(concat (+ (* 8 @) 7) \\\":\\\" ( * 8 @))\"]));")
10914 (defun verilog-auto-inst-port-list (sig-list indent-pt tpl-list tpl-num for-star par-values)
10915 "For `verilog-auto-inst' print a list of ports using `verilog-auto-inst-port'."
10916 (when verilog-auto-inst-sort
10917 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare)))
10918 (mapc (lambda (port)
10919 (verilog-auto-inst-port port indent-pt
10920 tpl-list tpl-num for-star par-values))
10923 (defun verilog-auto-inst-first ()
10924 "Insert , etc before first ever port in this instant, as part of \\[verilog-auto-inst]."
10925 ;; Do we need a trailing comma?
10926 ;; There maybe an ifdef or something similar before us. What a mess. Thus
10927 ;; to avoid trouble we only insert on preceding ) or *.
10928 ;; Insert first port on new line
10929 (insert "\n") ;; Must insert before search, so point will move forward if insert comma
10931 (verilog-re-search-backward-quick "[^ \t\n\f]" nil nil)
10932 (when (looking-at ")\\|\\*") ;; Generally don't insert, unless we are fairly sure
10936 (defun verilog-auto-star ()
10937 "Expand SystemVerilog .* pins, as part of \\[verilog-auto].
10939 If `verilog-auto-star-expand' is set, .* pins are treated if they were
10940 AUTOINST statements, otherwise they are ignored. For safety, Verilog mode
10941 will also ignore any .* that are not last in your pin list (this prevents
10942 it from deleting pins following the .* when it expands the AUTOINST.)
10944 On writing your file, unless `verilog-auto-star-save' is set, any
10945 non-templated expanded pins will be removed. You may do this at any time
10946 with \\[verilog-delete-auto-star-implicit].
10948 If you are converting a module to use .* for the first time, you may wish
10949 to use \\[verilog-inject-auto] and then replace the created AUTOINST with .*.
10951 See `verilog-auto-inst' for examples, templates, and more information."
10952 (when (verilog-auto-star-safe)
10953 (verilog-auto-inst)))
10955 (defun verilog-auto-inst ()
10956 "Expand AUTOINST statements, as part of \\[verilog-auto].
10957 Replace the pin connections to an instantiation or interface
10958 declaration with ones automatically derived from the module or
10959 interface header of the instantiated item.
10961 If `verilog-auto-star-expand' is set, also expand SystemVerilog .* ports,
10962 and delete them before saving unless `verilog-auto-star-save' is set.
10963 See `verilog-auto-star' for more information.
10965 The pins are printed in declaration order or alphabetically,
10966 based on the `verilog-auto-inst-sort' variable.
10969 Module names must be resolvable to filenames by adding a
10970 `verilog-library-extensions', and being found in the same directory, or
10971 by changing the variable `verilog-library-flags' or
10972 `verilog-library-directories'. Macros `modname are translated through the
10973 vh-{name} Emacs variable, if that is not found, it just ignores the `.
10975 In templates you must have one signal per line, ending in a ), or ));,
10976 and have proper () nesting, including a final ); to end the template.
10978 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
10980 SystemVerilog multidimensional input/output has only experimental support.
10982 SystemVerilog .name syntax is used if `verilog-auto-inst-dot-name' is set.
10984 Parameters referenced by the instantiation will remain symbolic, unless
10985 `verilog-auto-inst-param-value' is set.
10987 Gate primitives (and/or) may have AUTOINST for the purpose of
10988 AUTOWIRE declarations, etc. Gates are the only case when
10989 position based connections are passed.
10991 The array part of arrayed instances are ignored; this may
10992 result in undesirable default AUTOINST connections; use a
10995 For example, first take the submodule InstModule.v:
10997 module InstModule (o,i);
11000 wire [31:0] o = {32{i}};
11003 This is then used in an upper level module:
11005 module ExampInst (o,i);
11008 InstModule instName
11012 Typing \\[verilog-auto] will make this into:
11014 module ExampInst (o,i);
11017 InstModule instName
11025 Where the list of inputs and outputs came from the inst module.
11029 Unless you are instantiating a module multiple times, or the module is
11030 something trivial like an adder, DO NOT CHANGE SIGNAL NAMES ACROSS HIERARCHY.
11031 It just makes for unmaintainable code. To sanitize signal names, try
11032 vrename from URL `http://www.veripool.org'.
11034 When you need to violate this suggestion there are two ways to list
11035 exceptions, placing them before the AUTOINST, or using templates.
11037 Any ports defined before the /*AUTOINST*/ are not included in the list of
11038 automatics. This is similar to making a template as described below, but
11039 is restricted to simple connections just like you normally make. Also note
11040 that any signals before the AUTOINST will only be picked up by AUTOWIRE if
11041 you have the appropriate // Input or // Output comment, and exactly the
11042 same line formatting as AUTOINST itself uses.
11044 InstModule instName
11046 .i (my_i_dont_mess_with_it),
11054 For multiple instantiations based upon a single template, create a
11055 commented out template:
11057 /* InstModule AUTO_TEMPLATE (
11062 Templates go ABOVE the instantiation(s). When an instantiation is
11063 expanded `verilog-mode' simply searches up for the closest template.
11064 Thus you can have multiple templates for the same module, just alternate
11065 between the template for an instantiation and the instantiation itself.
11066 (For backward compatibility if no template is found above, it
11067 will also look below, but do not use this behavior in new designs.)
11069 The module name must be the same as the name of the module in the
11070 instantiation name, and the code \"AUTO_TEMPLATE\" must be in these exact
11071 words and capitalized. Only signals that must be different for each
11072 instantiation need to be listed.
11074 Inside a template, a [] in a connection name (with nothing else
11075 inside the brackets) will be replaced by the same bus subscript
11076 as it is being connected to, or the [] will be removed if it is
11077 a single bit signal.
11079 Inside a template, a [][] in a connection name will behave
11080 similarly to a [] for scalar or single-dimensional connection;
11081 for a multidimensional connection it will print a comment
11082 similar to that printed when a template is not used. Generally
11083 it is a good idea to do this for all connections in a template,
11084 as then they will work for any width signal, and with AUTOWIRE.
11085 See PTL_BUS becoming PTL_BUSNEW below.
11087 Inside a template, a [] in a connection name (with nothing else inside
11088 the brackets) will be replaced by the same bus subscript as it is being
11089 connected to, or the [] will be removed if it is a single bit signal.
11090 Generally it is a good idea to do this for all connections in a template,
11091 as then they will work for any width signal, and with AUTOWIRE. See
11092 PTL_BUS becoming PTL_BUSNEW below.
11094 If you have a complicated template, set `verilog-auto-inst-template-numbers'
11095 to see which regexps are matching. Don't leave that mode set after
11096 debugging is completed though, it will result in lots of extra differences
11097 and merge conflicts.
11099 Setting `verilog-auto-template-warn-unused' will report errors
11100 if any template lines are unused.
11104 /* InstModule AUTO_TEMPLATE (
11105 .ptl_bus (ptl_busnew[]),
11108 InstModule ms2m (/*AUTOINST*/);
11110 Typing \\[verilog-auto] will make this into:
11112 InstModule ms2m (/*AUTOINST*/
11114 .NotInTemplate (NotInTemplate),
11115 .ptl_bus (ptl_busnew[3:0]), // Templated
11119 Multiple Module Templates:
11121 The same template lines can be applied to multiple modules with
11122 the syntax as follows:
11124 /* InstModuleA AUTO_TEMPLATE
11125 InstModuleB AUTO_TEMPLATE
11126 InstModuleC AUTO_TEMPLATE
11127 InstModuleD AUTO_TEMPLATE (
11128 .ptl_bus (ptl_busnew[]),
11132 Note there is only one AUTO_TEMPLATE opening parenthesis.
11136 It is common to instantiate a cell multiple times, so templates make it
11137 trivial to substitute part of the cell name into the connection name.
11139 /* InstName AUTO_TEMPLATE <optional \"REGEXP\"> (
11141 .sig2 (sigy[@\"(% (+ 1 @) 4)\"]),
11145 If no regular expression is provided immediately after the AUTO_TEMPLATE
11146 keyword, then the @ character in any connection names will be replaced
11147 with the instantiation number; the first digits found in the cell's
11148 instantiation name.
11150 If a regular expression is provided, the @ character will be replaced
11151 with the first \(\) grouping that matches against the cell name. Using a
11152 regexp of \"\\([0-9]+\\)\" provides identical values for @ as when no
11153 regexp is provided. If you use multiple layers of parenthesis,
11154 \"test\\([^0-9]+\\)_\\([0-9]+\\)\" would replace @ with non-number
11155 characters after test and before _, whereas
11156 \"\\(test\\([a-z]+\\)_\\([0-9]+\\)\\)\" would replace @ with the entire
11161 /* InstModule AUTO_TEMPLATE (
11162 .ptl_mapvalidx (ptl_mapvalid[@]),
11163 .ptl_mapvalidp1x (ptl_mapvalid[@\"(% (+ 1 @) 4)\"]),
11166 InstModule ms2m (/*AUTOINST*/);
11168 Typing \\[verilog-auto] will make this into:
11170 InstModule ms2m (/*AUTOINST*/
11172 .ptl_mapvalidx (ptl_mapvalid[2]),
11173 .ptl_mapvalidp1x (ptl_mapvalid[3]));
11175 Note the @ character was replaced with the 2 from \"ms2m\".
11177 Alternatively, using a regular expression for @:
11179 /* InstModule AUTO_TEMPLATE \"_\\([a-z]+\\)\" (
11180 .ptl_mapvalidx (@_ptl_mapvalid),
11181 .ptl_mapvalidp1x (ptl_mapvalid_@),
11184 InstModule ms2_FOO (/*AUTOINST*/);
11185 InstModule ms2_BAR (/*AUTOINST*/);
11187 Typing \\[verilog-auto] will make this into:
11189 InstModule ms2_FOO (/*AUTOINST*/
11191 .ptl_mapvalidx (FOO_ptl_mapvalid),
11192 .ptl_mapvalidp1x (ptl_mapvalid_FOO));
11193 InstModule ms2_BAR (/*AUTOINST*/
11195 .ptl_mapvalidx (BAR_ptl_mapvalid),
11196 .ptl_mapvalidp1x (ptl_mapvalid_BAR));
11201 A template entry of the form
11203 .pci_req\\([0-9]+\\)_l (pci_req_jtag_[\\1]),
11205 will apply an Emacs style regular expression search for any port beginning
11206 in pci_req followed by numbers and ending in _l and connecting that to
11207 the pci_req_jtag_[] net, with the bus subscript coming from what matches
11208 inside the first set of \\( \\). Thus pci_req2_l becomes pci_req_jtag_[2].
11210 Since \\([0-9]+\\) is so common and ugly to read, a @ in the port name
11211 does the same thing. (Note a @ in the connection/replacement text is
11212 completely different -- still use \\1 there!) Thus this is the same as
11213 the above template:
11215 .pci_req@_l (pci_req_jtag_[\\1]),
11217 Here's another example to remove the _l, useful when naming conventions
11218 specify _ alone to mean active low. Note the use of [] to keep the bus
11221 .\\(.*\\)_l (\\1_[]),
11225 First any regular expression template is expanded.
11227 If the syntax @\"( ... )\" is found in a connection, the expression in
11228 quotes will be evaluated as a Lisp expression, with @ replaced by the
11229 instantiation number. The MAPVALIDP1X example above would put @+1 modulo
11230 4 into the brackets. Quote all double-quotes inside the expression with
11231 a leading backslash (\\\"...\\\"); or if the Lisp template is also a
11232 regexp template backslash the backslash quote (\\\\\"...\\\\\").
11234 There are special variables defined that are useful in these
11237 vl-name Name portion of the input/output port.
11238 vl-bits Bus bits portion of the input/output port ('[2:0]').
11239 vl-mbits Multidimensional array bits for port ('[2:0][3:0]').
11240 vl-width Width of the input/output port ('3' for [2:0]).
11241 May be a (...) expression if bits isn't a constant.
11242 vl-dir Direction of the pin input/output/inout/interface.
11243 vl-modport The modport, if an interface with a modport.
11244 vl-cell-type Module name/type of the cell ('InstModule').
11245 vl-cell-name Instance name of the cell ('instName').
11247 Normal Lisp variables may be used in expressions. See
11248 `verilog-read-defines' which can set vh-{definename} variables for use
11249 here. Also, any comments of the form:
11251 /*AUTO_LISP(setq foo 1)*/
11253 will evaluate any Lisp expression inside the parenthesis between the
11254 beginning of the buffer and the point of the AUTOINST. This allows
11255 functions to be defined or variables to be changed between instantiations.
11256 (See also `verilog-auto-insert-lisp' if you want the output from your
11257 lisp function to be inserted.)
11259 Note that when using lisp expressions errors may occur when @ is not a
11260 number; you may need to use the standard Emacs Lisp functions
11261 `number-to-string' and `string-to-number'.
11263 After the evaluation is completed, @ substitution and [] substitution
11266 For more information see the \\[verilog-faq] and forums at URL
11267 `http://www.veripool.org'."
11270 (let* ((pt (point))
11271 (for-star (save-excursion (backward-char 2) (looking-at "\\.\\*")))
11272 (indent-pt (save-excursion (verilog-backward-open-paren)
11273 (1+ (current-column))))
11274 (verilog-auto-inst-column (max verilog-auto-inst-column
11275 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
11276 (modi (verilog-modi-current))
11277 (moddecls (verilog-modi-get-decls modi))
11278 (vector-skip-list (unless verilog-auto-inst-vector
11279 (verilog-decls-get-signals moddecls)))
11280 submod submodi submoddecls
11281 inst skip-pins tpl-list tpl-num did-first par-values)
11283 ;; Find module name that is instantiated
11284 (setq submod (verilog-read-inst-module)
11285 inst (verilog-read-inst-name)
11286 vl-cell-type submod
11288 skip-pins (aref (verilog-read-inst-pins) 0))
11290 ;; Parse any AUTO_LISP() before here
11291 (verilog-read-auto-lisp (point-min) pt)
11293 ;; Read parameters (after AUTO_LISP)
11294 (setq par-values (and verilog-auto-inst-param-value
11295 (verilog-read-inst-param-value)))
11297 ;; Lookup position, etc of submodule
11298 ;; Note this may raise an error
11299 (when (and (not (member submod verilog-gate-keywords))
11300 (setq submodi (verilog-modi-lookup submod t)))
11301 (setq submoddecls (verilog-modi-get-decls submodi))
11302 ;; If there's a number in the instantiation, it may be an argument to the
11303 ;; automatic variable instantiation program.
11304 (let* ((tpl-info (verilog-read-auto-template submod))
11305 (tpl-regexp (aref tpl-info 0)))
11306 (setq tpl-num (if (verilog-string-match-fold tpl-regexp inst)
11307 (match-string 1 inst)
11309 tpl-list (aref tpl-info 1)))
11310 ;; Find submodule's signals and dump
11311 (let ((sig-list (and (equal (verilog-modi-get-type submodi) "interface")
11312 (verilog-signals-not-in
11313 (verilog-decls-get-vars submoddecls)
11315 (vl-dir "interfaced"))
11316 (when (and sig-list
11317 verilog-auto-inst-interfaced-ports)
11318 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11319 ;; Note these are searched for in verilog-read-sub-decls.
11320 (verilog-insert-indent "// Interfaced\n")
11321 (verilog-auto-inst-port-list sig-list indent-pt
11322 tpl-list tpl-num for-star par-values)))
11323 (let ((sig-list (verilog-signals-not-in
11324 (verilog-decls-get-interfaces submoddecls)
11326 (vl-dir "interface"))
11328 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11329 ;; Note these are searched for in verilog-read-sub-decls.
11330 (verilog-insert-indent "// Interfaces\n")
11331 (verilog-auto-inst-port-list sig-list indent-pt
11332 tpl-list tpl-num for-star par-values)))
11333 (let ((sig-list (verilog-signals-not-in
11334 (verilog-decls-get-outputs submoddecls)
11338 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11339 (verilog-insert-indent "// Outputs\n")
11340 (verilog-auto-inst-port-list sig-list indent-pt
11341 tpl-list tpl-num for-star par-values)))
11342 (let ((sig-list (verilog-signals-not-in
11343 (verilog-decls-get-inouts submoddecls)
11347 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11348 (verilog-insert-indent "// Inouts\n")
11349 (verilog-auto-inst-port-list sig-list indent-pt
11350 tpl-list tpl-num for-star par-values)))
11351 (let ((sig-list (verilog-signals-not-in
11352 (verilog-decls-get-inputs submoddecls)
11356 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11357 (verilog-insert-indent "// Inputs\n")
11358 (verilog-auto-inst-port-list sig-list indent-pt
11359 tpl-list tpl-num for-star par-values)))
11363 (re-search-backward "," pt t)
11366 (search-forward "\n") ;; Added by inst-port
11368 (if (search-forward ")" nil t) ;; From user, moved up a line
11370 (if (search-forward ";" nil t) ;; Don't error if user had syntax error and forgot it
11371 (delete-char -1)))))))))
11373 (defun verilog-auto-inst-param ()
11374 "Expand AUTOINSTPARAM statements, as part of \\[verilog-auto].
11375 Replace the parameter connections to an instantiation with ones
11376 automatically derived from the module header of the instantiated netlist.
11378 See \\[verilog-auto-inst] for limitations, and templates to customize the
11381 For example, first take the submodule InstModule.v:
11383 module InstModule (o,i);
11387 This is then used in an upper level module:
11389 module ExampInst (o,i);
11391 InstModule #(/*AUTOINSTPARAM*/)
11392 instName (/*AUTOINST*/);
11395 Typing \\[verilog-auto] will make this into:
11397 module ExampInst (o,i);
11400 InstModule #(/*AUTOINSTPARAM*/
11403 instName (/*AUTOINST*/);
11406 Where the list of parameter connections come from the inst module.
11410 You can customize the parameter connections using AUTO_TEMPLATEs,
11411 just as you would with \\[verilog-auto-inst]."
11414 (let* ((pt (point))
11415 (indent-pt (save-excursion (verilog-backward-open-paren)
11416 (1+ (current-column))))
11417 (verilog-auto-inst-column (max verilog-auto-inst-column
11418 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
11419 (modi (verilog-modi-current))
11420 (moddecls (verilog-modi-get-decls modi))
11421 (vector-skip-list (unless verilog-auto-inst-vector
11422 (verilog-decls-get-signals moddecls)))
11423 submod submodi submoddecls
11424 inst skip-pins tpl-list tpl-num did-first)
11425 ;; Find module name that is instantiated
11426 (setq submod (save-excursion
11427 ;; Get to the point where AUTOINST normally is to read the module
11428 (verilog-re-search-forward-quick "[(;]" nil nil)
11429 (verilog-read-inst-module))
11430 inst (save-excursion
11431 ;; Get to the point where AUTOINST normally is to read the module
11432 (verilog-re-search-forward-quick "[(;]" nil nil)
11433 (verilog-read-inst-name))
11434 vl-cell-type submod
11436 skip-pins (aref (verilog-read-inst-pins) 0))
11438 ;; Parse any AUTO_LISP() before here
11439 (verilog-read-auto-lisp (point-min) pt)
11441 ;; Lookup position, etc of submodule
11442 ;; Note this may raise an error
11443 (when (setq submodi (verilog-modi-lookup submod t))
11444 (setq submoddecls (verilog-modi-get-decls submodi))
11445 ;; If there's a number in the instantiation, it may be an argument to the
11446 ;; automatic variable instantiation program.
11447 (let* ((tpl-info (verilog-read-auto-template submod))
11448 (tpl-regexp (aref tpl-info 0)))
11449 (setq tpl-num (if (verilog-string-match-fold tpl-regexp inst)
11450 (match-string 1 inst)
11452 tpl-list (aref tpl-info 1)))
11453 ;; Find submodule's signals and dump
11454 (let ((sig-list (verilog-signals-not-in
11455 (verilog-decls-get-gparams submoddecls)
11457 (vl-dir "parameter"))
11459 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11460 ;; Note these are searched for in verilog-read-sub-decls.
11461 (verilog-insert-indent "// Parameters\n")
11462 (verilog-auto-inst-port-list sig-list indent-pt
11463 tpl-list tpl-num nil nil)))
11467 (re-search-backward "," pt t)
11470 (search-forward "\n") ;; Added by inst-port
11472 (if (search-forward ")" nil t) ;; From user, moved up a line
11473 (delete-char -1)))))))))
11475 (defun verilog-auto-reg ()
11476 "Expand AUTOREG statements, as part of \\[verilog-auto].
11477 Make reg statements for any output that isn't already declared,
11478 and isn't a wire output from a block. `verilog-auto-wire-type'
11479 may be used to change the datatype of the declarations.
11482 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
11484 This does NOT work on memories, declare those yourself.
11488 module ExampReg (o,i);
11495 Typing \\[verilog-auto] will make this into:
11497 module ExampReg (o,i);
11501 // Beginning of automatic regs (for this module's undeclared outputs)
11503 // End of automatics
11507 ;; Point must be at insertion point.
11508 (let* ((indent-pt (current-indentation))
11509 (modi (verilog-modi-current))
11510 (moddecls (verilog-modi-get-decls modi))
11511 (modsubdecls (verilog-modi-get-sub-decls modi))
11512 (sig-list (verilog-signals-not-in
11513 (verilog-decls-get-outputs moddecls)
11514 (append (verilog-signals-with ;; ignore typed signals
11516 (verilog-decls-get-outputs moddecls))
11517 (verilog-decls-get-vars moddecls)
11518 (verilog-decls-get-assigns moddecls)
11519 (verilog-decls-get-consts moddecls)
11520 (verilog-decls-get-gparams moddecls)
11521 (verilog-subdecls-get-interfaced modsubdecls)
11522 (verilog-subdecls-get-outputs modsubdecls)
11523 (verilog-subdecls-get-inouts modsubdecls)))))
11525 (verilog-forward-or-insert-line)
11526 (verilog-insert-indent "// Beginning of automatic regs (for this module's undeclared outputs)\n")
11527 (verilog-insert-definition modi sig-list "reg" indent-pt nil)
11528 (verilog-insert-indent "// End of automatics\n")))))
11530 (defun verilog-auto-reg-input ()
11531 "Expand AUTOREGINPUT statements, as part of \\[verilog-auto].
11532 Make reg statements instantiation inputs that aren't already declared.
11533 This is useful for making a top level shell for testing the module that is
11534 to be instantiated.
11537 This ONLY detects inputs of AUTOINSTants (see `verilog-read-sub-decls').
11539 This does NOT work on memories, declare those yourself.
11541 An example (see `verilog-auto-inst' for what else is going on here):
11543 module ExampRegInput (o,i);
11547 InstModule instName
11551 Typing \\[verilog-auto] will make this into:
11553 module ExampRegInput (o,i);
11557 // Beginning of automatic reg inputs (for undeclared ...
11558 reg [31:0] iv; // From inst of inst.v
11559 // End of automatics
11560 InstModule instName
11568 ;; Point must be at insertion point.
11569 (let* ((indent-pt (current-indentation))
11570 (modi (verilog-modi-current))
11571 (moddecls (verilog-modi-get-decls modi))
11572 (modsubdecls (verilog-modi-get-sub-decls modi))
11573 (sig-list (verilog-signals-combine-bus
11574 (verilog-signals-not-in
11575 (append (verilog-subdecls-get-inputs modsubdecls)
11576 (verilog-subdecls-get-inouts modsubdecls))
11577 (append (verilog-decls-get-signals moddecls)
11578 (verilog-decls-get-assigns moddecls))))))
11580 (verilog-forward-or-insert-line)
11581 (verilog-insert-indent "// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)\n")
11582 (verilog-insert-definition modi sig-list "reg" indent-pt nil)
11583 (verilog-insert-indent "// End of automatics\n")))))
11585 (defun verilog-auto-logic-setup ()
11586 "Prepare variables due to AUTOLOGIC."
11587 (unless verilog-auto-wire-type
11588 (set (make-local-variable 'verilog-auto-wire-type)
11591 (defun verilog-auto-logic ()
11592 "Expand AUTOLOGIC statements, as part of \\[verilog-auto].
11593 Make wire statements using the SystemVerilog logic keyword.
11594 This is currently equivalent to:
11598 with the below at the bottom of the file
11600 // Local Variables:
11601 // verilog-auto-logic-type:\"logic\"
11604 In the future AUTOLOGIC may declare additional identifiers,
11605 while AUTOWIRE will not."
11607 (verilog-auto-logic-setup)
11608 (verilog-auto-wire)))
11610 (defun verilog-auto-wire ()
11611 "Expand AUTOWIRE statements, as part of \\[verilog-auto].
11612 Make wire statements for instantiations outputs that aren't
11613 already declared. `verilog-auto-wire-type' may be used to change
11614 the datatype of the declarations.
11617 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'),
11618 and all buses must have widths, such as those from AUTOINST, or using []
11621 This does NOT work on memories or SystemVerilog .name connections,
11622 declare those yourself.
11624 Verilog mode will add \"Couldn't Merge\" comments to signals it cannot
11625 determine how to bus together. This occurs when you have ports with
11626 non-numeric or non-sequential bus subscripts. If Verilog mode
11627 mis-guessed, you'll have to declare them yourself.
11629 An example (see `verilog-auto-inst' for what else is going on here):
11631 module ExampWire (o,i);
11635 InstModule instName
11639 Typing \\[verilog-auto] will make this into:
11641 module ExampWire (o,i);
11645 // Beginning of automatic wires
11646 wire [31:0] ov; // From inst of inst.v
11647 // End of automatics
11648 InstModule instName
11657 ;; Point must be at insertion point.
11658 (let* ((indent-pt (current-indentation))
11659 (modi (verilog-modi-current))
11660 (moddecls (verilog-modi-get-decls modi))
11661 (modsubdecls (verilog-modi-get-sub-decls modi))
11662 (sig-list (verilog-signals-combine-bus
11663 (verilog-signals-not-in
11664 (append (verilog-subdecls-get-outputs modsubdecls)
11665 (verilog-subdecls-get-inouts modsubdecls))
11666 (verilog-decls-get-signals moddecls)))))
11668 (verilog-forward-or-insert-line)
11669 (verilog-insert-indent "// Beginning of automatic wires (for undeclared instantiated-module outputs)\n")
11670 (verilog-insert-definition modi sig-list "wire" indent-pt nil)
11671 (verilog-insert-indent "// End of automatics\n")
11672 ;; We used to optionally call verilog-pretty-declarations and
11673 ;; verilog-pretty-expr here, but it's too slow on huge modules,
11674 ;; plus makes everyone's module change. Finally those call
11675 ;; syntax-ppss which is broken when change hooks are disabled.
11678 (defun verilog-auto-output ()
11679 "Expand AUTOOUTPUT statements, as part of \\[verilog-auto].
11680 Make output statements for any output signal from an /*AUTOINST*/ that
11681 isn't an input to another AUTOINST. This is useful for modules which
11682 only instantiate other modules.
11685 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
11687 If placed inside the parenthesis of a module declaration, it creates
11688 Verilog 2001 style, else uses Verilog 1995 style.
11690 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
11691 instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
11693 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
11695 Signals matching `verilog-auto-output-ignore-regexp' are not included.
11697 An example (see `verilog-auto-inst' for what else is going on here):
11699 module ExampOutput (ov,i);
11702 InstModule instName
11706 Typing \\[verilog-auto] will make this into:
11708 module ExampOutput (ov,i);
11711 // Beginning of automatic outputs (from unused autoinst outputs)
11712 output [31:0] ov; // From inst of inst.v
11713 // End of automatics
11714 InstModule instName
11722 You may also provide an optional regular expression, in which case only
11723 signals matching the regular expression will be included. For example the
11724 same expansion will result from only extracting outputs starting with ov:
11726 /*AUTOOUTPUT(\"^ov\")*/"
11728 ;; Point must be at insertion point.
11729 (let* ((indent-pt (current-indentation))
11730 (params (verilog-read-auto-params 0 1))
11731 (regexp (nth 0 params))
11732 (v2k (verilog-in-paren-quick))
11733 (modi (verilog-modi-current))
11734 (moddecls (verilog-modi-get-decls modi))
11735 (modsubdecls (verilog-modi-get-sub-decls modi))
11736 (sig-list (verilog-signals-not-in
11737 (verilog-subdecls-get-outputs modsubdecls)
11738 (append (verilog-decls-get-outputs moddecls)
11739 (verilog-decls-get-inouts moddecls)
11740 (verilog-decls-get-inputs moddecls)
11741 (verilog-subdecls-get-inputs modsubdecls)
11742 (verilog-subdecls-get-inouts modsubdecls)))))
11744 (setq sig-list (verilog-signals-matching-regexp
11746 (setq sig-list (verilog-signals-not-matching-regexp
11747 sig-list verilog-auto-output-ignore-regexp))
11748 (verilog-forward-or-insert-line)
11749 (when v2k (verilog-repair-open-comma))
11751 (verilog-insert-indent "// Beginning of automatic outputs (from unused autoinst outputs)\n")
11752 (verilog-insert-definition modi sig-list "output" indent-pt v2k)
11753 (verilog-insert-indent "// End of automatics\n"))
11754 (when v2k (verilog-repair-close-comma)))))
11756 (defun verilog-auto-output-every ()
11757 "Expand AUTOOUTPUTEVERY statements, as part of \\[verilog-auto].
11758 Make output statements for any signals that aren't primary inputs or
11759 outputs already. This makes every signal in the design an output. This is
11760 useful to get Synopsys to preserve every signal in the design, since it
11761 won't optimize away the outputs.
11765 module ExampOutputEvery (o,i,tempa,tempb);
11768 /*AUTOOUTPUTEVERY*/
11770 wire tempb = tempa;
11774 Typing \\[verilog-auto] will make this into:
11776 module ExampOutputEvery (o,i,tempa,tempb);
11779 /*AUTOOUTPUTEVERY*/
11780 // Beginning of automatic outputs (every signal)
11783 // End of automatics
11785 wire tempb = tempa;
11789 ;;Point must be at insertion point
11790 (let* ((indent-pt (current-indentation))
11791 (v2k (verilog-in-paren-quick))
11792 (modi (verilog-modi-current))
11793 (moddecls (verilog-modi-get-decls modi))
11794 (sig-list (verilog-signals-combine-bus
11795 (verilog-signals-not-in
11796 (verilog-decls-get-signals moddecls)
11797 (verilog-decls-get-ports moddecls)))))
11798 (verilog-forward-or-insert-line)
11799 (when v2k (verilog-repair-open-comma))
11801 (verilog-insert-indent "// Beginning of automatic outputs (every signal)\n")
11802 (verilog-insert-definition modi sig-list "output" indent-pt v2k)
11803 (verilog-insert-indent "// End of automatics\n"))
11804 (when v2k (verilog-repair-close-comma)))))
11806 (defun verilog-auto-input ()
11807 "Expand AUTOINPUT statements, as part of \\[verilog-auto].
11808 Make input statements for any input signal into an /*AUTOINST*/ that
11809 isn't declared elsewhere inside the module. This is useful for modules which
11810 only instantiate other modules.
11813 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
11815 If placed inside the parenthesis of a module declaration, it creates
11816 Verilog 2001 style, else uses Verilog 1995 style.
11818 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
11819 instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
11821 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
11823 Signals matching `verilog-auto-input-ignore-regexp' are not included.
11825 An example (see `verilog-auto-inst' for what else is going on here):
11827 module ExampInput (ov,i);
11830 InstModule instName
11834 Typing \\[verilog-auto] will make this into:
11836 module ExampInput (ov,i);
11839 // Beginning of automatic inputs (from unused autoinst inputs)
11840 input i; // From inst of inst.v
11841 // End of automatics
11842 InstModule instName
11850 You may also provide an optional regular expression, in which case only
11851 signals matching the regular expression will be included. For example the
11852 same expansion will result from only extracting inputs starting with i:
11854 /*AUTOINPUT(\"^i\")*/"
11856 (let* ((indent-pt (current-indentation))
11857 (params (verilog-read-auto-params 0 1))
11858 (regexp (nth 0 params))
11859 (v2k (verilog-in-paren-quick))
11860 (modi (verilog-modi-current))
11861 (moddecls (verilog-modi-get-decls modi))
11862 (modsubdecls (verilog-modi-get-sub-decls modi))
11863 (sig-list (verilog-signals-not-in
11864 (verilog-subdecls-get-inputs modsubdecls)
11865 (append (verilog-decls-get-inputs moddecls)
11866 (verilog-decls-get-inouts moddecls)
11867 (verilog-decls-get-outputs moddecls)
11868 (verilog-decls-get-vars moddecls)
11869 (verilog-decls-get-consts moddecls)
11870 (verilog-decls-get-gparams moddecls)
11871 (verilog-subdecls-get-interfaced modsubdecls)
11872 (verilog-subdecls-get-outputs modsubdecls)
11873 (verilog-subdecls-get-inouts modsubdecls)))))
11875 (setq sig-list (verilog-signals-matching-regexp
11877 (setq sig-list (verilog-signals-not-matching-regexp
11878 sig-list verilog-auto-input-ignore-regexp))
11879 (verilog-forward-or-insert-line)
11880 (when v2k (verilog-repair-open-comma))
11882 (verilog-insert-indent "// Beginning of automatic inputs (from unused autoinst inputs)\n")
11883 (verilog-insert-definition modi sig-list "input" indent-pt v2k)
11884 (verilog-insert-indent "// End of automatics\n"))
11885 (when v2k (verilog-repair-close-comma)))))
11887 (defun verilog-auto-inout ()
11888 "Expand AUTOINOUT statements, as part of \\[verilog-auto].
11889 Make inout statements for any inout signal in an /*AUTOINST*/ that
11890 isn't declared elsewhere inside the module.
11893 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
11895 If placed inside the parenthesis of a module declaration, it creates
11896 Verilog 2001 style, else uses Verilog 1995 style.
11898 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
11899 instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
11901 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
11903 Signals matching `verilog-auto-inout-ignore-regexp' are not included.
11905 An example (see `verilog-auto-inst' for what else is going on here):
11907 module ExampInout (ov,i);
11910 InstModule instName
11914 Typing \\[verilog-auto] will make this into:
11916 module ExampInout (ov,i);
11919 // Beginning of automatic inouts (from unused autoinst inouts)
11920 inout [31:0] ov; // From inst of inst.v
11921 // End of automatics
11922 InstModule instName
11930 You may also provide an optional regular expression, in which case only
11931 signals matching the regular expression will be included. For example the
11932 same expansion will result from only extracting inouts starting with i:
11934 /*AUTOINOUT(\"^i\")*/"
11936 ;; Point must be at insertion point.
11937 (let* ((indent-pt (current-indentation))
11938 (params (verilog-read-auto-params 0 1))
11939 (regexp (nth 0 params))
11940 (v2k (verilog-in-paren-quick))
11941 (modi (verilog-modi-current))
11942 (moddecls (verilog-modi-get-decls modi))
11943 (modsubdecls (verilog-modi-get-sub-decls modi))
11944 (sig-list (verilog-signals-not-in
11945 (verilog-subdecls-get-inouts modsubdecls)
11946 (append (verilog-decls-get-outputs moddecls)
11947 (verilog-decls-get-inouts moddecls)
11948 (verilog-decls-get-inputs moddecls)
11949 (verilog-subdecls-get-inputs modsubdecls)
11950 (verilog-subdecls-get-outputs modsubdecls)))))
11952 (setq sig-list (verilog-signals-matching-regexp
11954 (setq sig-list (verilog-signals-not-matching-regexp
11955 sig-list verilog-auto-inout-ignore-regexp))
11956 (verilog-forward-or-insert-line)
11957 (when v2k (verilog-repair-open-comma))
11959 (verilog-insert-indent "// Beginning of automatic inouts (from unused autoinst inouts)\n")
11960 (verilog-insert-definition modi sig-list "inout" indent-pt v2k)
11961 (verilog-insert-indent "// End of automatics\n"))
11962 (when v2k (verilog-repair-close-comma)))))
11964 (defun verilog-auto-inout-module (&optional complement all-in)
11965 "Expand AUTOINOUTMODULE statements, as part of \\[verilog-auto].
11966 Take input/output/inout statements from the specified module and insert
11967 into the current module. This is useful for making null templates and
11968 shell modules which need to have identical I/O with another module.
11969 Any I/O which are already defined in this module will not be redefined.
11970 For the complement of this function, see `verilog-auto-inout-comp',
11971 and to make monitors with all inputs, see `verilog-auto-inout-in'.
11974 If placed inside the parenthesis of a module declaration, it creates
11975 Verilog 2001 style, else uses Verilog 1995 style.
11977 Concatenation and outputting partial buses is not supported.
11979 Module names must be resolvable to filenames. See `verilog-auto-inst'.
11981 Signals are not inserted in the same order as in the original module,
11982 though they will appear to be in the same order to an AUTOINST
11983 instantiating either module.
11985 Signals declared as \"output reg\" or \"output wire\" etc will
11986 lose the wire/reg declaration so that shell modules may
11987 generate those outputs differently. However, \"output logic\"
11992 module ExampShell (/*AUTOARG*/);
11993 /*AUTOINOUTMODULE(\"ExampMain\")*/
11996 module ExampMain (i,o,io);
12002 Typing \\[verilog-auto] will make this into:
12004 module ExampShell (/*AUTOARG*/i,o,io);
12005 /*AUTOINOUTMODULE(\"ExampMain\")*/
12006 // Beginning of automatic in/out/inouts (from specific module)
12010 // End of automatics
12013 You may also provide an optional regular expression, in which case only
12014 signals matching the regular expression will be included. For example the
12015 same expansion will result from only extracting signals starting with i:
12017 /*AUTOINOUTMODULE(\"ExampMain\",\"^i\")*/
12019 You may also provide an optional second regular expression, in
12020 which case only signals which have that pin direction and data
12021 type will be included. This matches against everything before
12022 the signal name in the declaration, for example against
12023 \"input\" (single bit), \"output logic\" (direction and type) or
12024 \"output [1:0]\" (direction and implicit type). You also
12025 probably want to skip spaces in your regexp.
12027 For example, the below will result in matching the output \"o\"
12028 against the previous example's module:
12030 /*AUTOINOUTMODULE(\"ExampMain\",\"\",\"^output.*\")*/"
12032 (let* ((params (verilog-read-auto-params 1 3))
12033 (submod (nth 0 params))
12034 (regexp (nth 1 params))
12035 (direction-re (nth 2 params))
12037 ;; Lookup position, etc of co-module
12038 ;; Note this may raise an error
12039 (when (setq submodi (verilog-modi-lookup submod t))
12040 (let* ((indent-pt (current-indentation))
12041 (v2k (verilog-in-paren-quick))
12042 (modi (verilog-modi-current))
12043 (moddecls (verilog-modi-get-decls modi))
12044 (submoddecls (verilog-modi-get-decls submodi))
12045 (sig-list-i (verilog-signals-not-in
12048 (verilog-decls-get-inputs submoddecls)
12049 (verilog-decls-get-inouts submoddecls)
12050 (verilog-decls-get-outputs submoddecls)))
12052 (verilog-decls-get-outputs submoddecls))
12053 (t (verilog-decls-get-inputs submoddecls)))
12054 (append (verilog-decls-get-inputs moddecls))))
12055 (sig-list-o (verilog-signals-not-in
12058 (verilog-decls-get-inputs submoddecls))
12059 (t (verilog-decls-get-outputs submoddecls)))
12060 (append (verilog-decls-get-outputs moddecls))))
12061 (sig-list-io (verilog-signals-not-in
12063 (t (verilog-decls-get-inouts submoddecls)))
12064 (append (verilog-decls-get-inouts moddecls))))
12065 (sig-list-if (verilog-signals-not-in
12066 (verilog-decls-get-interfaces submoddecls)
12067 (append (verilog-decls-get-interfaces moddecls)))))
12069 (setq sig-list-i (verilog-signals-edit-wire-reg
12070 (verilog-signals-matching-dir-re
12071 (verilog-signals-matching-regexp sig-list-i regexp)
12072 "input" direction-re))
12073 sig-list-o (verilog-signals-edit-wire-reg
12074 (verilog-signals-matching-dir-re
12075 (verilog-signals-matching-regexp sig-list-o regexp)
12076 "output" direction-re))
12077 sig-list-io (verilog-signals-edit-wire-reg
12078 (verilog-signals-matching-dir-re
12079 (verilog-signals-matching-regexp sig-list-io regexp)
12080 "inout" direction-re))
12081 sig-list-if (verilog-signals-matching-dir-re
12082 (verilog-signals-matching-regexp sig-list-if regexp)
12083 "interface" direction-re))
12084 (when v2k (verilog-repair-open-comma))
12085 (when (or sig-list-i sig-list-o sig-list-io sig-list-if)
12086 (verilog-insert-indent "// Beginning of automatic in/out/inouts (from specific module)\n")
12087 ;; Don't sort them so an upper AUTOINST will match the main module
12088 (verilog-insert-definition modi sig-list-o "output" indent-pt v2k t)
12089 (verilog-insert-definition modi sig-list-io "inout" indent-pt v2k t)
12090 (verilog-insert-definition modi sig-list-i "input" indent-pt v2k t)
12091 (verilog-insert-definition modi sig-list-if "interface" indent-pt v2k t)
12092 (verilog-insert-indent "// End of automatics\n"))
12093 (when v2k (verilog-repair-close-comma)))))))
12095 (defun verilog-auto-inout-comp ()
12096 "Expand AUTOINOUTCOMP statements, as part of \\[verilog-auto].
12097 Take input/output/inout statements from the specified module and
12098 insert the inverse into the current module (inputs become outputs
12099 and vice-versa.) This is useful for making test and stimulus
12100 modules which need to have complementing I/O with another module.
12101 Any I/O which are already defined in this module will not be
12102 redefined. For the complement of this function, see
12103 `verilog-auto-inout-module'.
12106 If placed inside the parenthesis of a module declaration, it creates
12107 Verilog 2001 style, else uses Verilog 1995 style.
12109 Concatenation and outputting partial buses is not supported.
12111 Module names must be resolvable to filenames. See `verilog-auto-inst'.
12113 Signals are not inserted in the same order as in the original module,
12114 though they will appear to be in the same order to an AUTOINST
12115 instantiating either module.
12119 module ExampShell (/*AUTOARG*/);
12120 /*AUTOINOUTCOMP(\"ExampMain\")*/
12123 module ExampMain (i,o,io);
12129 Typing \\[verilog-auto] will make this into:
12131 module ExampShell (/*AUTOARG*/i,o,io);
12132 /*AUTOINOUTCOMP(\"ExampMain\")*/
12133 // Beginning of automatic in/out/inouts (from specific module)
12137 // End of automatics
12140 You may also provide an optional regular expression, in which case only
12141 signals matching the regular expression will be included. For example the
12142 same expansion will result from only extracting signals starting with i:
12144 /*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/"
12145 (verilog-auto-inout-module t nil))
12147 (defun verilog-auto-inout-in ()
12148 "Expand AUTOINOUTIN statements, as part of \\[verilog-auto].
12149 Take input/output/inout statements from the specified module and
12150 insert them as all inputs into the current module. This is
12151 useful for making monitor modules which need to see all signals
12152 as inputs based on another module. Any I/O which are already
12153 defined in this module will not be redefined. See also
12154 `verilog-auto-inout-module'.
12157 If placed inside the parenthesis of a module declaration, it creates
12158 Verilog 2001 style, else uses Verilog 1995 style.
12160 Concatenation and outputting partial buses is not supported.
12162 Module names must be resolvable to filenames. See `verilog-auto-inst'.
12164 Signals are not inserted in the same order as in the original module,
12165 though they will appear to be in the same order to an AUTOINST
12166 instantiating either module.
12170 module ExampShell (/*AUTOARG*/);
12171 /*AUTOINOUTIN(\"ExampMain\")*/
12174 module ExampMain (i,o,io);
12180 Typing \\[verilog-auto] will make this into:
12182 module ExampShell (/*AUTOARG*/i,o,io);
12183 /*AUTOINOUTIN(\"ExampMain\")*/
12184 // Beginning of automatic in/out/inouts (from specific module)
12188 // End of automatics
12191 You may also provide an optional regular expression, in which case only
12192 signals matching the regular expression will be included. For example the
12193 same expansion will result from only extracting signals starting with i:
12195 /*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/"
12196 (verilog-auto-inout-module nil t))
12198 (defun verilog-auto-inout-param ()
12199 "Expand AUTOINOUTPARAM statements, as part of \\[verilog-auto].
12200 Take input/output/inout statements from the specified module and insert
12201 into the current module. This is useful for making null templates and
12202 shell modules which need to have identical I/O with another module.
12203 Any I/O which are already defined in this module will not be redefined.
12204 For the complement of this function, see `verilog-auto-inout-comp',
12205 and to make monitors with all inputs, see `verilog-auto-inout-in'.
12208 If placed inside the parenthesis of a module declaration, it creates
12209 Verilog 2001 style, else uses Verilog 1995 style.
12211 Module names must be resolvable to filenames. See `verilog-auto-inst'.
12213 Parameters are inserted in the same order as in the original module.
12215 Parameters do not have values, which is SystemVerilog 2009 syntax.
12219 module ExampShell ();
12220 /*AUTOINOUTPARAM(\"ExampMain\")*/
12223 module ExampMain ();
12224 parameter PARAM = 22;
12227 Typing \\[verilog-auto] will make this into:
12229 module ExampShell (/*AUTOARG*/i,o,io);
12230 /*AUTOINOUTPARAM(\"ExampMain\")*/
12231 // Beginning of automatic parameters (from specific module)
12233 // End of automatics
12236 You may also provide an optional regular expression, in which case only
12237 parameters matching the regular expression will be included. For example the
12238 same expansion will result from only extracting parameters starting with i:
12240 /*AUTOINOUTPARAM(\"ExampMain\",\"^i\")*/"
12242 (let* ((params (verilog-read-auto-params 1 2))
12243 (submod (nth 0 params))
12244 (regexp (nth 1 params))
12246 ;; Lookup position, etc of co-module
12247 ;; Note this may raise an error
12248 (when (setq submodi (verilog-modi-lookup submod t))
12249 (let* ((indent-pt (current-indentation))
12250 (v2k (verilog-in-paren-quick))
12251 (modi (verilog-modi-current))
12252 (moddecls (verilog-modi-get-decls modi))
12253 (submoddecls (verilog-modi-get-decls submodi))
12254 (sig-list-p (verilog-signals-not-in
12255 (verilog-decls-get-gparams submoddecls)
12256 (append (verilog-decls-get-gparams moddecls)))))
12258 (setq sig-list-p (verilog-signals-matching-regexp sig-list-p regexp))
12259 (when v2k (verilog-repair-open-comma))
12261 (verilog-insert-indent "// Beginning of automatic parameters (from specific module)\n")
12262 ;; Don't sort them so an upper AUTOINST will match the main module
12263 (verilog-insert-definition modi sig-list-p "parameter" indent-pt v2k t)
12264 (verilog-insert-indent "// End of automatics\n"))
12265 (when v2k (verilog-repair-close-comma)))))))
12267 (defun verilog-auto-inout-modport ()
12268 "Expand AUTOINOUTMODPORT statements, as part of \\[verilog-auto].
12269 Take input/output/inout statements from the specified interface
12270 and modport and insert into the current module. This is useful
12271 for making verification modules that connect to UVM interfaces.
12273 The first parameter is the name of an interface.
12275 The second parameter is a regexp of modports to read from in
12278 The optional third parameter is a regular expression, and only
12279 signals matching the regular expression will be included.
12282 If placed inside the parenthesis of a module declaration, it creates
12283 Verilog 2001 style, else uses Verilog 1995 style.
12285 Interface names must be resolvable to filenames. See `verilog-auto-inst'.
12287 As with other autos, any inputs/outputs declared in the module
12288 will suppress the AUTO from redeclaring an inputs/outputs by
12294 ( input logic clk );
12296 logic [7:0] req_dat;
12297 clocking mon_clkblk @(posedge clk);
12301 modport mp(clocking mon_clkblk);
12306 /*AUTOINOUTMODPORT(\"ExampIf\" \"mp\")*/
12307 // Beginning of automatic in/out/inouts (from modport)
12308 input [7:0] req_dat,
12310 // End of automatics
12312 /*AUTOASSIGNMODPORT(\"ExampIf\" \"mp\")*/
12315 Typing \\[verilog-auto] will make this into:
12320 /*AUTOINOUTMODPORT(\"ExampIf\" \"mp\")*/
12321 // Beginning of automatic in/out/inouts (from modport)
12324 // End of automatics
12327 If the modport is part of a UVM monitor/driver class, this
12328 creates a wrapper module that may be used to instantiate the
12329 driver/monitor using AUTOINST in the testbench."
12331 (let* ((params (verilog-read-auto-params 2 3))
12332 (submod (nth 0 params))
12333 (modport-re (nth 1 params))
12334 (regexp (nth 2 params))
12335 direction-re submodi) ;; direction argument not supported until requested
12336 ;; Lookup position, etc of co-module
12337 ;; Note this may raise an error
12338 (when (setq submodi (verilog-modi-lookup submod t))
12339 (let* ((indent-pt (current-indentation))
12340 (v2k (verilog-in-paren-quick))
12341 (modi (verilog-modi-current))
12342 (moddecls (verilog-modi-get-decls modi))
12343 (submoddecls (verilog-modi-get-decls submodi))
12344 (submodportdecls (verilog-modi-modport-lookup submodi modport-re))
12345 (sig-list-i (verilog-signals-in ;; Decls doesn't have data types, must resolve
12346 (verilog-decls-get-vars submoddecls)
12347 (verilog-signals-not-in
12348 (verilog-decls-get-inputs submodportdecls)
12349 (append (verilog-decls-get-ports submoddecls)
12350 (verilog-decls-get-ports moddecls)))))
12351 (sig-list-o (verilog-signals-in ;; Decls doesn't have data types, must resolve
12352 (verilog-decls-get-vars submoddecls)
12353 (verilog-signals-not-in
12354 (verilog-decls-get-outputs submodportdecls)
12355 (append (verilog-decls-get-ports submoddecls)
12356 (verilog-decls-get-ports moddecls)))))
12357 (sig-list-io (verilog-signals-in ;; Decls doesn't have data types, must resolve
12358 (verilog-decls-get-vars submoddecls)
12359 (verilog-signals-not-in
12360 (verilog-decls-get-inouts submodportdecls)
12361 (append (verilog-decls-get-ports submoddecls)
12362 (verilog-decls-get-ports moddecls))))))
12364 (setq sig-list-i (verilog-signals-edit-wire-reg
12365 (verilog-signals-matching-dir-re
12366 (verilog-signals-matching-regexp sig-list-i regexp)
12367 "input" direction-re))
12368 sig-list-o (verilog-signals-edit-wire-reg
12369 (verilog-signals-matching-dir-re
12370 (verilog-signals-matching-regexp sig-list-o regexp)
12371 "output" direction-re))
12372 sig-list-io (verilog-signals-edit-wire-reg
12373 (verilog-signals-matching-dir-re
12374 (verilog-signals-matching-regexp sig-list-io regexp)
12375 "inout" direction-re)))
12376 (when v2k (verilog-repair-open-comma))
12377 (when (or sig-list-i sig-list-o sig-list-io)
12378 (verilog-insert-indent "// Beginning of automatic in/out/inouts (from modport)\n")
12379 ;; Don't sort them so an upper AUTOINST will match the main module
12380 (verilog-insert-definition modi sig-list-o "output" indent-pt v2k t)
12381 (verilog-insert-definition modi sig-list-io "inout" indent-pt v2k t)
12382 (verilog-insert-definition modi sig-list-i "input" indent-pt v2k t)
12383 (verilog-insert-indent "// End of automatics\n"))
12384 (when v2k (verilog-repair-close-comma)))))))
12386 (defun verilog-auto-insert-lisp ()
12387 "Expand AUTOINSERTLISP statements, as part of \\[verilog-auto].
12388 The Lisp code provided is called, and the Lisp code calls
12389 `insert` to insert text into the current file beginning on the
12390 line after the AUTOINSERTLISP.
12392 See also AUTO_LISP, which takes a Lisp expression and evaluates
12393 it during `verilog-auto-inst' but does not insert any text.
12397 module ExampInsertLisp;
12398 /*AUTOINSERTLISP(my-verilog-insert-hello \"world\")*/
12401 // For this example we declare the function in the
12402 // module's file itself. Often you'd define it instead
12403 // in a site-start.el or init file.
12407 (defun my-verilog-insert-hello (who)
12408 (insert (concat \"initial $write(\\\"hello \" who \"\\\");\\n\")))
12412 Typing \\[verilog-auto] will call my-verilog-insert-hello and
12413 expand the above into:
12415 // Beginning of automatic insert lisp
12416 initial $write(\"hello world\");
12417 // End of automatics
12419 You can also call an external program and insert the returned
12422 /*AUTOINSERTLISP(insert (shell-command-to-string \"echo //hello\"))*/
12423 // Beginning of automatic insert lisp
12425 // End of automatics"
12427 ;; Point is at end of /*AUTO...*/
12428 (let* ((indent-pt (current-indentation))
12429 (cmd-end-pt (save-excursion (search-backward ")")
12431 (point))) ;; Closing paren
12432 (cmd-beg-pt (save-excursion (goto-char cmd-end-pt)
12433 (backward-sexp 1) ;; Inside comment
12434 (point))) ;; Beginning paren
12435 (cmd (buffer-substring-no-properties cmd-beg-pt cmd-end-pt)))
12436 (verilog-forward-or-insert-line)
12437 ;; Some commands don't move point (like insert-file) so we always
12438 ;; add the begin/end comments, then delete it if not needed
12439 (verilog-insert-indent "// Beginning of automatic insert lisp\n")
12440 (verilog-insert-indent "// End of automatics\n")
12444 (setq verilog-scan-cache-tick nil) ;; Clear cache; inserted unknown text
12445 (verilog-delete-empty-auto-pair))))
12447 (defun verilog-auto-sense-sigs (moddecls presense-sigs)
12448 "Return list of signals for current AUTOSENSE block."
12449 (let* ((sigss (verilog-read-always-signals))
12450 (sig-list (verilog-signals-not-params
12451 (verilog-signals-not-in (verilog-alw-get-inputs sigss)
12452 (append (and (not verilog-auto-sense-include-inputs)
12453 (verilog-alw-get-outputs-delayed sigss))
12454 (and (not verilog-auto-sense-include-inputs)
12455 (verilog-alw-get-outputs-immediate sigss))
12456 (verilog-alw-get-temps sigss)
12457 (verilog-decls-get-consts moddecls)
12458 (verilog-decls-get-gparams moddecls)
12462 (defun verilog-auto-sense ()
12463 "Expand AUTOSENSE statements, as part of \\[verilog-auto].
12464 Replace the always (/*AUTOSENSE*/) sensitivity list (/*AS*/ for short)
12465 with one automatically derived from all inputs declared in the always
12466 statement. Signals that are generated within the same always block are NOT
12467 placed into the sensitivity list (see `verilog-auto-sense-include-inputs').
12468 Long lines are split based on the `fill-column', see \\[set-fill-column].
12471 Verilog does not allow memories (multidimensional arrays) in sensitivity
12472 lists. AUTOSENSE will thus exclude them, and add a /*memory or*/ comment.
12475 AUTOSENSE cannot always determine if a `define is a constant or a signal
12476 (it could be in an include file for example). If a `define or other signal
12477 is put into the AUTOSENSE list and is not desired, use the AUTO_CONSTANT
12478 declaration anywhere in the module (parenthesis are required):
12480 /* AUTO_CONSTANT ( `this_is_really_constant_dont_autosense_it ) */
12482 Better yet, use a parameter, which will be understood to be constant
12486 If AUTOSENSE makes a mistake, please report it. (First try putting
12487 a begin/end after your always!) As a workaround, if a signal that
12488 shouldn't be in the sensitivity list was, use the AUTO_CONSTANT above.
12489 If a signal should be in the sensitivity list wasn't, placing it before
12490 the /*AUTOSENSE*/ comment will prevent it from being deleted when the
12491 autos are updated (or added if it occurs there already).
12495 always @ (/*AS*/) begin
12496 /* AUTO_CONSTANT (`constant) */
12497 outin = ina | inb | `constant;
12501 Typing \\[verilog-auto] will make this into:
12503 always @ (/*AS*/ina or inb) begin
12504 /* AUTO_CONSTANT (`constant) */
12505 outin = ina | inb | `constant;
12509 Note in Verilog 2001, you can often get the same result from the new @*
12510 operator. (This was added to the language in part due to AUTOSENSE!)
12513 outin = ina | inb | `constant;
12518 (let* ((start-pt (save-excursion
12519 (verilog-re-search-backward-quick "(" nil t)
12521 (indent-pt (save-excursion
12522 (or (and (goto-char start-pt) (1+ (current-column)))
12523 (current-indentation))))
12524 (modi (verilog-modi-current))
12525 (moddecls (verilog-modi-get-decls modi))
12526 (sig-memories (verilog-signals-memory
12527 (verilog-decls-get-vars moddecls)))
12528 sig-list not-first presense-sigs)
12529 ;; Read signals in always, eliminate outputs from sense list
12530 (setq presense-sigs (verilog-signals-from-signame
12532 (verilog-read-signals start-pt (point)))))
12533 (setq sig-list (verilog-auto-sense-sigs moddecls presense-sigs))
12535 (let ((tlen (length sig-list)))
12536 (setq sig-list (verilog-signals-not-in sig-list sig-memories))
12537 (if (not (eq tlen (length sig-list))) (verilog-insert " /*memory or*/ "))))
12538 (if (and presense-sigs ;; Add a "or" if not "(.... or /*AUTOSENSE*/"
12539 (save-excursion (goto-char (point))
12540 (verilog-re-search-backward-quick "[a-zA-Z0-9$_.%`]+" start-pt t)
12541 (verilog-re-search-backward-quick "\\s-" start-pt t)
12542 (while (looking-at "\\s-`endif")
12543 (verilog-re-search-backward-quick "[a-zA-Z0-9$_.%`]+" start-pt t)
12544 (verilog-re-search-backward-quick "\\s-" start-pt t))
12545 (not (looking-at "\\s-or\\b"))))
12546 (setq not-first t))
12547 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
12549 (cond ((> (+ 4 (current-column) (length (verilog-sig-name (car sig-list)))) fill-column) ;+4 for width of or
12551 (indent-to indent-pt)
12552 (if not-first (insert "or ")))
12553 (not-first (insert " or ")))
12554 (insert (verilog-sig-name (car sig-list)))
12555 (setq sig-list (cdr sig-list)
12558 (defun verilog-auto-reset ()
12559 "Expand AUTORESET statements, as part of \\[verilog-auto].
12560 Replace the /*AUTORESET*/ comment with code to initialize all
12561 registers set elsewhere in the always block.
12564 AUTORESET will not clear memories.
12566 AUTORESET uses <= if the signal has a <= assignment in the block,
12569 If <= is used, all = assigned variables are ignored if
12570 `verilog-auto-reset-blocking-in-non' is nil; they are presumed
12573 /*AUTORESET*/ presumes that any signals mentioned between the previous
12574 begin/case/if statement and the AUTORESET comment are being reset manually
12575 and should not be automatically reset. This includes omitting any signals
12576 used on the right hand side of assignments.
12578 By default, AUTORESET will include the width of the signal in the
12579 autos, SystemVerilog designs may want to change this. To control
12580 this behavior, see `verilog-auto-reset-widths'. In some cases
12581 AUTORESET must use a '0 assignment and it will print NOWIDTH; use
12582 `verilog-auto-reset-widths' unbased to prevent this.
12584 AUTORESET ties signals to deasserted, which is presumed to be zero.
12585 Signals that match `verilog-active-low-regexp' will be deasserted by tying
12588 AUTORESET may try to reset arrays or structures that cannot be
12589 reset by a simple assignment, resulting in compile errors. This
12590 is a feature to be taken as a hint that you need to reset these
12591 signals manually (or put them into a \"`ifdef NEVER signal<=`0;
12592 `endif\" so Verilog-Mode ignores them.)
12596 always @(posedge clk or negedge reset_l) begin
12597 if (!reset_l) begin
12608 Typing \\[verilog-auto] will make this into:
12610 always @(posedge core_clk or negedge reset_l) begin
12611 if (!reset_l) begin
12614 // Beginning of autoreset for uninitialized flops
12616 b = 0; // if `verilog-auto-reset-blocking-in-non' true
12617 // End of automatics
12629 (let* ((indent-pt (current-indentation))
12630 (modi (verilog-modi-current))
12631 (moddecls (verilog-modi-get-decls modi))
12632 (all-list (verilog-decls-get-signals moddecls))
12633 sigss sig-list dly-list prereset-sigs)
12634 ;; Read signals in always, eliminate outputs from reset list
12635 (setq prereset-sigs (verilog-signals-from-signame
12637 (verilog-read-signals
12639 (verilog-re-search-backward-quick "\\(@\\|\\<begin\\>\\|\\<if\\>\\|\\<case\\>\\)" nil t)
12643 (verilog-re-search-backward-quick "@" nil t)
12644 (setq sigss (verilog-read-always-signals)))
12645 (setq dly-list (verilog-alw-get-outputs-delayed sigss))
12646 (setq sig-list (verilog-signals-not-in (append
12647 (verilog-alw-get-outputs-delayed sigss)
12648 (when (or (not (verilog-alw-get-uses-delayed sigss))
12649 verilog-auto-reset-blocking-in-non)
12650 (verilog-alw-get-outputs-immediate sigss)))
12652 (verilog-alw-get-temps sigss)
12654 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
12657 (verilog-insert-indent "// Beginning of autoreset for uninitialized flops\n");
12659 (let ((sig (or (assoc (verilog-sig-name (car sig-list)) all-list) ;; As sig-list has no widths
12661 (indent-to indent-pt)
12662 (insert (verilog-sig-name sig)
12663 (if (assoc (verilog-sig-name sig) dly-list)
12664 (concat " <= " verilog-assignment-delay)
12666 (verilog-sig-tieoff sig)
12668 (setq sig-list (cdr sig-list))))
12669 (verilog-insert-indent "// End of automatics")))))
12671 (defun verilog-auto-tieoff ()
12672 "Expand AUTOTIEOFF statements, as part of \\[verilog-auto].
12673 Replace the /*AUTOTIEOFF*/ comment with code to wire-tie all unused output
12674 signals to deasserted.
12676 /*AUTOTIEOFF*/ is used to make stub modules; modules that have the same
12677 input/output list as another module, but no internals. Specifically, it
12678 finds all outputs in the module, and if that input is not otherwise declared
12679 as a register or wire, creates a tieoff.
12681 AUTORESET ties signals to deasserted, which is presumed to be zero.
12682 Signals that match `verilog-active-low-regexp' will be deasserted by tying
12685 You can add signals you do not want included in AUTOTIEOFF with
12686 `verilog-auto-tieoff-ignore-regexp'.
12688 `verilog-auto-wire-type' may be used to change the datatype of
12691 `verilog-auto-reset-widths' may be used to change how the tieoff
12692 value's width is generated.
12694 An example of making a stub for another module:
12696 module ExampStub (/*AUTOINST*/);
12697 /*AUTOINOUTPARAM(\"Foo\")*/
12698 /*AUTOINOUTMODULE(\"Foo\")*/
12700 // verilator lint_off UNUSED
12701 wire _unused_ok = &{1'b0,
12704 // verilator lint_on UNUSED
12707 Typing \\[verilog-auto] will make this into:
12709 module ExampStub (/*AUTOINST*/...);
12710 /*AUTOINOUTPARAM(\"Foo\")*/
12711 /*AUTOINOUTMODULE(\"Foo\")*/
12712 // Beginning of autotieoff
12714 // End of automatics
12717 // Beginning of autotieoff
12718 wire [2:0] foo = 3'b0;
12719 // End of automatics
12725 (let* ((indent-pt (current-indentation))
12726 (modi (verilog-modi-current))
12727 (moddecls (verilog-modi-get-decls modi))
12728 (modsubdecls (verilog-modi-get-sub-decls modi))
12729 (sig-list (verilog-signals-not-in
12730 (verilog-decls-get-outputs moddecls)
12731 (append (verilog-decls-get-vars moddecls)
12732 (verilog-decls-get-assigns moddecls)
12733 (verilog-decls-get-consts moddecls)
12734 (verilog-decls-get-gparams moddecls)
12735 (verilog-subdecls-get-interfaced modsubdecls)
12736 (verilog-subdecls-get-outputs modsubdecls)
12737 (verilog-subdecls-get-inouts modsubdecls)))))
12738 (setq sig-list (verilog-signals-not-matching-regexp
12739 sig-list verilog-auto-tieoff-ignore-regexp))
12741 (verilog-forward-or-insert-line)
12742 (verilog-insert-indent "// Beginning of automatic tieoffs (for this module's unterminated outputs)\n")
12743 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
12744 (verilog-modi-cache-add-vars modi sig-list) ; Before we trash list
12746 (let ((sig (car sig-list)))
12747 (cond ((equal verilog-auto-tieoff-declaration "assign")
12748 (indent-to indent-pt)
12749 (insert "assign " (verilog-sig-name sig)))
12751 (verilog-insert-one-definition sig verilog-auto-tieoff-declaration indent-pt)))
12752 (indent-to (max 48 (+ indent-pt 40)))
12753 (insert "= " (verilog-sig-tieoff sig)
12755 (setq sig-list (cdr sig-list))))
12756 (verilog-insert-indent "// End of automatics\n")))))
12758 (defun verilog-auto-undef ()
12759 "Expand AUTOUNDEF statements, as part of \\[verilog-auto].
12760 Take any `defines since the last AUTOUNDEF in the current file
12761 and create `undefs for them. This is used to insure that
12762 file-local defines do not pollute the global `define name space.
12765 AUTOUNDEF presumes any identifier following `define is the
12766 name of a define. Any `ifdefs are ignored.
12768 AUTOUNDEF suppresses creating an `undef for any define that was
12769 `undefed before the AUTOUNDEF. This may be used to work around
12770 the ignoring of `ifdefs as shown below.
12779 `undef M_BAZ // Emacs will see this and not `undef M_BAZ
12784 Typing \\[verilog-auto] will make this into:
12788 // Beginning of automatic undefs
12791 // End of automatics
12793 You may also provide an optional regular expression, in which case only
12794 defines the regular expression will be undefed."
12796 (let* ((params (verilog-read-auto-params 0 1))
12797 (regexp (nth 0 params))
12798 (indent-pt (current-indentation))
12802 ;; Scan from start of file, or last AUTOUNDEF
12803 (or (verilog-re-search-backward-quick "/\\*AUTOUNDEF\\>" end-pt t)
12804 (goto-char (point-min)))
12805 (while (verilog-re-search-forward-quick
12806 "`\\(define\\|undef\\)\\s-*\\([a-zA-Z_][a-zA-Z_0-9]*\\)" end-pt t)
12807 (cond ((equal (match-string-no-properties 1) "define")
12808 (setq def (match-string-no-properties 2))
12809 (when (and (or (not regexp)
12810 (string-match regexp def))
12811 (not (member def defs))) ;; delete-dups not in 21.1
12812 (setq defs (cons def defs))))
12814 (setq defs (delete (match-string-no-properties 2) defs))))))
12816 (setq defs (sort defs 'string<))
12818 (verilog-forward-or-insert-line)
12819 (verilog-insert-indent "// Beginning of automatic undefs\n")
12821 (verilog-insert-indent "`undef " (car defs) "\n")
12822 (setq defs (cdr defs)))
12823 (verilog-insert-indent "// End of automatics\n")))))
12825 (defun verilog-auto-unused ()
12826 "Expand AUTOUNUSED statements, as part of \\[verilog-auto].
12827 Replace the /*AUTOUNUSED*/ comment with a comma separated list of all unused
12828 input and inout signals.
12830 /*AUTOUNUSED*/ is used to make stub modules; modules that have the same
12831 input/output list as another module, but no internals. Specifically, it
12832 finds all inputs and inouts in the module, and if that input is not otherwise
12833 used, adds it to a comma separated list.
12835 The comma separated list is intended to be used to create a _unused_ok
12836 signal. Using the exact name \"_unused_ok\" for name of the temporary
12837 signal is recommended as it will insure maximum forward compatibility, it
12838 also makes lint warnings easy to understand; ignore any unused warnings
12839 with \"unused\" in the signal name.
12841 To reduce simulation time, the _unused_ok signal should be forced to a
12842 constant to prevent wiggling. The easiest thing to do is use a
12843 reduction-and with 1'b0 as shown.
12845 This way all unused signals are in one place, making it convenient to add
12846 your tool's specific pragmas around the assignment to disable any unused
12849 You can add signals you do not want included in AUTOUNUSED with
12850 `verilog-auto-unused-ignore-regexp'.
12852 An example of making a stub for another module:
12854 module ExampStub (/*AUTOINST*/);
12855 /*AUTOINOUTPARAM(\"Examp\")*/
12856 /*AUTOINOUTMODULE(\"Examp\")*/
12858 // verilator lint_off UNUSED
12859 wire _unused_ok = &{1'b0,
12862 // verilator lint_on UNUSED
12865 Typing \\[verilog-auto] will make this into:
12868 // verilator lint_off UNUSED
12869 wire _unused_ok = &{1'b0,
12871 // Beginning of automatics
12875 // End of automatics
12877 // verilator lint_on UNUSED
12882 (let* ((indent-pt (progn (search-backward "/*") (current-column)))
12883 (modi (verilog-modi-current))
12884 (moddecls (verilog-modi-get-decls modi))
12885 (modsubdecls (verilog-modi-get-sub-decls modi))
12886 (sig-list (verilog-signals-not-in
12887 (append (verilog-decls-get-inputs moddecls)
12888 (verilog-decls-get-inouts moddecls))
12889 (append (verilog-subdecls-get-inputs modsubdecls)
12890 (verilog-subdecls-get-inouts modsubdecls)))))
12891 (setq sig-list (verilog-signals-not-matching-regexp
12892 sig-list verilog-auto-unused-ignore-regexp))
12894 (verilog-forward-or-insert-line)
12895 (verilog-insert-indent "// Beginning of automatic unused inputs\n")
12896 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
12898 (let ((sig (car sig-list)))
12899 (indent-to indent-pt)
12900 (insert (verilog-sig-name sig) ",\n")
12901 (setq sig-list (cdr sig-list))))
12902 (verilog-insert-indent "// End of automatics\n")))))
12904 (defun verilog-enum-ascii (signm elim-regexp)
12905 "Convert an enum name SIGNM to an ascii string for insertion.
12906 Remove user provided prefix ELIM-REGEXP."
12907 (or elim-regexp (setq elim-regexp "_ DONT MATCH IT_"))
12908 (let ((case-fold-search t))
12909 ;; All upper becomes all lower for readability
12910 (downcase (verilog-string-replace-matches elim-regexp "" nil nil signm))))
12912 (defun verilog-auto-ascii-enum ()
12913 "Expand AUTOASCIIENUM statements, as part of \\[verilog-auto].
12914 Create a register to contain the ASCII decode of an enumerated signal type.
12915 This will allow trace viewers to show the ASCII name of states.
12917 First, parameters are built into an enumeration using the synopsys enum
12918 comment. The comment must be between the keyword and the symbol.
12919 \(Annoying, but that's what Synopsys's dc_shell FSM reader requires.)
12921 Next, registers which that enum applies to are also tagged with the same
12924 Finally, an AUTOASCIIENUM command is used.
12926 The first parameter is the name of the signal to be decoded.
12928 The second parameter is the name to store the ASCII code into. For the
12929 signal foo, I suggest the name _foo__ascii, where the leading _ indicates
12930 a signal that is just for simulation, and the magic characters _ascii
12931 tell viewers like Dinotrace to display in ASCII format.
12933 The third optional parameter is a string which will be removed
12934 from the state names. It defaults to \"\" which removes nothing.
12936 The fourth optional parameter is \"onehot\" to force one-hot
12937 decoding. If unspecified, if and only if the first parameter
12938 width is 2^(number of states in enum) and does NOT match the
12939 width of the enum, the signal is assumed to be a one-hot
12940 decode. Otherwise, it's a normal encoded state vector.
12942 `verilog-auto-wire-type' may be used to change the datatype of
12945 \"auto enum\" may be used in place of \"synopsys enum\".
12949 //== State enumeration
12950 parameter [2:0] // synopsys enum state_info
12954 //== State variables
12955 reg [2:0] /* synopsys enum state_info */
12956 state_r; /* synopsys state_vector state_r */
12957 reg [2:0] /* synopsys enum state_info */
12960 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
12962 Typing \\[verilog-auto] will make this into:
12964 ... same front matter ...
12966 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
12967 // Beginning of automatic ASCII enum decoding
12968 reg [39:0] state_ascii_r; // Decode of state_r
12969 always @(state_r) begin
12971 SM_IDLE: state_ascii_r = \"idle \";
12972 SM_SEND: state_ascii_r = \"send \";
12973 SM_WAIT1: state_ascii_r = \"wait1\";
12974 default: state_ascii_r = \"%Erro\";
12977 // End of automatics"
12979 (let* ((params (verilog-read-auto-params 2 4))
12980 (undecode-name (nth 0 params))
12981 (ascii-name (nth 1 params))
12982 (elim-regexp (and (nth 2 params)
12983 (not (equal (nth 2 params) ""))
12985 (one-hot-flag (nth 3 params))
12987 (indent-pt (current-indentation))
12988 (modi (verilog-modi-current))
12989 (moddecls (verilog-modi-get-decls modi))
12991 (sig-list-consts (append (verilog-decls-get-consts moddecls)
12992 (verilog-decls-get-gparams moddecls)))
12993 (sig-list-all (verilog-decls-get-iovars moddecls))
12995 (undecode-sig (or (assoc undecode-name sig-list-all)
12996 (error "%s: Signal %s not found in design" (verilog-point-text) undecode-name)))
12997 (undecode-enum (or (verilog-sig-enum undecode-sig)
12998 (error "%s: Signal %s does not have an enum tag" (verilog-point-text) undecode-name)))
13000 (enum-sigs (verilog-signals-not-in
13001 (or (verilog-signals-matching-enum sig-list-consts undecode-enum)
13002 (error "%s: No state definitions for %s" (verilog-point-text) undecode-enum))
13006 (string-match "onehot" (or one-hot-flag ""))
13007 (and ;; width(enum) != width(sig)
13008 (or (not (verilog-sig-bits (car enum-sigs)))
13009 (not (equal (verilog-sig-width (car enum-sigs))
13010 (verilog-sig-width undecode-sig))))
13011 ;; count(enums) == width(sig)
13012 (equal (number-to-string (length enum-sigs))
13013 (verilog-sig-width undecode-sig)))))
13017 ;; Find number of ascii chars needed
13018 (let ((tmp-sigs enum-sigs))
13020 (setq enum-chars (max enum-chars (length (verilog-sig-name (car tmp-sigs))))
13021 ascii-chars (max ascii-chars (length (verilog-enum-ascii
13022 (verilog-sig-name (car tmp-sigs))
13024 tmp-sigs (cdr tmp-sigs))))
13026 (verilog-forward-or-insert-line)
13027 (verilog-insert-indent "// Beginning of automatic ASCII enum decoding\n")
13028 (let ((decode-sig-list (list (list ascii-name (format "[%d:0]" (- (* ascii-chars 8) 1))
13029 (concat "Decode of " undecode-name) nil nil))))
13030 (verilog-insert-definition modi decode-sig-list "reg" indent-pt nil))
13032 (verilog-insert-indent "always @(" undecode-name ") begin\n")
13033 (setq indent-pt (+ indent-pt verilog-indent-level))
13034 (verilog-insert-indent "case ({" undecode-name "})\n")
13035 (setq indent-pt (+ indent-pt verilog-case-indent))
13037 (let ((tmp-sigs enum-sigs)
13038 (chrfmt (format "%%-%ds %s = \"%%-%ds\";\n"
13039 (+ (if one-hot 9 1) (max 8 enum-chars))
13040 ascii-name ascii-chars))
13041 (errname (substring "%Error" 0 (min 6 ascii-chars))))
13043 (verilog-insert-indent
13046 (concat (if one-hot "(")
13047 ;; Use enum-sigs length as that's numeric
13048 ;; verilog-sig-width undecode-sig might not be.
13049 (if one-hot (number-to-string (length enum-sigs)))
13050 ;; We use a shift instead of var[index]
13051 ;; so that a non-one hot value will show as error.
13052 (if one-hot "'b1<<")
13053 (verilog-sig-name (car tmp-sigs))
13054 (if one-hot ")") ":")
13055 (verilog-enum-ascii (verilog-sig-name (car tmp-sigs))
13057 (setq tmp-sigs (cdr tmp-sigs)))
13058 (verilog-insert-indent (format chrfmt "default:" errname)))
13060 (setq indent-pt (- indent-pt verilog-case-indent))
13061 (verilog-insert-indent "endcase\n")
13062 (setq indent-pt (- indent-pt verilog-indent-level))
13063 (verilog-insert-indent "end\n"
13064 "// End of automatics\n"))))
13066 (defun verilog-auto-templated-rel ()
13067 "Replace Templated relative line numbers with absolute line numbers.
13068 Internal use only. This hacks around the line numbers in AUTOINST Templates
13069 being different from the final output's line numbering."
13070 (let ((templateno 0) (template-line (list 0)) (buf-line 1))
13071 ;; Find line number each template is on
13072 ;; Count lines as we go, as otherwise it's O(n^2) to use count-lines
13073 (goto-char (point-min))
13074 (while (not (eobp))
13075 (when (looking-at ".*AUTO_TEMPLATE")
13076 (setq templateno (1+ templateno))
13077 (setq template-line (cons buf-line template-line)))
13078 (setq buf-line (1+ buf-line))
13080 (setq template-line (nreverse template-line))
13081 ;; Replace T# L# with absolute line number
13082 (goto-char (point-min))
13083 (while (re-search-forward " Templated T\\([0-9]+\\) L\\([0-9]+\\)" nil t)
13085 (concat " Templated "
13086 (int-to-string (+ (nth (string-to-number (match-string 1))
13088 (string-to-number (match-string 2)))))
13091 (defun verilog-auto-template-lint ()
13092 "Check AUTO_TEMPLATEs for unused lines.
13093 Enable with `verilog-auto-template-warn-unused'."
13094 (let ((name1 (or (buffer-file-name) (buffer-name))))
13096 (goto-char (point-min))
13097 (while (re-search-forward
13098 "^\\s-*/?\\*?\\s-*[a-zA-Z0-9`_$]+\\s-+AUTO_TEMPLATE" nil t)
13099 (let* ((tpl-info (verilog-read-auto-template-middle))
13100 (tpl-list (aref tpl-info 1))
13101 (tlines (append (nth 0 tpl-list) (nth 1 tpl-list)))
13104 (setq tpl-ass (car tlines)
13105 tlines (cdr tlines))
13107 (unless (or (not (eval-when-compile (fboundp 'make-hash-table))) ;; Not supported, no warning
13108 (not verilog-auto-template-hits)
13109 (gethash (vector (nth 2 tpl-ass) (nth 3 tpl-ass))
13110 verilog-auto-template-hits))
13111 (verilog-warn-error "%s:%d: AUTO_TEMPLATE line unused: \".%s (%s)\""
13113 (+ (elt tpl-ass 3) ;; Template line number
13114 (count-lines (point-min) (point)))
13115 (elt tpl-ass 0) (elt tpl-ass 1))
13123 (defun verilog-auto (&optional inject) ; Use verilog-inject-auto instead of passing an arg
13124 "Expand AUTO statements.
13125 Look for any /*AUTO...*/ commands in the code, as used in
13126 instantiations or argument headers. Update the list of signals
13127 following the /*AUTO...*/ command.
13129 Use \\[verilog-delete-auto] to remove the AUTOs.
13131 Use \\[verilog-diff-auto] to see differences in AUTO expansion.
13133 Use \\[verilog-inject-auto] to insert AUTOs for the first time.
13135 Use \\[verilog-faq] for a pointer to frequently asked questions.
13137 For new users, we recommend setting `verilog-case-fold' to nil
13138 and `verilog-auto-arg-sort' to t.
13140 The hooks `verilog-before-auto-hook' and `verilog-auto-hook' are
13141 called before and after this function, respectively.
13144 module ModuleName (/*AUTOARG*/);
13149 InstMod instName #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);
13151 You can also update the AUTOs from the shell using:
13152 emacs --batch <filenames.v> -f verilog-batch-auto
13153 Or fix indentation with:
13154 emacs --batch <filenames.v> -f verilog-batch-indent
13155 Likewise, you can delete or inject AUTOs with:
13156 emacs --batch <filenames.v> -f verilog-batch-delete-auto
13157 emacs --batch <filenames.v> -f verilog-batch-inject-auto
13158 Or check if AUTOs have the same expansion
13159 emacs --batch <filenames.v> -f verilog-batch-diff-auto
13161 Using \\[describe-function], see also:
13162 `verilog-auto-arg' for AUTOARG module instantiations
13163 `verilog-auto-ascii-enum' for AUTOASCIIENUM enumeration decoding
13164 `verilog-auto-assign-modport' for AUTOASSIGNMODPORT assignment to/from modport
13165 `verilog-auto-inout' for AUTOINOUT making hierarchy inouts
13166 `verilog-auto-inout-comp' for AUTOINOUTCOMP copy complemented i/o
13167 `verilog-auto-inout-in' for AUTOINOUTIN inputs for all i/o
13168 `verilog-auto-inout-modport' for AUTOINOUTMODPORT i/o from an interface modport
13169 `verilog-auto-inout-module' for AUTOINOUTMODULE copying i/o from elsewhere
13170 `verilog-auto-inout-param' for AUTOINOUTPARAM copying params from elsewhere
13171 `verilog-auto-input' for AUTOINPUT making hierarchy inputs
13172 `verilog-auto-insert-lisp' for AUTOINSERTLISP insert code from lisp function
13173 `verilog-auto-inst' for AUTOINST instantiation pins
13174 `verilog-auto-star' for AUTOINST .* SystemVerilog pins
13175 `verilog-auto-inst-param' for AUTOINSTPARAM instantiation params
13176 `verilog-auto-logic' for AUTOLOGIC declaring logic signals
13177 `verilog-auto-output' for AUTOOUTPUT making hierarchy outputs
13178 `verilog-auto-output-every' for AUTOOUTPUTEVERY making all outputs
13179 `verilog-auto-reg' for AUTOREG registers
13180 `verilog-auto-reg-input' for AUTOREGINPUT instantiation registers
13181 `verilog-auto-reset' for AUTORESET flop resets
13182 `verilog-auto-sense' for AUTOSENSE or AS always sensitivity lists
13183 `verilog-auto-tieoff' for AUTOTIEOFF output tieoffs
13184 `verilog-auto-undef' for AUTOUNDEF `undef of local `defines
13185 `verilog-auto-unused' for AUTOUNUSED unused inputs/inouts
13186 `verilog-auto-wire' for AUTOWIRE instantiation wires
13188 `verilog-read-defines' for reading `define values
13189 `verilog-read-includes' for reading `includes
13191 If you have bugs with these autos, please file an issue at
13192 URL `http://www.veripool.org/verilog-mode' or contact the AUTOAUTHOR
13193 Wilson Snyder (wsnyder@wsnyder.org)."
13195 (unless noninteractive (message "Updating AUTOs..."))
13196 (if (fboundp 'dinotrace-unannotate-all)
13197 (dinotrace-unannotate-all))
13198 (verilog-save-font-mods
13199 (let ((oldbuf (if (not (buffer-modified-p))
13201 (case-fold-search verilog-case-fold)
13202 ;; Cache directories; we don't write new files, so can't change
13203 (verilog-dir-cache-preserving t)
13204 ;; Cache current module
13205 (verilog-modi-cache-current-enable t)
13206 (verilog-modi-cache-current-max (point-min)) ; IE it's invalid
13207 verilog-modi-cache-current)
13209 ;; Disable change hooks for speed
13210 ;; This let can't be part of above let; must restore
13211 ;; after-change-functions before font-lock resumes
13212 (verilog-save-no-change-functions
13213 (verilog-save-scan-cache
13215 ;; Wipe cache; otherwise if we AUTOed a block above this one,
13216 ;; we'll misremember we have generated IOs, confusing AUTOOUTPUT
13217 (setq verilog-modi-cache-list nil)
13219 (setq verilog-auto-template-hits nil)
13220 ;; If we're not in verilog-mode, change syntax table so parsing works right
13221 (unless (eq major-mode `verilog-mode) (verilog-mode))
13222 ;; Allow user to customize
13223 (verilog-run-hooks 'verilog-before-auto-hook)
13224 ;; Try to save the user from needing to revert-file to reread file local-variables
13225 (verilog-auto-reeval-locals)
13226 (verilog-read-auto-lisp-present)
13227 (verilog-read-auto-lisp (point-min) (point-max))
13228 (verilog-getopt-flags)
13229 ;; From here on out, we can cache anything we read from disk
13230 (verilog-preserve-dir-cache
13231 ;; These two may seem obvious to do always, but on large includes it can be way too slow
13232 (when verilog-auto-read-includes
13233 (verilog-read-includes)
13234 (verilog-read-defines nil nil t))
13235 ;; Setup variables due to SystemVerilog expansion
13236 (verilog-auto-re-search-do "/\\*AUTOLOGIC\\*/" 'verilog-auto-logic-setup)
13237 ;; This particular ordering is important
13238 ;; INST: Lower modules correct, no internal dependencies, FIRST
13239 (verilog-preserve-modi-cache
13240 ;; Clear existing autos else we'll be screwed by existing ones
13241 (verilog-delete-auto)
13242 ;; Injection if appropriate
13244 (verilog-inject-inst)
13245 (verilog-inject-sense)
13246 (verilog-inject-arg))
13248 ;; Do user inserts first, so their code can insert AUTOs
13249 ;; We may provide an AUTOINSERTLISPLAST if another cleanup pass is needed
13250 (verilog-auto-re-search-do "/\\*AUTOINSERTLISP(.*?)\\*/"
13251 'verilog-auto-insert-lisp)
13252 ;; Expand instances before need the signals the instances input/output
13253 (verilog-auto-re-search-do "/\\*AUTOINSTPARAM\\*/" 'verilog-auto-inst-param)
13254 (verilog-auto-re-search-do "/\\*AUTOINST\\*/" 'verilog-auto-inst)
13255 (verilog-auto-re-search-do "\\.\\*" 'verilog-auto-star)
13256 ;; Doesn't matter when done, but combine it with a common changer
13257 (verilog-auto-re-search-do "/\\*\\(AUTOSENSE\\|AS\\)\\*/" 'verilog-auto-sense)
13258 (verilog-auto-re-search-do "/\\*AUTORESET\\*/" 'verilog-auto-reset)
13259 ;; Must be done before autoin/out as creates a reg
13260 (verilog-auto-re-search-do "/\\*AUTOASCIIENUM(.*?)\\*/" 'verilog-auto-ascii-enum)
13262 ;; first in/outs from other files
13263 (verilog-auto-re-search-do "/\\*AUTOINOUTMODPORT(.*?)\\*/" 'verilog-auto-inout-modport)
13264 (verilog-auto-re-search-do "/\\*AUTOINOUTMODULE(.*?)\\*/" 'verilog-auto-inout-module)
13265 (verilog-auto-re-search-do "/\\*AUTOINOUTCOMP(.*?)\\*/" 'verilog-auto-inout-comp)
13266 (verilog-auto-re-search-do "/\\*AUTOINOUTIN(.*?)\\*/" 'verilog-auto-inout-in)
13267 (verilog-auto-re-search-do "/\\*AUTOINOUTPARAM(.*?)\\*/" 'verilog-auto-inout-param)
13268 ;; next in/outs which need previous sucked inputs first
13269 (verilog-auto-re-search-do "/\\*AUTOOUTPUT\\((.*?)\\)?\\*/" 'verilog-auto-output)
13270 (verilog-auto-re-search-do "/\\*AUTOINPUT\\((.*?)\\)?\\*/" 'verilog-auto-input)
13271 (verilog-auto-re-search-do "/\\*AUTOINOUT\\((.*?)\\)?\\*/" 'verilog-auto-inout)
13272 ;; Then tie off those in/outs
13273 (verilog-auto-re-search-do "/\\*AUTOTIEOFF\\*/" 'verilog-auto-tieoff)
13274 ;; These can be anywhere after AUTOINSERTLISP
13275 (verilog-auto-re-search-do "/\\*AUTOUNDEF\\((.*?)\\)?\\*/" 'verilog-auto-undef)
13276 ;; Wires/regs must be after inputs/outputs
13277 (verilog-auto-re-search-do "/\\*AUTOASSIGNMODPORT(.*?)\\*/" 'verilog-auto-assign-modport)
13278 (verilog-auto-re-search-do "/\\*AUTOLOGIC\\*/" 'verilog-auto-logic)
13279 (verilog-auto-re-search-do "/\\*AUTOWIRE\\*/" 'verilog-auto-wire)
13280 (verilog-auto-re-search-do "/\\*AUTOREG\\*/" 'verilog-auto-reg)
13281 (verilog-auto-re-search-do "/\\*AUTOREGINPUT\\*/" 'verilog-auto-reg-input)
13282 ;; outputevery needs AUTOOUTPUTs done first
13283 (verilog-auto-re-search-do "/\\*AUTOOUTPUTEVERY\\*/" 'verilog-auto-output-every)
13284 ;; After we've created all new variables
13285 (verilog-auto-re-search-do "/\\*AUTOUNUSED\\*/" 'verilog-auto-unused)
13286 ;; Must be after all inputs outputs are generated
13287 (verilog-auto-re-search-do "/\\*AUTOARG\\*/" 'verilog-auto-arg)
13288 ;; Fix line numbers (comments only)
13289 (when verilog-auto-inst-template-numbers
13290 (verilog-auto-templated-rel))
13291 (when verilog-auto-template-warn-unused
13292 (verilog-auto-template-lint))))
13294 (verilog-run-hooks 'verilog-auto-hook)
13296 (when verilog-auto-delete-trailing-whitespace
13297 (verilog-delete-trailing-whitespace))
13299 (set (make-local-variable 'verilog-auto-update-tick) (buffer-chars-modified-tick))
13301 ;; If end result is same as when started, clear modified flag
13302 (cond ((and oldbuf (equal oldbuf (buffer-string)))
13303 (set-buffer-modified-p nil)
13304 (unless noninteractive (message "Updating AUTOs...done (no changes)")))
13305 (t (unless noninteractive (message "Updating AUTOs...done"))))
13306 ;; End of after-change protection
13309 ;; Currently handled in verilog-save-font-mods
13314 ;; Skeleton based code insertion
13316 (defvar verilog-template-map
13317 (let ((map (make-sparse-keymap)))
13318 (define-key map "a" 'verilog-sk-always)
13319 (define-key map "b" 'verilog-sk-begin)
13320 (define-key map "c" 'verilog-sk-case)
13321 (define-key map "f" 'verilog-sk-for)
13322 (define-key map "g" 'verilog-sk-generate)
13323 (define-key map "h" 'verilog-sk-header)
13324 (define-key map "i" 'verilog-sk-initial)
13325 (define-key map "j" 'verilog-sk-fork)
13326 (define-key map "m" 'verilog-sk-module)
13327 (define-key map "o" 'verilog-sk-ovm-class)
13328 (define-key map "p" 'verilog-sk-primitive)
13329 (define-key map "r" 'verilog-sk-repeat)
13330 (define-key map "s" 'verilog-sk-specify)
13331 (define-key map "t" 'verilog-sk-task)
13332 (define-key map "u" 'verilog-sk-uvm-object)
13333 (define-key map "w" 'verilog-sk-while)
13334 (define-key map "x" 'verilog-sk-casex)
13335 (define-key map "z" 'verilog-sk-casez)
13336 (define-key map "?" 'verilog-sk-if)
13337 (define-key map ":" 'verilog-sk-else-if)
13338 (define-key map "/" 'verilog-sk-comment)
13339 (define-key map "A" 'verilog-sk-assign)
13340 (define-key map "F" 'verilog-sk-function)
13341 (define-key map "I" 'verilog-sk-input)
13342 (define-key map "O" 'verilog-sk-output)
13343 (define-key map "S" 'verilog-sk-state-machine)
13344 (define-key map "=" 'verilog-sk-inout)
13345 (define-key map "U" 'verilog-sk-uvm-component)
13346 (define-key map "W" 'verilog-sk-wire)
13347 (define-key map "R" 'verilog-sk-reg)
13348 (define-key map "D" 'verilog-sk-define-signal)
13350 "Keymap used in Verilog mode for smart template operations.")
13354 ;; Place the templates into Verilog Mode. They may be inserted under any key.
13355 ;; C-c C-t will be the default. If you use templates a lot, you
13356 ;; may want to consider moving the binding to another key in your init
13359 ;; Note \C-c and letter are reserved for users
13360 (define-key verilog-mode-map "\C-c\C-t" verilog-template-map)
13362 ;;; ---- statement skeletons ------------------------------------------
13364 (define-skeleton verilog-sk-prompt-condition
13365 "Prompt for the loop condition."
13366 "[condition]: " str )
13368 (define-skeleton verilog-sk-prompt-init
13369 "Prompt for the loop init statement."
13370 "[initial statement]: " str )
13372 (define-skeleton verilog-sk-prompt-inc
13373 "Prompt for the loop increment statement."
13374 "[increment statement]: " str )
13376 (define-skeleton verilog-sk-prompt-name
13377 "Prompt for the name of something."
13380 (define-skeleton verilog-sk-prompt-clock
13381 "Prompt for the name of something."
13382 "name and edge of clock(s): " str)
13384 (defvar verilog-sk-reset nil)
13385 (defun verilog-sk-prompt-reset ()
13386 "Prompt for the name of a state machine reset."
13387 (setq verilog-sk-reset (read-string "name of reset: " "rst")))
13390 (define-skeleton verilog-sk-prompt-state-selector
13391 "Prompt for the name of a state machine selector."
13392 "name of selector (eg {a,b,c,d}): " str )
13394 (define-skeleton verilog-sk-prompt-output
13395 "Prompt for the name of something."
13398 (define-skeleton verilog-sk-prompt-msb
13399 "Prompt for most significant bit specification."
13400 "msb:" str & ?: & '(verilog-sk-prompt-lsb) | -1 )
13402 (define-skeleton verilog-sk-prompt-lsb
13403 "Prompt for least significant bit specification."
13406 (defvar verilog-sk-p nil)
13407 (define-skeleton verilog-sk-prompt-width
13408 "Prompt for a width specification."
13411 (setq verilog-sk-p (point))
13412 (verilog-sk-prompt-msb)
13413 (if (> (point) verilog-sk-p) "] " " ")))
13415 (defun verilog-sk-header ()
13416 "Insert a descriptive header at the top of the file.
13417 See also `verilog-header' for an alternative format."
13420 (goto-char (point-min))
13421 (verilog-sk-header-tmpl)))
13423 (define-skeleton verilog-sk-header-tmpl
13424 "Insert a comment block containing the module title, author, etc."
13426 "// -*- Mode: Verilog -*-"
13427 "\n// Filename : " (buffer-name)
13428 "\n// Description : " str
13429 "\n// Author : " (user-full-name)
13430 "\n// Created On : " (current-time-string)
13431 "\n// Last Modified By: " (user-full-name)
13432 "\n// Last Modified On: " (current-time-string)
13433 "\n// Update Count : 0"
13434 "\n// Status : Unknown, Use with caution!"
13437 (define-skeleton verilog-sk-module
13438 "Insert a module definition."
13440 > "module " '(verilog-sk-prompt-name) " (/*AUTOARG*/ ) ;" \n
13442 > (- verilog-indent-level-behavioral) "endmodule" (progn (electric-verilog-terminate-line) nil))
13444 ;;; ------------------------------------------------------------------------
13445 ;;; Define a default OVM class, with macros and new()
13446 ;;; ------------------------------------------------------------------------
13448 (define-skeleton verilog-sk-ovm-class
13449 "Insert a class definition"
13451 > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n
13453 > "`ovm_object_utils_begin(" name ")" \n
13454 > (- verilog-indent-level) " `ovm_object_utils_end" \n
13456 > "function new(name=\"" name "\");" \n
13457 > "super.new(name);" \n
13458 > (- verilog-indent-level) "endfunction" \n
13460 > "endclass" (progn (electric-verilog-terminate-line) nil))
13462 (define-skeleton verilog-sk-uvm-object
13463 "Insert a class definition"
13465 > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n
13467 > "`uvm_object_utils_begin(" name ")" \n
13468 > (- verilog-indent-level) "`uvm_object_utils_end" \n
13470 > "function new(name=\"" name "\");" \n
13471 > "super.new(name);" \n
13472 > (- verilog-indent-level) "endfunction" \n
13474 > "endclass" (progn (electric-verilog-terminate-line) nil))
13476 (define-skeleton verilog-sk-uvm-component
13477 "Insert a class definition"
13479 > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n
13481 > "`uvm_component_utils_begin(" name ")" \n
13482 > (- verilog-indent-level) "`uvm_component_utils_end" \n
13484 > "function new(name=\"\", uvm_component parent);" \n
13485 > "super.new(name, parent);" \n
13486 > (- verilog-indent-level) "endfunction" \n
13488 > "endclass" (progn (electric-verilog-terminate-line) nil))
13490 (define-skeleton verilog-sk-primitive
13491 "Insert a task definition."
13493 > "primitive " '(verilog-sk-prompt-name) " ( " '(verilog-sk-prompt-output) ("input:" ", " str ) " );"\n
13495 > (- verilog-indent-level-behavioral) "endprimitive" (progn (electric-verilog-terminate-line) nil))
13497 (define-skeleton verilog-sk-task
13498 "Insert a task definition."
13500 > "task " '(verilog-sk-prompt-name) & ?; \n
13504 > (- verilog-indent-level-behavioral) "end" \n
13505 > (- verilog-indent-level-behavioral) "endtask" (progn (electric-verilog-terminate-line) nil))
13507 (define-skeleton verilog-sk-function
13508 "Insert a function definition."
13510 > "function [" '(verilog-sk-prompt-width) | -1 '(verilog-sk-prompt-name) ?; \n
13514 > (- verilog-indent-level-behavioral) "end" \n
13515 > (- verilog-indent-level-behavioral) "endfunction" (progn (electric-verilog-terminate-line) nil))
13517 (define-skeleton verilog-sk-always
13518 "Insert always block. Uses the minibuffer to prompt
13519 for sensitivity list."
13521 > "always @ ( /*AUTOSENSE*/ ) begin\n"
13523 > (- verilog-indent-level-behavioral) "end" \n >
13526 (define-skeleton verilog-sk-initial
13527 "Insert an initial block."
13529 > "initial begin\n"
13531 > (- verilog-indent-level-behavioral) "end" \n > )
13533 (define-skeleton verilog-sk-specify
13534 "Insert specify block. "
13538 > (- verilog-indent-level-behavioral) "endspecify" \n > )
13540 (define-skeleton verilog-sk-generate
13541 "Insert generate block. "
13545 > (- verilog-indent-level-behavioral) "endgenerate" \n > )
13547 (define-skeleton verilog-sk-begin
13548 "Insert begin end block. Uses the minibuffer to prompt for name."
13550 > "begin" '(verilog-sk-prompt-name) \n
13552 > (- verilog-indent-level-behavioral) "end" )
13554 (define-skeleton verilog-sk-fork
13555 "Insert a fork join block."
13560 > (- verilog-indent-level-behavioral) "end" \n
13563 > (- verilog-indent-level-behavioral) "end" \n
13564 > (- verilog-indent-level-behavioral) "join" \n
13568 (define-skeleton verilog-sk-case
13569 "Build skeleton case statement, prompting for the selector expression,
13570 and the case items."
13571 "[selector expression]: "
13572 > "case (" str ") " \n
13573 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
13574 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
13576 (define-skeleton verilog-sk-casex
13577 "Build skeleton casex statement, prompting for the selector expression,
13578 and the case items."
13579 "[selector expression]: "
13580 > "casex (" str ") " \n
13581 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
13582 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
13584 (define-skeleton verilog-sk-casez
13585 "Build skeleton casez statement, prompting for the selector expression,
13586 and the case items."
13587 "[selector expression]: "
13588 > "casez (" str ") " \n
13589 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
13590 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
13592 (define-skeleton verilog-sk-if
13593 "Insert a skeleton if statement."
13594 > "if (" '(verilog-sk-prompt-condition) & ")" " begin" \n
13596 > (- verilog-indent-level-behavioral) "end " \n )
13598 (define-skeleton verilog-sk-else-if
13599 "Insert a skeleton else if statement."
13600 > (verilog-indent-line) "else if ("
13601 (progn (setq verilog-sk-p (point)) nil) '(verilog-sk-prompt-condition) (if (> (point) verilog-sk-p) ") " -1 ) & " begin" \n
13603 > "end" (progn (electric-verilog-terminate-line) nil))
13605 (define-skeleton verilog-sk-datadef
13606 "Common routine to get data definition."
13608 '(verilog-sk-prompt-width) | -1 ("name (RET to end):" str ", ") -2 ";" \n)
13610 (define-skeleton verilog-sk-input
13611 "Insert an input definition."
13613 > "input [" '(verilog-sk-datadef))
13615 (define-skeleton verilog-sk-output
13616 "Insert an output definition."
13618 > "output [" '(verilog-sk-datadef))
13620 (define-skeleton verilog-sk-inout
13621 "Insert an inout definition."
13623 > "inout [" '(verilog-sk-datadef))
13625 (defvar verilog-sk-signal nil)
13626 (define-skeleton verilog-sk-def-reg
13627 "Insert a reg definition."
13629 > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-signal ";" \n (verilog-pretty-declarations-auto) )
13631 (defun verilog-sk-define-signal ()
13632 "Insert a definition of signal under point at top of module."
13634 (let* ((sig-re "[a-zA-Z0-9_]*")
13635 (v1 (buffer-substring
13637 (skip-chars-backward sig-re)
13640 (skip-chars-forward sig-re)
13642 (if (not (member v1 verilog-keywords))
13644 (setq verilog-sk-signal v1)
13645 (verilog-beg-of-defun)
13646 (verilog-end-of-statement)
13647 (verilog-forward-syntactic-ws)
13648 (verilog-sk-def-reg)
13649 (message "signal at point is %s" v1))
13650 (message "object at point (%s) is a keyword" v1))))
13652 (define-skeleton verilog-sk-wire
13653 "Insert a wire definition."
13655 > "wire [" '(verilog-sk-datadef))
13657 (define-skeleton verilog-sk-reg
13658 "Insert a reg definition."
13660 > "reg [" '(verilog-sk-datadef))
13662 (define-skeleton verilog-sk-assign
13663 "Insert a skeleton assign statement."
13665 > "assign " '(verilog-sk-prompt-name) " = " _ ";" \n)
13667 (define-skeleton verilog-sk-while
13668 "Insert a skeleton while loop statement."
13670 > "while (" '(verilog-sk-prompt-condition) ") begin" \n
13672 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
13674 (define-skeleton verilog-sk-repeat
13675 "Insert a skeleton repeat loop statement."
13677 > "repeat (" '(verilog-sk-prompt-condition) ") begin" \n
13679 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
13681 (define-skeleton verilog-sk-for
13682 "Insert a skeleton while loop statement."
13685 '(verilog-sk-prompt-init) "; "
13686 '(verilog-sk-prompt-condition) "; "
13687 '(verilog-sk-prompt-inc)
13690 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
13692 (define-skeleton verilog-sk-comment
13693 "Inserts three comment lines, making a display comment."
13699 (define-skeleton verilog-sk-state-machine
13700 "Insert a state machine definition."
13701 "Name of state variable: "
13702 '(setq input "state")
13703 > "// State registers for " str | -23 \n
13704 '(setq verilog-sk-state str)
13705 > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-state ", next_" verilog-sk-state ?; \n
13708 > "// State FF for " verilog-sk-state \n
13709 > "always @ ( " (read-string "clock:" "posedge clk") " or " (verilog-sk-prompt-reset) " ) begin" \n
13710 > "if ( " verilog-sk-reset " ) " verilog-sk-state " = 0; else" \n
13711 > verilog-sk-state " = next_" verilog-sk-state ?; \n
13712 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil)
13714 > "// Next State Logic for " verilog-sk-state \n
13715 > "always @ ( /*AUTOSENSE*/ ) begin\n"
13716 > "case (" '(verilog-sk-prompt-state-selector) ") " \n
13717 > ("case selector: " str ": begin" \n > "next_" verilog-sk-state " = " _ ";" \n > (- verilog-indent-level-behavioral) "end" \n )
13718 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil)
13719 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil))
13723 ;; Include file loading with mouse/return event
13725 ;; idea & first impl.: M. Rouat (eldo-mode.el)
13726 ;; second (emacs/xemacs) impl.: G. Van der Plas (spice-mode.el)
13728 (if (featurep 'xemacs)
13729 (require 'overlay))
13731 (defconst verilog-include-file-regexp
13732 "^`include\\s-+\"\\([^\n\"]*\\)\""
13733 "Regexp that matches the include file.")
13735 (defvar verilog-mode-mouse-map
13736 (let ((map (make-sparse-keymap))) ; as described in info pages, make a map
13737 (set-keymap-parent map verilog-mode-map)
13738 ;; mouse button bindings
13739 (define-key map "\r" 'verilog-load-file-at-point)
13740 (if (featurep 'xemacs)
13741 (define-key map 'button2 'verilog-load-file-at-mouse);ffap-at-mouse ?
13742 (define-key map [mouse-2] 'verilog-load-file-at-mouse))
13743 (if (featurep 'xemacs)
13744 (define-key map 'Sh-button2 'mouse-yank) ; you wanna paste don't you ?
13745 (define-key map [S-mouse-2] 'mouse-yank-at-click))
13747 "Map containing mouse bindings for `verilog-mode'.")
13750 (defun verilog-highlight-region (beg end _old-len)
13751 "Colorize included files and modules in the (changed?) region.
13752 Clicking on the middle-mouse button loads them in a buffer (as in dired)."
13753 (when (or verilog-highlight-includes
13754 verilog-highlight-modules)
13756 (save-match-data ;; A query-replace may call this function - do not disturb
13757 (verilog-save-buffer-state
13758 (verilog-save-scan-cache
13761 (setq end-point (point-at-eol))
13763 (beginning-of-line) ; scan entire line
13764 ;; delete overlays existing on this line
13765 (let ((overlays (overlays-in (point) end-point)))
13768 (overlay-get (car overlays) 'detachable)
13769 (or (overlay-get (car overlays) 'verilog-include-file)
13770 (overlay-get (car overlays) 'verilog-inst-module)))
13771 (delete-overlay (car overlays)))
13772 (setq overlays (cdr overlays))))
13774 ;; make new include overlays
13775 (when verilog-highlight-includes
13776 (while (search-forward-regexp verilog-include-file-regexp end-point t)
13777 (goto-char (match-beginning 1))
13778 (let ((ov (make-overlay (match-beginning 1) (match-end 1))))
13779 (overlay-put ov 'start-closed 't)
13780 (overlay-put ov 'end-closed 't)
13781 (overlay-put ov 'evaporate 't)
13782 (overlay-put ov 'verilog-include-file 't)
13783 (overlay-put ov 'mouse-face 'highlight)
13784 (overlay-put ov 'local-map verilog-mode-mouse-map))))
13786 ;; make new module overlays
13788 ;; This scanner is syntax-fragile, so don't get bent
13789 (when verilog-highlight-modules
13790 (condition-case nil
13791 (while (verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-point t)
13793 (goto-char (match-beginning 0))
13794 (unless (verilog-inside-comment-or-string-p)
13795 (verilog-read-inst-module-matcher) ;; sets match 0
13796 (let* ((ov (make-overlay (match-beginning 0) (match-end 0))))
13797 (overlay-put ov 'start-closed 't)
13798 (overlay-put ov 'end-closed 't)
13799 (overlay-put ov 'evaporate 't)
13800 (overlay-put ov 'verilog-inst-module 't)
13801 (overlay-put ov 'mouse-face 'highlight)
13802 (overlay-put ov 'local-map verilog-mode-mouse-map)))))
13805 ;; Future highlights:
13806 ;; variables - make an Occur buffer of where referenced
13807 ;; pins - make an Occur buffer of the sig in the declaration module
13810 (defun verilog-highlight-buffer ()
13811 "Colorize included files and modules across the whole buffer."
13812 ;; Invoked via verilog-mode calling font-lock then `font-lock-mode-hook'
13814 ;; delete and remake overlays
13815 (verilog-highlight-region (point-min) (point-max) nil))
13817 ;; Deprecated, but was interactive, so we'll keep it around
13818 (defalias 'verilog-colorize-include-files-buffer 'verilog-highlight-buffer)
13820 ;; ffap-at-mouse isn't useful for Verilog mode. It uses library paths.
13821 ;; so define this function to do more or less the same as ffap-at-mouse
13822 ;; but first resolve filename...
13823 (defun verilog-load-file-at-mouse (event)
13824 "Load file under button 2 click's EVENT.
13825 Files are checked based on `verilog-library-flags'."
13827 (save-excursion ;; implement a Verilog specific ffap-at-mouse
13828 (mouse-set-point event)
13829 (verilog-load-file-at-point t)))
13831 ;; ffap isn't usable for Verilog mode. It uses library paths.
13832 ;; so define this function to do more or less the same as ffap
13833 ;; but first resolve filename...
13834 (defun verilog-load-file-at-point (&optional warn)
13835 "Load file under point.
13836 If WARN, throw warning if not found.
13837 Files are checked based on `verilog-library-flags'."
13839 (save-excursion ;; implement a Verilog specific ffap
13840 (let ((overlays (overlays-in (point) (point)))
13842 (while (and overlays (not hit))
13843 (when (overlay-get (car overlays) 'verilog-inst-module)
13844 (verilog-goto-defun-file (buffer-substring
13845 (overlay-start (car overlays))
13846 (overlay-end (car overlays))))
13848 (setq overlays (cdr overlays)))
13850 (beginning-of-line)
13851 (when (and (not hit)
13852 (looking-at verilog-include-file-regexp))
13853 (if (and (car (verilog-library-filenames
13854 (match-string 1) (buffer-file-name)))
13855 (file-readable-p (car (verilog-library-filenames
13856 (match-string 1) (buffer-file-name)))))
13857 (find-file (car (verilog-library-filenames
13858 (match-string 1) (buffer-file-name))))
13861 "File '%s' isn't readable, use shift-mouse2 to paste in this field"
13862 (match-string 1))))))))
13868 (defun verilog-faq ()
13869 "Tell the user their current version, and where to get the FAQ etc."
13871 (with-output-to-temp-buffer "*verilog-mode help*"
13872 (princ (format "You are using verilog-mode %s\n" verilog-mode-version))
13874 (princ "For new releases, see http://www.verilog.com\n")
13876 (princ "For frequently asked questions, see http://www.veripool.org/verilog-mode-faq.html\n")
13878 (princ "To submit a bug, use M-x verilog-submit-bug-report\n")
13881 (autoload 'reporter-submit-bug-report "reporter")
13882 (defvar reporter-prompt-for-summary-p)
13884 (defun verilog-submit-bug-report ()
13885 "Submit via mail a bug report on verilog-mode.el."
13887 (let ((reporter-prompt-for-summary-p t))
13888 (reporter-submit-bug-report
13889 "mac@verilog.com, wsnyder@wsnyder.org"
13890 (concat "verilog-mode v" verilog-mode-version)
13892 verilog-active-low-regexp
13893 verilog-after-save-font-hook
13894 verilog-align-ifelse
13895 verilog-assignment-delay
13896 verilog-auto-arg-sort
13897 verilog-auto-declare-nettype
13898 verilog-auto-delete-trailing-whitespace
13899 verilog-auto-endcomments
13901 verilog-auto-ignore-concat
13902 verilog-auto-indent-on-newline
13903 verilog-auto-inout-ignore-regexp
13904 verilog-auto-input-ignore-regexp
13905 verilog-auto-inst-column
13906 verilog-auto-inst-dot-name
13907 verilog-auto-inst-interfaced-ports
13908 verilog-auto-inst-param-value
13909 verilog-auto-inst-sort
13910 verilog-auto-inst-template-numbers
13911 verilog-auto-inst-vector
13912 verilog-auto-lineup
13913 verilog-auto-newline
13914 verilog-auto-output-ignore-regexp
13915 verilog-auto-read-includes
13916 verilog-auto-reset-blocking-in-non
13917 verilog-auto-reset-widths
13918 verilog-auto-save-policy
13919 verilog-auto-sense-defines-constant
13920 verilog-auto-sense-include-inputs
13921 verilog-auto-star-expand
13922 verilog-auto-star-save
13923 verilog-auto-template-warn-unused
13924 verilog-auto-tieoff-declaration
13925 verilog-auto-tieoff-ignore-regexp
13926 verilog-auto-unused-ignore-regexp
13927 verilog-auto-wire-type
13928 verilog-before-auto-hook
13929 verilog-before-delete-auto-hook
13930 verilog-before-getopt-flags-hook
13931 verilog-before-save-font-hook
13932 verilog-cache-enabled
13934 verilog-case-indent
13935 verilog-cexp-indent
13938 verilog-delete-auto-hook
13939 verilog-getopt-flags-hook
13940 verilog-highlight-grouping-keywords
13941 verilog-highlight-includes
13942 verilog-highlight-modules
13943 verilog-highlight-p1800-keywords
13944 verilog-highlight-translate-off
13945 verilog-indent-begin-after-if
13946 verilog-indent-declaration-macros
13947 verilog-indent-level
13948 verilog-indent-level-behavioral
13949 verilog-indent-level-declaration
13950 verilog-indent-level-directive
13951 verilog-indent-level-module
13952 verilog-indent-lists
13953 verilog-library-directories
13954 verilog-library-extensions
13955 verilog-library-files
13956 verilog-library-flags
13958 verilog-minimum-comment-distance
13960 verilog-mode-release-emacs
13961 verilog-mode-version
13962 verilog-preprocessor
13964 verilog-tab-always-indent
13965 verilog-tab-to-comment
13966 verilog-typedef-regexp
13972 I want to report a bug.
13974 Before I go further, I want to say that Verilog mode has changed my life.
13975 I save so much time, my files are colored nicely, my co workers respect
13976 my coding ability... until now. I'd really appreciate anything you
13977 could do to help me out with this minor deficiency in the product.
13979 I've taken a look at the Verilog-Mode FAQ at
13980 http://www.veripool.org/verilog-mode-faq.html.
13982 And, I've considered filing the bug on the issue tracker at
13983 http://www.veripool.org/verilog-mode-bugs
13984 since I realize that public bugs are easier for you to track,
13985 and for others to search, but would prefer to email.
13987 So, to reproduce the bug, start a fresh Emacs via " invocation-name "
13988 -no-init-file -no-site-file'. In a new buffer, in Verilog mode, type
13989 the code included below.
13991 Given those lines, I expected [[Fill in here]] to happen;
13992 but instead, [[Fill in here]] happens!.
13994 == The code: =="))))
13996 (provide 'verilog-mode)
13998 ;; Local Variables:
13999 ;; checkdoc-permit-comma-termination-flag:t
14000 ;; checkdoc-force-docstrings-flag:nil
14003 ;;; verilog-mode.el ends here