;;; Code:
;; This variable will always hold the version number of the mode
-(defconst verilog-mode-version "552"
+(defconst verilog-mode-version "556"
"Version of this Verilog mode.")
-(defconst verilog-mode-release-date "2009-11-25-GNU"
+(defconst verilog-mode-release-date "2009-12-10-GNU"
"Release date of this Verilog mode.")
(defconst verilog-mode-release-emacs t
"If non-nil, this version of Verilog mode was released with Emacs itself.")
:type '(radio (const :tag "Line up Assignments and Declarations" all)
(const :tag "Line up Assignment statements" assignments )
- (const :tag "Line up Declarartions" declarations)
+ (const :tag "Line up Declarations" declarations)
(function :tag "Other"))
:group 'verilog-mode-indent )
:help "Help on AUTOARG - declaring module port list"]
["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum)
:help "Help on AUTOASCIIENUM - creating ASCII for enumerations"]
- ["AUTOINOUTCOMP" (describe-function 'verilog-auto-inout-complement)
+ ["AUTOINOUTCOMP" (describe-function 'verilog-auto-inout-comp)
:help "Help on AUTOINOUTCOMP - copying complemented i/o from another file"]
["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module)
:help "Help on AUTOINOUTMODULE - copying i/o from another file"]
"`ovm_sequencer_utils_end"
) nil )))
+(defconst verilog-vmm-begin-re
+ (eval-when-compile
+ (verilog-regexp-opt
+ '(
+ "`vmm_data_member_begin"
+ "`vmm_env_member_begin"
+ "`vmm_scenario_member_begin"
+ "`vmm_subenv_member_begin"
+ "`vmm_xactor_member_begin"
+ ) nil ) ) )
+
+(defconst verilog-vmm-end-re
+ (eval-when-compile
+ (verilog-regexp-opt
+ '(
+ "`vmm_data_member_end"
+ "`vmm_env_member_end"
+ "`vmm_scenario_member_end"
+ "`vmm_subenv_member_end"
+ "`vmm_xactor_member_end"
+ ) nil ) ) )
+
+(defconst verilog-vmm-statement-re
+ (eval-when-compile
+ (verilog-regexp-opt
+ '(
+;; "`vmm_xactor_member_enum_array"
+ "`vmm_\\(data\\|env\\|scenario\\|subenv\\|xactor\\)_member_\\(scalar\\|string\\|enum\\|vmm_data\\|channel\\|xactor\\|subenv\\|user_defined\\)\\(_array\\)?"
+;; "`vmm_xactor_member_scalar_array"
+;; "`vmm_xactor_member_scalar"
+ ) nil )))
+
(defconst verilog-ovm-statement-re
(eval-when-compile
(verilog-regexp-opt
(concat
"\\(\\<else\\>\\)\\|" ; 1
"\\(\\<if\\>\\)\\|" ; 2
- "\\(\\<end\\>\\)\\|" ; 3
+ "\\(\\<assert\\>\\)\\|" ; 3
+ "\\(\\<end\\>\\)\\|" ; 3.1
"\\(\\<endcase\\>\\)\\|" ; 4
"\\(\\<endfunction\\>\\)\\|" ; 5
"\\(\\<endtask\\>\\)\\|" ; 6
"\\(\\<join\\(_any\\|_none\\)?\\>\\)\\|" ; 10
"\\(\\<endclass\\>\\)\\|" ; 11
"\\(\\<endgroup\\>\\)\\|" ; 12
+ ;; VMM
+ "\\(\\<`vmm_data_member_end\\>\\)\\|"
+ "\\(\\<`vmm_env_member_end\\>\\)\\|"
+ "\\(\\<`vmm_scenario_member_end\\>\\)\\|"
+ "\\(\\<`vmm_subenv_member_end\\>\\)\\|"
+ "\\(\\<`vmm_xactor_member_end\\>\\)\\|"
;; OVM
"\\(\\<`ovm_component_utils_end\\>\\)\\|"
"\\(\\<`ovm_field_utils_end\\>\\)\\|"
"`ovm_object_utils_end"
"`ovm_sequence_utils_end"
"`ovm_sequencer_utils_end"
-
+ ;; VMM
+ "`vmm_data_member_end"
+ "`vmm_env_member_end"
+ "`vmm_scenario_member_end"
+ "`vmm_subenv_member_end"
+ "`vmm_xactor_member_end"
))))
"`ovm_object_param_utils_begin"
"`ovm_sequence_utils_begin"
"`ovm_sequencer_utils_begin"
-
+ ;; VMM
+ "`vmm_data_member_begin"
+ "`vmm_env_member_begin"
+ "`vmm_scenario_member_begin"
+ "`vmm_subenv_member_begin"
+ "`vmm_xactor_member_begin"
))))
;; These are the same words, in a specific order in the regular
;; expression so that matching will work nicely for
"\\|\\(\\<\\(rand\\)?sequence\\>\\)" ;21 25
"\\|\\(\\<clocking\\>\\)" ;22 27
"\\|\\(\\<`ovm_[a-z_]+_begin\\>\\)" ;28
+ "\\|\\(\\<`vmm_[a-z_]+_member_begin\\>\\)"
;;
))
"endfunction"
"endgenerate"
"endmodule"
- "endprimative"
+ "endprimitive"
"endinterface"
"endpackage"
"endspecify"
"`ovm_object_utils_end"
"`ovm_sequence_utils_end"
"`ovm_sequencer_utils_end"
+ ;; VMM Begin tokens
+ "`vmm_data_member_begin"
+ "`vmm_env_member_begin"
+ "`vmm_scenario_member_begin"
+ "`vmm_subenv_member_begin"
+ "`vmm_xactor_member_begin"
+ ;; VMM End tokens
+ "`vmm_data_member_end"
+ "`vmm_env_member_end"
+ "`vmm_scenario_member_end"
+ "`vmm_subenv_member_end"
+ "`vmm_xactor_member_end"
))))
(defconst verilog-defun-level-not-generate-re
(while
;; If the current point does not begin a new
;; statement, as in the character ahead of us is a ';', or SOF
- ;; or the string after us unambiguosly starts a statement,
+ ;; or the string after us unambiguously starts a statement,
;; or the token before us unambiguously ends a statement,
;; then move back a token and test again.
(not (or
;; if we have a directive, done.
(if (save-excursion (beginning-of-line)
(and (looking-at verilog-directive-re-1)
- (not (looking-at "[ \t]*`ovm_"))))
+ (not (or (looking-at "[ \t]*`ovm_")
+ (looking-at "[ \t]*`vmm_")))))
(throw 'nesting 'directive))
;; indent structs as if there were module level
(if (verilog-in-struct-p)
(beginning-of-line)
(verilog-forward-syntactic-ws)
(throw 'nesting 'statement)))))
+ ((match-end 3) ; assert block
+ (setq elsec (1- elsec))
+ (verilog-beg-of-statement) ;; doesn't get to beginning
+ (if (looking-at (concat "\\(" verilog-label-re "\\)?"
+ "\\(assert\\|assume\\|cover\\)\\s-+property\\>"))
+ (throw 'nesting 'statement) ; We don't need an endproperty for these
+ (throw 'nesting 'block) ;We still need a endproperty
+ ))
(t ; endblock
; try to leap back to matching outward block by striding across
; indent level changing tokens then immediately
(let (( reg) (nest 1))
;; verilog-ends => else|if|end|join(_any|_none|)|endcase|endclass|endtable|endspecify|endfunction|endtask|endgenerate|endgroup
(cond
- ((match-end 3) ; end
+ ((match-end 4) ; end
;; Search back for matching begin
(setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
- ((match-end 4) ; endcase
+ ((match-end 5) ; endcase
;; Search back for matching case
(setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
- ((match-end 5) ; endfunction
+ ((match-end 6) ; endfunction
;; Search back for matching function
(setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
- ((match-end 6) ; endtask
+ ((match-end 7) ; endtask
;; Search back for matching task
(setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
- ((match-end 7) ; endspecify
+ ((match-end 8) ; endspecify
;; Search back for matching specify
(setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
- ((match-end 8) ; endtable
+ ((match-end 9) ; endtable
;; Search back for matching table
(setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
- ((match-end 9) ; endgenerate
+ ((match-end 10) ; endgenerate
;; Search back for matching generate
(setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
- ((match-end 10) ; joins
+ ((match-end 11) ; joins
;; Search back for matching fork
(setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|none\\)?\\>\\)" ))
- ((match-end 11) ; class
+ ((match-end 12) ; class
;; Search back for matching class
(setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
- ((match-end 12) ; covergroup
+ ((match-end 13) ; covergroup
;; Search back for matching covergroup
(setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" )))
(catch 'skip
((equal (char-after) ?\})
(let ((there (verilog-at-close-constraint-p)))
- (if there ;; we are at the } that closes a constraing. Find the { that opens it
+ (if there ;; we are at the } that closes a constraint. Find the { that opens it
(progn
(forward-char 1)
(backward-list 1)
((looking-at verilog-ovm-end-re)
;; 12: Search back for matching sequence
(setq reg (concat "\\(" verilog-ovm-begin-re "\\|" verilog-ovm-end-re "\\)")))
+ ((looking-at verilog-vmm-end-re)
+ ;; 12: Search back for matching sequence
+ (setq reg (concat "\\(" verilog-vmm-begin-re "\\|" verilog-vmm-end-re "\\)")))
((looking-at "\\<endinterface\\>")
;; 12: Search back for matching interface
(setq reg "\\(\\<interface\\>\\)\\|\\(\\<endinterface\\>\\)" ))
t)
((looking-at verilog-ovm-end-re)
t)
+ ;; JBA find VMM macros
+ ((looking-at verilog-vmm-statement-re)
+ nil )
+ ((looking-at verilog-vmm-begin-re)
+ t)
+ ((looking-at verilog-vmm-end-re)
+ nil)
+ ;; JBA trying to catch macro lines with no ; at end
+ ((looking-at "\\<`")
+ nil)
(t
(goto-char back)
(cond
(cond
((looking-at myre)
(goto-char (match-beginning 2))
- (if (not (verilog-parenthesis-depth)) ;; ignore parenthsized exprs
+ (if (not (verilog-parenthesis-depth)) ;; ignore parenthesized exprs
(if (eq (char-after) ?=)
(indent-to (1+ ind)) ; line up the = of the <= with surrounding =
(indent-to ind)
(while (progn (setq e (marker-position edpos))
(< (point) e))
(if (and (verilog-re-search-forward myre e 'move)
- (not (verilog-parenthesis-depth))) ;; skip parenthsized exprs
+ (not (verilog-parenthesis-depth))) ;; skip parenthesized exprs
(progn
(goto-char (match-beginning 2))
(verilog-backward-syntactic-ws)
((looking-at "\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
(goto-char (match-end 0))
(setq keywd (match-string 1))
- (when (string-match "^\\\\" keywd)
+ (when (string-match "^\\\\" (match-string 1))
(setq keywd (concat keywd " "))) ;; Escaped ID needs space at end
+ ;; Add any :: package names to same identifier
+ (while (looking-at "\\s-*::\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
+ (goto-char (match-end 0))
+ (setq keywd (concat keywd "::" (match-string 1)))
+ (when (string-match "^\\\\" (match-string 1))
+ (setq keywd (concat keywd " ")))) ;; Escaped ID needs space at end
(cond ((equal keywd "input")
(setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
expect-signal 'sigs-in io t modport nil))
(nth 3 fass))
(t
;; Read from file
- ;; Clear then restore any hilighting to make emacs19 happy
+ ;; Clear then restore any highlighting to make emacs19 happy
(let ((fontlocked (when (and (boundp 'font-lock-mode)
font-lock-mode)
(font-lock-mode 0)
"Insert , etc before first ever port in this instant, as part of \\[verilog-auto-inst]."
;; Do we need a trailing comma?
;; There maybe a ifdef or something similar before us. What a mess. Thus
- ;; to avoid trouble we only insert on preceeding ) or *.
+ ;; to avoid trouble we only insert on preceding ) or *.
;; Insert first port on new line
(insert "\n") ;; Must insert before search, so point will move forward if insert comma
(save-excursion
Limitations:
AUTORESET will not clear memories.
- AUTORESET uses <= if there are any <= assigmnents in the block,
+ AUTORESET uses <= if there are any <= assignments in the block,
else it uses =.
/*AUTORESET*/ presumes that any signals mentioned between the previous
(interactive)
(let ((reporter-prompt-for-summary-p t))
(reporter-submit-bug-report
- "mac@verilog.com"
+ "mac@verilog.com, wsnyder@wsnyder.org"
(concat "verilog-mode v" verilog-mode-version)
'(
verilog-align-ifelse
nil nil
(concat "Hi Mac,
-I want to report a bug. I've read the `Bugs' section of `Info' on
-Emacs, so I know how to make a clear and unambiguous report. To get
-to that Info section, I typed
-
-M-x info RET m " invocation-name " RET m bugs RET
+I want to report a bug.
Before I go further, I want to say that Verilog mode has changed my life.
I save so much time, my files are colored nicely, my co workers respect
my coding ability... until now. I'd really appreciate anything you
could do to help me out with this minor deficiency in the product.
-If you have bugs with the AUTO functions, please CC the AUTOAUTHOR Wilson
-Snyder (wsnyder@wsnyder.org) and/or see http://www.veripool.org.
-You may also want to look at the Verilog-Mode FAQ, see
+I've taken a look at the Verilog-Mode FAQ at
http://www.veripool.org/verilog-mode-faq.html.
-To reproduce the bug, start a fresh Emacs via " invocation-name "
+And, I've considered filing the bug on the issue tracker at
+http://www.veripool.org/verilog-mode-bugs
+since I realize that public bugs are easier for you to track,
+and for others to search, but would prefer to email.
+
+So, to reproduce the bug, start a fresh Emacs via " invocation-name "
-no-init-file -no-site-file'. In a new buffer, in Verilog mode, type
the code included below.